1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * ahci.c - AHCI SATA support
4 *
5 * Maintained by: Tejun Heo <tj@kernel.org>
6 * Please ALWAYS copy linux-ide@vger.kernel.org
7 * on emails.
8 *
9 * Copyright 2004-2005 Red Hat, Inc.
10 *
11 * libata documentation is available via 'make {ps|pdf}docs',
12 * as Documentation/driver-api/libata.rst
13 *
14 * AHCI hardware documentation:
15 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
16 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
17 */
18
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/pci.h>
22 #include <linux/blkdev.h>
23 #include <linux/delay.h>
24 #include <linux/interrupt.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/device.h>
27 #include <linux/dmi.h>
28 #include <linux/gfp.h>
29 #include <scsi/scsi_host.h>
30 #include <scsi/scsi_cmnd.h>
31 #include <linux/libata.h>
32 #include <linux/ahci-remap.h>
33 #include <linux/io-64-nonatomic-lo-hi.h>
34 #include "ahci.h"
35
36 #define DRV_NAME "ahci"
37 #define DRV_VERSION "3.0"
38
39 enum {
40 AHCI_PCI_BAR_STA2X11 = 0,
41 AHCI_PCI_BAR_CAVIUM = 0,
42 AHCI_PCI_BAR_LOONGSON = 0,
43 AHCI_PCI_BAR_ENMOTUS = 2,
44 AHCI_PCI_BAR_CAVIUM_GEN5 = 4,
45 AHCI_PCI_BAR_STANDARD = 5,
46 };
47
48 enum board_ids {
49 /* board IDs by feature in alphabetical order */
50 board_ahci,
51 board_ahci_43bit_dma,
52 board_ahci_ign_iferr,
53 board_ahci_no_debounce_delay,
54 board_ahci_no_msi,
55 /*
56 * board_ahci_pcs_quirk is for legacy Intel platforms.
57 * Modern Intel platforms should use board_ahci instead.
58 * (Some modern Intel platforms might have been added with
59 * board_ahci_pcs_quirk, however, we cannot change them to board_ahci
60 * without testing that the platform actually works without the quirk.)
61 */
62 board_ahci_pcs_quirk,
63 board_ahci_pcs_quirk_no_devslp,
64 board_ahci_pcs_quirk_no_sntf,
65 board_ahci_yes_fbs,
66 board_ahci_yes_fbs_atapi_dma,
67
68 /* board IDs for specific chipsets in alphabetical order */
69 board_ahci_al,
70 board_ahci_avn,
71 board_ahci_jmb585,
72 board_ahci_mcp65,
73 board_ahci_mcp77,
74 board_ahci_mcp89,
75 board_ahci_mv,
76 board_ahci_sb600,
77 board_ahci_sb700, /* for SB700 and SB800 */
78 board_ahci_vt8251,
79
80 /* aliases */
81 board_ahci_mcp_linux = board_ahci_mcp65,
82 board_ahci_mcp67 = board_ahci_mcp65,
83 board_ahci_mcp73 = board_ahci_mcp65,
84 board_ahci_mcp79 = board_ahci_mcp77,
85 };
86
87 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
88 static void ahci_remove_one(struct pci_dev *dev);
89 static void ahci_shutdown_one(struct pci_dev *dev);
90 static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv);
91 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
92 unsigned long deadline);
93 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
94 unsigned long deadline);
95 static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
96 static bool is_mcp89_apple(struct pci_dev *pdev);
97 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
98 unsigned long deadline);
99 #ifdef CONFIG_PM
100 static int ahci_pci_device_runtime_suspend(struct device *dev);
101 static int ahci_pci_device_runtime_resume(struct device *dev);
102 #ifdef CONFIG_PM_SLEEP
103 static int ahci_pci_device_suspend(struct device *dev);
104 static int ahci_pci_device_resume(struct device *dev);
105 #endif
106 #endif /* CONFIG_PM */
107
108 static const struct scsi_host_template ahci_sht = {
109 AHCI_SHT("ahci"),
110 };
111
112 static struct ata_port_operations ahci_vt8251_ops = {
113 .inherits = &ahci_ops,
114 .reset.hardreset = ahci_vt8251_hardreset,
115 };
116
117 static struct ata_port_operations ahci_p5wdh_ops = {
118 .inherits = &ahci_ops,
119 .reset.hardreset = ahci_p5wdh_hardreset,
120 };
121
122 static struct ata_port_operations ahci_avn_ops = {
123 .inherits = &ahci_ops,
124 .reset.hardreset = ahci_avn_hardreset,
125 };
126
127 static const struct ata_port_info ahci_port_info[] = {
128 /* by features */
129 [board_ahci] = {
130 .flags = AHCI_FLAG_COMMON,
131 .pio_mask = ATA_PIO4,
132 .udma_mask = ATA_UDMA6,
133 .port_ops = &ahci_ops,
134 },
135 [board_ahci_43bit_dma] = {
136 AHCI_HFLAGS (AHCI_HFLAG_43BIT_ONLY),
137 .flags = AHCI_FLAG_COMMON,
138 .pio_mask = ATA_PIO4,
139 .udma_mask = ATA_UDMA6,
140 .port_ops = &ahci_ops,
141 },
142 [board_ahci_ign_iferr] = {
143 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
144 .flags = AHCI_FLAG_COMMON,
145 .pio_mask = ATA_PIO4,
146 .udma_mask = ATA_UDMA6,
147 .port_ops = &ahci_ops,
148 },
149 [board_ahci_no_debounce_delay] = {
150 .flags = AHCI_FLAG_COMMON,
151 .link_flags = ATA_LFLAG_NO_DEBOUNCE_DELAY,
152 .pio_mask = ATA_PIO4,
153 .udma_mask = ATA_UDMA6,
154 .port_ops = &ahci_ops,
155 },
156 [board_ahci_no_msi] = {
157 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
158 .flags = AHCI_FLAG_COMMON,
159 .pio_mask = ATA_PIO4,
160 .udma_mask = ATA_UDMA6,
161 .port_ops = &ahci_ops,
162 },
163 [board_ahci_pcs_quirk] = {
164 AHCI_HFLAGS (AHCI_HFLAG_INTEL_PCS_QUIRK),
165 .flags = AHCI_FLAG_COMMON,
166 .pio_mask = ATA_PIO4,
167 .udma_mask = ATA_UDMA6,
168 .port_ops = &ahci_ops,
169 },
170 [board_ahci_pcs_quirk_no_devslp] = {
171 AHCI_HFLAGS (AHCI_HFLAG_INTEL_PCS_QUIRK |
172 AHCI_HFLAG_NO_DEVSLP),
173 .flags = AHCI_FLAG_COMMON,
174 .pio_mask = ATA_PIO4,
175 .udma_mask = ATA_UDMA6,
176 .port_ops = &ahci_ops,
177 },
178 [board_ahci_pcs_quirk_no_sntf] = {
179 AHCI_HFLAGS (AHCI_HFLAG_INTEL_PCS_QUIRK |
180 AHCI_HFLAG_NO_SNTF),
181 .flags = AHCI_FLAG_COMMON,
182 .pio_mask = ATA_PIO4,
183 .udma_mask = ATA_UDMA6,
184 .port_ops = &ahci_ops,
185 },
186 [board_ahci_yes_fbs] = {
187 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
188 .flags = AHCI_FLAG_COMMON,
189 .pio_mask = ATA_PIO4,
190 .udma_mask = ATA_UDMA6,
191 .port_ops = &ahci_ops,
192 },
193 [board_ahci_yes_fbs_atapi_dma] = {
194 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS |
195 AHCI_HFLAG_ATAPI_DMA_QUIRK),
196 .flags = AHCI_FLAG_COMMON,
197 .pio_mask = ATA_PIO4,
198 .udma_mask = ATA_UDMA6,
199 .port_ops = &ahci_ops,
200 },
201 /* by chipsets */
202 [board_ahci_al] = {
203 AHCI_HFLAGS (AHCI_HFLAG_NO_PMP | AHCI_HFLAG_NO_MSI),
204 .flags = AHCI_FLAG_COMMON,
205 .pio_mask = ATA_PIO4,
206 .udma_mask = ATA_UDMA6,
207 .port_ops = &ahci_ops,
208 },
209 [board_ahci_avn] = {
210 AHCI_HFLAGS (AHCI_HFLAG_INTEL_PCS_QUIRK),
211 .flags = AHCI_FLAG_COMMON,
212 .pio_mask = ATA_PIO4,
213 .udma_mask = ATA_UDMA6,
214 .port_ops = &ahci_avn_ops,
215 },
216 /* JMicron JMB582/585: 64-bit DMA is broken, force 32-bit */
217 [board_ahci_jmb585] = {
218 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR |
219 AHCI_HFLAG_32BIT_ONLY),
220 .flags = AHCI_FLAG_COMMON,
221 .pio_mask = ATA_PIO4,
222 .udma_mask = ATA_UDMA6,
223 .port_ops = &ahci_ops,
224 },
225 [board_ahci_mcp65] = {
226 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
227 AHCI_HFLAG_YES_NCQ),
228 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
229 .pio_mask = ATA_PIO4,
230 .udma_mask = ATA_UDMA6,
231 .port_ops = &ahci_ops,
232 },
233 [board_ahci_mcp77] = {
234 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
235 .flags = AHCI_FLAG_COMMON,
236 .pio_mask = ATA_PIO4,
237 .udma_mask = ATA_UDMA6,
238 .port_ops = &ahci_ops,
239 },
240 [board_ahci_mcp89] = {
241 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
242 .flags = AHCI_FLAG_COMMON,
243 .pio_mask = ATA_PIO4,
244 .udma_mask = ATA_UDMA6,
245 .port_ops = &ahci_ops,
246 },
247 [board_ahci_mv] = {
248 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
249 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
250 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
251 .pio_mask = ATA_PIO4,
252 .udma_mask = ATA_UDMA6,
253 .port_ops = &ahci_ops,
254 },
255 [board_ahci_sb600] = {
256 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
257 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
258 AHCI_HFLAG_32BIT_ONLY),
259 .flags = AHCI_FLAG_COMMON,
260 .pio_mask = ATA_PIO4,
261 .udma_mask = ATA_UDMA6,
262 .port_ops = &ahci_pmp_retry_srst_ops,
263 },
264 [board_ahci_sb700] = { /* for SB700 and SB800 */
265 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
266 .flags = AHCI_FLAG_COMMON,
267 .pio_mask = ATA_PIO4,
268 .udma_mask = ATA_UDMA6,
269 .port_ops = &ahci_pmp_retry_srst_ops,
270 },
271 [board_ahci_vt8251] = {
272 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
273 .flags = AHCI_FLAG_COMMON,
274 .pio_mask = ATA_PIO4,
275 .udma_mask = ATA_UDMA6,
276 .port_ops = &ahci_vt8251_ops,
277 },
278 };
279
280 static const struct pci_device_id ahci_pci_tbl[] = {
281 /* Intel */
282 {
283 /* Comet Lake PCH-H RAID */
284 PCI_VDEVICE(INTEL, 0x06d6),
285 .driver_data = board_ahci_pcs_quirk,
286 }, {
287 /* ICH6 */
288 PCI_VDEVICE(INTEL, 0x2652),
289 .driver_data = board_ahci_pcs_quirk,
290 }, {
291 /* ICH6M */
292 PCI_VDEVICE(INTEL, 0x2653),
293 .driver_data = board_ahci_pcs_quirk,
294 }, {
295 /* ICH7 */
296 PCI_VDEVICE(INTEL, 0x27c1),
297 .driver_data = board_ahci_pcs_quirk,
298 }, {
299 /* ICH7M */
300 PCI_VDEVICE(INTEL, 0x27c5),
301 .driver_data = board_ahci_pcs_quirk,
302 }, {
303 /* ICH7R */
304 PCI_VDEVICE(INTEL, 0x27c3),
305 .driver_data = board_ahci_pcs_quirk,
306 }, {
307 /* ULi M5288 */
308 PCI_VDEVICE(AL, 0x5288),
309 .driver_data = board_ahci_ign_iferr,
310 }, {
311 /* ESB2 */
312 PCI_VDEVICE(INTEL, 0x2681),
313 .driver_data = board_ahci_pcs_quirk,
314 }, {
315 /* ESB2 */
316 PCI_VDEVICE(INTEL, 0x2682),
317 .driver_data = board_ahci_pcs_quirk,
318 }, {
319 /* ESB2 */
320 PCI_VDEVICE(INTEL, 0x2683),
321 .driver_data = board_ahci_pcs_quirk,
322 }, {
323 /* ICH7-M DH */
324 PCI_VDEVICE(INTEL, 0x27c6),
325 .driver_data = board_ahci_pcs_quirk,
326 }, {
327 /* ICH8 */
328 PCI_VDEVICE(INTEL, 0x2821),
329 .driver_data = board_ahci_pcs_quirk,
330 }, {
331 /* ICH8/Lewisburg RAID*/
332 PCI_VDEVICE(INTEL, 0x2822),
333 .driver_data = board_ahci_pcs_quirk_no_sntf,
334 }, {
335 /* ICH8 */
336 PCI_VDEVICE(INTEL, 0x2824),
337 .driver_data = board_ahci_pcs_quirk,
338 }, {
339 /* ICH8M */
340 PCI_VDEVICE(INTEL, 0x2829),
341 .driver_data = board_ahci_pcs_quirk,
342 }, {
343 /* ICH8M */
344 PCI_VDEVICE(INTEL, 0x282a),
345 .driver_data = board_ahci_pcs_quirk,
346 }, {
347 /* ICH9 */
348 PCI_VDEVICE(INTEL, 0x2922),
349 .driver_data = board_ahci_pcs_quirk,
350 }, {
351 /* ICH9 */
352 PCI_VDEVICE(INTEL, 0x2923),
353 .driver_data = board_ahci_pcs_quirk,
354 }, {
355 /* ICH9 */
356 PCI_VDEVICE(INTEL, 0x2924),
357 .driver_data = board_ahci_pcs_quirk,
358 }, {
359 /* ICH9 */
360 PCI_VDEVICE(INTEL, 0x2925),
361 .driver_data = board_ahci_pcs_quirk,
362 }, {
363 /* ICH9 */
364 PCI_VDEVICE(INTEL, 0x2927),
365 .driver_data = board_ahci_pcs_quirk,
366 }, {
367 /* ICH9M */
368 PCI_VDEVICE(INTEL, 0x2929),
369 .driver_data = board_ahci_pcs_quirk,
370 }, {
371 /* ICH9M */
372 PCI_VDEVICE(INTEL, 0x292a),
373 .driver_data = board_ahci_pcs_quirk,
374 }, {
375 /* ICH9M */
376 PCI_VDEVICE(INTEL, 0x292b),
377 .driver_data = board_ahci_pcs_quirk,
378 }, {
379 /* ICH9M */
380 PCI_VDEVICE(INTEL, 0x292c),
381 .driver_data = board_ahci_pcs_quirk,
382 }, {
383 /* ICH9M */
384 PCI_VDEVICE(INTEL, 0x292f),
385 .driver_data = board_ahci_pcs_quirk,
386 }, {
387 /* ICH9 */
388 PCI_VDEVICE(INTEL, 0x294d),
389 .driver_data = board_ahci_pcs_quirk,
390 }, {
391 /* ICH9M */
392 PCI_VDEVICE(INTEL, 0x294e),
393 .driver_data = board_ahci_pcs_quirk,
394 }, {
395 /* Tolapai */
396 PCI_VDEVICE(INTEL, 0x502a),
397 .driver_data = board_ahci_pcs_quirk,
398 }, {
399 /* Tolapai */
400 PCI_VDEVICE(INTEL, 0x502b),
401 .driver_data = board_ahci_pcs_quirk,
402 }, {
403 /* ICH10 */
404 PCI_VDEVICE(INTEL, 0x3a05),
405 .driver_data = board_ahci_pcs_quirk,
406 }, {
407 /* ICH10 */
408 PCI_VDEVICE(INTEL, 0x3a22),
409 .driver_data = board_ahci_pcs_quirk,
410 }, {
411 /* ICH10 */
412 PCI_VDEVICE(INTEL, 0x3a25),
413 .driver_data = board_ahci_pcs_quirk,
414 }, {
415 /* PCH AHCI */
416 PCI_VDEVICE(INTEL, 0x3b22),
417 .driver_data = board_ahci_pcs_quirk,
418 }, {
419 /* PCH AHCI */
420 PCI_VDEVICE(INTEL, 0x3b23),
421 .driver_data = board_ahci_pcs_quirk,
422 }, {
423 /* PCH RAID */
424 PCI_VDEVICE(INTEL, 0x3b24),
425 .driver_data = board_ahci_pcs_quirk,
426 }, {
427 /* PCH RAID */
428 PCI_VDEVICE(INTEL, 0x3b25),
429 .driver_data = board_ahci_pcs_quirk,
430 }, {
431 /* PCH M AHCI */
432 PCI_VDEVICE(INTEL, 0x3b29),
433 .driver_data = board_ahci_pcs_quirk,
434 }, {
435 /* PCH RAID */
436 PCI_VDEVICE(INTEL, 0x3b2b),
437 .driver_data = board_ahci_pcs_quirk,
438 }, {
439 /* PCH M RAID */
440 PCI_VDEVICE(INTEL, 0x3b2c),
441 .driver_data = board_ahci_pcs_quirk,
442 }, {
443 /* PCH AHCI */
444 PCI_VDEVICE(INTEL, 0x3b2f),
445 .driver_data = board_ahci_pcs_quirk,
446 }, {
447 /* DNV AHCI */
448 PCI_VDEVICE(INTEL, 0x19b0),
449 .driver_data = board_ahci,
450 }, {
451 /* DNV AHCI */
452 PCI_VDEVICE(INTEL, 0x19b1),
453 .driver_data = board_ahci,
454 }, {
455 /* DNV AHCI */
456 PCI_VDEVICE(INTEL, 0x19b2),
457 .driver_data = board_ahci,
458 }, {
459 /* DNV AHCI */
460 PCI_VDEVICE(INTEL, 0x19b3),
461 .driver_data = board_ahci,
462 }, {
463 /* DNV AHCI */
464 PCI_VDEVICE(INTEL, 0x19b4),
465 .driver_data = board_ahci,
466 }, {
467 /* DNV AHCI */
468 PCI_VDEVICE(INTEL, 0x19b5),
469 .driver_data = board_ahci,
470 }, {
471 /* DNV AHCI */
472 PCI_VDEVICE(INTEL, 0x19b6),
473 .driver_data = board_ahci,
474 }, {
475 /* DNV AHCI */
476 PCI_VDEVICE(INTEL, 0x19b7),
477 .driver_data = board_ahci,
478 }, {
479 /* DNV AHCI */
480 PCI_VDEVICE(INTEL, 0x19bE),
481 .driver_data = board_ahci,
482 }, {
483 /* DNV AHCI */
484 PCI_VDEVICE(INTEL, 0x19bF),
485 .driver_data = board_ahci,
486 }, {
487 /* DNV AHCI */
488 PCI_VDEVICE(INTEL, 0x19c0),
489 .driver_data = board_ahci,
490 }, {
491 /* DNV AHCI */
492 PCI_VDEVICE(INTEL, 0x19c1),
493 .driver_data = board_ahci,
494 }, {
495 /* DNV AHCI */
496 PCI_VDEVICE(INTEL, 0x19c2),
497 .driver_data = board_ahci,
498 }, {
499 /* DNV AHCI */
500 PCI_VDEVICE(INTEL, 0x19c3),
501 .driver_data = board_ahci,
502 }, {
503 /* DNV AHCI */
504 PCI_VDEVICE(INTEL, 0x19c4),
505 .driver_data = board_ahci,
506 }, {
507 /* DNV AHCI */
508 PCI_VDEVICE(INTEL, 0x19c5),
509 .driver_data = board_ahci,
510 }, {
511 /* DNV AHCI */
512 PCI_VDEVICE(INTEL, 0x19c6),
513 .driver_data = board_ahci,
514 }, {
515 /* DNV AHCI */
516 PCI_VDEVICE(INTEL, 0x19c7),
517 .driver_data = board_ahci,
518 }, {
519 /* DNV AHCI */
520 PCI_VDEVICE(INTEL, 0x19cE),
521 .driver_data = board_ahci,
522 }, {
523 /* DNV AHCI */
524 PCI_VDEVICE(INTEL, 0x19cF),
525 .driver_data = board_ahci,
526 }, {
527 /* CPT AHCI */
528 PCI_VDEVICE(INTEL, 0x1c02),
529 .driver_data = board_ahci_pcs_quirk,
530 }, {
531 /* CPT M AHCI */
532 PCI_VDEVICE(INTEL, 0x1c03),
533 .driver_data = board_ahci_pcs_quirk,
534 }, {
535 /* CPT RAID */
536 PCI_VDEVICE(INTEL, 0x1c04),
537 .driver_data = board_ahci_pcs_quirk,
538 }, {
539 /* CPT M RAID */
540 PCI_VDEVICE(INTEL, 0x1c05),
541 .driver_data = board_ahci_pcs_quirk,
542 }, {
543 /* CPT RAID */
544 PCI_VDEVICE(INTEL, 0x1c06),
545 .driver_data = board_ahci_pcs_quirk,
546 }, {
547 /* CPT RAID */
548 PCI_VDEVICE(INTEL, 0x1c07),
549 .driver_data = board_ahci_pcs_quirk,
550 }, {
551 /* PBG AHCI */
552 PCI_VDEVICE(INTEL, 0x1d02),
553 .driver_data = board_ahci_pcs_quirk,
554 }, {
555 /* PBG RAID */
556 PCI_VDEVICE(INTEL, 0x1d04),
557 .driver_data = board_ahci_pcs_quirk,
558 }, {
559 /* PBG RAID */
560 PCI_VDEVICE(INTEL, 0x1d06),
561 .driver_data = board_ahci_pcs_quirk,
562 }, {
563 /* DH89xxCC AHCI */
564 PCI_VDEVICE(INTEL, 0x2323),
565 .driver_data = board_ahci_pcs_quirk,
566 }, {
567 /* Panther Point AHCI */
568 PCI_VDEVICE(INTEL, 0x1e02),
569 .driver_data = board_ahci_pcs_quirk,
570 }, {
571 /* Panther M AHCI */
572 PCI_VDEVICE(INTEL, 0x1e03),
573 .driver_data = board_ahci_pcs_quirk,
574 }, {
575 /* Panther Point RAID */
576 PCI_VDEVICE(INTEL, 0x1e04),
577 .driver_data = board_ahci_pcs_quirk,
578 }, {
579 /* Panther Point RAID */
580 PCI_VDEVICE(INTEL, 0x1e05),
581 .driver_data = board_ahci_pcs_quirk,
582 }, {
583 /* Panther Point RAID */
584 PCI_VDEVICE(INTEL, 0x1e06),
585 .driver_data = board_ahci_pcs_quirk,
586 }, {
587 /* Panther M RAID */
588 PCI_VDEVICE(INTEL, 0x1e07),
589 .driver_data = board_ahci_pcs_quirk,
590 }, {
591 /* Panther Point RAID */
592 PCI_VDEVICE(INTEL, 0x1e0e),
593 .driver_data = board_ahci_pcs_quirk,
594 }, {
595 /* Lynx Point AHCI */
596 PCI_VDEVICE(INTEL, 0x8c02),
597 .driver_data = board_ahci_pcs_quirk,
598 }, {
599 /* Lynx M AHCI */
600 PCI_VDEVICE(INTEL, 0x8c03),
601 .driver_data = board_ahci_pcs_quirk,
602 }, {
603 /* Lynx Point RAID */
604 PCI_VDEVICE(INTEL, 0x8c04),
605 .driver_data = board_ahci_pcs_quirk,
606 }, {
607 /* Lynx M RAID */
608 PCI_VDEVICE(INTEL, 0x8c05),
609 .driver_data = board_ahci_pcs_quirk,
610 }, {
611 /* Lynx Point RAID */
612 PCI_VDEVICE(INTEL, 0x8c06),
613 .driver_data = board_ahci_pcs_quirk,
614 }, {
615 /* Lynx M RAID */
616 PCI_VDEVICE(INTEL, 0x8c07),
617 .driver_data = board_ahci_pcs_quirk,
618 }, {
619 /* Lynx Point RAID */
620 PCI_VDEVICE(INTEL, 0x8c0e),
621 .driver_data = board_ahci_pcs_quirk,
622 }, {
623 /* Lynx M RAID */
624 PCI_VDEVICE(INTEL, 0x8c0f),
625 .driver_data = board_ahci_pcs_quirk,
626 }, {
627 /* Lynx LP AHCI */
628 PCI_VDEVICE(INTEL, 0x9c02),
629 .driver_data = board_ahci_pcs_quirk,
630 }, {
631 /* Lynx LP AHCI */
632 PCI_VDEVICE(INTEL, 0x9c03),
633 .driver_data = board_ahci_pcs_quirk,
634 }, {
635 /* Lynx LP RAID */
636 PCI_VDEVICE(INTEL, 0x9c04),
637 .driver_data = board_ahci_pcs_quirk,
638 }, {
639 /* Lynx LP RAID */
640 PCI_VDEVICE(INTEL, 0x9c05),
641 .driver_data = board_ahci_pcs_quirk,
642 }, {
643 /* Lynx LP RAID */
644 PCI_VDEVICE(INTEL, 0x9c06),
645 .driver_data = board_ahci_pcs_quirk,
646 }, {
647 /* Lynx LP RAID */
648 PCI_VDEVICE(INTEL, 0x9c07),
649 .driver_data = board_ahci_pcs_quirk,
650 }, {
651 /* Lynx LP RAID */
652 PCI_VDEVICE(INTEL, 0x9c0e),
653 .driver_data = board_ahci_pcs_quirk,
654 }, {
655 /* Lynx LP RAID */
656 PCI_VDEVICE(INTEL, 0x9c0f),
657 .driver_data = board_ahci_pcs_quirk,
658 }, {
659 /* Cannon Lake PCH-LP AHCI */
660 PCI_VDEVICE(INTEL, 0x9dd3),
661 .driver_data = board_ahci_pcs_quirk,
662 }, {
663 /* Avoton AHCI */
664 PCI_VDEVICE(INTEL, 0x1f22),
665 .driver_data = board_ahci_pcs_quirk,
666 }, {
667 /* Avoton AHCI */
668 PCI_VDEVICE(INTEL, 0x1f23),
669 .driver_data = board_ahci_pcs_quirk,
670 }, {
671 /* Avoton RAID */
672 PCI_VDEVICE(INTEL, 0x1f24),
673 .driver_data = board_ahci_pcs_quirk,
674 }, {
675 /* Avoton RAID */
676 PCI_VDEVICE(INTEL, 0x1f25),
677 .driver_data = board_ahci_pcs_quirk,
678 }, {
679 /* Avoton RAID */
680 PCI_VDEVICE(INTEL, 0x1f26),
681 .driver_data = board_ahci_pcs_quirk,
682 }, {
683 /* Avoton RAID */
684 PCI_VDEVICE(INTEL, 0x1f27),
685 .driver_data = board_ahci_pcs_quirk,
686 }, {
687 /* Avoton RAID */
688 PCI_VDEVICE(INTEL, 0x1f2e),
689 .driver_data = board_ahci_pcs_quirk,
690 }, {
691 /* Avoton RAID */
692 PCI_VDEVICE(INTEL, 0x1f2f),
693 .driver_data = board_ahci_pcs_quirk,
694 }, {
695 /* Avoton AHCI */
696 PCI_VDEVICE(INTEL, 0x1f32),
697 .driver_data = board_ahci_avn,
698 }, {
699 /* Avoton AHCI */
700 PCI_VDEVICE(INTEL, 0x1f33),
701 .driver_data = board_ahci_avn,
702 }, {
703 /* Avoton RAID */
704 PCI_VDEVICE(INTEL, 0x1f34),
705 .driver_data = board_ahci_avn,
706 }, {
707 /* Avoton RAID */
708 PCI_VDEVICE(INTEL, 0x1f35),
709 .driver_data = board_ahci_avn,
710 }, {
711 /* Avoton RAID */
712 PCI_VDEVICE(INTEL, 0x1f36),
713 .driver_data = board_ahci_avn,
714 }, {
715 /* Avoton RAID */
716 PCI_VDEVICE(INTEL, 0x1f37),
717 .driver_data = board_ahci_avn,
718 }, {
719 /* Avoton RAID */
720 PCI_VDEVICE(INTEL, 0x1f3e),
721 .driver_data = board_ahci_avn,
722 }, {
723 /* Avoton RAID */
724 PCI_VDEVICE(INTEL, 0x1f3f),
725 .driver_data = board_ahci_avn,
726 }, {
727 /* Wellsburg/Lewisburg AHCI*/
728 PCI_VDEVICE(INTEL, 0x2823),
729 .driver_data = board_ahci_pcs_quirk,
730 }, {
731 /* *burg SATA0 'RAID' */
732 PCI_VDEVICE(INTEL, 0x2826),
733 .driver_data = board_ahci_pcs_quirk,
734 }, {
735 /* *burg SATA1 'RAID' */
736 PCI_VDEVICE(INTEL, 0x2827),
737 .driver_data = board_ahci_pcs_quirk,
738 }, {
739 /* *burg SATA2 'RAID' */
740 PCI_VDEVICE(INTEL, 0x282f),
741 .driver_data = board_ahci_pcs_quirk,
742 }, {
743 /* Rocket Lake PCH-H RAID */
744 PCI_VDEVICE(INTEL, 0x43d4),
745 .driver_data = board_ahci_pcs_quirk,
746 }, {
747 /* Rocket Lake PCH-H RAID */
748 PCI_VDEVICE(INTEL, 0x43d5),
749 .driver_data = board_ahci_pcs_quirk,
750 }, {
751 /* Rocket Lake PCH-H RAID */
752 PCI_VDEVICE(INTEL, 0x43d6),
753 .driver_data = board_ahci_pcs_quirk,
754 }, {
755 /* Rocket Lake PCH-H RAID */
756 PCI_VDEVICE(INTEL, 0x43d7),
757 .driver_data = board_ahci_pcs_quirk,
758 }, {
759 /* Wellsburg AHCI */
760 PCI_VDEVICE(INTEL, 0x8d02),
761 .driver_data = board_ahci_pcs_quirk,
762 }, {
763 /* Wellsburg RAID */
764 PCI_VDEVICE(INTEL, 0x8d04),
765 .driver_data = board_ahci_pcs_quirk,
766 }, {
767 /* Wellsburg RAID */
768 PCI_VDEVICE(INTEL, 0x8d06),
769 .driver_data = board_ahci_pcs_quirk,
770 }, {
771 /* Wellsburg RAID */
772 PCI_VDEVICE(INTEL, 0x8d0e),
773 .driver_data = board_ahci_pcs_quirk,
774 }, {
775 /* Wellsburg AHCI */
776 PCI_VDEVICE(INTEL, 0x8d62),
777 .driver_data = board_ahci_pcs_quirk,
778 }, {
779 /* Wellsburg RAID */
780 PCI_VDEVICE(INTEL, 0x8d64),
781 .driver_data = board_ahci_pcs_quirk,
782 }, {
783 /* Wellsburg RAID */
784 PCI_VDEVICE(INTEL, 0x8d66),
785 .driver_data = board_ahci_pcs_quirk,
786 }, {
787 /* Wellsburg RAID */
788 PCI_VDEVICE(INTEL, 0x8d6e),
789 .driver_data = board_ahci_pcs_quirk,
790 }, {
791 /* Coleto Creek AHCI */
792 PCI_VDEVICE(INTEL, 0x23a3),
793 .driver_data = board_ahci_pcs_quirk,
794 }, {
795 /* Wildcat LP AHCI */
796 PCI_VDEVICE(INTEL, 0x9c83),
797 .driver_data = board_ahci_pcs_quirk,
798 }, {
799 /* Wildcat LP RAID */
800 PCI_VDEVICE(INTEL, 0x9c85),
801 .driver_data = board_ahci_pcs_quirk,
802 }, {
803 /* Wildcat LP RAID */
804 PCI_VDEVICE(INTEL, 0x9c87),
805 .driver_data = board_ahci_pcs_quirk,
806 }, {
807 /* Wildcat LP RAID */
808 PCI_VDEVICE(INTEL, 0x9c8f),
809 .driver_data = board_ahci_pcs_quirk,
810 }, {
811 /* 9 Series AHCI */
812 PCI_VDEVICE(INTEL, 0x8c82),
813 .driver_data = board_ahci_pcs_quirk,
814 }, {
815 /* 9 Series M AHCI */
816 PCI_VDEVICE(INTEL, 0x8c83),
817 .driver_data = board_ahci_pcs_quirk,
818 }, {
819 /* 9 Series RAID */
820 PCI_VDEVICE(INTEL, 0x8c84),
821 .driver_data = board_ahci_pcs_quirk,
822 }, {
823 /* 9 Series M RAID */
824 PCI_VDEVICE(INTEL, 0x8c85),
825 .driver_data = board_ahci_pcs_quirk,
826 }, {
827 /* 9 Series RAID */
828 PCI_VDEVICE(INTEL, 0x8c86),
829 .driver_data = board_ahci_pcs_quirk,
830 }, {
831 /* 9 Series M RAID */
832 PCI_VDEVICE(INTEL, 0x8c87),
833 .driver_data = board_ahci_pcs_quirk,
834 }, {
835 /* 9 Series RAID */
836 PCI_VDEVICE(INTEL, 0x8c8e),
837 .driver_data = board_ahci_pcs_quirk,
838 }, {
839 /* 9 Series M RAID */
840 PCI_VDEVICE(INTEL, 0x8c8f),
841 .driver_data = board_ahci_pcs_quirk,
842 }, {
843 /* Sunrise LP AHCI */
844 PCI_VDEVICE(INTEL, 0x9d03),
845 .driver_data = board_ahci_pcs_quirk,
846 }, {
847 /* Sunrise LP RAID */
848 PCI_VDEVICE(INTEL, 0x9d05),
849 .driver_data = board_ahci_pcs_quirk,
850 }, {
851 /* Sunrise LP RAID */
852 PCI_VDEVICE(INTEL, 0x9d07),
853 .driver_data = board_ahci_pcs_quirk,
854 }, {
855 /* Sunrise Point-H AHCI */
856 PCI_VDEVICE(INTEL, 0xa102),
857 .driver_data = board_ahci_pcs_quirk,
858 }, {
859 /* Sunrise M AHCI */
860 PCI_VDEVICE(INTEL, 0xa103),
861 .driver_data = board_ahci_pcs_quirk,
862 }, {
863 /* Sunrise Point-H RAID */
864 PCI_VDEVICE(INTEL, 0xa105),
865 .driver_data = board_ahci_pcs_quirk,
866 }, {
867 /* Sunrise Point-H RAID */
868 PCI_VDEVICE(INTEL, 0xa106),
869 .driver_data = board_ahci_pcs_quirk,
870 }, {
871 /* Sunrise M RAID */
872 PCI_VDEVICE(INTEL, 0xa107),
873 .driver_data = board_ahci_pcs_quirk,
874 }, {
875 /* Sunrise Point-H RAID */
876 PCI_VDEVICE(INTEL, 0xa10f),
877 .driver_data = board_ahci_pcs_quirk,
878 }, {
879 /* Lewisburg AHCI*/
880 PCI_VDEVICE(INTEL, 0xa182),
881 .driver_data = board_ahci_pcs_quirk,
882 }, {
883 /* Lewisburg RAID*/
884 PCI_VDEVICE(INTEL, 0xa186),
885 .driver_data = board_ahci_pcs_quirk,
886 }, {
887 /* Lewisburg RAID*/
888 PCI_VDEVICE(INTEL, 0xa1d2),
889 .driver_data = board_ahci_pcs_quirk,
890 }, {
891 /* Lewisburg RAID*/
892 PCI_VDEVICE(INTEL, 0xa1d6),
893 .driver_data = board_ahci_pcs_quirk,
894 }, {
895 /* Lewisburg AHCI*/
896 PCI_VDEVICE(INTEL, 0xa202),
897 .driver_data = board_ahci_pcs_quirk,
898 }, {
899 /* Lewisburg RAID*/
900 PCI_VDEVICE(INTEL, 0xa206),
901 .driver_data = board_ahci_pcs_quirk,
902 }, {
903 /* Lewisburg RAID*/
904 PCI_VDEVICE(INTEL, 0xa252),
905 .driver_data = board_ahci_pcs_quirk,
906 }, {
907 /* Lewisburg RAID*/
908 PCI_VDEVICE(INTEL, 0xa256),
909 .driver_data = board_ahci_pcs_quirk,
910 }, {
911 /* Cannon Lake PCH-H RAID */
912 PCI_VDEVICE(INTEL, 0xa356),
913 .driver_data = board_ahci_pcs_quirk,
914 }, {
915 /* Comet Lake-H RAID */
916 PCI_VDEVICE(INTEL, 0x06d7),
917 .driver_data = board_ahci_pcs_quirk,
918 }, {
919 /* Comet Lake PCH-V RAID */
920 PCI_VDEVICE(INTEL, 0xa386),
921 .driver_data = board_ahci_pcs_quirk,
922 }, {
923 /* Bay Trail AHCI */
924 PCI_VDEVICE(INTEL, 0x0f22),
925 .driver_data = board_ahci_pcs_quirk,
926 }, {
927 /* Bay Trail AHCI */
928 PCI_VDEVICE(INTEL, 0x0f23),
929 .driver_data = board_ahci_pcs_quirk_no_devslp,
930 }, {
931 /* Cherry Tr. AHCI */
932 PCI_VDEVICE(INTEL, 0x22a3),
933 .driver_data = board_ahci_pcs_quirk,
934 }, {
935 /* ApolloLake AHCI */
936 PCI_VDEVICE(INTEL, 0x5ae3),
937 .driver_data = board_ahci_pcs_quirk,
938 }, {
939 /* Ice Lake LP AHCI */
940 PCI_VDEVICE(INTEL, 0x34d3),
941 .driver_data = board_ahci_pcs_quirk,
942 }, {
943 /* Comet Lake PCH-U AHCI */
944 PCI_VDEVICE(INTEL, 0x02d3),
945 .driver_data = board_ahci_pcs_quirk,
946 }, {
947 /* Comet Lake PCH RAID */
948 PCI_VDEVICE(INTEL, 0x02d7),
949 .driver_data = board_ahci_pcs_quirk,
950 },
951
952 /* Elkhart Lake IDs 0x4b60 & 0x4b62 https://sata-io.org/product/8803 not tested yet */
953 {
954 /* Elkhart Lake AHCI */
955 PCI_VDEVICE(INTEL, 0x4b63),
956 .driver_data = board_ahci_pcs_quirk,
957 }, {
958 /* JMicron JMB582/585: force 32-bit DMA (broken 64-bit implementation) */
959 PCI_VDEVICE(JMICRON, 0x0582),
960 .driver_data = board_ahci_jmb585,
961
962 }, {
963 PCI_VDEVICE(JMICRON, 0x0585),
964 .driver_data = board_ahci_jmb585,
965 }, {
966 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
967 PCI_DEVICE(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID),
968 .class = PCI_CLASS_STORAGE_SATA_AHCI,
969 .class_mask = 0xffffff,
970 .driver_data = board_ahci_ign_iferr,
971
972 },
973 /* JMicron 362B and 362C have an AHCI function with IDE class code */
974 {
975 PCI_VDEVICE(JMICRON, 0x2362),
976 .driver_data = board_ahci_ign_iferr,
977
978 }, {
979 PCI_VDEVICE(JMICRON, 0x236f),
980 .driver_data = board_ahci_ign_iferr,
981
982 },
983 /* May need to update quirk_jmicron_async_suspend() for additions */
984
985 /* ATI */
986 {
987 /* ATI SB600 */
988 PCI_VDEVICE(ATI, 0x4380),
989 .driver_data = board_ahci_sb600,
990 }, {
991 /* ATI SB700/800 */
992 PCI_VDEVICE(ATI, 0x4390),
993 .driver_data = board_ahci_sb700,
994 }, {
995 /* ATI SB700/800 */
996 PCI_VDEVICE(ATI, 0x4391),
997 .driver_data = board_ahci_sb700,
998 }, {
999 /* ATI SB700/800 */
1000 PCI_VDEVICE(ATI, 0x4392),
1001 .driver_data = board_ahci_sb700,
1002 }, {
1003 /* ATI SB700/800 */
1004 PCI_VDEVICE(ATI, 0x4393),
1005 .driver_data = board_ahci_sb700,
1006 }, {
1007 /* ATI SB700/800 */
1008 PCI_VDEVICE(ATI, 0x4394),
1009 .driver_data = board_ahci_sb700,
1010 }, {
1011 /* ATI SB700/800 */
1012 PCI_VDEVICE(ATI, 0x4395),
1013 .driver_data = board_ahci_sb700,
1014 },
1015
1016 /* Amazon's Annapurna Labs support */
1017 {
1018 PCI_DEVICE(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031),
1019 .class = PCI_CLASS_STORAGE_SATA_AHCI,
1020 .class_mask = 0xffffff,
1021 .driver_data = board_ahci_al,
1022
1023 },
1024 /* AMD */
1025 {
1026 /* AMD Hudson-2 */
1027 PCI_VDEVICE(AMD, 0x7800),
1028 .driver_data = board_ahci,
1029 }, {
1030 /* AMD Hudson-2 (AHCI mode) */
1031 PCI_VDEVICE(AMD, 0x7801),
1032 .driver_data = board_ahci_no_debounce_delay,
1033 }, {
1034 /* AMD CZ */
1035 PCI_VDEVICE(AMD, 0x7900),
1036 .driver_data = board_ahci,
1037 }, {
1038 /* AMD Green Sardine */
1039 PCI_VDEVICE(AMD, 0x7901),
1040 .driver_data = board_ahci,
1041 },
1042 /* AMD is using RAID class only for ahci controllers */
1043 {
1044 PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
1045 .class = PCI_CLASS_STORAGE_RAID << 8,
1046 .class_mask = 0xffffff,
1047 .driver_data = board_ahci,
1048 },
1049
1050 /* Dell S140/S150 */
1051 {
1052 PCI_DEVICE_SUB(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
1053 PCI_SUBVENDOR_ID_DELL, PCI_ANY_ID),
1054 .class = PCI_CLASS_STORAGE_RAID << 8,
1055 .class_mask = 0xffffff,
1056 .driver_data = board_ahci_pcs_quirk,
1057
1058 },
1059
1060 /* VIA */
1061 {
1062 /* VIA VT8251 */
1063 PCI_VDEVICE(VIA, 0x3349),
1064 .driver_data = board_ahci_vt8251,
1065 }, {
1066 /* VIA VT8251 */
1067 PCI_VDEVICE(VIA, 0x6287),
1068 .driver_data = board_ahci_vt8251,
1069 },
1070
1071 /* NVIDIA */
1072 {
1073 /* MCP65 */
1074 PCI_VDEVICE(NVIDIA, 0x044c),
1075 .driver_data = board_ahci_mcp65,
1076 }, {
1077 /* MCP65 */
1078 PCI_VDEVICE(NVIDIA, 0x044d),
1079 .driver_data = board_ahci_mcp65,
1080 }, {
1081 /* MCP65 */
1082 PCI_VDEVICE(NVIDIA, 0x044e),
1083 .driver_data = board_ahci_mcp65,
1084 }, {
1085 /* MCP65 */
1086 PCI_VDEVICE(NVIDIA, 0x044f),
1087 .driver_data = board_ahci_mcp65,
1088 }, {
1089 /* MCP65 */
1090 PCI_VDEVICE(NVIDIA, 0x045c),
1091 .driver_data = board_ahci_mcp65,
1092 }, {
1093 /* MCP65 */
1094 PCI_VDEVICE(NVIDIA, 0x045d),
1095 .driver_data = board_ahci_mcp65,
1096 }, {
1097 /* MCP65 */
1098 PCI_VDEVICE(NVIDIA, 0x045e),
1099 .driver_data = board_ahci_mcp65,
1100 }, {
1101 /* MCP65 */
1102 PCI_VDEVICE(NVIDIA, 0x045f),
1103 .driver_data = board_ahci_mcp65,
1104 }, {
1105 /* MCP67 */
1106 PCI_VDEVICE(NVIDIA, 0x0550),
1107 .driver_data = board_ahci_mcp67,
1108 }, {
1109 /* MCP67 */
1110 PCI_VDEVICE(NVIDIA, 0x0551),
1111 .driver_data = board_ahci_mcp67,
1112 }, {
1113 /* MCP67 */
1114 PCI_VDEVICE(NVIDIA, 0x0552),
1115 .driver_data = board_ahci_mcp67,
1116 }, {
1117 /* MCP67 */
1118 PCI_VDEVICE(NVIDIA, 0x0553),
1119 .driver_data = board_ahci_mcp67,
1120 }, {
1121 /* MCP67 */
1122 PCI_VDEVICE(NVIDIA, 0x0554),
1123 .driver_data = board_ahci_mcp67,
1124 }, {
1125 /* MCP67 */
1126 PCI_VDEVICE(NVIDIA, 0x0555),
1127 .driver_data = board_ahci_mcp67,
1128 }, {
1129 /* MCP67 */
1130 PCI_VDEVICE(NVIDIA, 0x0556),
1131 .driver_data = board_ahci_mcp67,
1132 }, {
1133 /* MCP67 */
1134 PCI_VDEVICE(NVIDIA, 0x0557),
1135 .driver_data = board_ahci_mcp67,
1136 }, {
1137 /* MCP67 */
1138 PCI_VDEVICE(NVIDIA, 0x0558),
1139 .driver_data = board_ahci_mcp67,
1140 }, {
1141 /* MCP67 */
1142 PCI_VDEVICE(NVIDIA, 0x0559),
1143 .driver_data = board_ahci_mcp67,
1144 }, {
1145 /* MCP67 */
1146 PCI_VDEVICE(NVIDIA, 0x055a),
1147 .driver_data = board_ahci_mcp67,
1148 }, {
1149 /* MCP67 */
1150 PCI_VDEVICE(NVIDIA, 0x055b),
1151 .driver_data = board_ahci_mcp67,
1152 }, {
1153 /* Linux ID */
1154 PCI_VDEVICE(NVIDIA, 0x0580),
1155 .driver_data = board_ahci_mcp_linux,
1156 }, {
1157 /* Linux ID */
1158 PCI_VDEVICE(NVIDIA, 0x0581),
1159 .driver_data = board_ahci_mcp_linux,
1160 }, {
1161 /* Linux ID */
1162 PCI_VDEVICE(NVIDIA, 0x0582),
1163 .driver_data = board_ahci_mcp_linux,
1164 }, {
1165 /* Linux ID */
1166 PCI_VDEVICE(NVIDIA, 0x0583),
1167 .driver_data = board_ahci_mcp_linux,
1168 }, {
1169 /* Linux ID */
1170 PCI_VDEVICE(NVIDIA, 0x0584),
1171 .driver_data = board_ahci_mcp_linux,
1172 }, {
1173 /* Linux ID */
1174 PCI_VDEVICE(NVIDIA, 0x0585),
1175 .driver_data = board_ahci_mcp_linux,
1176 }, {
1177 /* Linux ID */
1178 PCI_VDEVICE(NVIDIA, 0x0586),
1179 .driver_data = board_ahci_mcp_linux,
1180 }, {
1181 /* Linux ID */
1182 PCI_VDEVICE(NVIDIA, 0x0587),
1183 .driver_data = board_ahci_mcp_linux,
1184 }, {
1185 /* Linux ID */
1186 PCI_VDEVICE(NVIDIA, 0x0588),
1187 .driver_data = board_ahci_mcp_linux,
1188 }, {
1189 /* Linux ID */
1190 PCI_VDEVICE(NVIDIA, 0x0589),
1191 .driver_data = board_ahci_mcp_linux,
1192 }, {
1193 /* Linux ID */
1194 PCI_VDEVICE(NVIDIA, 0x058a),
1195 .driver_data = board_ahci_mcp_linux,
1196 }, {
1197 /* Linux ID */
1198 PCI_VDEVICE(NVIDIA, 0x058b),
1199 .driver_data = board_ahci_mcp_linux,
1200 }, {
1201 /* Linux ID */
1202 PCI_VDEVICE(NVIDIA, 0x058c),
1203 .driver_data = board_ahci_mcp_linux,
1204 }, {
1205 /* Linux ID */
1206 PCI_VDEVICE(NVIDIA, 0x058d),
1207 .driver_data = board_ahci_mcp_linux,
1208 }, {
1209 /* Linux ID */
1210 PCI_VDEVICE(NVIDIA, 0x058e),
1211 .driver_data = board_ahci_mcp_linux,
1212 }, {
1213 /* Linux ID */
1214 PCI_VDEVICE(NVIDIA, 0x058f),
1215 .driver_data = board_ahci_mcp_linux,
1216 }, {
1217 /* MCP73 */
1218 PCI_VDEVICE(NVIDIA, 0x07f0),
1219 .driver_data = board_ahci_mcp73,
1220 }, {
1221 /* MCP73 */
1222 PCI_VDEVICE(NVIDIA, 0x07f1),
1223 .driver_data = board_ahci_mcp73,
1224 }, {
1225 /* MCP73 */
1226 PCI_VDEVICE(NVIDIA, 0x07f2),
1227 .driver_data = board_ahci_mcp73,
1228 }, {
1229 /* MCP73 */
1230 PCI_VDEVICE(NVIDIA, 0x07f3),
1231 .driver_data = board_ahci_mcp73,
1232 }, {
1233 /* MCP73 */
1234 PCI_VDEVICE(NVIDIA, 0x07f4),
1235 .driver_data = board_ahci_mcp73,
1236 }, {
1237 /* MCP73 */
1238 PCI_VDEVICE(NVIDIA, 0x07f5),
1239 .driver_data = board_ahci_mcp73,
1240 }, {
1241 /* MCP73 */
1242 PCI_VDEVICE(NVIDIA, 0x07f6),
1243 .driver_data = board_ahci_mcp73,
1244 }, {
1245 /* MCP73 */
1246 PCI_VDEVICE(NVIDIA, 0x07f7),
1247 .driver_data = board_ahci_mcp73,
1248 }, {
1249 /* MCP73 */
1250 PCI_VDEVICE(NVIDIA, 0x07f8),
1251 .driver_data = board_ahci_mcp73,
1252 }, {
1253 /* MCP73 */
1254 PCI_VDEVICE(NVIDIA, 0x07f9),
1255 .driver_data = board_ahci_mcp73,
1256 }, {
1257 /* MCP73 */
1258 PCI_VDEVICE(NVIDIA, 0x07fa),
1259 .driver_data = board_ahci_mcp73,
1260 }, {
1261 /* MCP73 */
1262 PCI_VDEVICE(NVIDIA, 0x07fb),
1263 .driver_data = board_ahci_mcp73,
1264 }, {
1265 /* MCP77 */
1266 PCI_VDEVICE(NVIDIA, 0x0ad0),
1267 .driver_data = board_ahci_mcp77,
1268 }, {
1269 /* MCP77 */
1270 PCI_VDEVICE(NVIDIA, 0x0ad1),
1271 .driver_data = board_ahci_mcp77,
1272 }, {
1273 /* MCP77 */
1274 PCI_VDEVICE(NVIDIA, 0x0ad2),
1275 .driver_data = board_ahci_mcp77,
1276 }, {
1277 /* MCP77 */
1278 PCI_VDEVICE(NVIDIA, 0x0ad3),
1279 .driver_data = board_ahci_mcp77,
1280 }, {
1281 /* MCP77 */
1282 PCI_VDEVICE(NVIDIA, 0x0ad4),
1283 .driver_data = board_ahci_mcp77,
1284 }, {
1285 /* MCP77 */
1286 PCI_VDEVICE(NVIDIA, 0x0ad5),
1287 .driver_data = board_ahci_mcp77,
1288 }, {
1289 /* MCP77 */
1290 PCI_VDEVICE(NVIDIA, 0x0ad6),
1291 .driver_data = board_ahci_mcp77,
1292 }, {
1293 /* MCP77 */
1294 PCI_VDEVICE(NVIDIA, 0x0ad7),
1295 .driver_data = board_ahci_mcp77,
1296 }, {
1297 /* MCP77 */
1298 PCI_VDEVICE(NVIDIA, 0x0ad8),
1299 .driver_data = board_ahci_mcp77,
1300 }, {
1301 /* MCP77 */
1302 PCI_VDEVICE(NVIDIA, 0x0ad9),
1303 .driver_data = board_ahci_mcp77,
1304 }, {
1305 /* MCP77 */
1306 PCI_VDEVICE(NVIDIA, 0x0ada),
1307 .driver_data = board_ahci_mcp77,
1308 }, {
1309 /* MCP77 */
1310 PCI_VDEVICE(NVIDIA, 0x0adb),
1311 .driver_data = board_ahci_mcp77,
1312 }, {
1313 /* MCP79 */
1314 PCI_VDEVICE(NVIDIA, 0x0ab4),
1315 .driver_data = board_ahci_mcp79,
1316 }, {
1317 /* MCP79 */
1318 PCI_VDEVICE(NVIDIA, 0x0ab5),
1319 .driver_data = board_ahci_mcp79,
1320 }, {
1321 /* MCP79 */
1322 PCI_VDEVICE(NVIDIA, 0x0ab6),
1323 .driver_data = board_ahci_mcp79,
1324 }, {
1325 /* MCP79 */
1326 PCI_VDEVICE(NVIDIA, 0x0ab7),
1327 .driver_data = board_ahci_mcp79,
1328 }, {
1329 /* MCP79 */
1330 PCI_VDEVICE(NVIDIA, 0x0ab8),
1331 .driver_data = board_ahci_mcp79,
1332 }, {
1333 /* MCP79 */
1334 PCI_VDEVICE(NVIDIA, 0x0ab9),
1335 .driver_data = board_ahci_mcp79,
1336 }, {
1337 /* MCP79 */
1338 PCI_VDEVICE(NVIDIA, 0x0aba),
1339 .driver_data = board_ahci_mcp79,
1340 }, {
1341 /* MCP79 */
1342 PCI_VDEVICE(NVIDIA, 0x0abb),
1343 .driver_data = board_ahci_mcp79,
1344 }, {
1345 /* MCP79 */
1346 PCI_VDEVICE(NVIDIA, 0x0abc),
1347 .driver_data = board_ahci_mcp79,
1348 }, {
1349 /* MCP79 */
1350 PCI_VDEVICE(NVIDIA, 0x0abd),
1351 .driver_data = board_ahci_mcp79,
1352 }, {
1353 /* MCP79 */
1354 PCI_VDEVICE(NVIDIA, 0x0abe),
1355 .driver_data = board_ahci_mcp79,
1356 }, {
1357 /* MCP79 */
1358 PCI_VDEVICE(NVIDIA, 0x0abf),
1359 .driver_data = board_ahci_mcp79,
1360 }, {
1361 /* MCP89 */
1362 PCI_VDEVICE(NVIDIA, 0x0d84),
1363 .driver_data = board_ahci_mcp89,
1364 }, {
1365 /* MCP89 */
1366 PCI_VDEVICE(NVIDIA, 0x0d85),
1367 .driver_data = board_ahci_mcp89,
1368 }, {
1369 /* MCP89 */
1370 PCI_VDEVICE(NVIDIA, 0x0d86),
1371 .driver_data = board_ahci_mcp89,
1372 }, {
1373 /* MCP89 */
1374 PCI_VDEVICE(NVIDIA, 0x0d87),
1375 .driver_data = board_ahci_mcp89,
1376 }, {
1377 /* MCP89 */
1378 PCI_VDEVICE(NVIDIA, 0x0d88),
1379 .driver_data = board_ahci_mcp89,
1380 }, {
1381 /* MCP89 */
1382 PCI_VDEVICE(NVIDIA, 0x0d89),
1383 .driver_data = board_ahci_mcp89,
1384 }, {
1385 /* MCP89 */
1386 PCI_VDEVICE(NVIDIA, 0x0d8a),
1387 .driver_data = board_ahci_mcp89,
1388 }, {
1389 /* MCP89 */
1390 PCI_VDEVICE(NVIDIA, 0x0d8b),
1391 .driver_data = board_ahci_mcp89,
1392 }, {
1393 /* MCP89 */
1394 PCI_VDEVICE(NVIDIA, 0x0d8c),
1395 .driver_data = board_ahci_mcp89,
1396 }, {
1397 /* MCP89 */
1398 PCI_VDEVICE(NVIDIA, 0x0d8d),
1399 .driver_data = board_ahci_mcp89,
1400 }, {
1401 /* MCP89 */
1402 PCI_VDEVICE(NVIDIA, 0x0d8e),
1403 .driver_data = board_ahci_mcp89,
1404 }, {
1405 /* MCP89 */
1406 PCI_VDEVICE(NVIDIA, 0x0d8f),
1407 .driver_data = board_ahci_mcp89,
1408 },
1409
1410 /* SiS */
1411 {
1412 /* SiS 966 */
1413 PCI_VDEVICE(SI, 0x1184),
1414 .driver_data = board_ahci,
1415 }, {
1416 /* SiS 968 */
1417 PCI_VDEVICE(SI, 0x1185),
1418 .driver_data = board_ahci,
1419 }, {
1420 /* SiS 968 */
1421 PCI_VDEVICE(SI, 0x0186),
1422 .driver_data = board_ahci,
1423 },
1424
1425 /* ST Microelectronics */
1426 {
1427 /* ST ConneXt */
1428 PCI_VDEVICE(STMICRO, 0xCC06),
1429 .driver_data = board_ahci,
1430 },
1431
1432 /* Marvell */
1433 {
1434 /* 6145 */
1435 PCI_VDEVICE(MARVELL, 0x6145),
1436 .driver_data = board_ahci_mv,
1437 }, {
1438 /* 6121 */
1439 PCI_VDEVICE(MARVELL, 0x6121),
1440 .driver_data = board_ahci_mv,
1441 }, {
1442 /* 88se9128 */
1443 PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
1444 .class = PCI_CLASS_STORAGE_SATA_AHCI,
1445 .class_mask = 0xffffff,
1446 .driver_data = board_ahci_yes_fbs,
1447 }, {
1448 /* 88se9125 */
1449 PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
1450 .driver_data = board_ahci_yes_fbs,
1451 }, {
1452 /* 88se9170 */
1453 PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
1454 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
1455 .driver_data = board_ahci_yes_fbs,
1456 }, {
1457 /* 88se9172 */
1458 PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
1459 .driver_data = board_ahci_yes_fbs,
1460 }, {
1461 /* 88se9182 */
1462 PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
1463 .driver_data = board_ahci_yes_fbs,
1464 }, {
1465 /* 88se9172 */
1466 PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
1467 .driver_data = board_ahci_yes_fbs,
1468 }, {
1469 /* 88se9172 on some Gigabyte */
1470 PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
1471 .driver_data = board_ahci_yes_fbs,
1472 }, {
1473 PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
1474 .driver_data = board_ahci_yes_fbs,
1475 }, {
1476 PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */
1477 .driver_data = board_ahci_yes_fbs,
1478 }, {
1479 PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
1480 .driver_data = board_ahci_yes_fbs,
1481 }, {
1482 PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9215),
1483 .driver_data = board_ahci_yes_fbs_atapi_dma,
1484 }, {
1485 PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
1486 .driver_data = board_ahci_yes_fbs,
1487 }, {
1488 PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9235),
1489 .driver_data = board_ahci_no_debounce_delay,
1490 },
1491
1492 /* TTI */
1493 {
1494 /* highpoint rocketraid 642L */
1495 PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642),
1496 .driver_data = board_ahci_yes_fbs,
1497 }, {
1498 /* highpoint rocketraid 644L */
1499 PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0645),
1500 .driver_data = board_ahci_yes_fbs,
1501 },
1502
1503 /* Promise */
1504 {
1505 /* PDC42819 */
1506 PCI_VDEVICE(PROMISE, 0x3f20),
1507 .driver_data = board_ahci,
1508 }, {
1509 /* FastTrak TX8660 ahci-mode */
1510 PCI_VDEVICE(PROMISE, 0x3781),
1511 .driver_data = board_ahci,
1512 },
1513
1514 /* ASMedia */
1515 {
1516 /* ASM1060 */
1517 PCI_VDEVICE(ASMEDIA, 0x0601),
1518 .driver_data = board_ahci_43bit_dma,
1519 }, {
1520 /* ASM1060 */
1521 PCI_VDEVICE(ASMEDIA, 0x0602),
1522 .driver_data = board_ahci_43bit_dma,
1523 }, {
1524 /* ASM1061 */
1525 PCI_VDEVICE(ASMEDIA, 0x0611),
1526 .driver_data = board_ahci_43bit_dma,
1527 }, {
1528 /* ASM1061/1062 */
1529 PCI_VDEVICE(ASMEDIA, 0x0612),
1530 .driver_data = board_ahci_43bit_dma,
1531 }, {
1532 /* ASM1061R */
1533 PCI_VDEVICE(ASMEDIA, 0x0621),
1534 .driver_data = board_ahci_43bit_dma,
1535 }, {
1536 /* ASM1062R */
1537 PCI_VDEVICE(ASMEDIA, 0x0622),
1538 .driver_data = board_ahci_43bit_dma,
1539 }, {
1540 /* ASM1062+JMB575 */
1541 PCI_VDEVICE(ASMEDIA, 0x0624),
1542 .driver_data = board_ahci_43bit_dma,
1543 }, {
1544 /* ASM1062A */
1545 PCI_VDEVICE(ASMEDIA, 0x1062),
1546 .driver_data = board_ahci,
1547 }, {
1548 /* ASM1064 */
1549 PCI_VDEVICE(ASMEDIA, 0x1064),
1550 .driver_data = board_ahci,
1551 }, {
1552 /* ASM1164 */
1553 PCI_VDEVICE(ASMEDIA, 0x1164),
1554 .driver_data = board_ahci,
1555 }, {
1556 /* ASM1165 */
1557 PCI_VDEVICE(ASMEDIA, 0x1165),
1558 .driver_data = board_ahci,
1559 }, {
1560 /* ASM1166 */
1561 PCI_VDEVICE(ASMEDIA, 0x1166),
1562 .driver_data = board_ahci,
1563 }, {
1564 /*
1565 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
1566 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
1567 */
1568 PCI_VDEVICE(SAMSUNG, 0x1600),
1569 .driver_data = board_ahci_no_msi,
1570
1571 }, {
1572 PCI_VDEVICE(SAMSUNG, 0xa800),
1573 .driver_data = board_ahci_no_msi,
1574 }, {
1575 /* Enmotus */
1576 PCI_DEVICE(0x1c44, 0x8000),
1577 .driver_data = board_ahci,
1578 }, {
1579 /* Loongson */
1580 PCI_VDEVICE(LOONGSON, 0x7a08),
1581 .driver_data = board_ahci,
1582
1583 }, {
1584 /* Generic, PCI class code for AHCI */
1585 PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff),
1586 .driver_data = board_ahci,
1587 },
1588
1589 { } /* terminate list */
1590 };
1591
1592 static const struct dev_pm_ops ahci_pci_pm_ops = {
1593 SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume)
1594 SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend,
1595 ahci_pci_device_runtime_resume, NULL)
1596 };
1597
1598 static struct pci_driver ahci_pci_driver = {
1599 .name = DRV_NAME,
1600 .id_table = ahci_pci_tbl,
1601 .probe = ahci_init_one,
1602 .remove = ahci_remove_one,
1603 .shutdown = ahci_shutdown_one,
1604 .driver = {
1605 .pm = &ahci_pci_pm_ops,
1606 },
1607 };
1608
1609 #if IS_ENABLED(CONFIG_PATA_MARVELL)
1610 static int marvell_enable;
1611 #else
1612 static int marvell_enable = 1;
1613 #endif
1614 module_param(marvell_enable, int, 0644);
1615 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
1616
1617 static int mobile_lpm_policy = -1;
1618 module_param(mobile_lpm_policy, int, 0644);
1619 MODULE_PARM_DESC(mobile_lpm_policy,
1620 "Default LPM policy. Despite its name, this parameter applies "
1621 "to all chipsets, including desktop and server chipsets");
1622
1623 static char *ahci_mask_port_map;
1624 module_param_named(mask_port_map, ahci_mask_port_map, charp, 0444);
1625 MODULE_PARM_DESC(mask_port_map,
1626 "32-bits port map masks to ignore controllers ports. "
1627 "Valid values are: "
1628 "\"<mask>\" to apply the same mask to all AHCI controller "
1629 "devices, and \"<pci_dev>=<mask>,<pci_dev>=<mask>,...\" to "
1630 "specify different masks for the controllers specified, "
1631 "where <pci_dev> is the PCI ID of an AHCI controller in the "
1632 "form \"domain:bus:dev.func\"");
1633
1634 static char *ahci_mask_port_ext;
1635 module_param_named(mask_port_ext, ahci_mask_port_ext, charp, 0444);
1636 MODULE_PARM_DESC(mask_port_ext,
1637 "32-bits mask to ignore the external/hotplug capability of ports. "
1638 "Valid values are: "
1639 "\"<mask>\" to apply the same mask to all AHCI controller "
1640 "devices, and \"<pci_dev>=<mask>,<pci_dev>=<mask>,...\" to "
1641 "specify different masks for the controllers specified, "
1642 "where <pci_dev> is the PCI ID of an AHCI controller in the "
1643 "form \"domain:bus:dev.func\"");
1644
ahci_port_mask(struct device * dev,char * mask_s)1645 static u32 ahci_port_mask(struct device *dev, char *mask_s)
1646 {
1647 unsigned int mask;
1648
1649 if (kstrtouint(mask_s, 0, &mask)) {
1650 dev_err(dev, "Invalid port map mask\n");
1651 return 0;
1652 }
1653
1654 return mask;
1655 }
1656
ahci_get_port_mask(struct device * dev,char * mask_p)1657 static u32 ahci_get_port_mask(struct device *dev, char *mask_p)
1658 {
1659 char *param, *end, *str, *mask_s;
1660 char *name;
1661 u32 mask = 0;
1662
1663 if (!mask_p || !strlen(mask_p))
1664 return 0;
1665
1666 str = kstrdup(mask_p, GFP_KERNEL);
1667 if (!str)
1668 return 0;
1669
1670 /* Handle single mask case */
1671 if (!strchr(str, '=')) {
1672 mask = ahci_port_mask(dev, str);
1673 goto free;
1674 }
1675
1676 /*
1677 * Mask list case: parse the parameter to get the mask only if
1678 * the device name matches.
1679 */
1680 param = str;
1681 end = param + strlen(param);
1682 while (param && param < end && *param) {
1683 name = param;
1684 param = strchr(name, '=');
1685 if (!param)
1686 break;
1687
1688 *param = '\0';
1689 param++;
1690 if (param >= end)
1691 break;
1692
1693 if (strcmp(dev_name(dev), name) != 0) {
1694 param = strchr(param, ',');
1695 if (param)
1696 param++;
1697 continue;
1698 }
1699
1700 mask_s = param;
1701 param = strchr(mask_s, ',');
1702 if (param) {
1703 *param = '\0';
1704 param++;
1705 }
1706
1707 mask = ahci_port_mask(dev, mask_s);
1708 }
1709
1710 free:
1711 kfree(str);
1712
1713 return mask;
1714 }
1715
ahci_pci_save_initial_config(struct pci_dev * pdev,struct ahci_host_priv * hpriv)1716 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
1717 struct ahci_host_priv *hpriv)
1718 {
1719 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
1720 dev_info(&pdev->dev, "JMB361 has only one port\n");
1721 hpriv->saved_port_map = 1;
1722 }
1723
1724 /*
1725 * Temporary Marvell 6145 hack: PATA port presence
1726 * is asserted through the standard AHCI port
1727 * presence register, as bit 4 (counting from 0)
1728 */
1729 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
1730 if (pdev->device == 0x6121)
1731 hpriv->mask_port_map = 0x3;
1732 else
1733 hpriv->mask_port_map = 0xf;
1734 dev_info(&pdev->dev,
1735 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
1736 }
1737
1738 /* Handle port map masks passed as module parameter. */
1739 hpriv->mask_port_map =
1740 ahci_get_port_mask(&pdev->dev, ahci_mask_port_map);
1741 hpriv->mask_port_ext =
1742 ahci_get_port_mask(&pdev->dev, ahci_mask_port_ext);
1743
1744 ahci_save_initial_config(&pdev->dev, hpriv);
1745 }
1746
ahci_pci_reset_controller(struct ata_host * host)1747 static int ahci_pci_reset_controller(struct ata_host *host)
1748 {
1749 struct pci_dev *pdev = to_pci_dev(host->dev);
1750 struct ahci_host_priv *hpriv = host->private_data;
1751 int rc;
1752
1753 rc = ahci_reset_controller(host);
1754 if (rc)
1755 return rc;
1756
1757 /*
1758 * If platform firmware failed to enable ports, try to enable
1759 * them here.
1760 */
1761 ahci_intel_pcs_quirk(pdev, hpriv);
1762
1763 return 0;
1764 }
1765
ahci_pci_init_controller(struct ata_host * host)1766 static void ahci_pci_init_controller(struct ata_host *host)
1767 {
1768 struct ahci_host_priv *hpriv = host->private_data;
1769 struct pci_dev *pdev = to_pci_dev(host->dev);
1770 void __iomem *port_mmio;
1771 u32 tmp;
1772 int mv;
1773
1774 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
1775 if (pdev->device == 0x6121)
1776 mv = 2;
1777 else
1778 mv = 4;
1779 port_mmio = __ahci_port_base(hpriv, mv);
1780
1781 writel(0, port_mmio + PORT_IRQ_MASK);
1782
1783 /* clear port IRQ */
1784 tmp = readl(port_mmio + PORT_IRQ_STAT);
1785 dev_dbg(&pdev->dev, "PORT_IRQ_STAT 0x%x\n", tmp);
1786 if (tmp)
1787 writel(tmp, port_mmio + PORT_IRQ_STAT);
1788 }
1789
1790 ahci_init_controller(host);
1791 }
1792
ahci_vt8251_hardreset(struct ata_link * link,unsigned int * class,unsigned long deadline)1793 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
1794 unsigned long deadline)
1795 {
1796 struct ata_port *ap = link->ap;
1797 struct ahci_host_priv *hpriv = ap->host->private_data;
1798 bool online;
1799 int rc;
1800
1801 hpriv->stop_engine(ap);
1802
1803 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
1804 deadline, &online, NULL);
1805
1806 hpriv->start_engine(ap);
1807
1808 /* vt8251 doesn't clear BSY on signature FIS reception,
1809 * request follow-up softreset.
1810 */
1811 return online ? -EAGAIN : rc;
1812 }
1813
ahci_p5wdh_hardreset(struct ata_link * link,unsigned int * class,unsigned long deadline)1814 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
1815 unsigned long deadline)
1816 {
1817 struct ata_port *ap = link->ap;
1818 struct ahci_port_priv *pp = ap->private_data;
1819 struct ahci_host_priv *hpriv = ap->host->private_data;
1820 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1821 struct ata_taskfile tf;
1822 bool online;
1823 int rc;
1824
1825 hpriv->stop_engine(ap);
1826
1827 /* clear D2H reception area to properly wait for D2H FIS */
1828 ata_tf_init(link->device, &tf);
1829 tf.status = ATA_BUSY;
1830 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1831
1832 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
1833 deadline, &online, NULL);
1834
1835 hpriv->start_engine(ap);
1836
1837 /* The pseudo configuration device on SIMG4726 attached to
1838 * ASUS P5W-DH Deluxe doesn't send signature FIS after
1839 * hardreset if no device is attached to the first downstream
1840 * port && the pseudo device locks up on SRST w/ PMP==0. To
1841 * work around this, wait for !BSY only briefly. If BSY isn't
1842 * cleared, perform CLO and proceed to IDENTIFY (achieved by
1843 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
1844 *
1845 * Wait for two seconds. Devices attached to downstream port
1846 * which can't process the following IDENTIFY after this will
1847 * have to be reset again. For most cases, this should
1848 * suffice while making probing snappish enough.
1849 */
1850 if (online) {
1851 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
1852 ahci_check_ready);
1853 if (rc)
1854 ahci_kick_engine(ap);
1855 }
1856 return rc;
1857 }
1858
1859 /*
1860 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports.
1861 *
1862 * It has been observed with some SSDs that the timing of events in the
1863 * link synchronization phase can leave the port in a state that can not
1864 * be recovered by a SATA-hard-reset alone. The failing signature is
1865 * SStatus.DET stuck at 1 ("Device presence detected but Phy
1866 * communication not established"). It was found that unloading and
1867 * reloading the driver when this problem occurs allows the drive
1868 * connection to be recovered (DET advanced to 0x3). The critical
1869 * component of reloading the driver is that the port state machines are
1870 * reset by bouncing "port enable" in the AHCI PCS configuration
1871 * register. So, reproduce that effect by bouncing a port whenever we
1872 * see DET==1 after a reset.
1873 */
ahci_avn_hardreset(struct ata_link * link,unsigned int * class,unsigned long deadline)1874 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
1875 unsigned long deadline)
1876 {
1877 const unsigned int *timing = sata_ehc_deb_timing(&link->eh_context);
1878 struct ata_port *ap = link->ap;
1879 struct ahci_port_priv *pp = ap->private_data;
1880 struct ahci_host_priv *hpriv = ap->host->private_data;
1881 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1882 unsigned long tmo = deadline - jiffies;
1883 struct ata_taskfile tf;
1884 bool online;
1885 int rc, i;
1886
1887 hpriv->stop_engine(ap);
1888
1889 for (i = 0; i < 2; i++) {
1890 u16 val;
1891 u32 sstatus;
1892 int port = ap->port_no;
1893 struct ata_host *host = ap->host;
1894 struct pci_dev *pdev = to_pci_dev(host->dev);
1895
1896 /* clear D2H reception area to properly wait for D2H FIS */
1897 ata_tf_init(link->device, &tf);
1898 tf.status = ATA_BUSY;
1899 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1900
1901 rc = sata_link_hardreset(link, timing, deadline, &online,
1902 ahci_check_ready);
1903
1904 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 ||
1905 (sstatus & 0xf) != 1)
1906 break;
1907
1908 ata_link_info(link, "avn bounce port%d\n", port);
1909
1910 pci_read_config_word(pdev, 0x92, &val);
1911 val &= ~(1 << port);
1912 pci_write_config_word(pdev, 0x92, val);
1913 ata_msleep(ap, 1000);
1914 val |= 1 << port;
1915 pci_write_config_word(pdev, 0x92, val);
1916 deadline += tmo;
1917 }
1918
1919 hpriv->start_engine(ap);
1920
1921 if (online)
1922 *class = ahci_dev_classify(ap);
1923
1924 return rc;
1925 }
1926
1927
1928 #ifdef CONFIG_PM
ahci_pci_disable_interrupts(struct ata_host * host)1929 static void ahci_pci_disable_interrupts(struct ata_host *host)
1930 {
1931 struct ahci_host_priv *hpriv = host->private_data;
1932 void __iomem *mmio = hpriv->mmio;
1933 u32 ctl;
1934
1935 /* AHCI spec rev1.1 section 8.3.3:
1936 * Software must disable interrupts prior to requesting a
1937 * transition of the HBA to D3 state.
1938 */
1939 ctl = readl(mmio + HOST_CTL);
1940 ctl &= ~HOST_IRQ_EN;
1941 writel(ctl, mmio + HOST_CTL);
1942 readl(mmio + HOST_CTL); /* flush */
1943 }
1944
ahci_pci_device_runtime_suspend(struct device * dev)1945 static int ahci_pci_device_runtime_suspend(struct device *dev)
1946 {
1947 struct pci_dev *pdev = to_pci_dev(dev);
1948 struct ata_host *host = pci_get_drvdata(pdev);
1949
1950 ahci_pci_disable_interrupts(host);
1951 return 0;
1952 }
1953
ahci_pci_device_runtime_resume(struct device * dev)1954 static int ahci_pci_device_runtime_resume(struct device *dev)
1955 {
1956 struct pci_dev *pdev = to_pci_dev(dev);
1957 struct ata_host *host = pci_get_drvdata(pdev);
1958 int rc;
1959
1960 rc = ahci_pci_reset_controller(host);
1961 if (rc)
1962 return rc;
1963 ahci_pci_init_controller(host);
1964 return 0;
1965 }
1966
1967 #ifdef CONFIG_PM_SLEEP
ahci_pci_device_suspend(struct device * dev)1968 static int ahci_pci_device_suspend(struct device *dev)
1969 {
1970 struct pci_dev *pdev = to_pci_dev(dev);
1971 struct ata_host *host = pci_get_drvdata(pdev);
1972 struct ahci_host_priv *hpriv = host->private_data;
1973
1974 if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
1975 dev_err(&pdev->dev,
1976 "BIOS update required for suspend/resume\n");
1977 return -EIO;
1978 }
1979
1980 ahci_pci_disable_interrupts(host);
1981 ata_host_suspend(host, PMSG_SUSPEND);
1982 return 0;
1983 }
1984
ahci_pci_device_resume(struct device * dev)1985 static int ahci_pci_device_resume(struct device *dev)
1986 {
1987 struct pci_dev *pdev = to_pci_dev(dev);
1988 struct ata_host *host = pci_get_drvdata(pdev);
1989 int rc;
1990
1991 /* Apple BIOS helpfully mangles the registers on resume */
1992 if (is_mcp89_apple(pdev))
1993 ahci_mcp89_apple_enable(pdev);
1994
1995 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
1996 rc = ahci_pci_reset_controller(host);
1997 if (rc)
1998 return rc;
1999
2000 ahci_pci_init_controller(host);
2001 }
2002
2003 ata_host_resume(host);
2004
2005 return 0;
2006 }
2007 #endif
2008
2009 #endif /* CONFIG_PM */
2010
ahci_configure_dma_masks(struct pci_dev * pdev,struct ahci_host_priv * hpriv)2011 static int ahci_configure_dma_masks(struct pci_dev *pdev,
2012 struct ahci_host_priv *hpriv)
2013 {
2014 int dma_bits;
2015 int rc;
2016
2017 if (hpriv->cap & HOST_CAP_64) {
2018 dma_bits = 64;
2019 if (hpriv->flags & AHCI_HFLAG_43BIT_ONLY)
2020 dma_bits = 43;
2021 } else {
2022 dma_bits = 32;
2023 }
2024
2025 /*
2026 * If the device fixup already set the dma_mask to some non-standard
2027 * value, don't extend it here. This happens on STA2X11, for example.
2028 *
2029 * XXX: manipulating the DMA mask from platform code is completely
2030 * bogus, platform code should use dev->bus_dma_limit instead..
2031 */
2032 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
2033 return 0;
2034
2035 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(dma_bits));
2036 if (rc)
2037 dev_err(&pdev->dev, "DMA enable failed\n");
2038 return rc;
2039 }
2040
ahci_pci_print_info(struct ata_host * host)2041 static void ahci_pci_print_info(struct ata_host *host)
2042 {
2043 struct pci_dev *pdev = to_pci_dev(host->dev);
2044 u16 cc;
2045 const char *scc_s;
2046
2047 pci_read_config_word(pdev, 0x0a, &cc);
2048 if (cc == PCI_CLASS_STORAGE_IDE)
2049 scc_s = "IDE";
2050 else if (cc == PCI_CLASS_STORAGE_SATA)
2051 scc_s = "SATA";
2052 else if (cc == PCI_CLASS_STORAGE_RAID)
2053 scc_s = "RAID";
2054 else
2055 scc_s = "unknown";
2056
2057 ahci_print_info(host, scc_s);
2058 }
2059
2060 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
2061 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
2062 * support PMP and the 4726 either directly exports the device
2063 * attached to the first downstream port or acts as a hardware storage
2064 * controller and emulate a single ATA device (can be RAID 0/1 or some
2065 * other configuration).
2066 *
2067 * When there's no device attached to the first downstream port of the
2068 * 4726, "Config Disk" appears, which is a pseudo ATA device to
2069 * configure the 4726. However, ATA emulation of the device is very
2070 * lame. It doesn't send signature D2H Reg FIS after the initial
2071 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
2072 *
2073 * The following function works around the problem by always using
2074 * hardreset on the port and not depending on receiving signature FIS
2075 * afterward. If signature FIS isn't received soon, ATA class is
2076 * assumed without follow-up softreset.
2077 */
ahci_p5wdh_workaround(struct ata_host * host)2078 static void ahci_p5wdh_workaround(struct ata_host *host)
2079 {
2080 static const struct dmi_system_id sysids[] = {
2081 {
2082 .ident = "P5W DH Deluxe",
2083 .matches = {
2084 DMI_MATCH(DMI_SYS_VENDOR,
2085 "ASUSTEK COMPUTER INC"),
2086 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
2087 },
2088 },
2089 { }
2090 };
2091 struct pci_dev *pdev = to_pci_dev(host->dev);
2092
2093 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
2094 dmi_check_system(sysids)) {
2095 struct ata_port *ap = host->ports[1];
2096
2097 dev_info(&pdev->dev,
2098 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
2099
2100 ap->ops = &ahci_p5wdh_ops;
2101 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
2102 }
2103 }
2104
2105 /*
2106 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
2107 * booting in BIOS compatibility mode. We restore the registers but not ID.
2108 */
ahci_mcp89_apple_enable(struct pci_dev * pdev)2109 static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
2110 {
2111 u32 val;
2112
2113 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
2114
2115 pci_read_config_dword(pdev, 0xf8, &val);
2116 val |= 1 << 0x1b;
2117 /* the following changes the device ID, but appears not to affect function */
2118 /* val = (val & ~0xf0000000) | 0x80000000; */
2119 pci_write_config_dword(pdev, 0xf8, val);
2120
2121 pci_read_config_dword(pdev, 0x54c, &val);
2122 val |= 1 << 0xc;
2123 pci_write_config_dword(pdev, 0x54c, val);
2124
2125 pci_read_config_dword(pdev, 0x4a4, &val);
2126 val &= 0xff;
2127 val |= 0x01060100;
2128 pci_write_config_dword(pdev, 0x4a4, val);
2129
2130 pci_read_config_dword(pdev, 0x54c, &val);
2131 val &= ~(1 << 0xc);
2132 pci_write_config_dword(pdev, 0x54c, val);
2133
2134 pci_read_config_dword(pdev, 0xf8, &val);
2135 val &= ~(1 << 0x1b);
2136 pci_write_config_dword(pdev, 0xf8, val);
2137 }
2138
is_mcp89_apple(struct pci_dev * pdev)2139 static bool is_mcp89_apple(struct pci_dev *pdev)
2140 {
2141 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
2142 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
2143 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
2144 pdev->subsystem_device == 0xcb89;
2145 }
2146
2147 /* only some SB600 ahci controllers can do 64bit DMA */
ahci_sb600_enable_64bit(struct pci_dev * pdev)2148 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
2149 {
2150 static const struct dmi_system_id sysids[] = {
2151 /*
2152 * The oldest version known to be broken is 0901 and
2153 * working is 1501 which was released on 2007-10-26.
2154 * Enable 64bit DMA on 1501 and anything newer.
2155 *
2156 * Please read bko#9412 for more info.
2157 */
2158 {
2159 .ident = "ASUS M2A-VM",
2160 .matches = {
2161 DMI_MATCH(DMI_BOARD_VENDOR,
2162 "ASUSTeK Computer INC."),
2163 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
2164 },
2165 .driver_data = "20071026", /* yyyymmdd */
2166 },
2167 /*
2168 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
2169 * support 64bit DMA.
2170 *
2171 * BIOS versions earlier than 1.5 had the Manufacturer DMI
2172 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
2173 * This spelling mistake was fixed in BIOS version 1.5, so
2174 * 1.5 and later have the Manufacturer as
2175 * "MICRO-STAR INTERNATIONAL CO.,LTD".
2176 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
2177 *
2178 * BIOS versions earlier than 1.9 had a Board Product Name
2179 * DMI field of "MS-7376". This was changed to be
2180 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
2181 * match on DMI_BOARD_NAME of "MS-7376".
2182 */
2183 {
2184 .ident = "MSI K9A2 Platinum",
2185 .matches = {
2186 DMI_MATCH(DMI_BOARD_VENDOR,
2187 "MICRO-STAR INTER"),
2188 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
2189 },
2190 },
2191 /*
2192 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
2193 * 64bit DMA.
2194 *
2195 * This board also had the typo mentioned above in the
2196 * Manufacturer DMI field (fixed in BIOS version 1.5), so
2197 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
2198 */
2199 {
2200 .ident = "MSI K9AGM2",
2201 .matches = {
2202 DMI_MATCH(DMI_BOARD_VENDOR,
2203 "MICRO-STAR INTER"),
2204 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
2205 },
2206 },
2207 /*
2208 * All BIOS versions for the Asus M3A support 64bit DMA.
2209 * (all release versions from 0301 to 1206 were tested)
2210 */
2211 {
2212 .ident = "ASUS M3A",
2213 .matches = {
2214 DMI_MATCH(DMI_BOARD_VENDOR,
2215 "ASUSTeK Computer INC."),
2216 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
2217 },
2218 },
2219 { }
2220 };
2221 const struct dmi_system_id *match;
2222 int year, month, date;
2223 char buf[9];
2224
2225 match = dmi_first_match(sysids);
2226 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
2227 !match)
2228 return false;
2229
2230 if (!match->driver_data)
2231 goto enable_64bit;
2232
2233 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
2234 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
2235
2236 if (strcmp(buf, match->driver_data) >= 0)
2237 goto enable_64bit;
2238 else {
2239 dev_warn(&pdev->dev,
2240 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
2241 match->ident);
2242 return false;
2243 }
2244
2245 enable_64bit:
2246 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
2247 return true;
2248 }
2249
ahci_broken_system_poweroff(struct pci_dev * pdev)2250 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
2251 {
2252 static const struct dmi_system_id broken_systems[] = {
2253 {
2254 .ident = "HP Compaq nx6310",
2255 .matches = {
2256 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
2257 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
2258 },
2259 /* PCI slot number of the controller */
2260 .driver_data = (void *)0x1FUL,
2261 },
2262 {
2263 .ident = "HP Compaq 6720s",
2264 .matches = {
2265 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
2266 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
2267 },
2268 /* PCI slot number of the controller */
2269 .driver_data = (void *)0x1FUL,
2270 },
2271
2272 { } /* terminate list */
2273 };
2274 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
2275
2276 if (dmi) {
2277 unsigned long slot = (unsigned long)dmi->driver_data;
2278 /* apply the quirk only to on-board controllers */
2279 return slot == PCI_SLOT(pdev->devfn);
2280 }
2281
2282 return false;
2283 }
2284
ahci_broken_suspend(struct pci_dev * pdev)2285 static bool ahci_broken_suspend(struct pci_dev *pdev)
2286 {
2287 static const struct dmi_system_id sysids[] = {
2288 /*
2289 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
2290 * to the harddisk doesn't become online after
2291 * resuming from STR. Warn and fail suspend.
2292 *
2293 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
2294 *
2295 * Use dates instead of versions to match as HP is
2296 * apparently recycling both product and version
2297 * strings.
2298 *
2299 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
2300 */
2301 {
2302 .ident = "dv4",
2303 .matches = {
2304 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
2305 DMI_MATCH(DMI_PRODUCT_NAME,
2306 "HP Pavilion dv4 Notebook PC"),
2307 },
2308 .driver_data = "20090105", /* F.30 */
2309 },
2310 {
2311 .ident = "dv5",
2312 .matches = {
2313 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
2314 DMI_MATCH(DMI_PRODUCT_NAME,
2315 "HP Pavilion dv5 Notebook PC"),
2316 },
2317 .driver_data = "20090506", /* F.16 */
2318 },
2319 {
2320 .ident = "dv6",
2321 .matches = {
2322 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
2323 DMI_MATCH(DMI_PRODUCT_NAME,
2324 "HP Pavilion dv6 Notebook PC"),
2325 },
2326 .driver_data = "20090423", /* F.21 */
2327 },
2328 {
2329 .ident = "HDX18",
2330 .matches = {
2331 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
2332 DMI_MATCH(DMI_PRODUCT_NAME,
2333 "HP HDX18 Notebook PC"),
2334 },
2335 .driver_data = "20090430", /* F.23 */
2336 },
2337 /*
2338 * Acer eMachines G725 has the same problem. BIOS
2339 * V1.03 is known to be broken. V3.04 is known to
2340 * work. Between, there are V1.06, V2.06 and V3.03
2341 * that we don't have much idea about. For now,
2342 * assume that anything older than V3.04 is broken.
2343 *
2344 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
2345 */
2346 {
2347 .ident = "G725",
2348 .matches = {
2349 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
2350 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
2351 },
2352 .driver_data = "20091216", /* V3.04 */
2353 },
2354 { } /* terminate list */
2355 };
2356 const struct dmi_system_id *dmi = dmi_first_match(sysids);
2357 int year, month, date;
2358 char buf[9];
2359
2360 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
2361 return false;
2362
2363 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
2364 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
2365
2366 return strcmp(buf, dmi->driver_data) < 0;
2367 }
2368
ahci_broken_lpm(struct pci_dev * pdev)2369 static bool ahci_broken_lpm(struct pci_dev *pdev)
2370 {
2371 /*
2372 * Platforms with LPM problems.
2373 * If driver_data is NULL, there is no existing BIOS version with
2374 * functioning LPM.
2375 * If driver_data is non-NULL, then driver_data contains the DMI BIOS
2376 * build date of the first BIOS version with functioning LPM (i.e. older
2377 * BIOS versions have broken LPM).
2378 */
2379 static const struct dmi_system_id sysids[] = {
2380 {
2381 .matches = {
2382 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
2383 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X250"),
2384 },
2385 .driver_data = "20180406", /* 1.31 */
2386 },
2387 {
2388 .matches = {
2389 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
2390 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad L450"),
2391 },
2392 .driver_data = "20180420", /* 1.28 */
2393 },
2394 {
2395 .matches = {
2396 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
2397 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T450s"),
2398 },
2399 .driver_data = "20180315", /* 1.33 */
2400 },
2401 {
2402 .matches = {
2403 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
2404 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad W541"),
2405 },
2406 .driver_data = "20180409", /* 2.35 */
2407 },
2408 {
2409 .matches = {
2410 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
2411 DMI_MATCH(DMI_PRODUCT_NAME, "ASUSPRO D840MB_M840SA"),
2412 },
2413 /* 320 is broken, there is no known good version. */
2414 },
2415 {
2416 /*
2417 * AMD 500 Series Chipset SATA Controller [1022:43eb]
2418 * on this motherboard timeouts on ports 5 and 6 when
2419 * LPM is enabled, at least with WDC WD20EFAX-68FB5N0
2420 * hard drives. LPM with the same drive works fine on
2421 * all other ports on the same controller.
2422 */
2423 .matches = {
2424 DMI_MATCH(DMI_BOARD_VENDOR,
2425 "ASUSTeK COMPUTER INC."),
2426 DMI_MATCH(DMI_BOARD_NAME,
2427 "ROG STRIX B550-F GAMING (WI-FI)"),
2428 },
2429 /* 3621 is broken, there is no known good version. */
2430 },
2431 { } /* terminate list */
2432 };
2433 const struct dmi_system_id *dmi = dmi_first_match(sysids);
2434 int year, month, date;
2435 char buf[9];
2436
2437 if (!dmi)
2438 return false;
2439
2440 if (!dmi->driver_data)
2441 return true;
2442
2443 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
2444 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
2445
2446 return strcmp(buf, dmi->driver_data) < 0;
2447 }
2448
ahci_broken_online(struct pci_dev * pdev)2449 static bool ahci_broken_online(struct pci_dev *pdev)
2450 {
2451 #define ENCODE_BUSDEVFN(bus, slot, func) \
2452 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
2453 static const struct dmi_system_id sysids[] = {
2454 /*
2455 * There are several gigabyte boards which use
2456 * SIMG5723s configured as hardware RAID. Certain
2457 * 5723 firmware revisions shipped there keep the link
2458 * online but fail to answer properly to SRST or
2459 * IDENTIFY when no device is attached downstream
2460 * causing libata to retry quite a few times leading
2461 * to excessive detection delay.
2462 *
2463 * As these firmwares respond to the second reset try
2464 * with invalid device signature, considering unknown
2465 * sig as offline works around the problem acceptably.
2466 */
2467 {
2468 .ident = "EP45-DQ6",
2469 .matches = {
2470 DMI_MATCH(DMI_BOARD_VENDOR,
2471 "Gigabyte Technology Co., Ltd."),
2472 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
2473 },
2474 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
2475 },
2476 {
2477 .ident = "EP45-DS5",
2478 .matches = {
2479 DMI_MATCH(DMI_BOARD_VENDOR,
2480 "Gigabyte Technology Co., Ltd."),
2481 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
2482 },
2483 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
2484 },
2485 { } /* terminate list */
2486 };
2487 #undef ENCODE_BUSDEVFN
2488 const struct dmi_system_id *dmi = dmi_first_match(sysids);
2489 unsigned int val;
2490
2491 if (!dmi)
2492 return false;
2493
2494 val = (unsigned long)dmi->driver_data;
2495
2496 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
2497 }
2498
2499 #ifdef CONFIG_ATA_ACPI
ahci_gtf_filter_workaround(struct ata_host * host)2500 static void ahci_gtf_filter_workaround(struct ata_host *host)
2501 {
2502 static const struct dmi_system_id sysids[] = {
2503 /*
2504 * Aspire 3810T issues a bunch of SATA enable commands
2505 * via _GTF including an invalid one and one which is
2506 * rejected by the device. Among the successful ones
2507 * is FPDMA non-zero offset enable which when enabled
2508 * only on the drive side leads to NCQ command
2509 * failures. Filter it out.
2510 */
2511 {
2512 .ident = "Aspire 3810T",
2513 .matches = {
2514 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
2515 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
2516 },
2517 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
2518 },
2519 { }
2520 };
2521 const struct dmi_system_id *dmi = dmi_first_match(sysids);
2522 unsigned int filter;
2523 int i;
2524
2525 if (!dmi)
2526 return;
2527
2528 filter = (unsigned long)dmi->driver_data;
2529 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
2530 filter, dmi->ident);
2531
2532 for (i = 0; i < host->n_ports; i++) {
2533 struct ata_port *ap = host->ports[i];
2534 struct ata_link *link;
2535 struct ata_device *dev;
2536
2537 ata_for_each_link(link, ap, EDGE)
2538 ata_for_each_dev(dev, link, ALL)
2539 dev->gtf_filter |= filter;
2540 }
2541 }
2542 #else
ahci_gtf_filter_workaround(struct ata_host * host)2543 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
2544 {}
2545 #endif
2546
2547 /*
2548 * On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected
2549 * as DUMMY, or detected but eventually get a "link down" and never get up
2550 * again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the
2551 * port_map may hold a value of 0x00.
2552 *
2553 * Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports
2554 * and can significantly reduce the occurrence of the problem.
2555 *
2556 * https://bugzilla.kernel.org/show_bug.cgi?id=189471
2557 */
acer_sa5_271_workaround(struct ahci_host_priv * hpriv,struct pci_dev * pdev)2558 static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv,
2559 struct pci_dev *pdev)
2560 {
2561 static const struct dmi_system_id sysids[] = {
2562 {
2563 .ident = "Acer Switch Alpha 12",
2564 .matches = {
2565 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
2566 DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271")
2567 },
2568 },
2569 { }
2570 };
2571
2572 if (dmi_check_system(sysids)) {
2573 dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n");
2574 if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) {
2575 hpriv->port_map = 0x7;
2576 hpriv->cap = 0xC734FF02;
2577 }
2578 }
2579 }
2580
2581 #ifdef CONFIG_ARM64
2582 /*
2583 * Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently.
2584 * Workaround is to make sure all pending IRQs are served before leaving
2585 * handler.
2586 */
ahci_thunderx_irq_handler(int irq,void * dev_instance)2587 static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance)
2588 {
2589 struct ata_host *host = dev_instance;
2590 struct ahci_host_priv *hpriv;
2591 unsigned int rc = 0;
2592 void __iomem *mmio;
2593 u32 irq_stat, irq_masked;
2594 unsigned int handled = 1;
2595
2596 hpriv = host->private_data;
2597 mmio = hpriv->mmio;
2598 irq_stat = readl(mmio + HOST_IRQ_STAT);
2599 if (!irq_stat)
2600 return IRQ_NONE;
2601
2602 do {
2603 irq_masked = irq_stat & hpriv->port_map;
2604 spin_lock(&host->lock);
2605 rc = ahci_handle_port_intr(host, irq_masked);
2606 if (!rc)
2607 handled = 0;
2608 writel(irq_stat, mmio + HOST_IRQ_STAT);
2609 irq_stat = readl(mmio + HOST_IRQ_STAT);
2610 spin_unlock(&host->lock);
2611 } while (irq_stat);
2612
2613 return IRQ_RETVAL(handled);
2614 }
2615 #endif
2616
2617 /*
2618 * The Marvell 88SE6111/6121/6145 ("Thor") family stops reporting interrupts
2619 * for a port when HOST_IRQ_STAT is cleared while PxIS still holds bits: PxIS
2620 * keeps its content, HOST_IRQ_STAT reads back as 0, the port is never looked
2621 * at again and the command in flight only ends in a timeout. On a 88SE6121
2622 * this makes every SATA-2 or SATA-3 disk fail to IDENTIFY, while SATA-1 disks
2623 * happen to win the race often enough to work.
2624 *
2625 * Clearing the host status before servicing the ports avoids it. Marvell's
2626 * own driver for these chips does the same and says so ("clear global before
2627 * channel"), and ahci_xgene handles its broken edge latch the same way. The
2628 * price is at most one spurious interrupt per valid one, which is why this is
2629 * not the generic behaviour - see AHCI 1.1 section 10.6.2.
2630 *
2631 * Link: https://bugzilla.kernel.org/show_bug.cgi?id=216094
2632 */
ahci_mv_irq_handler(int irq,void * dev_instance)2633 static irqreturn_t ahci_mv_irq_handler(int irq, void *dev_instance)
2634 {
2635 struct ata_host *host = dev_instance;
2636 struct ahci_host_priv *hpriv = host->private_data;
2637 void __iomem *mmio = hpriv->mmio;
2638 unsigned int rc;
2639 u32 irq_stat, irq_masked;
2640
2641 irq_stat = readl(mmio + HOST_IRQ_STAT);
2642 if (!irq_stat)
2643 return IRQ_NONE;
2644
2645 irq_masked = irq_stat & hpriv->port_map;
2646
2647 spin_lock(&host->lock);
2648
2649 /*
2650 * Use the unmasked value to clear the interrupt, as a spurious pending
2651 * event on a dummy port might cause a screaming IRQ.
2652 */
2653 writel(irq_stat, mmio + HOST_IRQ_STAT);
2654
2655 rc = ahci_handle_port_intr(host, irq_masked);
2656
2657 spin_unlock(&host->lock);
2658
2659 return IRQ_RETVAL(rc);
2660 }
2661
ahci_remap_check(struct pci_dev * pdev,int bar,struct ahci_host_priv * hpriv)2662 static void ahci_remap_check(struct pci_dev *pdev, int bar,
2663 struct ahci_host_priv *hpriv)
2664 {
2665 int i;
2666 u32 cap;
2667
2668 /*
2669 * Check if this device might have remapped nvme devices.
2670 */
2671 if (pdev->vendor != PCI_VENDOR_ID_INTEL ||
2672 pci_resource_len(pdev, bar) < SZ_512K ||
2673 bar != AHCI_PCI_BAR_STANDARD ||
2674 !(readl(hpriv->mmio + AHCI_VSCAP) & 1))
2675 return;
2676
2677 cap = readq(hpriv->mmio + AHCI_REMAP_CAP);
2678 for (i = 0; i < AHCI_MAX_REMAP; i++) {
2679 if ((cap & (1 << i)) == 0)
2680 continue;
2681 if (readl(hpriv->mmio + ahci_remap_dcc(i))
2682 != PCI_CLASS_STORAGE_EXPRESS)
2683 continue;
2684
2685 /* We've found a remapped device */
2686 hpriv->remapped_nvme++;
2687 }
2688
2689 if (!hpriv->remapped_nvme)
2690 return;
2691
2692 dev_warn(&pdev->dev, "Found %u remapped NVMe devices.\n",
2693 hpriv->remapped_nvme);
2694 dev_warn(&pdev->dev,
2695 "Switch your BIOS from RAID to AHCI mode to use them.\n");
2696
2697 /*
2698 * Don't rely on the msi-x capability in the remap case,
2699 * share the legacy interrupt across ahci and remapped devices.
2700 */
2701 hpriv->flags |= AHCI_HFLAG_NO_MSI;
2702 }
2703
ahci_get_irq_vector(struct ata_host * host,int port)2704 static int ahci_get_irq_vector(struct ata_host *host, int port)
2705 {
2706 return pci_irq_vector(to_pci_dev(host->dev), port);
2707 }
2708
ahci_init_irq(struct pci_dev * pdev,unsigned int n_ports,struct ahci_host_priv * hpriv)2709 static void ahci_init_irq(struct pci_dev *pdev, unsigned int n_ports,
2710 struct ahci_host_priv *hpriv)
2711 {
2712 int nvec;
2713
2714 if (hpriv->flags & AHCI_HFLAG_NO_MSI) {
2715 pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_INTX);
2716 return;
2717 }
2718
2719 /*
2720 * If number of MSIs is less than number of ports then Sharing Last
2721 * Message mode could be enforced. In this case assume that advantage
2722 * of multiple MSIs is negated and use single MSI mode instead.
2723 */
2724 if (n_ports > 1) {
2725 nvec = pci_alloc_irq_vectors(pdev, n_ports, INT_MAX,
2726 PCI_IRQ_MSIX | PCI_IRQ_MSI);
2727 if (nvec > 0) {
2728 if (!(readl(hpriv->mmio + HOST_CTL) & HOST_MRSM)) {
2729 hpriv->get_irq_vector = ahci_get_irq_vector;
2730 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
2731 return;
2732 }
2733
2734 /*
2735 * Fallback to single MSI mode if the controller
2736 * enforced MRSM mode.
2737 */
2738 printk(KERN_INFO
2739 "ahci: MRSM is on, fallback to single MSI\n");
2740 pci_free_irq_vectors(pdev);
2741 }
2742 }
2743
2744 /*
2745 * If the host is not capable of supporting per-port vectors, fall
2746 * back to single MSI before finally attempting single MSI-X or
2747 * a legacy INTx.
2748 */
2749 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
2750 if (nvec == 1)
2751 return;
2752 pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX | PCI_IRQ_INTX);
2753 }
2754
ahci_mark_external_port(struct ata_port * ap)2755 static void ahci_mark_external_port(struct ata_port *ap)
2756 {
2757 struct ahci_host_priv *hpriv = ap->host->private_data;
2758 void __iomem *port_mmio = ahci_port_base(ap);
2759 u32 tmp;
2760
2761 /*
2762 * Mark external ports (hotplug-capable, eSATA), unless we were asked to
2763 * ignore this feature.
2764 */
2765 tmp = readl(port_mmio + PORT_CMD);
2766 if (((tmp & PORT_CMD_ESP) && (hpriv->cap & HOST_CAP_SXS)) ||
2767 (tmp & PORT_CMD_HPCP)) {
2768 if (hpriv->mask_port_ext & (1U << ap->port_no)) {
2769 ata_port_info(ap,
2770 "Ignoring external/hotplug capability\n");
2771 return;
2772 }
2773 ap->pflags |= ATA_PFLAG_EXTERNAL;
2774 }
2775 }
2776
ahci_update_initial_lpm_policy(struct ata_port * ap)2777 static void ahci_update_initial_lpm_policy(struct ata_port *ap)
2778 {
2779 struct ahci_host_priv *hpriv = ap->host->private_data;
2780 int policy = CONFIG_SATA_MOBILE_LPM_POLICY;
2781
2782 /*
2783 * AHCI contains a known incompatibility between LPM and hot-plug
2784 * removal events, see 7.3.1 Hot Plug Removal Detection and Power
2785 * Management Interaction in AHCI 1.3.1. Therefore, do not enable
2786 * LPM if the port advertises itself as an external port.
2787 */
2788 if (ap->pflags & ATA_PFLAG_EXTERNAL) {
2789 ap->flags |= ATA_FLAG_NO_LPM;
2790 ap->target_lpm_policy = ATA_LPM_MAX_POWER;
2791 return;
2792 }
2793
2794 /* If no Partial or no Slumber, we cannot support DIPM. */
2795 if ((ap->host->flags & ATA_HOST_NO_PART) ||
2796 (ap->host->flags & ATA_HOST_NO_SSC)) {
2797 ata_port_dbg(ap, "Host does not support DIPM\n");
2798 ap->flags |= ATA_FLAG_NO_DIPM;
2799 }
2800
2801 /* If no LPM states are supported by the HBA, do not bother with LPM */
2802 if ((ap->host->flags & ATA_HOST_NO_PART) &&
2803 (ap->host->flags & ATA_HOST_NO_SSC) &&
2804 (ap->host->flags & ATA_HOST_NO_DEVSLP)) {
2805 ata_port_dbg(ap,
2806 "No LPM states supported, forcing LPM max_power\n");
2807 ap->flags |= ATA_FLAG_NO_LPM;
2808 ap->target_lpm_policy = ATA_LPM_MAX_POWER;
2809 return;
2810 }
2811
2812 /* user modified policy via module param */
2813 if (mobile_lpm_policy != -1) {
2814 policy = mobile_lpm_policy;
2815 goto update_policy;
2816 }
2817
2818 if (policy > ATA_LPM_MED_POWER && pm_suspend_default_s2idle()) {
2819 if (hpriv->cap & HOST_CAP_PART)
2820 policy = ATA_LPM_MIN_POWER_WITH_PARTIAL;
2821 else if (hpriv->cap & HOST_CAP_SSC)
2822 policy = ATA_LPM_MIN_POWER;
2823 }
2824
2825 update_policy:
2826 if (policy >= ATA_LPM_UNKNOWN && policy <= ATA_LPM_MIN_POWER)
2827 ap->target_lpm_policy = policy;
2828 }
2829
ahci_intel_pcs_quirk(struct pci_dev * pdev,struct ahci_host_priv * hpriv)2830 static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv)
2831 {
2832 u16 tmp16;
2833
2834 if (!(hpriv->flags & AHCI_HFLAG_INTEL_PCS_QUIRK))
2835 return;
2836
2837 /*
2838 * port_map is determined from PORTS_IMPL PCI register which is
2839 * implemented as write or write-once register. If the register
2840 * isn't programmed, ahci automatically generates it from number
2841 * of ports, which is good enough for PCS programming. It is
2842 * otherwise expected that platform firmware enables the ports
2843 * before the OS boots.
2844 */
2845 pci_read_config_word(pdev, PCS_6, &tmp16);
2846 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
2847 tmp16 |= hpriv->port_map;
2848 pci_write_config_word(pdev, PCS_6, tmp16);
2849 }
2850 }
2851
remapped_nvme_show(struct device * dev,struct device_attribute * attr,char * buf)2852 static ssize_t remapped_nvme_show(struct device *dev,
2853 struct device_attribute *attr,
2854 char *buf)
2855 {
2856 struct ata_host *host = dev_get_drvdata(dev);
2857 struct ahci_host_priv *hpriv = host->private_data;
2858
2859 return sysfs_emit(buf, "%u\n", hpriv->remapped_nvme);
2860 }
2861
2862 static DEVICE_ATTR_RO(remapped_nvme);
2863
ahci_validate_bar_size(struct pci_dev * pdev,int bar,struct ahci_host_priv * hpriv)2864 static int ahci_validate_bar_size(struct pci_dev *pdev, int bar,
2865 struct ahci_host_priv *hpriv)
2866 {
2867 u32 cap = readl(hpriv->mmio + HOST_CAP);
2868 unsigned int max_ports = ahci_nr_ports(cap);
2869 u32 last_port_end = 0x100 + (max_ports * 0x80);
2870 resource_size_t bar_size = pci_resource_len(pdev, bar);
2871
2872 if (last_port_end > bar_size) {
2873 dev_warn(&pdev->dev,
2874 "BAR%d too small for %u ports (last port ends at %#x, BAR %pa)\n",
2875 bar, max_ports, last_port_end, &bar_size);
2876 return -ENODEV;
2877 }
2878
2879 return 0;
2880 }
2881
ahci_init_one(struct pci_dev * pdev,const struct pci_device_id * ent)2882 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2883 {
2884 unsigned int board_id = ent->driver_data;
2885 struct ata_port_info pi = ahci_port_info[board_id];
2886 const struct ata_port_info *ppi[] = { &pi, NULL };
2887 struct device *dev = &pdev->dev;
2888 struct ahci_host_priv *hpriv;
2889 struct ata_host *host;
2890 int n_ports, i, rc;
2891 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
2892
2893 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
2894
2895 ata_print_version_once(&pdev->dev, DRV_VERSION);
2896
2897 /* The AHCI driver can only drive the SATA ports, the PATA driver
2898 can drive them all so if both drivers are selected make sure
2899 AHCI stays out of the way */
2900 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
2901 return -ENODEV;
2902
2903 /* Apple BIOS on MCP89 prevents us using AHCI */
2904 if (is_mcp89_apple(pdev))
2905 ahci_mcp89_apple_enable(pdev);
2906
2907 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
2908 * At the moment, we can only use the AHCI mode. Let the users know
2909 * that for SAS drives they're out of luck.
2910 */
2911 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
2912 dev_info(&pdev->dev,
2913 "PDC42819 can only drive SATA devices with this driver\n");
2914
2915 /* Some devices use non-standard BARs */
2916 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
2917 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
2918 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
2919 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
2920 else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) {
2921 if (pdev->device == 0xa01c)
2922 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
2923 if (pdev->device == 0xa084)
2924 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5;
2925 } else if (pdev->vendor == PCI_VENDOR_ID_LOONGSON) {
2926 if (pdev->device == 0x7a08)
2927 ahci_pci_bar = AHCI_PCI_BAR_LOONGSON;
2928 }
2929
2930 /* acquire resources */
2931 rc = pcim_enable_device(pdev);
2932 if (rc)
2933 return rc;
2934
2935 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
2936 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
2937 u8 map;
2938
2939 /* ICH6s share the same PCI ID for both piix and ahci
2940 * modes. Enabling ahci mode while MAP indicates
2941 * combined mode is a bad idea. Yield to ata_piix.
2942 */
2943 pci_read_config_byte(pdev, ICH_MAP, &map);
2944 if (map & 0x3) {
2945 dev_info(&pdev->dev,
2946 "controller is in combined mode, can't enable AHCI mode\n");
2947 return -ENODEV;
2948 }
2949 }
2950
2951 /* AHCI controllers often implement SFF compatible interface.
2952 * Grab all PCI BARs just in case.
2953 */
2954 rc = pcim_request_all_regions(pdev, DRV_NAME);
2955 if (rc == -EBUSY)
2956 pcim_pin_device(pdev);
2957 if (rc)
2958 return rc;
2959
2960 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
2961 if (!hpriv)
2962 return -ENOMEM;
2963 hpriv->flags |= (unsigned long)pi.private_data;
2964
2965 /* the Marvell "Thor" family needs HOST_IRQ_STAT cleared first */
2966 if (board_id == board_ahci_mv)
2967 hpriv->irq_handler = ahci_mv_irq_handler;
2968
2969 /* MCP65 revision A1 and A2 can't do MSI */
2970 if (board_id == board_ahci_mcp65 &&
2971 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
2972 hpriv->flags |= AHCI_HFLAG_NO_MSI;
2973
2974 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
2975 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
2976 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
2977
2978 /* only some SB600s can do 64bit DMA */
2979 if (ahci_sb600_enable_64bit(pdev))
2980 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
2981
2982 hpriv->mmio = pcim_iomap(pdev, ahci_pci_bar, 0);
2983 if (!hpriv->mmio)
2984 return -ENOMEM;
2985
2986 rc = ahci_validate_bar_size(pdev, ahci_pci_bar, hpriv);
2987 if (rc)
2988 return rc;
2989
2990 /* detect remapped nvme devices */
2991 ahci_remap_check(pdev, ahci_pci_bar, hpriv);
2992
2993 sysfs_add_file_to_group(&pdev->dev.kobj,
2994 &dev_attr_remapped_nvme.attr,
2995 NULL);
2996
2997 #ifdef CONFIG_ARM64
2998 if (pdev->vendor == PCI_VENDOR_ID_HUAWEI &&
2999 pdev->device == 0xa235 &&
3000 pdev->revision < 0x30)
3001 hpriv->flags |= AHCI_HFLAG_NO_SXS;
3002
3003 if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
3004 hpriv->irq_handler = ahci_thunderx_irq_handler;
3005 #endif
3006
3007 /* save initial config */
3008 ahci_pci_save_initial_config(pdev, hpriv);
3009
3010 /* prepare host */
3011 if (hpriv->cap & HOST_CAP_NCQ) {
3012 pi.flags |= ATA_FLAG_NCQ;
3013 /*
3014 * Auto-activate optimization is supposed to be
3015 * supported on all AHCI controllers indicating NCQ
3016 * capability, but it seems to be broken on some
3017 * chipsets including NVIDIAs.
3018 */
3019 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
3020 pi.flags |= ATA_FLAG_FPDMA_AA;
3021
3022 /*
3023 * All AHCI controllers should be forward-compatible
3024 * with the new auxiliary field. This code should be
3025 * conditionalized if any buggy AHCI controllers are
3026 * encountered.
3027 */
3028 pi.flags |= ATA_FLAG_FPDMA_AUX;
3029 }
3030
3031 if (hpriv->cap & HOST_CAP_PMP)
3032 pi.flags |= ATA_FLAG_PMP;
3033
3034 ahci_set_em_messages(hpriv, &pi);
3035
3036 if (ahci_broken_system_poweroff(pdev)) {
3037 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
3038 dev_info(&pdev->dev,
3039 "quirky BIOS, skipping spindown on poweroff\n");
3040 }
3041
3042 if (ahci_broken_lpm(pdev)) {
3043 pi.flags |= ATA_FLAG_NO_LPM;
3044 dev_warn(&pdev->dev,
3045 "BIOS update required for Link Power Management support\n");
3046 }
3047
3048 if (ahci_broken_suspend(pdev)) {
3049 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
3050 dev_warn(&pdev->dev,
3051 "BIOS update required for suspend/resume\n");
3052 }
3053
3054 if (ahci_broken_online(pdev)) {
3055 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
3056 dev_info(&pdev->dev,
3057 "online status unreliable, applying workaround\n");
3058 }
3059
3060
3061 /* Acer SA5-271 workaround modifies private_data */
3062 acer_sa5_271_workaround(hpriv, pdev);
3063
3064 /* CAP.NP sometimes indicate the index of the last enabled
3065 * port, at other times, that of the last possible port, so
3066 * determining the maximum port number requires looking at
3067 * both CAP.NP and port_map.
3068 */
3069 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
3070
3071 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
3072 if (!host) {
3073 rc = -ENOMEM;
3074 goto err_rm_sysfs_file;
3075 }
3076 host->private_data = hpriv;
3077
3078 ahci_init_irq(pdev, n_ports, hpriv);
3079
3080 hpriv->irq = pci_irq_vector(pdev, 0);
3081
3082 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
3083 host->flags |= ATA_HOST_PARALLEL_SCAN;
3084 else
3085 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
3086
3087 if (!(hpriv->cap & HOST_CAP_PART))
3088 host->flags |= ATA_HOST_NO_PART;
3089
3090 if (!(hpriv->cap & HOST_CAP_SSC))
3091 host->flags |= ATA_HOST_NO_SSC;
3092
3093 if (!(hpriv->cap2 & HOST_CAP2_SDS))
3094 host->flags |= ATA_HOST_NO_DEVSLP;
3095
3096 if (pi.flags & ATA_FLAG_EM)
3097 ahci_reset_em(host);
3098
3099 for (i = 0; i < host->n_ports; i++) {
3100 struct ata_port *ap = host->ports[i];
3101
3102 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
3103 ata_port_pbar_desc(ap, ahci_pci_bar,
3104 0x100 + ap->port_no * 0x80, "port");
3105
3106 /* set enclosure management message type */
3107 if (ap->flags & ATA_FLAG_EM)
3108 ap->em_message_type = hpriv->em_msg_type;
3109
3110 /* disabled/not-implemented port */
3111 if (!(hpriv->port_map & (1 << i))) {
3112 ap->ops = &ata_dummy_port_ops;
3113 } else {
3114 ahci_mark_external_port(ap);
3115 ahci_update_initial_lpm_policy(ap);
3116 }
3117 }
3118
3119 /* apply workaround for ASUS P5W DH Deluxe mainboard */
3120 ahci_p5wdh_workaround(host);
3121
3122 /* apply gtf filter quirk */
3123 ahci_gtf_filter_workaround(host);
3124
3125 /* initialize adapter */
3126 rc = ahci_configure_dma_masks(pdev, hpriv);
3127 if (rc)
3128 goto err_rm_sysfs_file;
3129
3130 rc = ahci_pci_reset_controller(host);
3131 if (rc)
3132 goto err_rm_sysfs_file;
3133
3134 ahci_pci_init_controller(host);
3135 ahci_pci_print_info(host);
3136
3137 pci_set_master(pdev);
3138
3139 rc = ahci_host_activate(host, &ahci_sht);
3140 if (rc)
3141 goto err_rm_sysfs_file;
3142
3143 pm_runtime_put_noidle(&pdev->dev);
3144 return 0;
3145
3146 err_rm_sysfs_file:
3147 sysfs_remove_file_from_group(&pdev->dev.kobj,
3148 &dev_attr_remapped_nvme.attr, NULL);
3149 return rc;
3150 }
3151
ahci_shutdown_one(struct pci_dev * pdev)3152 static void ahci_shutdown_one(struct pci_dev *pdev)
3153 {
3154 ata_pci_shutdown_one(pdev);
3155 }
3156
ahci_remove_one(struct pci_dev * pdev)3157 static void ahci_remove_one(struct pci_dev *pdev)
3158 {
3159 sysfs_remove_file_from_group(&pdev->dev.kobj,
3160 &dev_attr_remapped_nvme.attr,
3161 NULL);
3162 pm_runtime_get_noresume(&pdev->dev);
3163 ata_pci_remove_one(pdev);
3164 }
3165
3166 module_pci_driver(ahci_pci_driver);
3167
3168 MODULE_AUTHOR("Jeff Garzik");
3169 MODULE_DESCRIPTION("AHCI SATA low-level driver");
3170 MODULE_LICENSE("GPL");
3171 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
3172 MODULE_VERSION(DRV_VERSION);
3173