1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2021 THine Electronics, Inc. 4 * Copyright (C) 2023 Ideas on Board Oy 5 */ 6 7 #include <linux/unaligned.h> 8 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/device.h> 12 #include <linux/firmware.h> 13 #include <linux/gpio/consumer.h> 14 #include <linux/i2c.h> 15 #include <linux/init.h> 16 #include <linux/iopoll.h> 17 #include <linux/kernel.h> 18 #include <linux/module.h> 19 #include <linux/mtd/spi-nor.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/property.h> 22 #include <linux/regulator/consumer.h> 23 #include <linux/slab.h> 24 #include <linux/types.h> 25 26 #include <media/v4l2-async.h> 27 #include <media/v4l2-cci.h> 28 #include <media/v4l2-ctrls.h> 29 #include <media/v4l2-device.h> 30 #include <media/v4l2-fwnode.h> 31 #include <media/v4l2-subdev.h> 32 33 #include <uapi/linux/thp7312.h> 34 35 /* ISP registers */ 36 37 #define THP7312_REG_FIRMWARE_VERSION_1 CCI_REG8(0xf000) 38 #define THP7312_REG_CAMERA_STATUS CCI_REG8(0xf001) 39 #define THP7312_REG_FIRMWARE_VERSION_2 CCI_REG8(0xf005) 40 #define THP7312_REG_SET_OUTPUT_ENABLE CCI_REG8(0xf008) 41 #define THP7312_OUTPUT_ENABLE 0x01 42 #define THP7312_OUTPUT_DISABLE 0x00 43 #define THP7312_REG_SET_OUTPUT_COLOR_COMPRESSION CCI_REG8(0xf009) 44 #define THP7312_REG_SET_OUTPUT_COLOR_UYVY 0x00 45 #define THP7312_REG_SET_OUTPUT_COLOR_YUY2 0x04 46 #define THP7312_REG_FLIP_MIRROR CCI_REG8(0xf00c) 47 #define THP7312_REG_FLIP_MIRROR_FLIP BIT(0) 48 #define THP7312_REG_FLIP_MIRROR_MIRROR BIT(1) 49 #define THP7312_REG_VIDEO_IMAGE_SIZE CCI_REG8(0xf00d) 50 #define THP7312_VIDEO_IMAGE_SIZE_640x360 0x52 51 #define THP7312_VIDEO_IMAGE_SIZE_640x460 0x03 52 #define THP7312_VIDEO_IMAGE_SIZE_1280x720 0x0a 53 #define THP7312_VIDEO_IMAGE_SIZE_1920x1080 0x0b 54 #define THP7312_VIDEO_IMAGE_SIZE_3840x2160 0x0d 55 #define THP7312_VIDEO_IMAGE_SIZE_4160x3120 0x14 56 #define THP7312_VIDEO_IMAGE_SIZE_2016x1512 0x20 57 #define THP7312_VIDEO_IMAGE_SIZE_2048x1536 0x21 58 #define THP7312_REG_VIDEO_FRAME_RATE_MODE CCI_REG8(0xf00f) 59 #define THP7312_VIDEO_FRAME_RATE_MODE1 0x80 60 #define THP7312_VIDEO_FRAME_RATE_MODE2 0x81 61 #define THP7312_VIDEO_FRAME_RATE_MODE3 0x82 62 #define THP7312_REG_SET_DRIVING_MODE CCI_REG8(0xf010) 63 #define THP7312_REG_DRIVING_MODE_STATUS CCI_REG8(0xf011) 64 #define THP7312_REG_JPEG_COMPRESSION_FACTOR CCI_REG8(0xf01b) 65 #define THP7312_REG_AE_EXPOSURE_COMPENSATION CCI_REG8(0xf022) 66 #define THP7312_REG_AE_FLICKER_MODE CCI_REG8(0xf023) 67 #define THP7312_AE_FLICKER_MODE_50 0x00 68 #define THP7312_AE_FLICKER_MODE_60 0x01 69 #define THP7312_AE_FLICKER_MODE_DISABLE 0x80 70 #define THP7312_REG_AE_FIX_FRAME_RATE CCI_REG8(0xf02e) 71 #define THP7312_REG_MANUAL_WB_RED_GAIN CCI_REG8(0xf036) 72 #define THP7312_REG_MANUAL_WB_BLUE_GAIN CCI_REG8(0xf037) 73 #define THP7312_REG_WB_MODE CCI_REG8(0xf039) 74 #define THP7312_WB_MODE_AUTO 0x00 75 #define THP7312_WB_MODE_MANUAL 0x11 76 #define THP7312_REG_MANUAL_FOCUS_POSITION CCI_REG16(0xf03c) 77 #define THP7312_REG_AF_CONTROL CCI_REG8(0xf040) 78 #define THP7312_REG_AF_CONTROL_AF 0x01 79 #define THP7312_REG_AF_CONTROL_MANUAL 0x10 80 #define THP7312_REG_AF_CONTROL_LOCK 0x80 81 #define THP7312_REG_AF_SETTING CCI_REG8(0xf041) 82 #define THP7312_REG_AF_SETTING_ONESHOT_CONTRAST 0x00 83 #define THP7312_REG_AF_SETTING_ONESHOT_PDAF 0x40 84 #define THP7312_REG_AF_SETTING_ONESHOT_HYBRID 0x80 85 #define THP7312_REG_AF_SETTING_CONTINUOUS_CONTRAST 0x30 86 #define THP7312_REG_AF_SETTING_CONTINUOUS_PDAF 0x70 87 #define THP7312_REG_AF_SETTING_CONTINUOUS_HYBRID 0xf0 88 #define THP7312_REG_AF_SUPPORT CCI_REG8(0xf043) 89 #define THP7312_AF_SUPPORT_PDAF BIT(1) 90 #define THP7312_AF_SUPPORT_CONTRAST BIT(0) 91 #define THP7312_REG_SATURATION CCI_REG8(0xf052) 92 #define THP7312_REG_SHARPNESS CCI_REG8(0xf053) 93 #define THP7312_REG_BRIGHTNESS CCI_REG8(0xf056) 94 #define THP7312_REG_CONTRAST CCI_REG8(0xf057) 95 #define THP7312_REG_NOISE_REDUCTION CCI_REG8(0xf059) 96 #define THP7312_REG_NOISE_REDUCTION_FIXED BIT(7) 97 98 #define TH7312_REG_CUSTOM_MIPI_SET CCI_REG8(0xf0f6) 99 #define TH7312_REG_CUSTOM_MIPI_STATUS CCI_REG8(0xf0f7) 100 #define TH7312_REG_CUSTOM_MIPI_RD CCI_REG8(0xf0f8) 101 #define TH7312_REG_CUSTOM_MIPI_TD CCI_REG8(0xf0f9) 102 103 /* 104 * Firmware update registers. Those use a different address space than the 105 * normal operation ISP registers. 106 */ 107 108 #define THP7312_REG_FW_DRIVABILITY CCI_REG32(0xd65c) 109 #define THP7312_REG_FW_DEST_BANK_ADDR CCI_REG32(0xff08) 110 #define THP7312_REG_FW_VERIFY_RESULT CCI_REG8(0xff60) 111 #define THP7312_REG_FW_RESET_FLASH CCI_REG8(0xff61) 112 #define THP7312_REG_FW_MEMORY_IO_SETTING CCI_REG8(0xff62) 113 #define THP7312_FW_MEMORY_IO_GPIO0 1 114 #define THP7312_FW_MEMORY_IO_GPIO1 0 115 #define THP7312_REG_FW_CRC_RESULT CCI_REG32(0xff64) 116 #define THP7312_REG_FW_STATUS CCI_REG8(0xfffc) 117 118 #define THP7312_FW_VERSION(major, minor) (((major) << 8) | (minor)) 119 #define THP7312_FW_VERSION_MAJOR(v) ((v) >> 8) 120 #define THP7312_FW_VERSION_MINOR(v) ((v) & 0xff) 121 122 enum thp7312_focus_method { 123 THP7312_FOCUS_METHOD_CONTRAST, 124 THP7312_FOCUS_METHOD_PDAF, 125 THP7312_FOCUS_METHOD_HYBRID, 126 }; 127 128 /* 129 * enum thp7312_focus_state - State of the focus handler 130 * 131 * @THP7312_FOCUS_STATE_MANUAL: Manual focus, controlled through the 132 * V4L2_CID_FOCUS_ABSOLUTE control 133 * @THP7312_FOCUS_STATE_AUTO: Continuous auto-focus 134 * @THP7312_FOCUS_STATE_LOCKED: Lock the focus to a fixed position. This state 135 * is entered when switching from auto to manual mode. 136 * @THP7312_FOCUS_STATE_ONESHOT: One-shot auto-focus 137 * 138 * Valid transitions are as follow: 139 * 140 * digraph fsm { 141 * node [shape=circle]; 142 * 143 * manual [label="MANUAL"]; 144 * auto [label="AUTO"]; 145 * locked [label="LOCKED"]; 146 * oneshot [label="ONESHOT"]; 147 * 148 * manual -> auto [label="FOCUS_AUTO <- true"] 149 * locked -> auto [label="FOCUS_AUTO <- true"] 150 * oneshot -> auto [label="FOCUS_AUTO <- true"] 151 * auto -> locked [label="FOCUS_AUTO <- false"] 152 * 153 * locked -> manual [label="FOCUS_ABSOLUTE <- *"] 154 * oneshot -> manual [label="FOCUS_ABSOLUTE <- *"] 155 * 156 * manual -> oneshot [label="FOCUS_START <- *"] 157 * locked -> oneshot [label="FOCUS_START <- *"] 158 * } 159 */ 160 enum thp7312_focus_state { 161 THP7312_FOCUS_STATE_MANUAL, 162 THP7312_FOCUS_STATE_AUTO, 163 THP7312_FOCUS_STATE_LOCKED, 164 THP7312_FOCUS_STATE_ONESHOT, 165 }; 166 167 enum thp7312_boot_mode { 168 THP7312_BOOT_MODE_2WIRE_SLAVE = 0, 169 THP7312_BOOT_MODE_SPI_MASTER = 1, 170 }; 171 172 struct thp7312_frame_rate { 173 u32 fps; 174 u32 link_freq; 175 u8 reg_frame_rate_mode; 176 }; 177 178 struct thp7312_mode_info { 179 u32 width; 180 u32 height; 181 u8 reg_image_size; 182 const struct thp7312_frame_rate *rates; 183 }; 184 185 static const u32 thp7312_colour_fmts[] = { 186 MEDIA_BUS_FMT_YUYV8_1X16, 187 }; 188 189 /* regulator supplies */ 190 static const char * const thp7312_supply_name[] = { 191 "vddcore", 192 "vhtermrx", 193 "vddtx", 194 "vddhost", 195 "vddcmos", 196 "vddgpio-0", 197 "vddgpio-1", 198 }; 199 200 static const struct thp7312_mode_info thp7312_mode_info_data[] = { 201 { 202 .width = 1920, 203 .height = 1080, 204 .reg_image_size = THP7312_VIDEO_IMAGE_SIZE_1920x1080, 205 .rates = (const struct thp7312_frame_rate[]) { 206 { 30, 300000000, 0x81 }, 207 { 60, 387500000, 0x82 }, 208 { 0 } 209 }, 210 }, { 211 .width = 2048, 212 .height = 1536, 213 .reg_image_size = THP7312_VIDEO_IMAGE_SIZE_2048x1536, 214 .rates = (const struct thp7312_frame_rate[]) { 215 { 30, 300000000, 0x81 }, 216 { 0 } 217 } 218 }, { 219 .width = 3840, 220 .height = 2160, 221 .reg_image_size = THP7312_VIDEO_IMAGE_SIZE_3840x2160, 222 .rates = (const struct thp7312_frame_rate[]) { 223 { 30, 600000000, 0x81 }, 224 { 0 } 225 }, 226 }, { 227 .width = 4160, 228 .height = 3120, 229 .reg_image_size = THP7312_VIDEO_IMAGE_SIZE_4160x3120, 230 .rates = (const struct thp7312_frame_rate[]) { 231 { 20, 600000000, 0x81 }, 232 { 0 } 233 }, 234 }, 235 }; 236 237 struct thp7312_device; 238 239 struct thp7312_sensor_info { 240 const char *model; 241 }; 242 243 struct thp7312_sensor { 244 const struct thp7312_sensor_info *info; 245 u8 lane_remap; 246 }; 247 248 struct thp7312_device { 249 struct device *dev; 250 struct regmap *regmap; 251 252 struct v4l2_subdev sd; 253 struct media_pad pad; 254 255 struct gpio_desc *reset_gpio; 256 struct regulator_bulk_data supplies[ARRAY_SIZE(thp7312_supply_name)]; 257 struct clk *iclk; 258 259 u8 lane_remap; 260 261 struct thp7312_sensor sensors[1]; 262 263 enum thp7312_boot_mode boot_mode; 264 265 struct v4l2_ctrl_handler ctrl_handler; 266 bool ctrls_applied; 267 268 s64 link_freq; 269 270 struct { 271 struct v4l2_ctrl *hflip; 272 struct v4l2_ctrl *vflip; 273 }; 274 275 struct { 276 struct v4l2_ctrl *focus_auto; 277 struct v4l2_ctrl *focus_absolute; 278 struct v4l2_ctrl *focus_start; 279 struct v4l2_ctrl *focus_method; 280 }; 281 282 enum thp7312_focus_state focus_state; 283 284 struct { 285 struct v4l2_ctrl *noise_reduction_auto; 286 struct v4l2_ctrl *noise_reduction_absolute; 287 }; 288 289 /* Lock to protect fw_cancel */ 290 struct mutex fw_lock; 291 struct fw_upload *fwl; 292 u8 *fw_write_buf; 293 bool fw_cancel; 294 295 u16 fw_version; 296 }; 297 298 static const struct thp7312_sensor_info thp7312_sensor_info[] = { 299 { 300 .model = "sony,imx258", 301 }, 302 }; 303 304 static inline struct thp7312_device *to_thp7312_dev(struct v4l2_subdev *sd) 305 { 306 return container_of(sd, struct thp7312_device, sd); 307 } 308 309 static const struct thp7312_mode_info * 310 thp7312_find_mode(unsigned int width, unsigned int height, bool nearest) 311 { 312 const struct thp7312_mode_info *mode; 313 314 mode = v4l2_find_nearest_size(thp7312_mode_info_data, 315 ARRAY_SIZE(thp7312_mode_info_data), 316 width, height, width, height); 317 318 if (!nearest && (mode->width != width || mode->height != height)) 319 return NULL; 320 321 return mode; 322 } 323 324 static const struct thp7312_frame_rate * 325 thp7312_find_rate(const struct thp7312_mode_info *mode, unsigned int fps, 326 bool nearest) 327 { 328 const struct thp7312_frame_rate *best_rate = NULL; 329 const struct thp7312_frame_rate *rate; 330 unsigned int best_delta = UINT_MAX; 331 332 if (!mode) 333 return NULL; 334 335 for (rate = mode->rates; rate->fps && best_delta; ++rate) { 336 unsigned int delta = abs(rate->fps - fps); 337 338 if (delta <= best_delta) { 339 best_delta = delta; 340 best_rate = rate; 341 } 342 } 343 344 if (!nearest && best_delta) 345 return NULL; 346 347 return best_rate; 348 } 349 350 /* ----------------------------------------------------------------------------- 351 * Device Access & Configuration 352 */ 353 354 #define thp7312_read_poll_timeout(dev, addr, val, cond, sleep_us, timeout_us) \ 355 ({ \ 356 int __ret, __err; \ 357 __ret = read_poll_timeout(cci_read, __err, __err || (cond), sleep_us, \ 358 timeout_us, false, (dev)->regmap, addr, \ 359 &(val), NULL); \ 360 __ret ? : __err; \ 361 }) 362 363 static int thp7312_map_data_lanes(u8 *lane_remap, const u8 *lanes, u8 num_lanes) 364 { 365 u8 used_lanes = 0; 366 u8 val = 0; 367 unsigned int i; 368 369 /* 370 * The value that we write to the register is the index in the 371 * data-lanes array, so we need to do a conversion. Do this in the same 372 * pass as validating data-lanes. 373 */ 374 for (i = 0; i < num_lanes; i++) { 375 if (lanes[i] < 1 || lanes[i] > 4) 376 return -EINVAL; 377 378 if (used_lanes & (BIT(lanes[i]))) 379 return -EINVAL; 380 381 used_lanes |= BIT(lanes[i]); 382 383 /* 384 * data-lanes is 1-indexed while the field position in the 385 * register is 0-indexed. 386 */ 387 val |= i << ((lanes[i] - 1) * 2); 388 } 389 390 *lane_remap = val; 391 392 return 0; 393 } 394 395 static int thp7312_set_mipi_lanes(struct thp7312_device *thp7312) 396 { 397 struct device *dev = thp7312->dev; 398 int ret = 0; 399 u64 val; 400 401 cci_write(thp7312->regmap, TH7312_REG_CUSTOM_MIPI_RD, 402 thp7312->sensors[0].lane_remap, &ret); 403 cci_write(thp7312->regmap, TH7312_REG_CUSTOM_MIPI_TD, 404 thp7312->lane_remap, &ret); 405 cci_write(thp7312->regmap, TH7312_REG_CUSTOM_MIPI_SET, 1, &ret); 406 407 if (ret) 408 return ret; 409 410 ret = thp7312_read_poll_timeout(thp7312, TH7312_REG_CUSTOM_MIPI_STATUS, 411 val, val == 0x00, 100000, 2000000); 412 if (ret) { 413 dev_err(dev, "Failed to poll MIPI lane status: %d\n", ret); 414 return ret; 415 } 416 417 return 0; 418 } 419 420 static int thp7312_change_mode(struct thp7312_device *thp7312, 421 const struct thp7312_mode_info *mode, 422 const struct thp7312_frame_rate *rate) 423 { 424 struct device *dev = thp7312->dev; 425 u64 val = 0; 426 int ret; 427 428 ret = thp7312_read_poll_timeout(thp7312, THP7312_REG_CAMERA_STATUS, val, 429 val == 0x80, 20000, 200000); 430 if (ret < 0) { 431 dev_err(dev, "%s(): failed to poll ISP: %d\n", __func__, ret); 432 return ret; 433 } 434 435 cci_write(thp7312->regmap, THP7312_REG_VIDEO_IMAGE_SIZE, 436 mode->reg_image_size, &ret); 437 cci_write(thp7312->regmap, THP7312_REG_VIDEO_FRAME_RATE_MODE, 438 rate->reg_frame_rate_mode, &ret); 439 cci_write(thp7312->regmap, THP7312_REG_JPEG_COMPRESSION_FACTOR, 0x5e, 440 &ret); 441 cci_write(thp7312->regmap, THP7312_REG_SET_DRIVING_MODE, 0x01, &ret); 442 443 if (ret) 444 return ret; 445 446 ret = thp7312_read_poll_timeout(thp7312, THP7312_REG_DRIVING_MODE_STATUS, 447 val, val == 0x01, 20000, 100000); 448 if (ret < 0) { 449 dev_err(dev, "%s(): failed\n", __func__); 450 return ret; 451 } 452 453 return 0; 454 } 455 456 static int thp7312_set_framefmt(struct thp7312_device *thp7312, 457 struct v4l2_mbus_framefmt *format) 458 { 459 u8 val; 460 461 switch (format->code) { 462 case MEDIA_BUS_FMT_UYVY8_1X16: 463 /* YUV422, UYVY */ 464 val = THP7312_REG_SET_OUTPUT_COLOR_UYVY; 465 break; 466 case MEDIA_BUS_FMT_YUYV8_1X16: 467 /* YUV422, YUYV */ 468 val = THP7312_REG_SET_OUTPUT_COLOR_YUY2; 469 break; 470 default: 471 /* Should never happen */ 472 return -EINVAL; 473 } 474 475 return cci_write(thp7312->regmap, 476 THP7312_REG_SET_OUTPUT_COLOR_COMPRESSION, val, NULL); 477 } 478 479 static int thp7312_init_mode(struct thp7312_device *thp7312, 480 struct v4l2_subdev_state *sd_state) 481 { 482 const struct thp7312_mode_info *mode; 483 const struct thp7312_frame_rate *rate; 484 struct v4l2_mbus_framefmt *fmt; 485 struct v4l2_fract *interval; 486 int ret; 487 488 /* 489 * TODO: The mode and rate should be cached in the subdev state, once 490 * support for extending states will be available. 491 */ 492 fmt = v4l2_subdev_state_get_format(sd_state, 0); 493 interval = v4l2_subdev_state_get_interval(sd_state, 0); 494 495 mode = thp7312_find_mode(fmt->width, fmt->height, false); 496 rate = thp7312_find_rate(mode, interval->denominator, false); 497 498 if (WARN_ON(!mode || !rate)) 499 return -EINVAL; 500 501 ret = thp7312_set_framefmt(thp7312, fmt); 502 if (ret) 503 return ret; 504 505 return thp7312_change_mode(thp7312, mode, rate); 506 } 507 508 static int thp7312_stream_enable(struct thp7312_device *thp7312, bool enable) 509 { 510 return cci_write(thp7312->regmap, THP7312_REG_SET_OUTPUT_ENABLE, 511 enable ? THP7312_OUTPUT_ENABLE : THP7312_OUTPUT_DISABLE, 512 NULL); 513 } 514 515 static int thp7312_check_status_stream_mode(struct thp7312_device *thp7312) 516 { 517 struct device *dev = thp7312->dev; 518 u64 status = 0; 519 int ret; 520 521 while (status != 0x80) { 522 ret = cci_read(thp7312->regmap, THP7312_REG_CAMERA_STATUS, 523 &status, NULL); 524 if (ret) 525 return ret; 526 527 if (status == 0x80) { 528 dev_dbg(dev, "Camera initialization done\n"); 529 return 0; 530 } 531 532 if (status != 0x00) { 533 dev_err(dev, "Invalid camera status %llx\n", status); 534 return -EINVAL; 535 } 536 537 dev_dbg(dev, "Camera initializing...\n"); 538 usleep_range(70000, 80000); 539 } 540 541 return 0; 542 } 543 544 static void thp7312_reset(struct thp7312_device *thp7312) 545 { 546 unsigned long rate; 547 548 gpiod_set_value_cansleep(thp7312->reset_gpio, 1); 549 550 /* 551 * The minimum reset duration is 8 clock cycles, make it 10 to provide 552 * a safety margin. 553 */ 554 rate = clk_get_rate(thp7312->iclk); 555 fsleep(DIV_ROUND_UP(10 * USEC_PER_SEC, rate)); 556 557 gpiod_set_value_cansleep(thp7312->reset_gpio, 0); 558 559 /* 560 * TODO: The documentation states that the device needs 2ms to 561 * initialize after reset is deasserted. It then proceeds to load the 562 * firmware from the flash memory, which takes an unspecified amount of 563 * time. Check if this delay could be reduced. 564 */ 565 fsleep(300000); 566 } 567 568 /* ----------------------------------------------------------------------------- 569 * Power Management 570 */ 571 572 static void __thp7312_power_off(struct thp7312_device *thp7312) 573 { 574 regulator_bulk_disable(ARRAY_SIZE(thp7312->supplies), thp7312->supplies); 575 clk_disable_unprepare(thp7312->iclk); 576 } 577 578 static void thp7312_power_off(struct thp7312_device *thp7312) 579 { 580 __thp7312_power_off(thp7312); 581 } 582 583 static int __thp7312_power_on(struct thp7312_device *thp7312) 584 { 585 struct device *dev = thp7312->dev; 586 int ret; 587 588 ret = regulator_bulk_enable(ARRAY_SIZE(thp7312->supplies), 589 thp7312->supplies); 590 if (ret < 0) 591 return ret; 592 593 ret = clk_prepare_enable(thp7312->iclk); 594 if (ret < 0) { 595 dev_err(dev, "clk prepare enable failed\n"); 596 regulator_bulk_disable(ARRAY_SIZE(thp7312->supplies), 597 thp7312->supplies); 598 return ret; 599 } 600 601 /* 602 * We cannot assume that turning off and on again will reset, so do a 603 * software reset on power up. 604 */ 605 thp7312_reset(thp7312); 606 607 return 0; 608 } 609 610 static int thp7312_power_on(struct thp7312_device *thp7312) 611 { 612 int ret; 613 614 ret = __thp7312_power_on(thp7312); 615 if (ret < 0) 616 return ret; 617 618 ret = thp7312_check_status_stream_mode(thp7312); 619 if (ret < 0) 620 goto error; 621 622 ret = thp7312_set_mipi_lanes(thp7312); 623 if (ret) 624 goto error; 625 626 return 0; 627 628 error: 629 thp7312_power_off(thp7312); 630 return ret; 631 } 632 633 static int __maybe_unused thp7312_pm_runtime_suspend(struct device *dev) 634 { 635 struct v4l2_subdev *sd = dev_get_drvdata(dev); 636 struct thp7312_device *thp7312 = to_thp7312_dev(sd); 637 638 thp7312_power_off(thp7312); 639 640 thp7312->ctrls_applied = false; 641 642 return 0; 643 } 644 645 static int __maybe_unused thp7312_pm_runtime_resume(struct device *dev) 646 { 647 struct v4l2_subdev *sd = dev_get_drvdata(dev); 648 struct thp7312_device *thp7312 = to_thp7312_dev(sd); 649 650 return thp7312_power_on(thp7312); 651 } 652 653 static const struct dev_pm_ops thp7312_pm_ops = { 654 SET_RUNTIME_PM_OPS(thp7312_pm_runtime_suspend, 655 thp7312_pm_runtime_resume, NULL) 656 }; 657 658 /* ----------------------------------------------------------------------------- 659 * V4L2 Subdev Operations 660 */ 661 662 static bool thp7312_find_bus_code(u32 code) 663 { 664 unsigned int i; 665 666 for (i = 0; i < ARRAY_SIZE(thp7312_colour_fmts); ++i) { 667 if (thp7312_colour_fmts[i] == code) 668 return true; 669 } 670 671 return false; 672 } 673 674 static int thp7312_enum_mbus_code(struct v4l2_subdev *sd, 675 struct v4l2_subdev_state *sd_state, 676 struct v4l2_subdev_mbus_code_enum *code) 677 { 678 if (code->index >= ARRAY_SIZE(thp7312_colour_fmts)) 679 return -EINVAL; 680 681 code->code = thp7312_colour_fmts[code->index]; 682 683 return 0; 684 } 685 686 static int thp7312_enum_frame_size(struct v4l2_subdev *sd, 687 struct v4l2_subdev_state *sd_state, 688 struct v4l2_subdev_frame_size_enum *fse) 689 { 690 if (!thp7312_find_bus_code(fse->code)) 691 return -EINVAL; 692 693 if (fse->index >= ARRAY_SIZE(thp7312_mode_info_data)) 694 return -EINVAL; 695 696 fse->min_width = thp7312_mode_info_data[fse->index].width; 697 fse->max_width = fse->min_width; 698 fse->min_height = thp7312_mode_info_data[fse->index].height; 699 fse->max_height = fse->min_height; 700 701 return 0; 702 } 703 704 static int thp7312_enum_frame_interval(struct v4l2_subdev *sd, 705 struct v4l2_subdev_state *sd_state, 706 struct v4l2_subdev_frame_interval_enum *fie) 707 { 708 const struct thp7312_frame_rate *rate; 709 const struct thp7312_mode_info *mode; 710 unsigned int index = fie->index; 711 712 if (!thp7312_find_bus_code(fie->code)) 713 return -EINVAL; 714 715 mode = thp7312_find_mode(fie->width, fie->height, false); 716 if (!mode) 717 return -EINVAL; 718 719 for (rate = mode->rates; rate->fps; ++rate, --index) { 720 if (!index) { 721 fie->interval.numerator = 1; 722 fie->interval.denominator = rate->fps; 723 724 return 0; 725 } 726 } 727 728 return -EINVAL; 729 } 730 731 static int thp7312_set_fmt(struct v4l2_subdev *sd, 732 const struct v4l2_subdev_client_info *ci, 733 struct v4l2_subdev_state *sd_state, 734 struct v4l2_subdev_format *format) 735 { 736 struct thp7312_device *thp7312 = to_thp7312_dev(sd); 737 struct v4l2_mbus_framefmt *mbus_fmt = &format->format; 738 struct v4l2_mbus_framefmt *fmt; 739 struct v4l2_fract *interval; 740 const struct thp7312_mode_info *mode; 741 742 if (!thp7312_find_bus_code(mbus_fmt->code)) 743 mbus_fmt->code = thp7312_colour_fmts[0]; 744 745 mode = thp7312_find_mode(mbus_fmt->width, mbus_fmt->height, true); 746 747 fmt = v4l2_subdev_state_get_format(sd_state, 0); 748 749 fmt->code = mbus_fmt->code; 750 fmt->width = mode->width; 751 fmt->height = mode->height; 752 fmt->colorspace = V4L2_COLORSPACE_SRGB; 753 fmt->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(fmt->colorspace); 754 fmt->quantization = V4L2_QUANTIZATION_FULL_RANGE; 755 fmt->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(fmt->colorspace); 756 757 *mbus_fmt = *fmt; 758 759 interval = v4l2_subdev_state_get_interval(sd_state, 0); 760 interval->numerator = 1; 761 interval->denominator = mode->rates[0].fps; 762 763 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) 764 thp7312->link_freq = mode->rates[0].link_freq; 765 766 return 0; 767 } 768 769 static int thp7312_set_frame_interval(struct v4l2_subdev *sd, 770 struct v4l2_subdev_state *sd_state, 771 struct v4l2_subdev_frame_interval *fi) 772 { 773 struct thp7312_device *thp7312 = to_thp7312_dev(sd); 774 const struct thp7312_mode_info *mode; 775 const struct thp7312_frame_rate *rate; 776 const struct v4l2_mbus_framefmt *fmt; 777 struct v4l2_fract *interval; 778 unsigned int fps; 779 780 /* Avoid divisions by 0, pick the highest frame if the interval is 0. */ 781 fps = fi->interval.numerator 782 ? DIV_ROUND_CLOSEST(fi->interval.denominator, fi->interval.numerator) 783 : UINT_MAX; 784 785 fmt = v4l2_subdev_state_get_format(sd_state, 0); 786 mode = thp7312_find_mode(fmt->width, fmt->height, false); 787 rate = thp7312_find_rate(mode, fps, true); 788 789 interval = v4l2_subdev_state_get_interval(sd_state, 0); 790 interval->numerator = 1; 791 interval->denominator = rate->fps; 792 793 if (fi->which == V4L2_SUBDEV_FORMAT_ACTIVE) 794 thp7312->link_freq = rate->link_freq; 795 796 fi->interval = *interval; 797 798 return 0; 799 } 800 801 static int thp7312_s_stream(struct v4l2_subdev *sd, int enable) 802 { 803 struct thp7312_device *thp7312 = to_thp7312_dev(sd); 804 struct v4l2_subdev_state *sd_state; 805 int ret; 806 807 sd_state = v4l2_subdev_lock_and_get_active_state(sd); 808 809 if (!enable) { 810 thp7312_stream_enable(thp7312, false); 811 812 pm_runtime_put_autosuspend(thp7312->dev); 813 814 v4l2_subdev_unlock_state(sd_state); 815 816 return 0; 817 } 818 819 ret = pm_runtime_resume_and_get(thp7312->dev); 820 if (ret) 821 goto finish_unlock; 822 823 ret = thp7312_init_mode(thp7312, sd_state); 824 if (ret) 825 goto finish_pm; 826 827 if (!thp7312->ctrls_applied) { 828 ret = __v4l2_ctrl_handler_setup(&thp7312->ctrl_handler); 829 if (ret) 830 goto finish_pm; 831 832 thp7312->ctrls_applied = true; 833 } 834 835 ret = thp7312_stream_enable(thp7312, true); 836 if (ret) 837 goto finish_pm; 838 839 goto finish_unlock; 840 841 finish_pm: 842 pm_runtime_put_autosuspend(thp7312->dev); 843 finish_unlock: 844 v4l2_subdev_unlock_state(sd_state); 845 846 return ret; 847 } 848 849 static int thp7312_init_state(struct v4l2_subdev *sd, 850 struct v4l2_subdev_state *sd_state) 851 { 852 const struct thp7312_mode_info *default_mode = &thp7312_mode_info_data[0]; 853 struct v4l2_mbus_framefmt *fmt; 854 struct v4l2_fract *interval; 855 856 fmt = v4l2_subdev_state_get_format(sd_state, 0); 857 interval = v4l2_subdev_state_get_interval(sd_state, 0); 858 859 /* 860 * default init sequence initialize thp7312 to 861 * YUV422 YUYV VGA@30fps 862 */ 863 fmt->code = MEDIA_BUS_FMT_YUYV8_1X16; 864 fmt->colorspace = V4L2_COLORSPACE_SRGB; 865 fmt->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(fmt->colorspace); 866 fmt->quantization = V4L2_QUANTIZATION_FULL_RANGE; 867 fmt->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(fmt->colorspace); 868 fmt->width = default_mode->width; 869 fmt->height = default_mode->height; 870 fmt->field = V4L2_FIELD_NONE; 871 872 interval->numerator = 1; 873 interval->denominator = default_mode->rates[0].fps; 874 875 return 0; 876 } 877 878 static const struct v4l2_subdev_core_ops thp7312_core_ops = { 879 .log_status = v4l2_ctrl_subdev_log_status, 880 }; 881 882 static const struct v4l2_subdev_video_ops thp7312_video_ops = { 883 .s_stream = thp7312_s_stream, 884 }; 885 886 static const struct v4l2_subdev_pad_ops thp7312_pad_ops = { 887 .enum_mbus_code = thp7312_enum_mbus_code, 888 .get_fmt = v4l2_subdev_get_fmt, 889 .set_fmt = thp7312_set_fmt, 890 .get_frame_interval = v4l2_subdev_get_frame_interval, 891 .set_frame_interval = thp7312_set_frame_interval, 892 .enum_frame_size = thp7312_enum_frame_size, 893 .enum_frame_interval = thp7312_enum_frame_interval, 894 }; 895 896 static const struct v4l2_subdev_ops thp7312_subdev_ops = { 897 .core = &thp7312_core_ops, 898 .video = &thp7312_video_ops, 899 .pad = &thp7312_pad_ops, 900 }; 901 902 static const struct v4l2_subdev_internal_ops thp7312_internal_ops = { 903 .init_state = thp7312_init_state, 904 }; 905 906 /* ----------------------------------------------------------------------------- 907 * V4L2 Control Operations 908 */ 909 910 static inline struct thp7312_device *to_thp7312_from_ctrl(struct v4l2_ctrl *ctrl) 911 { 912 return container_of(ctrl->handler, struct thp7312_device, ctrl_handler); 913 } 914 915 /* 0: 3000cm, 18: 8cm */ 916 static const u16 thp7312_focus_values[] = { 917 3000, 1000, 600, 450, 350, 918 290, 240, 200, 170, 150, 919 140, 130, 120, 110, 100, 920 93, 87, 83, 80, 921 }; 922 923 static int thp7312_set_focus(struct thp7312_device *thp7312) 924 { 925 enum thp7312_focus_state new_state = thp7312->focus_state; 926 bool continuous; 927 u8 af_control; 928 u8 af_setting; 929 int ret = 0; 930 931 /* Start by programming the manual focus position if it has changed. */ 932 if (thp7312->focus_absolute->is_new) { 933 unsigned int value; 934 935 value = thp7312_focus_values[thp7312->focus_absolute->val]; 936 937 ret = cci_write(thp7312->regmap, 938 THP7312_REG_MANUAL_FOCUS_POSITION, value, NULL); 939 if (ret) 940 return ret; 941 } 942 943 /* Calculate the new focus state. */ 944 switch (thp7312->focus_state) { 945 case THP7312_FOCUS_STATE_MANUAL: 946 default: 947 if (thp7312->focus_auto->val) 948 new_state = THP7312_FOCUS_STATE_AUTO; 949 else if (thp7312->focus_start->is_new) 950 new_state = THP7312_FOCUS_STATE_ONESHOT; 951 break; 952 953 case THP7312_FOCUS_STATE_AUTO: 954 if (!thp7312->focus_auto->val) 955 new_state = THP7312_FOCUS_STATE_LOCKED; 956 break; 957 958 case THP7312_FOCUS_STATE_LOCKED: 959 if (thp7312->focus_auto->val) 960 new_state = THP7312_FOCUS_STATE_AUTO; 961 else if (thp7312->focus_start->is_new) 962 new_state = THP7312_FOCUS_STATE_ONESHOT; 963 else if (thp7312->focus_absolute->is_new) 964 new_state = THP7312_FOCUS_STATE_MANUAL; 965 break; 966 967 case THP7312_FOCUS_STATE_ONESHOT: 968 if (thp7312->focus_auto->val) 969 new_state = THP7312_FOCUS_STATE_AUTO; 970 else if (thp7312->focus_start->is_new) 971 new_state = THP7312_FOCUS_STATE_ONESHOT; 972 else if (thp7312->focus_absolute->is_new) 973 new_state = THP7312_FOCUS_STATE_MANUAL; 974 break; 975 } 976 977 /* 978 * If neither the state nor the focus method has changed, and no new 979 * one-shot focus is requested, there's nothing new to program to the 980 * hardware. 981 */ 982 if (thp7312->focus_state == new_state && 983 !thp7312->focus_method->is_new && !thp7312->focus_start->is_new) 984 return 0; 985 986 continuous = new_state == THP7312_FOCUS_STATE_MANUAL || 987 new_state == THP7312_FOCUS_STATE_ONESHOT; 988 989 switch (thp7312->focus_method->val) { 990 case THP7312_FOCUS_METHOD_CONTRAST: 991 default: 992 af_setting = continuous 993 ? THP7312_REG_AF_SETTING_CONTINUOUS_CONTRAST 994 : THP7312_REG_AF_SETTING_ONESHOT_CONTRAST; 995 break; 996 case THP7312_FOCUS_METHOD_PDAF: 997 af_setting = continuous 998 ? THP7312_REG_AF_SETTING_CONTINUOUS_PDAF 999 : THP7312_REG_AF_SETTING_ONESHOT_PDAF; 1000 break; 1001 case THP7312_FOCUS_METHOD_HYBRID: 1002 af_setting = continuous 1003 ? THP7312_REG_AF_SETTING_CONTINUOUS_HYBRID 1004 : THP7312_REG_AF_SETTING_ONESHOT_HYBRID; 1005 break; 1006 } 1007 1008 switch (new_state) { 1009 case THP7312_FOCUS_STATE_MANUAL: 1010 default: 1011 af_control = THP7312_REG_AF_CONTROL_MANUAL; 1012 break; 1013 case THP7312_FOCUS_STATE_AUTO: 1014 case THP7312_FOCUS_STATE_ONESHOT: 1015 af_control = THP7312_REG_AF_CONTROL_AF; 1016 break; 1017 case THP7312_FOCUS_STATE_LOCKED: 1018 af_control = THP7312_REG_AF_CONTROL_LOCK; 1019 break; 1020 } 1021 1022 cci_write(thp7312->regmap, THP7312_REG_AF_SETTING, af_setting, &ret); 1023 1024 if (new_state == THP7312_FOCUS_STATE_MANUAL && 1025 (thp7312->focus_state == THP7312_FOCUS_STATE_AUTO || 1026 thp7312->focus_state == THP7312_FOCUS_STATE_ONESHOT)) { 1027 /* When switching to manual state, lock AF first. */ 1028 cci_write(thp7312->regmap, THP7312_REG_AF_CONTROL, 1029 THP7312_REG_AF_CONTROL_LOCK, &ret); 1030 } 1031 1032 cci_write(thp7312->regmap, THP7312_REG_AF_CONTROL, af_control, &ret); 1033 1034 if (ret) 1035 return ret; 1036 1037 thp7312->focus_state = new_state; 1038 1039 return 0; 1040 } 1041 1042 static int thp7312_s_ctrl(struct v4l2_ctrl *ctrl) 1043 { 1044 struct thp7312_device *thp7312 = to_thp7312_from_ctrl(ctrl); 1045 int ret = 0; 1046 u8 value; 1047 1048 if (ctrl->flags & V4L2_CTRL_FLAG_INACTIVE) 1049 return -EINVAL; 1050 1051 if (!pm_runtime_get_if_active(thp7312->dev)) 1052 return 0; 1053 1054 switch (ctrl->id) { 1055 case V4L2_CID_BRIGHTNESS: 1056 cci_write(thp7312->regmap, THP7312_REG_BRIGHTNESS, 1057 ctrl->val + 10, &ret); 1058 break; 1059 1060 case V4L2_CID_THP7312_LOW_LIGHT_COMPENSATION: 1061 /* 0 = Auto adjust frame rate, 1 = Fix frame rate */ 1062 cci_write(thp7312->regmap, THP7312_REG_AE_FIX_FRAME_RATE, 1063 ctrl->val ? 0 : 1, &ret); 1064 break; 1065 1066 case V4L2_CID_FOCUS_AUTO: 1067 case V4L2_CID_FOCUS_ABSOLUTE: 1068 case V4L2_CID_AUTO_FOCUS_START: 1069 case V4L2_CID_THP7312_AUTO_FOCUS_METHOD: 1070 ret = thp7312_set_focus(thp7312); 1071 break; 1072 1073 case V4L2_CID_HFLIP: 1074 case V4L2_CID_VFLIP: 1075 value = (thp7312->hflip->val ? THP7312_REG_FLIP_MIRROR_MIRROR : 0) 1076 | (thp7312->vflip->val ? THP7312_REG_FLIP_MIRROR_FLIP : 0); 1077 1078 cci_write(thp7312->regmap, THP7312_REG_FLIP_MIRROR, value, &ret); 1079 break; 1080 1081 case V4L2_CID_THP7312_NOISE_REDUCTION_AUTO: 1082 case V4L2_CID_THP7312_NOISE_REDUCTION_ABSOLUTE: 1083 value = thp7312->noise_reduction_auto->val ? 0 1084 : THP7312_REG_NOISE_REDUCTION_FIXED | 1085 thp7312->noise_reduction_absolute->val; 1086 1087 cci_write(thp7312->regmap, THP7312_REG_NOISE_REDUCTION, value, 1088 &ret); 1089 break; 1090 1091 case V4L2_CID_AUTO_WHITE_BALANCE: 1092 value = ctrl->val ? THP7312_WB_MODE_AUTO : THP7312_WB_MODE_MANUAL; 1093 1094 cci_write(thp7312->regmap, THP7312_REG_WB_MODE, value, &ret); 1095 break; 1096 1097 case V4L2_CID_RED_BALANCE: 1098 cci_write(thp7312->regmap, THP7312_REG_MANUAL_WB_RED_GAIN, 1099 ctrl->val, &ret); 1100 break; 1101 1102 case V4L2_CID_BLUE_BALANCE: 1103 cci_write(thp7312->regmap, THP7312_REG_MANUAL_WB_BLUE_GAIN, 1104 ctrl->val, &ret); 1105 break; 1106 1107 case V4L2_CID_AUTO_EXPOSURE_BIAS: 1108 cci_write(thp7312->regmap, THP7312_REG_AE_EXPOSURE_COMPENSATION, 1109 ctrl->val, &ret); 1110 break; 1111 1112 case V4L2_CID_POWER_LINE_FREQUENCY: 1113 if (ctrl->val == V4L2_CID_POWER_LINE_FREQUENCY_60HZ) { 1114 value = THP7312_AE_FLICKER_MODE_60; 1115 } else if (ctrl->val == V4L2_CID_POWER_LINE_FREQUENCY_50HZ) { 1116 value = THP7312_AE_FLICKER_MODE_50; 1117 } else { 1118 if (thp7312->fw_version == THP7312_FW_VERSION(40, 3)) { 1119 /* THP7312_AE_FLICKER_MODE_DISABLE is not supported */ 1120 value = THP7312_AE_FLICKER_MODE_50; 1121 } else { 1122 value = THP7312_AE_FLICKER_MODE_DISABLE; 1123 } 1124 } 1125 1126 cci_write(thp7312->regmap, THP7312_REG_AE_FLICKER_MODE, 1127 value, &ret); 1128 break; 1129 1130 case V4L2_CID_SATURATION: 1131 cci_write(thp7312->regmap, THP7312_REG_SATURATION, 1132 ctrl->val, &ret); 1133 break; 1134 1135 case V4L2_CID_CONTRAST: 1136 cci_write(thp7312->regmap, THP7312_REG_CONTRAST, 1137 ctrl->val, &ret); 1138 break; 1139 1140 case V4L2_CID_SHARPNESS: 1141 cci_write(thp7312->regmap, THP7312_REG_SHARPNESS, 1142 ctrl->val, &ret); 1143 break; 1144 1145 default: 1146 break; 1147 } 1148 1149 pm_runtime_put_autosuspend(thp7312->dev); 1150 1151 return ret; 1152 } 1153 1154 static const struct v4l2_ctrl_ops thp7312_ctrl_ops = { 1155 .s_ctrl = thp7312_s_ctrl, 1156 }; 1157 1158 /* 1159 * Refer to Documentation/userspace-api/media/drivers/thp7312.rst for details. 1160 */ 1161 static const struct v4l2_ctrl_config thp7312_ctrl_focus_method_cdaf = { 1162 .ops = &thp7312_ctrl_ops, 1163 .id = V4L2_CID_THP7312_AUTO_FOCUS_METHOD, 1164 .name = "Auto-Focus Method", 1165 .type = V4L2_CTRL_TYPE_INTEGER, 1166 .min = THP7312_FOCUS_METHOD_CONTRAST, 1167 .def = THP7312_FOCUS_METHOD_CONTRAST, 1168 .max = THP7312_FOCUS_METHOD_CONTRAST, 1169 .step = 1, 1170 }; 1171 1172 static const struct v4l2_ctrl_config thp7312_ctrl_focus_method_pdaf = { 1173 .ops = &thp7312_ctrl_ops, 1174 .id = V4L2_CID_THP7312_AUTO_FOCUS_METHOD, 1175 .name = "Auto-Focus Method", 1176 .type = V4L2_CTRL_TYPE_INTEGER, 1177 .min = THP7312_FOCUS_METHOD_CONTRAST, 1178 .def = THP7312_FOCUS_METHOD_HYBRID, 1179 .max = THP7312_FOCUS_METHOD_HYBRID, 1180 .step = 1, 1181 }; 1182 1183 static const struct v4l2_ctrl_config thp7312_v4l2_ctrls_custom[] = { 1184 { 1185 .ops = &thp7312_ctrl_ops, 1186 .id = V4L2_CID_THP7312_LOW_LIGHT_COMPENSATION, 1187 .name = "Low Light Compensation", 1188 .type = V4L2_CTRL_TYPE_BOOLEAN, 1189 .min = 0, 1190 .def = 1, 1191 .max = 1, 1192 .step = 1, 1193 }, { 1194 .ops = &thp7312_ctrl_ops, 1195 .id = V4L2_CID_THP7312_NOISE_REDUCTION_AUTO, 1196 .name = "Noise Reduction Auto", 1197 .type = V4L2_CTRL_TYPE_BOOLEAN, 1198 .min = 0, 1199 .def = 1, 1200 .max = 1, 1201 .step = 1, 1202 }, { 1203 .ops = &thp7312_ctrl_ops, 1204 .id = V4L2_CID_THP7312_NOISE_REDUCTION_ABSOLUTE, 1205 .name = "Noise Reduction Level", 1206 .type = V4L2_CTRL_TYPE_INTEGER, 1207 .min = 0, 1208 .def = 0, 1209 .max = 10, 1210 .step = 1, 1211 }, 1212 }; 1213 1214 static const s64 exp_bias_qmenu[] = { 1215 -2000, -1667, -1333, -1000, -667, -333, 0, 333, 667, 1000, 1333, 1667, 2000 1216 }; 1217 1218 static int thp7312_init_controls(struct thp7312_device *thp7312) 1219 { 1220 struct v4l2_ctrl_handler *hdl = &thp7312->ctrl_handler; 1221 struct device *dev = thp7312->dev; 1222 struct v4l2_fwnode_device_properties props; 1223 struct v4l2_ctrl *link_freq; 1224 unsigned int num_controls; 1225 unsigned int i; 1226 u8 af_support; 1227 int ret; 1228 1229 /* 1230 * Check what auto-focus methods the connected sensor supports, if any. 1231 * Firmwares before v90.03 didn't expose the AF_SUPPORT register, 1232 * consider both CDAF and PDAF as supported in that case. 1233 */ 1234 if (thp7312->fw_version >= THP7312_FW_VERSION(90, 3)) { 1235 u64 val; 1236 1237 ret = cci_read(thp7312->regmap, THP7312_REG_AF_SUPPORT, &val, 1238 NULL); 1239 if (ret) 1240 return ret; 1241 1242 af_support = val & (THP7312_AF_SUPPORT_PDAF | 1243 THP7312_AF_SUPPORT_CONTRAST); 1244 } else { 1245 af_support = THP7312_AF_SUPPORT_PDAF 1246 | THP7312_AF_SUPPORT_CONTRAST; 1247 } 1248 1249 num_controls = 14 + ARRAY_SIZE(thp7312_v4l2_ctrls_custom) 1250 + (af_support ? 4 : 0); 1251 1252 v4l2_ctrl_handler_init(hdl, num_controls); 1253 1254 if (af_support) { 1255 const struct v4l2_ctrl_config *af_method; 1256 1257 af_method = af_support & THP7312_AF_SUPPORT_PDAF 1258 ? &thp7312_ctrl_focus_method_pdaf 1259 : &thp7312_ctrl_focus_method_cdaf; 1260 1261 thp7312->focus_state = THP7312_FOCUS_STATE_MANUAL; 1262 1263 thp7312->focus_auto = 1264 v4l2_ctrl_new_std(hdl, &thp7312_ctrl_ops, 1265 V4L2_CID_FOCUS_AUTO, 1266 0, 1, 1, 1); 1267 thp7312->focus_absolute = 1268 v4l2_ctrl_new_std(hdl, &thp7312_ctrl_ops, 1269 V4L2_CID_FOCUS_ABSOLUTE, 1270 0, ARRAY_SIZE(thp7312_focus_values), 1271 1, 0); 1272 thp7312->focus_method = 1273 v4l2_ctrl_new_custom(hdl, af_method, NULL); 1274 thp7312->focus_start = 1275 v4l2_ctrl_new_std(hdl, &thp7312_ctrl_ops, 1276 V4L2_CID_AUTO_FOCUS_START, 1277 1, 1, 1, 1); 1278 1279 v4l2_ctrl_cluster(4, &thp7312->focus_auto); 1280 } 1281 1282 v4l2_ctrl_new_std(hdl, &thp7312_ctrl_ops, V4L2_CID_AUTO_WHITE_BALANCE, 1283 0, 1, 1, 1); 1284 /* 32: 1x, 255: 7.95x */ 1285 v4l2_ctrl_new_std(hdl, &thp7312_ctrl_ops, V4L2_CID_RED_BALANCE, 1286 32, 255, 1, 64); 1287 /* 32: 1x, 255: 7.95x */ 1288 v4l2_ctrl_new_std(hdl, &thp7312_ctrl_ops, V4L2_CID_BLUE_BALANCE, 1289 32, 255, 1, 50); 1290 1291 v4l2_ctrl_new_std(hdl, &thp7312_ctrl_ops, V4L2_CID_BRIGHTNESS, 1292 -10, 10, 1, 0); 1293 v4l2_ctrl_new_std(hdl, &thp7312_ctrl_ops, V4L2_CID_SATURATION, 1294 0, 31, 1, 10); 1295 v4l2_ctrl_new_std(hdl, &thp7312_ctrl_ops, V4L2_CID_CONTRAST, 1296 0, 20, 1, 10); 1297 v4l2_ctrl_new_std(hdl, &thp7312_ctrl_ops, V4L2_CID_SHARPNESS, 1298 0, 31, 1, 8); 1299 1300 thp7312->hflip = v4l2_ctrl_new_std(hdl, &thp7312_ctrl_ops, 1301 V4L2_CID_HFLIP, 0, 1, 1, 0); 1302 thp7312->vflip = v4l2_ctrl_new_std(hdl, &thp7312_ctrl_ops, 1303 V4L2_CID_VFLIP, 0, 1, 1, 0); 1304 1305 v4l2_ctrl_cluster(2, &thp7312->hflip); 1306 1307 v4l2_ctrl_new_int_menu(hdl, &thp7312_ctrl_ops, 1308 V4L2_CID_AUTO_EXPOSURE_BIAS, 1309 ARRAY_SIZE(exp_bias_qmenu) - 1, 1310 ARRAY_SIZE(exp_bias_qmenu) / 2, exp_bias_qmenu); 1311 1312 v4l2_ctrl_new_std_menu(hdl, &thp7312_ctrl_ops, 1313 V4L2_CID_POWER_LINE_FREQUENCY, 1314 V4L2_CID_POWER_LINE_FREQUENCY_60HZ, 0, 1315 V4L2_CID_POWER_LINE_FREQUENCY_50HZ); 1316 1317 thp7312->link_freq = thp7312_mode_info_data[0].rates[0].link_freq; 1318 1319 link_freq = v4l2_ctrl_new_int_menu(hdl, &thp7312_ctrl_ops, 1320 V4L2_CID_LINK_FREQ, 0, 0, 1321 &thp7312->link_freq); 1322 1323 /* Set properties from fwnode (e.g. rotation, orientation). */ 1324 ret = v4l2_fwnode_device_parse(dev, &props); 1325 if (ret) { 1326 dev_err(dev, "Failed to parse fwnode: %d\n", ret); 1327 goto error; 1328 } 1329 1330 ret = v4l2_ctrl_new_fwnode_properties(hdl, &thp7312_ctrl_ops, &props); 1331 if (ret) { 1332 dev_err(dev, "Failed to create new v4l2 ctrl for fwnode properties: %d\n", ret); 1333 goto error; 1334 } 1335 1336 for (i = 0; i < ARRAY_SIZE(thp7312_v4l2_ctrls_custom); i++) { 1337 const struct v4l2_ctrl_config *ctrl_cfg = 1338 &thp7312_v4l2_ctrls_custom[i]; 1339 struct v4l2_ctrl *ctrl; 1340 1341 ctrl = v4l2_ctrl_new_custom(hdl, ctrl_cfg, NULL); 1342 1343 if (ctrl_cfg->id == V4L2_CID_THP7312_NOISE_REDUCTION_AUTO) 1344 thp7312->noise_reduction_auto = ctrl; 1345 else if (ctrl_cfg->id == V4L2_CID_THP7312_NOISE_REDUCTION_ABSOLUTE) 1346 thp7312->noise_reduction_absolute = ctrl; 1347 } 1348 1349 v4l2_ctrl_cluster(2, &thp7312->noise_reduction_auto); 1350 1351 if (hdl->error) { 1352 dev_err(dev, "v4l2_ctrl_handler error\n"); 1353 ret = hdl->error; 1354 goto error; 1355 } 1356 1357 link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; 1358 1359 return ret; 1360 1361 error: 1362 v4l2_ctrl_handler_free(hdl); 1363 return ret; 1364 } 1365 1366 /* ----------------------------------------------------------------------------- 1367 * Firmware Update 1368 */ 1369 1370 /* 1371 * The firmware data is made of 128kB of RAM firmware, followed by a 1372 * variable-size "header". Both are stored in flash memory. 1373 */ 1374 #define THP7312_FW_RAM_SIZE (128 * 1024) 1375 #define THP7312_FW_MIN_SIZE (THP7312_FW_RAM_SIZE + 4) 1376 #define THP7312_FW_MAX_SIZE (THP7312_FW_RAM_SIZE + 64 * 1024) 1377 1378 /* 1379 * Data is first uploaded to the THP7312 128kB SRAM, and then written to flash. 1380 * The SRAM is exposed over I2C as 32kB banks, and up to 4kB of data can be 1381 * transferred in a single I2C write. 1382 */ 1383 #define THP7312_RAM_BANK_SIZE (32 * 1024) 1384 #define THP7312_FW_DOWNLOAD_UNIT (4 * 1024) 1385 1386 #define THP7312_FLASH_MEMORY_ERASE_TIMEOUT 40 1387 1388 #define THP7312_FLASH_MAX_REG_READ_SIZE 10 1389 #define THP7312_FLASH_MAX_REG_DATA_SIZE 10 1390 1391 static const u8 thp7312_cmd_config_flash_mem_if[] = { 1392 0xd5, 0x18, 0x00, 0x00, 0x00, 0x80 1393 }; 1394 1395 static const u8 thp7312_cmd_write_to_reg[] = { 1396 0xd5, 0x0c, 0x80, 0x00, 0x00, 0x00 1397 }; 1398 1399 static const u8 thp7312_cmd_read_reg[] = { 1400 0xd5, 0x04 1401 }; 1402 1403 /* 1404 * THP7312 Write data from RAM to Flash Memory 1405 * Command ID FF700F 1406 * Format: FF700F AA AA AA BB BB BB 1407 * AA AA AA: destination start address 1408 * BB BB BB: (write size - 1) 1409 * Source address always starts from 0 1410 */ 1411 static const u8 thp7312_cmd_write_ram_to_flash[] = { 0xff, 0x70, 0x0f }; 1412 1413 /* 1414 * THP7312 Calculate CRC command 1415 * Command ID: FF70 09 1416 * Format: FF70 09 AA AA AA BB BB BB 1417 * AA AA AA: Start address of calculation 1418 * BB BB BB: (calculate size - 1) 1419 */ 1420 static const u8 thp7312_cmd_calc_crc[] = { 0xff, 0x70, 0x09 }; 1421 1422 static const u8 thp7312_jedec_rdid[] = { SPINOR_OP_RDID, 0x00, 0x00, 0x00 }; 1423 static const u8 thp7312_jedec_rdsr[] = { SPINOR_OP_RDSR, 0x00, 0x00, 0x00 }; 1424 static const u8 thp7312_jedec_wen[] = { SPINOR_OP_WREN }; 1425 1426 static int thp7312_read_firmware_version(struct thp7312_device *thp7312) 1427 { 1428 u64 val = 0; 1429 int ret = 0; 1430 u8 major; 1431 u8 minor; 1432 1433 cci_read(thp7312->regmap, THP7312_REG_FIRMWARE_VERSION_1, &val, &ret); 1434 major = val; 1435 1436 cci_read(thp7312->regmap, THP7312_REG_FIRMWARE_VERSION_2, &val, &ret); 1437 minor = val; 1438 1439 thp7312->fw_version = THP7312_FW_VERSION(major, minor); 1440 return ret; 1441 } 1442 1443 static int thp7312_write_buf(struct thp7312_device *thp7312, 1444 const u8 *write_buf, u16 write_size) 1445 { 1446 struct i2c_client *client = to_i2c_client(thp7312->dev); 1447 int ret; 1448 1449 ret = i2c_master_send(client, write_buf, write_size); 1450 return ret >= 0 ? 0 : ret; 1451 } 1452 1453 static int __thp7312_flash_reg_write(struct thp7312_device *thp7312, 1454 const u8 *write_buf, u16 write_size) 1455 { 1456 struct device *dev = thp7312->dev; 1457 u8 temp_write_buf[THP7312_FLASH_MAX_REG_DATA_SIZE + 2]; 1458 int ret; 1459 1460 if (write_size > THP7312_FLASH_MAX_REG_DATA_SIZE) { 1461 dev_err(dev, "%s: Write size error size = %d\n", 1462 __func__, write_size); 1463 return -EINVAL; 1464 } 1465 1466 ret = thp7312_write_buf(thp7312, thp7312_cmd_config_flash_mem_if, 1467 sizeof(thp7312_cmd_config_flash_mem_if)); 1468 if (ret < 0) { 1469 dev_err(dev, "%s: Failed to config flash memory IF: %d\n", 1470 __func__, ret); 1471 return ret; 1472 } 1473 1474 temp_write_buf[0] = 0xd5; 1475 temp_write_buf[1] = 0x00; 1476 memcpy((temp_write_buf + 2), write_buf, write_size); 1477 ret = thp7312_write_buf(thp7312, temp_write_buf, write_size + 2); 1478 if (ret < 0) 1479 return ret; 1480 1481 thp7312_write_buf(thp7312, thp7312_cmd_write_to_reg, 1482 sizeof(thp7312_cmd_write_to_reg)); 1483 1484 return 0; 1485 } 1486 1487 static int __thp7312_flash_reg_read(struct thp7312_device *thp7312, 1488 const u8 *write_buf, u16 write_size, 1489 u8 *read_buf, u16 read_size) 1490 { 1491 struct i2c_client *client = to_i2c_client(thp7312->dev); 1492 struct i2c_msg msgs[2]; 1493 int ret; 1494 1495 ret = __thp7312_flash_reg_write(thp7312, write_buf, write_size); 1496 if (ret) 1497 return ret; 1498 1499 msgs[0].addr = client->addr; 1500 msgs[0].flags = 0; 1501 msgs[0].len = sizeof(thp7312_cmd_read_reg); 1502 msgs[0].buf = (u8 *)thp7312_cmd_read_reg; 1503 1504 msgs[1].addr = client->addr; 1505 msgs[1].flags = I2C_M_RD; 1506 msgs[1].len = read_size; 1507 msgs[1].buf = read_buf; 1508 1509 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); 1510 return ret >= 0 ? 0 : ret; 1511 } 1512 1513 #define thp7312_flash_reg_write(thp7312, wrbuf) \ 1514 __thp7312_flash_reg_write(thp7312, wrbuf, sizeof(wrbuf)) 1515 1516 #define thp7312_flash_reg_read(thp7312, wrbuf, rdbuf) \ 1517 __thp7312_flash_reg_read(thp7312, wrbuf, sizeof(wrbuf), \ 1518 rdbuf, sizeof(rdbuf)) 1519 1520 static enum fw_upload_err thp7312_fw_prepare_config(struct thp7312_device *thp7312) 1521 { 1522 struct device *dev = thp7312->dev; 1523 int ret; 1524 1525 ret = cci_write(thp7312->regmap, THP7312_REG_FW_MEMORY_IO_SETTING, 1526 THP7312_FW_MEMORY_IO_GPIO0, NULL); 1527 if (ret) { 1528 dev_err(dev, "Failed to set flash memory I/O\n"); 1529 return FW_UPLOAD_ERR_HW_ERROR; 1530 } 1531 1532 /* Set max drivability. */ 1533 ret = cci_write(thp7312->regmap, THP7312_REG_FW_DRIVABILITY, 0x00777777, 1534 NULL); 1535 if (ret) { 1536 dev_err(dev, "Failed to set drivability: %d\n", ret); 1537 return FW_UPLOAD_ERR_HW_ERROR; 1538 } 1539 1540 return FW_UPLOAD_ERR_NONE; 1541 } 1542 1543 static enum fw_upload_err thp7312_fw_prepare_check(struct thp7312_device *thp7312) 1544 { 1545 struct device *dev = thp7312->dev; 1546 u8 read_buf[3] = { 0 }; 1547 int ret; 1548 1549 /* Get JEDEC ID */ 1550 ret = thp7312_flash_reg_read(thp7312, thp7312_jedec_rdid, read_buf); 1551 if (ret) { 1552 dev_err(dev, "Failed to get JEDEC ID: %d\n", ret); 1553 return FW_UPLOAD_ERR_HW_ERROR; 1554 } 1555 1556 dev_dbg(dev, "Flash Memory: JEDEC ID = 0x%x 0x%x 0x%x\n", 1557 read_buf[0], read_buf[1], read_buf[2]); 1558 1559 return FW_UPLOAD_ERR_NONE; 1560 } 1561 1562 static enum fw_upload_err thp7312_fw_prepare_reset(struct thp7312_device *thp7312) 1563 { 1564 struct device *dev = thp7312->dev; 1565 int ret; 1566 1567 ret = cci_write(thp7312->regmap, THP7312_REG_FW_RESET_FLASH, 0x81, NULL); 1568 if (ret) { 1569 dev_err(dev, "Failed to reset flash memory: %d\n", ret); 1570 return FW_UPLOAD_ERR_HW_ERROR; 1571 } 1572 1573 return FW_UPLOAD_ERR_NONE; 1574 } 1575 1576 /* TODO: Erase only the amount of blocks necessary */ 1577 static enum fw_upload_err thp7312_flash_erase(struct thp7312_device *thp7312) 1578 { 1579 struct device *dev = thp7312->dev; 1580 u8 read_buf[1] = { 0 }; 1581 unsigned int i; 1582 u8 block; 1583 int ret; 1584 1585 for (block = 0; block < 3; block++) { 1586 const u8 jedec_se[] = { SPINOR_OP_SE, block, 0x00, 0x00 }; 1587 1588 ret = thp7312_flash_reg_write(thp7312, thp7312_jedec_wen); 1589 if (ret < 0) { 1590 dev_err(dev, "Failed to enable flash for writing\n"); 1591 return FW_UPLOAD_ERR_RW_ERROR; 1592 } 1593 1594 ret = thp7312_flash_reg_write(thp7312, jedec_se); 1595 if (ret < 0) { 1596 dev_err(dev, "Failed to erase flash sector\n"); 1597 return FW_UPLOAD_ERR_RW_ERROR; 1598 } 1599 1600 for (i = 0; i < THP7312_FLASH_MEMORY_ERASE_TIMEOUT; i++) { 1601 usleep_range(100000, 101000); 1602 thp7312_flash_reg_read(thp7312, thp7312_jedec_rdsr, 1603 read_buf); 1604 1605 /* Check Busy bit. Busy == 0x0 means erase complete. */ 1606 if (!(read_buf[0] & SR_WIP)) 1607 break; 1608 } 1609 1610 if (i == THP7312_FLASH_MEMORY_ERASE_TIMEOUT) 1611 return FW_UPLOAD_ERR_TIMEOUT; 1612 } 1613 1614 thp7312_flash_reg_read(thp7312, thp7312_jedec_rdsr, read_buf); 1615 1616 /* Check WEL bit. */ 1617 if (read_buf[0] & SR_WEL) 1618 return FW_UPLOAD_ERR_HW_ERROR; 1619 1620 return FW_UPLOAD_ERR_NONE; 1621 } 1622 1623 static enum fw_upload_err 1624 thp7312_write_download_data_by_unit(struct thp7312_device *thp7312, 1625 unsigned int addr, const u8 *data, 1626 unsigned int size) 1627 { 1628 struct device *dev = thp7312->dev; 1629 u8 *write_buf = thp7312->fw_write_buf; 1630 int ret; 1631 1632 dev_dbg(dev, "%s: addr = 0x%04x, data = 0x%p, size = %u\n", 1633 __func__, addr, data, size); 1634 1635 write_buf[0] = (addr >> 8) & 0xff; 1636 write_buf[1] = (addr >> 0) & 0xff; 1637 memcpy(&write_buf[2], data, size); 1638 1639 /* 1640 * THP7312 Firmware download to RAM 1641 * Command ID (address to download): 0x0000 - 0x7fff 1642 * Format:: 0000 XX XX XX ........ XX 1643 */ 1644 ret = thp7312_write_buf(thp7312, write_buf, size + 2); 1645 if (ret < 0) 1646 dev_err(dev, "Unit transfer ERROR %s(): ret = %d\n", __func__, ret); 1647 1648 return ret >= 0 ? FW_UPLOAD_ERR_NONE : FW_UPLOAD_ERR_RW_ERROR; 1649 } 1650 1651 static enum fw_upload_err thp7312_fw_load_to_ram(struct thp7312_device *thp7312, 1652 const u8 *data, u32 size) 1653 { 1654 struct device *dev = thp7312->dev; 1655 enum fw_upload_err ret; 1656 unsigned int num_banks; 1657 unsigned int i, j; 1658 1659 num_banks = DIV_ROUND_UP(size, THP7312_RAM_BANK_SIZE); 1660 1661 dev_dbg(dev, "%s: loading %u bytes in SRAM (%u banks)\n", __func__, 1662 size, num_banks); 1663 1664 for (i = 0; i < num_banks; i++) { 1665 const u32 bank_addr = 0x10000000 | (i * THP7312_RAM_BANK_SIZE); 1666 unsigned int bank_size; 1667 unsigned int num_chunks; 1668 1669 ret = cci_write(thp7312->regmap, THP7312_REG_FW_DEST_BANK_ADDR, 1670 bank_addr, NULL); 1671 if (ret) 1672 return FW_UPLOAD_ERR_HW_ERROR; 1673 1674 bank_size = min_t(u32, size, THP7312_RAM_BANK_SIZE); 1675 num_chunks = DIV_ROUND_UP(bank_size, THP7312_FW_DOWNLOAD_UNIT); 1676 1677 dev_dbg(dev, "%s: loading %u bytes in SRAM bank %u (%u chunks)\n", 1678 __func__, bank_size, i, num_chunks); 1679 1680 for (j = 0 ; j < num_chunks; j++) { 1681 unsigned int chunk_addr; 1682 unsigned int chunk_size; 1683 1684 chunk_addr = j * THP7312_FW_DOWNLOAD_UNIT; 1685 chunk_size = min_t(u32, size, THP7312_FW_DOWNLOAD_UNIT); 1686 1687 ret = thp7312_write_download_data_by_unit(thp7312, chunk_addr, 1688 data, chunk_size); 1689 if (ret != FW_UPLOAD_ERR_NONE) { 1690 dev_err(dev, "Unit transfer ERROR at bank transfer %s(): %d\n", 1691 __func__, j); 1692 return ret; 1693 } 1694 1695 data += chunk_size; 1696 size -= chunk_size; 1697 } 1698 } 1699 1700 return FW_UPLOAD_ERR_NONE; 1701 } 1702 1703 static enum fw_upload_err thp7312_fw_write_to_flash(struct thp7312_device *thp7312, 1704 u32 dest, u32 write_size) 1705 { 1706 u8 command[sizeof(thp7312_cmd_write_ram_to_flash) + 6]; 1707 static const u32 cmd_size = sizeof(thp7312_cmd_write_ram_to_flash); 1708 u64 val; 1709 int ret; 1710 1711 memcpy(command, thp7312_cmd_write_ram_to_flash, cmd_size); 1712 1713 command[cmd_size] = (dest & 0xff0000) >> 16; 1714 command[cmd_size + 1] = (dest & 0x00ff00) >> 8; 1715 command[cmd_size + 2] = (dest & 0x0000ff); 1716 command[cmd_size + 3] = ((write_size - 1) & 0xff0000) >> 16; 1717 command[cmd_size + 4] = ((write_size - 1) & 0x00ff00) >> 8; 1718 command[cmd_size + 5] = ((write_size - 1) & 0x0000ff); 1719 1720 ret = thp7312_write_buf(thp7312, command, sizeof(command)); 1721 if (ret < 0) 1722 return FW_UPLOAD_ERR_RW_ERROR; 1723 1724 usleep_range(8000000, 8100000); 1725 1726 ret = cci_read(thp7312->regmap, THP7312_REG_FW_VERIFY_RESULT, &val, 1727 NULL); 1728 if (ret < 0) 1729 return FW_UPLOAD_ERR_RW_ERROR; 1730 1731 return val ? FW_UPLOAD_ERR_HW_ERROR : FW_UPLOAD_ERR_NONE; 1732 } 1733 1734 static enum fw_upload_err thp7312_fw_check_crc(struct thp7312_device *thp7312, 1735 const u8 *fw_data, u32 fw_size) 1736 { 1737 struct device *dev = thp7312->dev; 1738 u16 header_size = fw_size - THP7312_FW_RAM_SIZE; 1739 u8 command[sizeof(thp7312_cmd_calc_crc) + 6]; 1740 static const u32 cmd_size = sizeof(thp7312_cmd_calc_crc); 1741 u32 size = THP7312_FW_RAM_SIZE - 4; 1742 u32 fw_crc; 1743 u64 crc; 1744 int ret; 1745 1746 memcpy(command, thp7312_cmd_calc_crc, cmd_size); 1747 1748 command[cmd_size] = 0; 1749 command[cmd_size + 1] = (header_size >> 8) & 0xff; 1750 command[cmd_size + 2] = header_size & 0xff; 1751 1752 command[cmd_size + 3] = (size >> 16) & 0xff; 1753 command[cmd_size + 4] = (size >> 8) & 0xff; 1754 command[cmd_size + 5] = size & 0xff; 1755 1756 ret = thp7312_write_buf(thp7312, command, sizeof(command)); 1757 if (ret < 0) 1758 return FW_UPLOAD_ERR_RW_ERROR; 1759 1760 usleep_range(2000000, 2100000); 1761 1762 fw_crc = get_unaligned_be32(&fw_data[fw_size - 4]); 1763 1764 ret = cci_read(thp7312->regmap, THP7312_REG_FW_CRC_RESULT, &crc, NULL); 1765 if (ret < 0) 1766 return FW_UPLOAD_ERR_RW_ERROR; 1767 1768 if (fw_crc != crc) { 1769 dev_err(dev, "CRC mismatch: firmware 0x%08x, flash 0x%08llx\n", 1770 fw_crc, crc); 1771 return FW_UPLOAD_ERR_HW_ERROR; 1772 } 1773 1774 return FW_UPLOAD_ERR_NONE; 1775 } 1776 1777 static enum fw_upload_err thp7312_fw_prepare(struct fw_upload *fw_upload, 1778 const u8 *data, u32 size) 1779 { 1780 struct thp7312_device *thp7312 = fw_upload->dd_handle; 1781 struct device *dev = thp7312->dev; 1782 enum fw_upload_err ret; 1783 1784 mutex_lock(&thp7312->fw_lock); 1785 thp7312->fw_cancel = false; 1786 mutex_unlock(&thp7312->fw_lock); 1787 1788 if (size < THP7312_FW_MIN_SIZE || size > THP7312_FW_MAX_SIZE) { 1789 dev_err(dev, "%s: Invalid firmware size %d; must be between %d and %d\n", 1790 __func__, size, THP7312_FW_MIN_SIZE, THP7312_FW_MAX_SIZE); 1791 return FW_UPLOAD_ERR_INVALID_SIZE; 1792 } 1793 1794 ret = thp7312_fw_prepare_config(thp7312); 1795 if (ret != FW_UPLOAD_ERR_NONE) 1796 return ret; 1797 1798 ret = thp7312_fw_prepare_check(thp7312); 1799 if (ret != FW_UPLOAD_ERR_NONE) 1800 return ret; 1801 1802 ret = thp7312_fw_prepare_reset(thp7312); 1803 if (ret != FW_UPLOAD_ERR_NONE) 1804 return ret; 1805 1806 mutex_lock(&thp7312->fw_lock); 1807 ret = thp7312->fw_cancel ? FW_UPLOAD_ERR_CANCELED : FW_UPLOAD_ERR_NONE; 1808 mutex_unlock(&thp7312->fw_lock); 1809 1810 return ret; 1811 } 1812 1813 static enum fw_upload_err thp7312_fw_write(struct fw_upload *fw_upload, 1814 const u8 *data, u32 offset, 1815 u32 size, u32 *written) 1816 { 1817 struct thp7312_device *thp7312 = fw_upload->dd_handle; 1818 struct device *dev = thp7312->dev; 1819 u16 header_size = size - THP7312_FW_RAM_SIZE; 1820 enum fw_upload_err ret; 1821 bool cancel; 1822 1823 mutex_lock(&thp7312->fw_lock); 1824 cancel = thp7312->fw_cancel; 1825 mutex_unlock(&thp7312->fw_lock); 1826 1827 if (cancel) 1828 return FW_UPLOAD_ERR_CANCELED; 1829 1830 ret = thp7312_flash_erase(thp7312); 1831 if (ret != FW_UPLOAD_ERR_NONE) 1832 return ret; 1833 1834 ret = thp7312_fw_load_to_ram(thp7312, data, THP7312_FW_RAM_SIZE); 1835 if (ret != FW_UPLOAD_ERR_NONE) 1836 return ret; 1837 1838 ret = thp7312_fw_write_to_flash(thp7312, 0, 0x1ffff); 1839 if (ret != FW_UPLOAD_ERR_NONE) 1840 return ret; 1841 1842 ret = thp7312_fw_load_to_ram(thp7312, data + THP7312_FW_RAM_SIZE, header_size); 1843 if (ret != FW_UPLOAD_ERR_NONE) 1844 return ret; 1845 1846 ret = thp7312_fw_write_to_flash(thp7312, 0x20000, header_size - 1); 1847 if (ret != FW_UPLOAD_ERR_NONE) 1848 return ret; 1849 1850 ret = thp7312_fw_check_crc(thp7312, data, size); 1851 if (ret != FW_UPLOAD_ERR_NONE) 1852 return ret; 1853 1854 dev_info(dev, "Successfully wrote firmware\n"); 1855 1856 *written = size; 1857 return FW_UPLOAD_ERR_NONE; 1858 } 1859 1860 static enum fw_upload_err thp7312_fw_poll_complete(struct fw_upload *fw_upload) 1861 { 1862 return FW_UPLOAD_ERR_NONE; 1863 } 1864 1865 /* 1866 * This may be called asynchronously with an on-going update. All other 1867 * functions are called sequentially in a single thread. To avoid contention on 1868 * register accesses, only update the cancel_request flag. Other functions will 1869 * check this flag and handle the cancel request synchronously. 1870 */ 1871 static void thp7312_fw_cancel(struct fw_upload *fw_upload) 1872 { 1873 struct thp7312_device *thp7312 = fw_upload->dd_handle; 1874 1875 mutex_lock(&thp7312->fw_lock); 1876 thp7312->fw_cancel = true; 1877 mutex_unlock(&thp7312->fw_lock); 1878 } 1879 1880 static const struct fw_upload_ops thp7312_fw_upload_ops = { 1881 .prepare = thp7312_fw_prepare, 1882 .write = thp7312_fw_write, 1883 .poll_complete = thp7312_fw_poll_complete, 1884 .cancel = thp7312_fw_cancel, 1885 }; 1886 1887 static int thp7312_register_flash_mode(struct thp7312_device *thp7312) 1888 { 1889 struct device *dev = thp7312->dev; 1890 struct fw_upload *fwl; 1891 u64 val; 1892 int ret; 1893 1894 dev_info(dev, "booted in flash mode\n"); 1895 1896 mutex_init(&thp7312->fw_lock); 1897 1898 thp7312->fw_write_buf = devm_kzalloc(dev, THP7312_FW_DOWNLOAD_UNIT + 2, 1899 GFP_KERNEL); 1900 if (!thp7312->fw_write_buf) 1901 return -ENOMEM; 1902 1903 ret = __thp7312_power_on(thp7312); 1904 if (ret < 0) 1905 return dev_err_probe(dev, ret, "Failed to power on\n"); 1906 1907 ret = cci_read(thp7312->regmap, THP7312_REG_FW_STATUS, &val, NULL); 1908 if (ret) { 1909 dev_err_probe(dev, ret, "Camera status read failed\n"); 1910 goto error; 1911 } 1912 1913 fwl = firmware_upload_register(THIS_MODULE, dev, "thp7312-firmware", 1914 &thp7312_fw_upload_ops, thp7312); 1915 if (IS_ERR(fwl)) { 1916 ret = PTR_ERR(fwl); 1917 dev_err_probe(dev, ret, "Failed to register firmware upload\n"); 1918 goto error; 1919 } 1920 1921 thp7312->fwl = fwl; 1922 return 0; 1923 1924 error: 1925 __thp7312_power_off(thp7312); 1926 return ret; 1927 } 1928 1929 /* ----------------------------------------------------------------------------- 1930 * Probe & Remove 1931 */ 1932 1933 static int thp7312_get_regulators(struct thp7312_device *thp7312) 1934 { 1935 unsigned int i; 1936 1937 for (i = 0; i < ARRAY_SIZE(thp7312->supplies); i++) 1938 thp7312->supplies[i].supply = thp7312_supply_name[i]; 1939 1940 return devm_regulator_bulk_get(thp7312->dev, 1941 ARRAY_SIZE(thp7312->supplies), 1942 thp7312->supplies); 1943 } 1944 1945 static int thp7312_sensor_parse_dt(struct thp7312_device *thp7312, 1946 struct fwnode_handle *node) 1947 { 1948 struct device *dev = thp7312->dev; 1949 struct thp7312_sensor *sensor; 1950 const char *model; 1951 u8 data_lanes[4]; 1952 u32 values[4]; 1953 unsigned int i; 1954 u32 reg; 1955 int ret; 1956 1957 /* Retrieve the sensor index from the reg property. */ 1958 ret = fwnode_property_read_u32(node, "reg", ®); 1959 if (ret < 0) { 1960 dev_err(dev, "'reg' property missing in sensor node\n"); 1961 return -EINVAL; 1962 } 1963 1964 if (reg >= ARRAY_SIZE(thp7312->sensors)) { 1965 dev_err(dev, "Out-of-bounds 'reg' value %u\n", reg); 1966 return -EINVAL; 1967 } 1968 1969 sensor = &thp7312->sensors[reg]; 1970 if (sensor->info) { 1971 dev_err(dev, "Duplicate entry for sensor %u\n", reg); 1972 return -EINVAL; 1973 } 1974 1975 ret = fwnode_property_read_string(node, "thine,model", &model); 1976 if (ret < 0) { 1977 dev_err(dev, "'thine,model' property missing in sensor node\n"); 1978 return -EINVAL; 1979 } 1980 1981 for (i = 0; i < ARRAY_SIZE(thp7312_sensor_info); i++) { 1982 const struct thp7312_sensor_info *info = 1983 &thp7312_sensor_info[i]; 1984 1985 if (!strcmp(info->model, model)) { 1986 sensor->info = info; 1987 break; 1988 } 1989 } 1990 1991 if (!sensor->info) { 1992 dev_err(dev, "Unsupported sensor model %s\n", model); 1993 return -EINVAL; 1994 } 1995 1996 ret = fwnode_property_read_u32_array(node, "data-lanes", values, 1997 ARRAY_SIZE(values)); 1998 if (ret < 0) { 1999 dev_err(dev, "Failed to read property data-lanes: %d\n", ret); 2000 return ret; 2001 } 2002 2003 for (i = 0; i < ARRAY_SIZE(data_lanes); ++i) 2004 data_lanes[i] = values[i]; 2005 2006 ret = thp7312_map_data_lanes(&sensor->lane_remap, data_lanes, 2007 ARRAY_SIZE(data_lanes)); 2008 if (ret) { 2009 dev_err(dev, "Invalid sensor@%u data-lanes value\n", reg); 2010 return ret; 2011 } 2012 2013 return 0; 2014 } 2015 2016 static int thp7312_parse_dt(struct thp7312_device *thp7312) 2017 { 2018 struct v4l2_fwnode_endpoint ep = { 2019 .bus_type = V4L2_MBUS_CSI2_DPHY, 2020 }; 2021 struct device *dev = thp7312->dev; 2022 struct fwnode_handle *endpoint; 2023 struct fwnode_handle *sensors; 2024 unsigned int num_sensors = 0; 2025 struct fwnode_handle *node; 2026 int ret; 2027 2028 endpoint = fwnode_graph_get_next_endpoint(dev_fwnode(dev), NULL); 2029 if (!endpoint) 2030 return dev_err_probe(dev, -EINVAL, "Endpoint node not found\n"); 2031 2032 ret = v4l2_fwnode_endpoint_parse(endpoint, &ep); 2033 fwnode_handle_put(endpoint); 2034 if (ret) 2035 return dev_err_probe(dev, ret, "Could not parse endpoint\n"); 2036 2037 ret = thp7312_map_data_lanes(&thp7312->lane_remap, 2038 ep.bus.mipi_csi2.data_lanes, 2039 ep.bus.mipi_csi2.num_data_lanes); 2040 if (ret) { 2041 dev_err(dev, "Invalid data-lanes value\n"); 2042 return ret; 2043 } 2044 2045 /* 2046 * The thine,boot-mode property is optional and default to 2047 * THP7312_BOOT_MODE_SPI_MASTER (1). 2048 */ 2049 thp7312->boot_mode = THP7312_BOOT_MODE_SPI_MASTER; 2050 ret = device_property_read_u32(dev, "thine,boot-mode", 2051 &thp7312->boot_mode); 2052 if (ret && ret != -EINVAL) 2053 return dev_err_probe(dev, ret, "Property '%s' is invalid\n", 2054 "thine,boot-mode"); 2055 2056 if (thp7312->boot_mode != THP7312_BOOT_MODE_2WIRE_SLAVE && 2057 thp7312->boot_mode != THP7312_BOOT_MODE_SPI_MASTER) 2058 return dev_err_probe(dev, -EINVAL, "Invalid '%s' value %u\n", 2059 "thine,boot-mode", thp7312->boot_mode); 2060 2061 /* Sensors */ 2062 sensors = device_get_named_child_node(dev, "sensors"); 2063 if (!sensors) { 2064 dev_err(dev, "'sensors' child node not found\n"); 2065 return -EINVAL; 2066 } 2067 2068 fwnode_for_each_available_child_node(sensors, node) { 2069 if (fwnode_name_eq(node, "sensor")) { 2070 if (!thp7312_sensor_parse_dt(thp7312, node)) 2071 num_sensors++; 2072 } 2073 } 2074 2075 fwnode_handle_put(sensors); 2076 2077 if (!num_sensors) { 2078 dev_err(dev, "No sensor found\n"); 2079 return -EINVAL; 2080 } 2081 2082 return 0; 2083 } 2084 2085 static int thp7312_probe(struct i2c_client *client) 2086 { 2087 struct device *dev = &client->dev; 2088 struct thp7312_device *thp7312; 2089 int ret; 2090 2091 thp7312 = devm_kzalloc(dev, sizeof(*thp7312), GFP_KERNEL); 2092 if (!thp7312) 2093 return -ENOMEM; 2094 2095 thp7312->dev = dev; 2096 2097 thp7312->regmap = devm_cci_regmap_init_i2c(client, 16); 2098 if (IS_ERR(thp7312->regmap)) 2099 return dev_err_probe(dev, PTR_ERR(thp7312->regmap), 2100 "Unable to initialize I2C\n"); 2101 2102 ret = thp7312_parse_dt(thp7312); 2103 if (ret < 0) 2104 return ret; 2105 2106 ret = thp7312_get_regulators(thp7312); 2107 if (ret) 2108 return dev_err_probe(dev, ret, "Failed to get regulators\n"); 2109 2110 thp7312->iclk = devm_clk_get(dev, NULL); 2111 if (IS_ERR(thp7312->iclk)) 2112 return dev_err_probe(dev, PTR_ERR(thp7312->iclk), 2113 "Failed to get iclk\n"); 2114 2115 thp7312->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH); 2116 if (IS_ERR(thp7312->reset_gpio)) 2117 return dev_err_probe(dev, PTR_ERR(thp7312->reset_gpio), 2118 "Failed to get reset gpio\n"); 2119 2120 if (thp7312->boot_mode == THP7312_BOOT_MODE_2WIRE_SLAVE) 2121 return thp7312_register_flash_mode(thp7312); 2122 2123 v4l2_i2c_subdev_init(&thp7312->sd, client, &thp7312_subdev_ops); 2124 thp7312->sd.internal_ops = &thp7312_internal_ops; 2125 thp7312->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 2126 thp7312->pad.flags = MEDIA_PAD_FL_SOURCE; 2127 thp7312->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; 2128 2129 ret = media_entity_pads_init(&thp7312->sd.entity, 1, &thp7312->pad); 2130 if (ret) 2131 return ret; 2132 2133 /* 2134 * Enable power management. The driver supports runtime PM, but needs to 2135 * work when runtime PM is disabled in the kernel. To that end, power 2136 * the device manually here. 2137 */ 2138 ret = thp7312_power_on(thp7312); 2139 if (ret) 2140 goto err_entity_cleanup; 2141 2142 ret = thp7312_read_firmware_version(thp7312); 2143 if (ret < 0) { 2144 dev_err(dev, "Camera is not found\n"); 2145 goto err_power_off; 2146 } 2147 2148 ret = thp7312_init_controls(thp7312); 2149 if (ret) { 2150 dev_err(dev, "Failed to initialize controls\n"); 2151 goto err_power_off; 2152 } 2153 2154 thp7312->sd.ctrl_handler = &thp7312->ctrl_handler; 2155 thp7312->sd.state_lock = thp7312->ctrl_handler.lock; 2156 2157 ret = v4l2_subdev_init_finalize(&thp7312->sd); 2158 if (ret < 0) { 2159 dev_err(dev, "Subdev active state initialization failed\n"); 2160 goto err_free_ctrls; 2161 } 2162 2163 /* 2164 * Enable runtime PM with autosuspend. As the device has been powered 2165 * manually, mark it as active, and increase the usage count without 2166 * resuming the device. 2167 */ 2168 pm_runtime_set_active(dev); 2169 pm_runtime_get_noresume(dev); 2170 pm_runtime_enable(dev); 2171 pm_runtime_set_autosuspend_delay(dev, 1000); 2172 pm_runtime_use_autosuspend(dev); 2173 2174 ret = v4l2_async_register_subdev(&thp7312->sd); 2175 if (ret < 0) { 2176 dev_err(dev, "Subdev registration failed\n"); 2177 goto err_pm; 2178 } 2179 2180 /* 2181 * Decrease the PM usage count. The device will get suspended after the 2182 * autosuspend delay, turning the power off. 2183 */ 2184 pm_runtime_put_autosuspend(dev); 2185 2186 dev_info(dev, "THP7312 firmware version %02u.%02u\n", 2187 THP7312_FW_VERSION_MAJOR(thp7312->fw_version), 2188 THP7312_FW_VERSION_MINOR(thp7312->fw_version)); 2189 2190 return 0; 2191 2192 err_pm: 2193 pm_runtime_disable(dev); 2194 pm_runtime_put_noidle(dev); 2195 v4l2_subdev_cleanup(&thp7312->sd); 2196 err_free_ctrls: 2197 v4l2_ctrl_handler_free(&thp7312->ctrl_handler); 2198 err_power_off: 2199 thp7312_power_off(thp7312); 2200 err_entity_cleanup: 2201 media_entity_cleanup(&thp7312->sd.entity); 2202 return ret; 2203 } 2204 2205 static void thp7312_remove(struct i2c_client *client) 2206 { 2207 struct v4l2_subdev *sd = i2c_get_clientdata(client); 2208 struct thp7312_device *thp7312 = to_thp7312_dev(sd); 2209 2210 if (thp7312->boot_mode == THP7312_BOOT_MODE_2WIRE_SLAVE) { 2211 firmware_upload_unregister(thp7312->fwl); 2212 __thp7312_power_off(thp7312); 2213 return; 2214 } 2215 2216 v4l2_async_unregister_subdev(&thp7312->sd); 2217 v4l2_subdev_cleanup(&thp7312->sd); 2218 media_entity_cleanup(&thp7312->sd.entity); 2219 v4l2_ctrl_handler_free(&thp7312->ctrl_handler); 2220 2221 /* 2222 * Disable runtime PM. In case runtime PM is disabled in the kernel, 2223 * make sure to turn power off manually. 2224 */ 2225 pm_runtime_disable(thp7312->dev); 2226 if (!pm_runtime_status_suspended(thp7312->dev)) 2227 thp7312_power_off(thp7312); 2228 pm_runtime_set_suspended(thp7312->dev); 2229 } 2230 2231 static const struct of_device_id thp7312_dt_ids[] = { 2232 { .compatible = "thine,thp7312" }, 2233 { /* sentinel */ } 2234 }; 2235 MODULE_DEVICE_TABLE(of, thp7312_dt_ids); 2236 2237 static struct i2c_driver thp7312_i2c_driver = { 2238 .driver = { 2239 .name = "thp7312", 2240 .pm = &thp7312_pm_ops, 2241 .of_match_table = thp7312_dt_ids, 2242 }, 2243 .probe = thp7312_probe, 2244 .remove = thp7312_remove, 2245 }; 2246 2247 module_i2c_driver(thp7312_i2c_driver); 2248 2249 MODULE_DESCRIPTION("THP7312 MIPI Camera Subdev Driver"); 2250 MODULE_LICENSE("GPL"); 2251