1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * ADXL355 3-Axis Digital Accelerometer IIO core driver 4 * 5 * Copyright (c) 2021 Puranjay Mohan <puranjay12@gmail.com> 6 * 7 * Datasheet: https://www.analog.com/media/en/technical-documentation/data-sheets/adxl354_adxl355.pdf 8 */ 9 10 #include <linux/bits.h> 11 #include <linux/bitfield.h> 12 #include <linux/iio/buffer.h> 13 #include <linux/iio/iio.h> 14 #include <linux/iio/trigger.h> 15 #include <linux/iio/triggered_buffer.h> 16 #include <linux/iio/trigger_consumer.h> 17 #include <linux/limits.h> 18 #include <linux/math64.h> 19 #include <linux/module.h> 20 #include <linux/mod_devicetable.h> 21 #include <linux/property.h> 22 #include <linux/regmap.h> 23 #include <linux/units.h> 24 25 #include <linux/unaligned.h> 26 27 #include "adxl355.h" 28 29 /* ADXL355 Register Definitions */ 30 #define ADXL355_DEVID_AD_REG 0x00 31 #define ADXL355_DEVID_MST_REG 0x01 32 #define ADXL355_PARTID_REG 0x02 33 #define ADXL355_STATUS_REG 0x04 34 #define ADXL355_FIFO_ENTRIES_REG 0x05 35 #define ADXL355_TEMP2_REG 0x06 36 #define ADXL355_XDATA3_REG 0x08 37 #define ADXL355_YDATA3_REG 0x0B 38 #define ADXL355_ZDATA3_REG 0x0E 39 #define ADXL355_FIFO_DATA_REG 0x11 40 #define ADXL355_OFFSET_X_H_REG 0x1E 41 #define ADXL355_OFFSET_Y_H_REG 0x20 42 #define ADXL355_OFFSET_Z_H_REG 0x22 43 #define ADXL355_ACT_EN_REG 0x24 44 #define ADXL355_ACT_THRESH_H_REG 0x25 45 #define ADXL355_ACT_THRESH_L_REG 0x26 46 #define ADXL355_ACT_COUNT_REG 0x27 47 #define ADXL355_FILTER_REG 0x28 48 #define ADXL355_FILTER_ODR_MSK GENMASK(3, 0) 49 #define ADXL355_FILTER_HPF_MSK GENMASK(6, 4) 50 #define ADXL355_FIFO_SAMPLES_REG 0x29 51 #define ADXL355_INT_MAP_REG 0x2A 52 #define ADXL355_SYNC_REG 0x2B 53 #define ADXL355_RANGE_REG 0x2C 54 #define ADXL355_POWER_CTL_REG 0x2D 55 #define ADXL355_POWER_CTL_MODE_MSK GENMASK(1, 0) 56 #define ADXL355_POWER_CTL_DRDY_MSK BIT(2) 57 #define ADXL355_SELF_TEST_REG 0x2E 58 #define ADXL355_RESET_REG 0x2F 59 #define ADXL355_BASE_ADDR_SHADOW_REG 0x50 60 #define ADXL355_SHADOW_REG_COUNT 5 61 62 #define ADXL355_DEVID_AD_VAL 0xAD 63 #define ADXL355_DEVID_MST_VAL 0x1D 64 #define ADXL355_PARTID_VAL 0xED 65 #define ADXL359_PARTID_VAL 0xE9 66 #define ADXL355_RESET_CODE 0x52 67 68 static const struct regmap_range adxl355_read_reg_range[] = { 69 regmap_reg_range(ADXL355_DEVID_AD_REG, ADXL355_FIFO_DATA_REG), 70 regmap_reg_range(ADXL355_OFFSET_X_H_REG, ADXL355_SELF_TEST_REG), 71 }; 72 73 const struct regmap_access_table adxl355_readable_regs_tbl = { 74 .yes_ranges = adxl355_read_reg_range, 75 .n_yes_ranges = ARRAY_SIZE(adxl355_read_reg_range), 76 }; 77 EXPORT_SYMBOL_NS_GPL(adxl355_readable_regs_tbl, "IIO_ADXL355"); 78 79 static const struct regmap_range adxl355_write_reg_range[] = { 80 regmap_reg_range(ADXL355_OFFSET_X_H_REG, ADXL355_RESET_REG), 81 }; 82 83 const struct regmap_access_table adxl355_writeable_regs_tbl = { 84 .yes_ranges = adxl355_write_reg_range, 85 .n_yes_ranges = ARRAY_SIZE(adxl355_write_reg_range), 86 }; 87 EXPORT_SYMBOL_NS_GPL(adxl355_writeable_regs_tbl, "IIO_ADXL355"); 88 89 const struct adxl355_chip_info adxl35x_chip_info[] = { 90 [ADXL355] = { 91 .name = "adxl355", 92 .part_id = ADXL355_PARTID_VAL, 93 /* 94 * At +/- 2g with 20-bit resolution, scale is given in datasheet 95 * as 3.9ug/LSB = 0.0000039 * 9.80665 = 0.00003824593 m/s^2. 96 */ 97 .accel_scale = { 98 .integer = 0, 99 .decimal = 38245, 100 }, 101 /* 102 * The datasheet defines an intercept of 1885 LSB at 25 degC 103 * and a slope of -9.05 LSB/C. The following formula can be used 104 * to find the temperature: 105 * Temp = ((RAW - 1885)/(-9.05)) + 25 but this doesn't follow 106 * the format of the IIO which is Temp = (RAW + OFFSET) * SCALE. 107 * Hence using some rearranging we get the scale as -110.497238 108 * and offset as -2111.25. 109 */ 110 .temp_offset = { 111 .integer = -2111, 112 .decimal = 250000, 113 }, 114 }, 115 [ADXL359] = { 116 .name = "adxl359", 117 .part_id = ADXL359_PARTID_VAL, 118 /* 119 * At +/- 10g with 20-bit resolution, scale is given in datasheet 120 * as 19.5ug/LSB = 0.0000195 * 9.80665 = 0.0.00019122967 m/s^2. 121 */ 122 .accel_scale = { 123 .integer = 0, 124 .decimal = 191229, 125 }, 126 /* 127 * The datasheet defines an intercept of 1852 LSB at 25 degC 128 * and a slope of -9.05 LSB/C. The following formula can be used 129 * to find the temperature: 130 * Temp = ((RAW - 1852)/(-9.05)) + 25 but this doesn't follow 131 * the format of the IIO which is Temp = (RAW + OFFSET) * SCALE. 132 * Hence using some rearranging we get the scale as -110.497238 133 * and offset as -2079.25. 134 */ 135 .temp_offset = { 136 .integer = -2079, 137 .decimal = 250000, 138 }, 139 }, 140 }; 141 EXPORT_SYMBOL_NS_GPL(adxl35x_chip_info, "IIO_ADXL355"); 142 143 enum adxl355_op_mode { 144 ADXL355_MEASUREMENT, 145 ADXL355_STANDBY, 146 ADXL355_TEMP_OFF, 147 }; 148 149 enum adxl355_odr { 150 ADXL355_ODR_4000HZ, 151 ADXL355_ODR_2000HZ, 152 ADXL355_ODR_1000HZ, 153 ADXL355_ODR_500HZ, 154 ADXL355_ODR_250HZ, 155 ADXL355_ODR_125HZ, 156 ADXL355_ODR_62_5HZ, 157 ADXL355_ODR_31_25HZ, 158 ADXL355_ODR_15_625HZ, 159 ADXL355_ODR_7_813HZ, 160 ADXL355_ODR_3_906HZ, 161 }; 162 163 enum adxl355_hpf_3db { 164 ADXL355_HPF_OFF, 165 ADXL355_HPF_24_7, 166 ADXL355_HPF_6_2084, 167 ADXL355_HPF_1_5545, 168 ADXL355_HPF_0_3862, 169 ADXL355_HPF_0_0954, 170 ADXL355_HPF_0_0238, 171 }; 172 173 static const int adxl355_odr_table[][2] = { 174 [0] = {4000, 0}, 175 [1] = {2000, 0}, 176 [2] = {1000, 0}, 177 [3] = {500, 0}, 178 [4] = {250, 0}, 179 [5] = {125, 0}, 180 [6] = {62, 500000}, 181 [7] = {31, 250000}, 182 [8] = {15, 625000}, 183 [9] = {7, 813000}, 184 [10] = {3, 906000}, 185 }; 186 187 static const int adxl355_hpf_3db_multipliers[] = { 188 0, 189 247000, 190 62084, 191 15545, 192 3862, 193 954, 194 238, 195 }; 196 197 enum adxl355_chans { 198 chan_x, chan_y, chan_z, 199 }; 200 201 struct adxl355_chan_info { 202 u8 data_reg; 203 u8 offset_reg; 204 }; 205 206 static const struct adxl355_chan_info adxl355_chans[] = { 207 [chan_x] = { 208 .data_reg = ADXL355_XDATA3_REG, 209 .offset_reg = ADXL355_OFFSET_X_H_REG 210 }, 211 [chan_y] = { 212 .data_reg = ADXL355_YDATA3_REG, 213 .offset_reg = ADXL355_OFFSET_Y_H_REG 214 }, 215 [chan_z] = { 216 .data_reg = ADXL355_ZDATA3_REG, 217 .offset_reg = ADXL355_OFFSET_Z_H_REG 218 }, 219 }; 220 221 struct adxl355_data { 222 const struct adxl355_chip_info *chip_info; 223 struct regmap *regmap; 224 struct device *dev; 225 struct mutex lock; /* lock to protect op_mode */ 226 enum adxl355_op_mode op_mode; 227 enum adxl355_odr odr; 228 enum adxl355_hpf_3db hpf_3db; 229 int calibbias[3]; 230 int adxl355_hpf_3db_table[7][2]; 231 struct iio_trigger *dready_trig; 232 union { 233 u8 transf_buf[3]; 234 struct { 235 u8 buf[14]; 236 aligned_s64 ts; 237 } buffer; 238 } __aligned(IIO_DMA_MINALIGN); 239 }; 240 241 static int adxl355_set_op_mode(struct adxl355_data *data, 242 enum adxl355_op_mode op_mode) 243 { 244 int ret; 245 246 if (data->op_mode == op_mode) 247 return 0; 248 249 ret = regmap_update_bits(data->regmap, ADXL355_POWER_CTL_REG, 250 ADXL355_POWER_CTL_MODE_MSK, op_mode); 251 if (ret) 252 return ret; 253 254 data->op_mode = op_mode; 255 256 return ret; 257 } 258 259 static int adxl355_data_rdy_trigger_set_state(struct iio_trigger *trig, 260 bool state) 261 { 262 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 263 struct adxl355_data *data = iio_priv(indio_dev); 264 int ret; 265 266 mutex_lock(&data->lock); 267 ret = regmap_update_bits(data->regmap, ADXL355_POWER_CTL_REG, 268 ADXL355_POWER_CTL_DRDY_MSK, 269 FIELD_PREP(ADXL355_POWER_CTL_DRDY_MSK, 270 state ? 0 : 1)); 271 mutex_unlock(&data->lock); 272 273 return ret; 274 } 275 276 static void adxl355_fill_3db_frequency_table(struct adxl355_data *data) 277 { 278 u32 multiplier; 279 u64 div, rem; 280 u64 odr; 281 int i; 282 283 odr = mul_u64_u32_shr(adxl355_odr_table[data->odr][0], MEGA, 0) + 284 adxl355_odr_table[data->odr][1]; 285 286 for (i = 0; i < ARRAY_SIZE(adxl355_hpf_3db_multipliers); i++) { 287 multiplier = adxl355_hpf_3db_multipliers[i]; 288 div = div64_u64_rem(mul_u64_u32_shr(odr, multiplier, 0), 289 TERA * 100, &rem); 290 291 data->adxl355_hpf_3db_table[i][0] = div; 292 data->adxl355_hpf_3db_table[i][1] = div_u64(rem, MEGA * 100); 293 } 294 } 295 296 static int adxl355_setup(struct adxl355_data *data) 297 { 298 unsigned int regval; 299 int retries = 5; /* the number is chosen based on empirical reasons */ 300 int ret; 301 u8 *shadow_regs __free(kfree) = kzalloc(ADXL355_SHADOW_REG_COUNT, GFP_KERNEL); 302 303 if (!shadow_regs) 304 return -ENOMEM; 305 306 ret = regmap_read(data->regmap, ADXL355_DEVID_AD_REG, ®val); 307 if (ret) 308 return ret; 309 310 if (regval != ADXL355_DEVID_AD_VAL) { 311 dev_err(data->dev, "Invalid ADI ID 0x%02x\n", regval); 312 return -ENODEV; 313 } 314 315 ret = regmap_read(data->regmap, ADXL355_DEVID_MST_REG, ®val); 316 if (ret) 317 return ret; 318 319 if (regval != ADXL355_DEVID_MST_VAL) { 320 dev_err(data->dev, "Invalid MEMS ID 0x%02x\n", regval); 321 return -ENODEV; 322 } 323 324 ret = regmap_read(data->regmap, ADXL355_PARTID_REG, ®val); 325 if (ret) 326 return ret; 327 328 if (regval != ADXL355_PARTID_VAL) 329 dev_warn(data->dev, "Invalid DEV ID 0x%02x\n", regval); 330 331 /* Read shadow registers to be compared after reset */ 332 ret = regmap_bulk_read(data->regmap, 333 ADXL355_BASE_ADDR_SHADOW_REG, 334 shadow_regs, ADXL355_SHADOW_REG_COUNT); 335 if (ret) 336 return ret; 337 338 do { 339 if (--retries == 0) 340 return dev_err_probe(data->dev, -EIO, "Shadow registers mismatch\n"); 341 342 /* 343 * Perform a software reset to make sure the device is in a consistent 344 * state after start-up. 345 */ 346 ret = regmap_write(data->regmap, ADXL355_RESET_REG, 347 ADXL355_RESET_CODE); 348 if (ret) 349 return ret; 350 351 /* Wait at least 5ms after software reset */ 352 fsleep(5 * USEC_PER_MSEC); 353 354 /* Read shadow registers for comparison */ 355 ret = regmap_bulk_read(data->regmap, 356 ADXL355_BASE_ADDR_SHADOW_REG, 357 data->buffer.buf, 358 ADXL355_SHADOW_REG_COUNT); 359 if (ret) 360 return ret; 361 } while (memcmp(shadow_regs, data->buffer.buf, 362 ADXL355_SHADOW_REG_COUNT)); 363 364 ret = regmap_update_bits(data->regmap, ADXL355_POWER_CTL_REG, 365 ADXL355_POWER_CTL_DRDY_MSK, 366 FIELD_PREP(ADXL355_POWER_CTL_DRDY_MSK, 1)); 367 if (ret) 368 return ret; 369 370 adxl355_fill_3db_frequency_table(data); 371 372 return adxl355_set_op_mode(data, ADXL355_MEASUREMENT); 373 } 374 375 static int adxl355_get_temp_data(struct adxl355_data *data, u8 addr) 376 { 377 return regmap_bulk_read(data->regmap, addr, data->transf_buf, 2); 378 } 379 380 static int adxl355_read_axis(struct adxl355_data *data, u8 addr) 381 { 382 int ret; 383 384 ret = regmap_bulk_read(data->regmap, addr, data->transf_buf, 385 ARRAY_SIZE(data->transf_buf)); 386 if (ret) 387 return ret; 388 389 return get_unaligned_be24(data->transf_buf); 390 } 391 392 static int adxl355_find_match(const int (*freq_tbl)[2], const int n, 393 const int val, const int val2) 394 { 395 int i; 396 397 for (i = 0; i < n; i++) { 398 if (freq_tbl[i][0] == val && freq_tbl[i][1] == val2) 399 return i; 400 } 401 402 return -EINVAL; 403 } 404 405 static int adxl355_set_odr(struct adxl355_data *data, 406 enum adxl355_odr odr) 407 { 408 int ret; 409 410 mutex_lock(&data->lock); 411 412 if (data->odr == odr) { 413 mutex_unlock(&data->lock); 414 return 0; 415 } 416 417 ret = adxl355_set_op_mode(data, ADXL355_STANDBY); 418 if (ret) 419 goto err_unlock; 420 421 ret = regmap_update_bits(data->regmap, ADXL355_FILTER_REG, 422 ADXL355_FILTER_ODR_MSK, 423 FIELD_PREP(ADXL355_FILTER_ODR_MSK, odr)); 424 if (ret) 425 goto err_set_opmode; 426 427 data->odr = odr; 428 adxl355_fill_3db_frequency_table(data); 429 430 ret = adxl355_set_op_mode(data, ADXL355_MEASUREMENT); 431 if (ret) 432 goto err_set_opmode; 433 434 mutex_unlock(&data->lock); 435 return 0; 436 437 err_set_opmode: 438 adxl355_set_op_mode(data, ADXL355_MEASUREMENT); 439 err_unlock: 440 mutex_unlock(&data->lock); 441 return ret; 442 } 443 444 static int adxl355_set_hpf_3db(struct adxl355_data *data, 445 enum adxl355_hpf_3db hpf) 446 { 447 int ret; 448 449 mutex_lock(&data->lock); 450 451 if (data->hpf_3db == hpf) { 452 mutex_unlock(&data->lock); 453 return 0; 454 } 455 456 ret = adxl355_set_op_mode(data, ADXL355_STANDBY); 457 if (ret) 458 goto err_unlock; 459 460 ret = regmap_update_bits(data->regmap, ADXL355_FILTER_REG, 461 ADXL355_FILTER_HPF_MSK, 462 FIELD_PREP(ADXL355_FILTER_HPF_MSK, hpf)); 463 if (ret) 464 goto err_set_opmode; 465 466 data->hpf_3db = hpf; 467 468 ret = adxl355_set_op_mode(data, ADXL355_MEASUREMENT); 469 if (ret) 470 goto err_set_opmode; 471 472 mutex_unlock(&data->lock); 473 return 0; 474 475 err_set_opmode: 476 adxl355_set_op_mode(data, ADXL355_MEASUREMENT); 477 err_unlock: 478 mutex_unlock(&data->lock); 479 return ret; 480 } 481 482 static int adxl355_set_calibbias(struct adxl355_data *data, 483 enum adxl355_chans chan, int calibbias) 484 { 485 int ret; 486 487 mutex_lock(&data->lock); 488 489 ret = adxl355_set_op_mode(data, ADXL355_STANDBY); 490 if (ret) 491 goto err_unlock; 492 493 put_unaligned_be16(calibbias, data->transf_buf); 494 ret = regmap_bulk_write(data->regmap, 495 adxl355_chans[chan].offset_reg, 496 data->transf_buf, 2); 497 if (ret) 498 goto err_set_opmode; 499 500 data->calibbias[chan] = calibbias; 501 502 ret = adxl355_set_op_mode(data, ADXL355_MEASUREMENT); 503 if (ret) 504 goto err_set_opmode; 505 506 mutex_unlock(&data->lock); 507 return 0; 508 509 err_set_opmode: 510 adxl355_set_op_mode(data, ADXL355_MEASUREMENT); 511 err_unlock: 512 mutex_unlock(&data->lock); 513 return ret; 514 } 515 516 static int adxl355_read_raw(struct iio_dev *indio_dev, 517 struct iio_chan_spec const *chan, 518 int *val, int *val2, long mask) 519 { 520 struct adxl355_data *data = iio_priv(indio_dev); 521 int ret; 522 523 switch (mask) { 524 case IIO_CHAN_INFO_RAW: 525 switch (chan->type) { 526 case IIO_TEMP: 527 ret = adxl355_get_temp_data(data, chan->address); 528 if (ret < 0) 529 return ret; 530 *val = get_unaligned_be16(data->transf_buf); 531 532 return IIO_VAL_INT; 533 case IIO_ACCEL: 534 ret = adxl355_read_axis(data, adxl355_chans[ 535 chan->address].data_reg); 536 if (ret < 0) 537 return ret; 538 *val = sign_extend32(ret >> chan->scan_type.shift, 539 chan->scan_type.realbits - 1); 540 return IIO_VAL_INT; 541 default: 542 return -EINVAL; 543 } 544 545 case IIO_CHAN_INFO_SCALE: 546 switch (chan->type) { 547 case IIO_TEMP: 548 /* 549 * Temperature scale is -110.497238. 550 * See the detailed explanation in adxl35x_chip_info 551 * definition above. 552 */ 553 *val = -110; 554 *val2 = 497238; 555 return IIO_VAL_INT_PLUS_MICRO; 556 case IIO_ACCEL: 557 *val = data->chip_info->accel_scale.integer; 558 *val2 = data->chip_info->accel_scale.decimal; 559 return IIO_VAL_INT_PLUS_NANO; 560 default: 561 return -EINVAL; 562 } 563 case IIO_CHAN_INFO_OFFSET: 564 *val = data->chip_info->temp_offset.integer; 565 *val2 = data->chip_info->temp_offset.decimal; 566 return IIO_VAL_INT_PLUS_MICRO; 567 case IIO_CHAN_INFO_CALIBBIAS: 568 *val = sign_extend32(data->calibbias[chan->address], 15); 569 return IIO_VAL_INT; 570 case IIO_CHAN_INFO_SAMP_FREQ: 571 *val = adxl355_odr_table[data->odr][0]; 572 *val2 = adxl355_odr_table[data->odr][1]; 573 return IIO_VAL_INT_PLUS_MICRO; 574 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY: 575 *val = data->adxl355_hpf_3db_table[data->hpf_3db][0]; 576 *val2 = data->adxl355_hpf_3db_table[data->hpf_3db][1]; 577 return IIO_VAL_INT_PLUS_MICRO; 578 default: 579 return -EINVAL; 580 } 581 } 582 583 static int adxl355_write_raw(struct iio_dev *indio_dev, 584 struct iio_chan_spec const *chan, 585 int val, int val2, long mask) 586 { 587 struct adxl355_data *data = iio_priv(indio_dev); 588 int odr_idx, hpf_idx, calibbias; 589 590 switch (mask) { 591 case IIO_CHAN_INFO_SAMP_FREQ: 592 odr_idx = adxl355_find_match(adxl355_odr_table, 593 ARRAY_SIZE(adxl355_odr_table), 594 val, val2); 595 if (odr_idx < 0) 596 return odr_idx; 597 598 return adxl355_set_odr(data, odr_idx); 599 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY: 600 hpf_idx = adxl355_find_match(data->adxl355_hpf_3db_table, 601 ARRAY_SIZE(data->adxl355_hpf_3db_table), 602 val, val2); 603 if (hpf_idx < 0) 604 return hpf_idx; 605 606 return adxl355_set_hpf_3db(data, hpf_idx); 607 case IIO_CHAN_INFO_CALIBBIAS: 608 calibbias = clamp_t(int, val, S16_MIN, S16_MAX); 609 610 return adxl355_set_calibbias(data, chan->address, calibbias); 611 default: 612 return -EINVAL; 613 } 614 } 615 616 static int adxl355_read_avail(struct iio_dev *indio_dev, 617 struct iio_chan_spec const *chan, 618 const int **vals, int *type, int *length, 619 long mask) 620 { 621 struct adxl355_data *data = iio_priv(indio_dev); 622 623 switch (mask) { 624 case IIO_CHAN_INFO_SAMP_FREQ: 625 *vals = (const int *)adxl355_odr_table; 626 *type = IIO_VAL_INT_PLUS_MICRO; 627 /* Values are stored in a 2D matrix */ 628 *length = ARRAY_SIZE(adxl355_odr_table) * 2; 629 630 return IIO_AVAIL_LIST; 631 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY: 632 *vals = (const int *)data->adxl355_hpf_3db_table; 633 *type = IIO_VAL_INT_PLUS_MICRO; 634 /* Values are stored in a 2D matrix */ 635 *length = ARRAY_SIZE(data->adxl355_hpf_3db_table) * 2; 636 637 return IIO_AVAIL_LIST; 638 default: 639 return -EINVAL; 640 } 641 } 642 643 static const unsigned long adxl355_avail_scan_masks[] = { 644 GENMASK(3, 0), 645 0 646 }; 647 648 static const struct iio_info adxl355_info = { 649 .read_raw = adxl355_read_raw, 650 .write_raw = adxl355_write_raw, 651 .read_avail = &adxl355_read_avail, 652 }; 653 654 static const struct iio_trigger_ops adxl355_trigger_ops = { 655 .set_trigger_state = &adxl355_data_rdy_trigger_set_state, 656 .validate_device = &iio_trigger_validate_own_device, 657 }; 658 659 static irqreturn_t adxl355_trigger_handler(int irq, void *p) 660 { 661 struct iio_poll_func *pf = p; 662 struct iio_dev *indio_dev = pf->indio_dev; 663 struct adxl355_data *data = iio_priv(indio_dev); 664 int ret; 665 666 mutex_lock(&data->lock); 667 668 /* 669 * data->buffer is used both for triggered buffer support 670 * and read/write_raw(), hence, it has to be zeroed here before usage. 671 */ 672 data->buffer.buf[0] = 0; 673 674 /* 675 * The acceleration data is 24 bits and big endian. It has to be saved 676 * in 32 bits, hence, it is saved in the 2nd byte of the 4 byte buffer. 677 * The buf array is 14 bytes as it includes 3x4=12 bytes for 678 * acceleration data of x, y, and z axis. It also includes 2 bytes for 679 * temperature data. 680 */ 681 ret = regmap_bulk_read(data->regmap, ADXL355_XDATA3_REG, 682 &data->buffer.buf[1], 3); 683 if (ret) 684 goto out_unlock_notify; 685 686 ret = regmap_bulk_read(data->regmap, ADXL355_YDATA3_REG, 687 &data->buffer.buf[5], 3); 688 if (ret) 689 goto out_unlock_notify; 690 691 ret = regmap_bulk_read(data->regmap, ADXL355_ZDATA3_REG, 692 &data->buffer.buf[9], 3); 693 if (ret) 694 goto out_unlock_notify; 695 696 ret = regmap_bulk_read(data->regmap, ADXL355_TEMP2_REG, 697 &data->buffer.buf[12], 2); 698 if (ret) 699 goto out_unlock_notify; 700 701 iio_push_to_buffers_with_ts(indio_dev, &data->buffer, 702 sizeof(data->buffer), pf->timestamp); 703 704 out_unlock_notify: 705 mutex_unlock(&data->lock); 706 iio_trigger_notify_done(indio_dev->trig); 707 708 return IRQ_HANDLED; 709 } 710 711 #define ADXL355_ACCEL_CHANNEL(index, reg, axis) { \ 712 .type = IIO_ACCEL, \ 713 .address = reg, \ 714 .modified = 1, \ 715 .channel2 = IIO_MOD_##axis, \ 716 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 717 BIT(IIO_CHAN_INFO_CALIBBIAS), \ 718 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 719 BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 720 BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY), \ 721 .info_mask_shared_by_type_available = \ 722 BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 723 BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY), \ 724 .scan_index = index, \ 725 .scan_type = { \ 726 .sign = 's', \ 727 .realbits = 20, \ 728 .storagebits = 32, \ 729 .shift = 4, \ 730 .endianness = IIO_BE, \ 731 } \ 732 } 733 734 static const struct iio_chan_spec adxl355_channels[] = { 735 ADXL355_ACCEL_CHANNEL(0, chan_x, X), 736 ADXL355_ACCEL_CHANNEL(1, chan_y, Y), 737 ADXL355_ACCEL_CHANNEL(2, chan_z, Z), 738 { 739 .type = IIO_TEMP, 740 .address = ADXL355_TEMP2_REG, 741 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 742 BIT(IIO_CHAN_INFO_SCALE) | 743 BIT(IIO_CHAN_INFO_OFFSET), 744 .scan_index = 3, 745 .scan_type = { 746 .sign = 'u', 747 .realbits = 12, 748 .storagebits = 16, 749 .endianness = IIO_BE, 750 }, 751 }, 752 IIO_CHAN_SOFT_TIMESTAMP(4), 753 }; 754 755 static int adxl355_probe_trigger(struct iio_dev *indio_dev, int irq) 756 { 757 struct adxl355_data *data = iio_priv(indio_dev); 758 int ret; 759 760 data->dready_trig = devm_iio_trigger_alloc(data->dev, "%s-dev%d", 761 indio_dev->name, 762 iio_device_id(indio_dev)); 763 if (!data->dready_trig) 764 return -ENOMEM; 765 766 data->dready_trig->ops = &adxl355_trigger_ops; 767 iio_trigger_set_drvdata(data->dready_trig, indio_dev); 768 769 ret = devm_request_irq(data->dev, irq, &iio_trigger_generic_data_rdy_poll, 770 IRQF_NO_THREAD, "adxl355_irq", data->dready_trig); 771 if (ret) 772 return dev_err_probe(data->dev, ret, "request irq %d failed\n", 773 irq); 774 775 ret = devm_iio_trigger_register(data->dev, data->dready_trig); 776 if (ret) 777 return dev_err_probe(data->dev, ret, "iio trigger register failed\n"); 778 779 indio_dev->trig = iio_trigger_get(data->dready_trig); 780 781 return 0; 782 } 783 784 int adxl355_core_probe(struct device *dev, struct regmap *regmap, 785 const struct adxl355_chip_info *chip_info) 786 { 787 struct adxl355_data *data; 788 struct iio_dev *indio_dev; 789 int ret; 790 int irq; 791 792 indio_dev = devm_iio_device_alloc(dev, sizeof(*data)); 793 if (!indio_dev) 794 return -ENOMEM; 795 796 data = iio_priv(indio_dev); 797 data->regmap = regmap; 798 data->dev = dev; 799 data->op_mode = ADXL355_STANDBY; 800 data->chip_info = chip_info; 801 ret = devm_mutex_init(dev, &data->lock); 802 if (ret) 803 return ret; 804 805 indio_dev->name = chip_info->name; 806 indio_dev->info = &adxl355_info; 807 indio_dev->modes = INDIO_DIRECT_MODE; 808 indio_dev->channels = adxl355_channels; 809 indio_dev->num_channels = ARRAY_SIZE(adxl355_channels); 810 indio_dev->available_scan_masks = adxl355_avail_scan_masks; 811 812 ret = adxl355_setup(data); 813 if (ret) 814 return dev_err_probe(dev, ret, "ADXL355 setup failed\n"); 815 816 ret = devm_iio_triggered_buffer_setup(dev, indio_dev, 817 &iio_pollfunc_store_time, 818 &adxl355_trigger_handler, NULL); 819 if (ret) 820 return dev_err_probe(dev, ret, "iio triggered buffer setup failed\n"); 821 822 irq = fwnode_irq_get_byname(dev_fwnode(dev), "DRDY"); 823 if (irq > 0) { 824 ret = adxl355_probe_trigger(indio_dev, irq); 825 if (ret) 826 return ret; 827 } 828 829 return devm_iio_device_register(dev, indio_dev); 830 } 831 EXPORT_SYMBOL_NS_GPL(adxl355_core_probe, "IIO_ADXL355"); 832 833 MODULE_AUTHOR("Puranjay Mohan <puranjay12@gmail.com>"); 834 MODULE_DESCRIPTION("ADXL355 3-Axis Digital Accelerometer core driver"); 835 MODULE_LICENSE("GPL v2"); 836