1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * ADXL345 3-Axis Digital Accelerometer IIO core driver
4 *
5 * Copyright (c) 2017 Eva Rachel Retuya <eraretuya@gmail.com>
6 *
7 * Datasheet: https://www.analog.com/media/en/technical-documentation/data-sheets/ADXL345.pdf
8 */
9
10 #include <linux/bitfield.h>
11 #include <linux/bitops.h>
12 #include <linux/interrupt.h>
13 #include <linux/module.h>
14 #include <linux/property.h>
15 #include <linux/regmap.h>
16 #include <linux/units.h>
17
18 #include <linux/iio/iio.h>
19 #include <linux/iio/sysfs.h>
20 #include <linux/iio/buffer.h>
21 #include <linux/iio/events.h>
22 #include <linux/iio/kfifo_buf.h>
23
24 #include "adxl345.h"
25
26 #define ADXL345_FIFO_BYPASS 0
27 #define ADXL345_FIFO_FIFO 1
28 #define ADXL345_FIFO_STREAM 2
29
30 #define ADXL345_DIRS 3
31
32 #define ADXL345_INT_NONE 0xff
33 #define ADXL345_INT1 0
34 #define ADXL345_INT2 1
35
36 #define ADXL345_REG_TAP_AXIS_MSK GENMASK(2, 0)
37 #define ADXL345_REG_TAP_SUPPRESS_MSK BIT(3)
38 #define ADXL345_REG_TAP_SUPPRESS BIT(3)
39 #define ADXL345_POWER_CTL_INACT_MSK (ADXL345_POWER_CTL_AUTO_SLEEP | ADXL345_POWER_CTL_LINK)
40
41 #define ADXL345_TAP_Z_EN BIT(0)
42 #define ADXL345_TAP_Y_EN BIT(1)
43 #define ADXL345_TAP_X_EN BIT(2)
44 #define ADXL345_REG_TAP_SUPPRESS BIT(3)
45
46 #define ADXL345_INACT_Z_EN BIT(0)
47 #define ADXL345_INACT_Y_EN BIT(1)
48 #define ADXL345_INACT_X_EN BIT(2)
49 #define ADXL345_REG_INACT_ACDC BIT(3)
50 #define ADXL345_ACT_INACT_NO_AXIS_EN 0x00
51 #define ADXL345_INACT_XYZ_EN (ADXL345_INACT_Z_EN | ADXL345_INACT_Y_EN | ADXL345_INACT_X_EN)
52
53 #define ADXL345_ACT_Z_EN BIT(4)
54 #define ADXL345_ACT_Y_EN BIT(5)
55 #define ADXL345_ACT_X_EN BIT(6)
56 #define ADXL345_REG_ACT_ACDC BIT(7)
57 #define ADXL345_ACT_XYZ_EN (ADXL345_ACT_Z_EN | ADXL345_ACT_Y_EN | ADXL345_ACT_X_EN)
58
59 #define ADXL345_COUPLING_DC 0
60 #define ADXL345_COUPLING_AC 1
61 #define ADXL345_REG_NO_ACDC 0x00
62
63 /* single/double tap */
64 enum adxl345_tap_type {
65 ADXL345_SINGLE_TAP,
66 ADXL345_DOUBLE_TAP,
67 };
68
69 static const unsigned int adxl345_tap_int_reg[] = {
70 [ADXL345_SINGLE_TAP] = ADXL345_INT_SINGLE_TAP,
71 [ADXL345_DOUBLE_TAP] = ADXL345_INT_DOUBLE_TAP,
72 };
73
74 enum adxl345_tap_time_type {
75 ADXL345_TAP_TIME_LATENT,
76 ADXL345_TAP_TIME_WINDOW,
77 ADXL345_TAP_TIME_DUR,
78 };
79
80 static const unsigned int adxl345_tap_time_reg[] = {
81 [ADXL345_TAP_TIME_LATENT] = ADXL345_REG_LATENT,
82 [ADXL345_TAP_TIME_WINDOW] = ADXL345_REG_WINDOW,
83 [ADXL345_TAP_TIME_DUR] = ADXL345_REG_DUR,
84 };
85
86 /* activity/inactivity */
87 enum adxl345_activity_type {
88 ADXL345_ACTIVITY,
89 ADXL345_INACTIVITY,
90 ADXL345_ACTIVITY_AC,
91 ADXL345_INACTIVITY_AC,
92 ADXL345_INACTIVITY_FF,
93 };
94
95 static const unsigned int adxl345_act_int_reg[] = {
96 [ADXL345_ACTIVITY] = ADXL345_INT_ACTIVITY,
97 [ADXL345_INACTIVITY] = ADXL345_INT_INACTIVITY,
98 [ADXL345_ACTIVITY_AC] = ADXL345_INT_ACTIVITY,
99 [ADXL345_INACTIVITY_AC] = ADXL345_INT_INACTIVITY,
100 [ADXL345_INACTIVITY_FF] = ADXL345_INT_FREE_FALL,
101 };
102
103 static const unsigned int adxl345_act_thresh_reg[] = {
104 [ADXL345_ACTIVITY] = ADXL345_REG_THRESH_ACT,
105 [ADXL345_INACTIVITY] = ADXL345_REG_THRESH_INACT,
106 [ADXL345_ACTIVITY_AC] = ADXL345_REG_THRESH_ACT,
107 [ADXL345_INACTIVITY_AC] = ADXL345_REG_THRESH_INACT,
108 [ADXL345_INACTIVITY_FF] = ADXL345_REG_THRESH_FF,
109 };
110
111 static const unsigned int adxl345_act_acdc_msk[] = {
112 [ADXL345_ACTIVITY] = ADXL345_REG_ACT_ACDC,
113 [ADXL345_INACTIVITY] = ADXL345_REG_INACT_ACDC,
114 [ADXL345_ACTIVITY_AC] = ADXL345_REG_ACT_ACDC,
115 [ADXL345_INACTIVITY_AC] = ADXL345_REG_INACT_ACDC,
116 [ADXL345_INACTIVITY_FF] = ADXL345_REG_NO_ACDC,
117 };
118
119 enum adxl345_odr {
120 ADXL345_ODR_0P10HZ = 0,
121 ADXL345_ODR_0P20HZ,
122 ADXL345_ODR_0P39HZ,
123 ADXL345_ODR_0P78HZ,
124 ADXL345_ODR_1P56HZ,
125 ADXL345_ODR_3P13HZ,
126 ADXL345_ODR_6P25HZ,
127 ADXL345_ODR_12P50HZ,
128 ADXL345_ODR_25HZ,
129 ADXL345_ODR_50HZ,
130 ADXL345_ODR_100HZ,
131 ADXL345_ODR_200HZ,
132 ADXL345_ODR_400HZ,
133 ADXL345_ODR_800HZ,
134 ADXL345_ODR_1600HZ,
135 ADXL345_ODR_3200HZ,
136 };
137
138 enum adxl345_range {
139 ADXL345_2G_RANGE = 0,
140 ADXL345_4G_RANGE,
141 ADXL345_8G_RANGE,
142 ADXL345_16G_RANGE,
143 };
144
145 /* Certain features recommend 12.5 Hz - 400 Hz ODR */
146 static const int adxl345_odr_tbl[][2] = {
147 [ADXL345_ODR_0P10HZ] = { 0, 97000 },
148 [ADXL345_ODR_0P20HZ] = { 0, 195000 },
149 [ADXL345_ODR_0P39HZ] = { 0, 390000 },
150 [ADXL345_ODR_0P78HZ] = { 0, 781000 },
151 [ADXL345_ODR_1P56HZ] = { 1, 562000 },
152 [ADXL345_ODR_3P13HZ] = { 3, 125000 },
153 [ADXL345_ODR_6P25HZ] = { 6, 250000 },
154 [ADXL345_ODR_12P50HZ] = { 12, 500000 },
155 [ADXL345_ODR_25HZ] = { 25, 0 },
156 [ADXL345_ODR_50HZ] = { 50, 0 },
157 [ADXL345_ODR_100HZ] = { 100, 0 },
158 [ADXL345_ODR_200HZ] = { 200, 0 },
159 [ADXL345_ODR_400HZ] = { 400, 0 },
160 [ADXL345_ODR_800HZ] = { 800, 0 },
161 [ADXL345_ODR_1600HZ] = { 1600, 0 },
162 [ADXL345_ODR_3200HZ] = { 3200, 0 },
163 };
164
165 /*
166 * Full resolution frequency table:
167 * (g * 2 * 9.80665) / (2^(resolution) - 1)
168 *
169 * resolution := 13 (full)
170 * g := 2|4|8|16
171 *
172 * 2g at 13bit: 0.004789
173 * 4g at 13bit: 0.009578
174 * 8g at 13bit: 0.019156
175 * 16g at 16bit: 0.038312
176 */
177 static const int adxl345_fullres_range_tbl[][2] = {
178 [ADXL345_2G_RANGE] = { 0, 4789 },
179 [ADXL345_4G_RANGE] = { 0, 9578 },
180 [ADXL345_8G_RANGE] = { 0, 19156 },
181 [ADXL345_16G_RANGE] = { 0, 38312 },
182 };
183
184 /* scaling */
185 static const int adxl345_range_factor_tbl[] = {
186 [ADXL345_2G_RANGE] = 1,
187 [ADXL345_4G_RANGE] = 2,
188 [ADXL345_8G_RANGE] = 4,
189 [ADXL345_16G_RANGE] = 8,
190 };
191
192 struct adxl345_state {
193 const struct adxl345_chip_info *info;
194 struct regmap *regmap;
195 bool fifo_delay; /* delay: delay is needed for SPI */
196 u8 watermark;
197 u8 fifo_mode;
198
199 u8 inact_threshold;
200 u32 inact_time_ms;
201
202 u32 tap_duration_us;
203 u32 tap_latent_us;
204 u32 tap_window_us;
205
206 __le16 fifo_buf[ADXL345_DIRS * ADXL345_FIFO_SIZE + 1] __aligned(IIO_DMA_MINALIGN);
207 };
208
209 static const struct iio_event_spec adxl345_events[] = {
210 {
211 /* activity */
212 .type = IIO_EV_TYPE_MAG,
213 .dir = IIO_EV_DIR_RISING,
214 .mask_shared_by_type =
215 BIT(IIO_EV_INFO_ENABLE) |
216 BIT(IIO_EV_INFO_SCALE) |
217 BIT(IIO_EV_INFO_VALUE),
218 },
219 {
220 /* activity, ac bit set */
221 .type = IIO_EV_TYPE_MAG_ADAPTIVE,
222 .dir = IIO_EV_DIR_RISING,
223 .mask_shared_by_type =
224 BIT(IIO_EV_INFO_ENABLE) |
225 BIT(IIO_EV_INFO_SCALE) |
226 BIT(IIO_EV_INFO_VALUE),
227 },
228 {
229 /* single tap */
230 .type = IIO_EV_TYPE_GESTURE,
231 .dir = IIO_EV_DIR_SINGLETAP,
232 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
233 .mask_shared_by_type =
234 BIT(IIO_EV_INFO_SCALE) |
235 BIT(IIO_EV_INFO_VALUE) |
236 BIT(IIO_EV_INFO_TIMEOUT),
237 },
238 {
239 /* double tap */
240 .type = IIO_EV_TYPE_GESTURE,
241 .dir = IIO_EV_DIR_DOUBLETAP,
242 .mask_shared_by_type =
243 BIT(IIO_EV_INFO_ENABLE) |
244 BIT(IIO_EV_INFO_SCALE) |
245 BIT(IIO_EV_INFO_VALUE) |
246 BIT(IIO_EV_INFO_RESET_TIMEOUT) |
247 BIT(IIO_EV_INFO_TAP2_MIN_DELAY),
248 },
249 };
250
251 #define ADXL345_CHANNEL(index, reg, axis) { \
252 .type = IIO_ACCEL, \
253 .modified = 1, \
254 .channel2 = IIO_MOD_##axis, \
255 .address = (reg), \
256 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
257 BIT(IIO_CHAN_INFO_CALIBBIAS), \
258 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
259 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
260 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE) | \
261 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
262 .scan_index = (index), \
263 .scan_type = { \
264 .sign = 's', \
265 .realbits = 13, \
266 .storagebits = 16, \
267 .endianness = IIO_LE, \
268 }, \
269 .event_spec = adxl345_events, \
270 .num_event_specs = ARRAY_SIZE(adxl345_events), \
271 }
272
273 enum adxl345_chans {
274 chan_x, chan_y, chan_z,
275 };
276
277 static const struct iio_event_spec adxl345_fake_chan_events[] = {
278 {
279 /* inactivity */
280 .type = IIO_EV_TYPE_MAG,
281 .dir = IIO_EV_DIR_FALLING,
282 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
283 .mask_shared_by_type =
284 BIT(IIO_EV_INFO_SCALE) |
285 BIT(IIO_EV_INFO_VALUE) |
286 BIT(IIO_EV_INFO_PERIOD),
287 },
288 {
289 /* inactivity, AC bit set */
290 .type = IIO_EV_TYPE_MAG_ADAPTIVE,
291 .dir = IIO_EV_DIR_FALLING,
292 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
293 .mask_shared_by_type =
294 BIT(IIO_EV_INFO_SCALE) |
295 BIT(IIO_EV_INFO_VALUE) |
296 BIT(IIO_EV_INFO_PERIOD),
297 },
298 };
299
300 static const struct iio_chan_spec adxl345_channels[] = {
301 ADXL345_CHANNEL(0, chan_x, X),
302 ADXL345_CHANNEL(1, chan_y, Y),
303 ADXL345_CHANNEL(2, chan_z, Z),
304 {
305 .type = IIO_ACCEL,
306 .modified = 1,
307 .channel2 = IIO_MOD_X_AND_Y_AND_Z,
308 .scan_index = -1, /* Fake channel */
309 .event_spec = adxl345_fake_chan_events,
310 .num_event_specs = ARRAY_SIZE(adxl345_fake_chan_events),
311 },
312 };
313
314 static const unsigned long adxl345_scan_masks[] = {
315 BIT(chan_x) | BIT(chan_y) | BIT(chan_z),
316 0
317 };
318
adxl345_is_volatile_reg(struct device * dev,unsigned int reg)319 bool adxl345_is_volatile_reg(struct device *dev, unsigned int reg)
320 {
321 switch (reg) {
322 case ADXL345_REG_DATA_AXIS(0):
323 case ADXL345_REG_DATA_AXIS(1):
324 case ADXL345_REG_DATA_AXIS(2):
325 case ADXL345_REG_DATA_AXIS(3):
326 case ADXL345_REG_DATA_AXIS(4):
327 case ADXL345_REG_DATA_AXIS(5):
328 case ADXL345_REG_ACT_TAP_STATUS:
329 case ADXL345_REG_FIFO_STATUS:
330 case ADXL345_REG_INT_SOURCE:
331 return true;
332 default:
333 return false;
334 }
335 }
336 EXPORT_SYMBOL_NS_GPL(adxl345_is_volatile_reg, "IIO_ADXL345");
337
338 /**
339 * adxl345_set_measure_en() - Enable and disable measuring.
340 *
341 * @st: The device data.
342 * @en: Enable measurements, else standby mode.
343 *
344 * For lowest power operation, standby mode can be used. In standby mode,
345 * current consumption is supposed to be reduced to 0.1uA (typical). In this
346 * mode no measurements are made. Placing the device into standby mode
347 * preserves the contents of FIFO.
348 *
349 * Return: Returns 0 if successful, or a negative error value.
350 */
adxl345_set_measure_en(struct adxl345_state * st,bool en)351 static int adxl345_set_measure_en(struct adxl345_state *st, bool en)
352 {
353 return regmap_assign_bits(st->regmap, ADXL345_REG_POWER_CTL,
354 ADXL345_POWER_CTL_MEASURE, en);
355 }
356
357 /* activity / inactivity */
358
adxl345_set_inact_threshold(struct adxl345_state * st,unsigned int threshold)359 static int adxl345_set_inact_threshold(struct adxl345_state *st,
360 unsigned int threshold)
361 {
362 int ret;
363
364 st->inact_threshold = min(U8_MAX, threshold);
365
366 ret = regmap_write(st->regmap,
367 adxl345_act_thresh_reg[ADXL345_INACTIVITY],
368 st->inact_threshold);
369 if (ret)
370 return ret;
371
372 return regmap_write(st->regmap,
373 adxl345_act_thresh_reg[ADXL345_INACTIVITY_FF],
374 st->inact_threshold);
375 }
376
adxl345_set_default_time(struct adxl345_state * st)377 static int adxl345_set_default_time(struct adxl345_state *st)
378 {
379 int max_boundary = U8_MAX;
380 int min_boundary = 10;
381 enum adxl345_odr odr;
382 unsigned int regval;
383 unsigned int val;
384 int ret;
385
386 /* Generated inactivity time based on ODR */
387 ret = regmap_read(st->regmap, ADXL345_REG_BW_RATE, ®val);
388 if (ret)
389 return ret;
390
391 odr = FIELD_GET(ADXL345_BW_RATE_MSK, regval);
392 val = clamp(max_boundary - adxl345_odr_tbl[odr][0],
393 min_boundary, max_boundary);
394 st->inact_time_ms = MILLI * val;
395
396 /* Inactivity time in s */
397 return regmap_write(st->regmap, ADXL345_REG_TIME_INACT, val);
398 }
399
adxl345_set_inactivity_time(struct adxl345_state * st,u32 val_int)400 static int adxl345_set_inactivity_time(struct adxl345_state *st, u32 val_int)
401 {
402 st->inact_time_ms = MILLI * val_int;
403
404 return regmap_write(st->regmap, ADXL345_REG_TIME_INACT, val_int);
405 }
406
adxl345_set_freefall_time(struct adxl345_state * st,u32 val_fract)407 static int adxl345_set_freefall_time(struct adxl345_state *st, u32 val_fract)
408 {
409 /*
410 * Datasheet max. value is 255 * 5000 us = 1.275000 seconds.
411 *
412 * Recommended values between 100ms and 350ms (0x14 to 0x46)
413 */
414 st->inact_time_ms = DIV_ROUND_UP(val_fract, MILLI);
415
416 return regmap_write(st->regmap, ADXL345_REG_TIME_FF,
417 DIV_ROUND_CLOSEST(val_fract, 5));
418 }
419
420 /**
421 * adxl345_set_inact_time - Configure inactivity time explicitly or by ODR.
422 * @st: The sensor state instance.
423 * @val_int: The inactivity time, integer part.
424 * @val_fract: The inactivity time, fractional part when val_int is 0.
425 *
426 * Inactivity time can be configured between 1 and 255 seconds. If a user sets
427 * val_s to 0, a default inactivity time is calculated automatically (since 0 is
428 * also invalid and undefined by the sensor).
429 *
430 * In such cases, power consumption should be considered: the inactivity period
431 * should be shorter at higher sampling frequencies and longer at lower ones.
432 * Specifically, for frequencies above 255 Hz, the default is set to 10 seconds;
433 * for frequencies below 10 Hz, it defaults to 255 seconds.
434 *
435 * The calculation method subtracts the integer part of the configured sample
436 * frequency from 255 to estimate the inactivity time in seconds. Sub-Hertz
437 * values are ignored in this approximation. Since the recommended output data
438 * rates (ODRs) for features like activity/inactivity detection, sleep modes,
439 * and free fall range between 12.5 Hz and 400 Hz, frequencies outside this
440 * range will either use the defined boundary defaults or require explicit
441 * configuration via val_s.
442 *
443 * Return: 0 or error value.
444 */
adxl345_set_inact_time(struct adxl345_state * st,u32 val_int,u32 val_fract)445 static int adxl345_set_inact_time(struct adxl345_state *st, u32 val_int,
446 u32 val_fract)
447 {
448 if (val_int > 0) {
449 /* Time >= 1s, inactivity */
450 return adxl345_set_inactivity_time(st, val_int);
451 } else if (val_int == 0) {
452 if (val_fract > 0) {
453 /* Time < 1s, free-fall */
454 return adxl345_set_freefall_time(st, val_fract);
455 } else if (val_fract == 0) {
456 /* Time == 0.0s */
457 return adxl345_set_default_time(st);
458 }
459 }
460
461 /* Do not support negative or wrong input. */
462 return -EINVAL;
463 }
464
465 /**
466 * adxl345_is_act_inact_ac() - Verify if AC or DC coupling is currently enabled.
467 *
468 * @st: The device data.
469 * @type: The activity or inactivity type.
470 *
471 * Given a type of activity / inactivity combined with either AC coupling set or
472 * default to DC, this function verifies if the combination is currently
473 * configured, hence enabled or not.
474 *
475 * Return: true if configured coupling matches the provided type, else a negative
476 * error value.
477 */
adxl345_is_act_inact_ac(struct adxl345_state * st,enum adxl345_activity_type type)478 static int adxl345_is_act_inact_ac(struct adxl345_state *st,
479 enum adxl345_activity_type type)
480 {
481 unsigned int regval;
482 bool coupling;
483 int ret;
484
485 if (type == ADXL345_INACTIVITY_FF)
486 return true;
487
488 ret = regmap_read(st->regmap, ADXL345_REG_ACT_INACT_CTRL, ®val);
489 if (ret)
490 return ret;
491
492 coupling = adxl345_act_acdc_msk[type] & regval;
493
494 switch (type) {
495 case ADXL345_ACTIVITY:
496 case ADXL345_INACTIVITY:
497 return coupling == ADXL345_COUPLING_DC;
498 case ADXL345_ACTIVITY_AC:
499 case ADXL345_INACTIVITY_AC:
500 return coupling == ADXL345_COUPLING_AC;
501 default:
502 return -EINVAL;
503 }
504 }
505
506 /**
507 * adxl345_set_act_inact_ac() - Configure AC coupling or DC coupling.
508 *
509 * @st: The device data.
510 * @type: Provide a type of activity or inactivity.
511 * @cmd_en: enable or disable AC coupling.
512 *
513 * Enables AC coupling or DC coupling depending on the provided type argument.
514 * Note: Activity and inactivity can be either AC coupled or DC coupled not
515 * both at the same time.
516 *
517 * Return: 0 if successful, else error value.
518 */
adxl345_set_act_inact_ac(struct adxl345_state * st,enum adxl345_activity_type type,bool cmd_en)519 static int adxl345_set_act_inact_ac(struct adxl345_state *st,
520 enum adxl345_activity_type type,
521 bool cmd_en)
522 {
523 unsigned int act_inact_ac;
524
525 if (type == ADXL345_ACTIVITY_AC || type == ADXL345_INACTIVITY_AC)
526 act_inact_ac = ADXL345_COUPLING_AC && cmd_en;
527 else
528 act_inact_ac = ADXL345_COUPLING_DC && cmd_en;
529
530 /*
531 * A setting of false selects dc-coupled operation, and a setting of
532 * true enables ac-coupled operation. In dc-coupled operation, the
533 * current acceleration magnitude is compared directly with
534 * ADXL345_REG_THRESH_ACT and ADXL345_REG_THRESH_INACT to determine
535 * whether activity or inactivity is detected.
536 *
537 * In ac-coupled operation for activity detection, the acceleration
538 * value at the start of activity detection is taken as a reference
539 * value. New samples of acceleration are then compared to this
540 * reference value, and if the magnitude of the difference exceeds the
541 * ADXL345_REG_THRESH_ACT value, the device triggers an activity
542 * interrupt.
543 *
544 * Similarly, in ac-coupled operation for inactivity detection, a
545 * reference value is used for comparison and is updated whenever the
546 * device exceeds the inactivity threshold. After the reference value
547 * is selected, the device compares the magnitude of the difference
548 * between the reference value and the current acceleration with
549 * ADXL345_REG_THRESH_INACT. If the difference is less than the value in
550 * ADXL345_REG_THRESH_INACT for the time in ADXL345_REG_TIME_INACT, the
551 * device is considered inactive and the inactivity interrupt is
552 * triggered. [quoted from p. 24, ADXL345 datasheet Rev. G]
553 *
554 * In a conclusion, the first acceleration snapshot sample which hit the
555 * threshold in a particular direction is always taken as acceleration
556 * reference value to that direction. Since for the hardware activity
557 * and inactivity depend on the x/y/z axis, so do ac and dc coupling.
558 * Note, this sw driver always enables or disables all three x/y/z axis
559 * for detection via act_axis_ctrl and inact_axis_ctrl, respectively.
560 * Where in dc-coupling samples are compared against the thresholds, in
561 * ac-coupling measurement difference to the first acceleration
562 * reference value are compared against the threshold. So, ac-coupling
563 * allows for a bit more dynamic compensation depending on the initial
564 * sample.
565 */
566 return regmap_assign_bits(st->regmap, ADXL345_REG_ACT_INACT_CTRL,
567 adxl345_act_acdc_msk[type], act_inact_ac);
568 }
569
adxl345_is_act_inact_en(struct adxl345_state * st,enum adxl345_activity_type type)570 static int adxl345_is_act_inact_en(struct adxl345_state *st,
571 enum adxl345_activity_type type)
572 {
573 unsigned int axis_ctrl;
574 unsigned int regval;
575 bool int_en, en;
576 int ret;
577
578 ret = regmap_read(st->regmap, ADXL345_REG_ACT_INACT_CTRL, &axis_ctrl);
579 if (ret)
580 return ret;
581
582 /* Check if axis for activity are enabled */
583 switch (type) {
584 case ADXL345_ACTIVITY:
585 case ADXL345_ACTIVITY_AC:
586 en = FIELD_GET(ADXL345_ACT_XYZ_EN, axis_ctrl);
587 if (!en)
588 return false;
589 break;
590 case ADXL345_INACTIVITY:
591 case ADXL345_INACTIVITY_AC:
592 en = FIELD_GET(ADXL345_INACT_XYZ_EN, axis_ctrl);
593 if (!en)
594 return false;
595 break;
596 case ADXL345_INACTIVITY_FF:
597 en = true;
598 break;
599 default:
600 return -EINVAL;
601 }
602
603 /* Check if specific interrupt is enabled */
604 ret = regmap_read(st->regmap, ADXL345_REG_INT_ENABLE, ®val);
605 if (ret)
606 return ret;
607
608 int_en = adxl345_act_int_reg[type] & regval;
609 if (!int_en)
610 return false;
611
612 /* Check if configured coupling matches provided type */
613 return adxl345_is_act_inact_ac(st, type);
614 }
615
adxl345_set_act_inact_linkbit(struct adxl345_state * st,enum adxl345_activity_type type,bool en)616 static int adxl345_set_act_inact_linkbit(struct adxl345_state *st,
617 enum adxl345_activity_type type,
618 bool en)
619 {
620 int act_ac_en, inact_ac_en;
621 int act_en, inact_en;
622
623 act_en = adxl345_is_act_inact_en(st, ADXL345_ACTIVITY);
624 if (act_en < 0)
625 return act_en;
626
627 act_ac_en = adxl345_is_act_inact_en(st, ADXL345_ACTIVITY_AC);
628 if (act_ac_en < 0)
629 return act_ac_en;
630
631 if (type == ADXL345_INACTIVITY_FF) {
632 inact_en = false;
633 } else {
634 inact_en = adxl345_is_act_inact_en(st, ADXL345_INACTIVITY);
635 if (inact_en < 0)
636 return inact_en;
637
638 inact_ac_en = adxl345_is_act_inact_en(st, ADXL345_INACTIVITY_AC);
639 if (inact_ac_en < 0)
640 return inact_ac_en;
641
642 inact_en = inact_en || inact_ac_en;
643 }
644
645 act_en = act_en || act_ac_en;
646
647 return regmap_assign_bits(st->regmap, ADXL345_REG_POWER_CTL,
648 ADXL345_POWER_CTL_INACT_MSK,
649 en && act_en && inact_en);
650 }
651
adxl345_set_act_inact_en(struct adxl345_state * st,enum adxl345_activity_type type,bool cmd_en)652 static int adxl345_set_act_inact_en(struct adxl345_state *st,
653 enum adxl345_activity_type type,
654 bool cmd_en)
655 {
656 unsigned int axis_ctrl;
657 unsigned int threshold;
658 unsigned int period;
659 int ret;
660
661 if (cmd_en) {
662 /* When turning on, check if threshold is valid */
663 if (type == ADXL345_ACTIVITY || type == ADXL345_ACTIVITY_AC) {
664 ret = regmap_read(st->regmap,
665 adxl345_act_thresh_reg[type],
666 &threshold);
667 if (ret)
668 return ret;
669 } else {
670 threshold = st->inact_threshold;
671 }
672
673 if (!threshold) /* Just ignore the command if threshold is 0 */
674 return 0;
675
676 /* When turning on inactivity, check if inact time is valid */
677 if (type == ADXL345_INACTIVITY || type == ADXL345_INACTIVITY_AC) {
678 ret = regmap_read(st->regmap,
679 ADXL345_REG_TIME_INACT,
680 &period);
681 if (ret)
682 return ret;
683
684 if (!period)
685 return 0;
686 }
687 } else {
688 /*
689 * When turning off an activity, ensure that the correct
690 * coupling event is specified. This step helps prevent misuse -
691 * for example, if an AC-coupled activity is active and the
692 * current call attempts to turn off a DC-coupled activity, this
693 * inconsistency should be detected here.
694 */
695 if (adxl345_is_act_inact_ac(st, type) <= 0)
696 return 0;
697 }
698
699 /* Start modifying configuration registers */
700 ret = adxl345_set_measure_en(st, false);
701 if (ret)
702 return ret;
703
704 /* Enable axis according to the command */
705 switch (type) {
706 case ADXL345_ACTIVITY:
707 case ADXL345_ACTIVITY_AC:
708 axis_ctrl = ADXL345_ACT_XYZ_EN;
709 break;
710 case ADXL345_INACTIVITY:
711 case ADXL345_INACTIVITY_AC:
712 axis_ctrl = ADXL345_INACT_XYZ_EN;
713 break;
714 case ADXL345_INACTIVITY_FF:
715 axis_ctrl = ADXL345_ACT_INACT_NO_AXIS_EN;
716 break;
717 default:
718 return -EINVAL;
719 }
720
721 ret = regmap_assign_bits(st->regmap, ADXL345_REG_ACT_INACT_CTRL,
722 axis_ctrl, cmd_en);
723 if (ret)
724 return ret;
725
726 /* Update AC/DC-coupling according to the command */
727 ret = adxl345_set_act_inact_ac(st, type, cmd_en);
728 if (ret)
729 return ret;
730
731 /* Enable the interrupt line, according to the command */
732 ret = regmap_assign_bits(st->regmap, ADXL345_REG_INT_ENABLE,
733 adxl345_act_int_reg[type], cmd_en);
734 if (ret)
735 return ret;
736
737 /* Set link-bit and auto-sleep only when ACT and INACT are enabled */
738 ret = adxl345_set_act_inact_linkbit(st, type, cmd_en);
739 if (ret)
740 return ret;
741
742 return adxl345_set_measure_en(st, true);
743 }
744
745 /* tap */
746
_adxl345_set_tap_int(struct adxl345_state * st,enum adxl345_tap_type type,bool state)747 static int _adxl345_set_tap_int(struct adxl345_state *st,
748 enum adxl345_tap_type type, bool state)
749 {
750 unsigned int int_map = 0x00;
751 unsigned int tap_threshold;
752 bool axis_valid;
753 bool singletap_args_valid = false;
754 bool doubletap_args_valid = false;
755 bool en = false;
756 u32 axis_ctrl;
757 int ret;
758
759 ret = regmap_read(st->regmap, ADXL345_REG_TAP_AXIS, &axis_ctrl);
760 if (ret)
761 return ret;
762
763 axis_valid = FIELD_GET(ADXL345_REG_TAP_AXIS_MSK, axis_ctrl) > 0;
764
765 ret = regmap_read(st->regmap, ADXL345_REG_THRESH_TAP, &tap_threshold);
766 if (ret)
767 return ret;
768
769 /*
770 * Note: A value of 0 for threshold and/or dur may result in undesirable
771 * behavior if single tap/double tap interrupts are enabled.
772 */
773 singletap_args_valid = tap_threshold > 0 && st->tap_duration_us > 0;
774
775 if (type == ADXL345_SINGLE_TAP) {
776 en = axis_valid && singletap_args_valid;
777 } else {
778 /* doubletap: Window must be equal or greater than latent! */
779 doubletap_args_valid = st->tap_latent_us > 0 &&
780 st->tap_window_us > 0 &&
781 st->tap_window_us >= st->tap_latent_us;
782
783 en = axis_valid && singletap_args_valid && doubletap_args_valid;
784 }
785
786 if (state && en)
787 int_map |= adxl345_tap_int_reg[type];
788
789 return regmap_update_bits(st->regmap, ADXL345_REG_INT_ENABLE,
790 adxl345_tap_int_reg[type], int_map);
791 }
792
adxl345_is_tap_en(struct adxl345_state * st,enum iio_modifier axis,enum adxl345_tap_type type,bool * en)793 static int adxl345_is_tap_en(struct adxl345_state *st,
794 enum iio_modifier axis,
795 enum adxl345_tap_type type, bool *en)
796 {
797 unsigned int regval;
798 u32 axis_ctrl;
799 int ret;
800
801 ret = regmap_read(st->regmap, ADXL345_REG_TAP_AXIS, &axis_ctrl);
802 if (ret)
803 return ret;
804
805 /* Verify if axis is enabled for the tap detection. */
806 switch (axis) {
807 case IIO_MOD_X:
808 *en = FIELD_GET(ADXL345_TAP_X_EN, axis_ctrl);
809 break;
810 case IIO_MOD_Y:
811 *en = FIELD_GET(ADXL345_TAP_Y_EN, axis_ctrl);
812 break;
813 case IIO_MOD_Z:
814 *en = FIELD_GET(ADXL345_TAP_Z_EN, axis_ctrl);
815 break;
816 default:
817 *en = false;
818 return -EINVAL;
819 }
820
821 if (*en) {
822 /*
823 * If axis allow for tap detection, verify if the interrupt is
824 * enabled for tap detection.
825 */
826 ret = regmap_read(st->regmap, ADXL345_REG_INT_ENABLE, ®val);
827 if (ret)
828 return ret;
829
830 *en = adxl345_tap_int_reg[type] & regval;
831 }
832
833 return 0;
834 }
835
adxl345_set_singletap_en(struct adxl345_state * st,enum iio_modifier axis,bool en)836 static int adxl345_set_singletap_en(struct adxl345_state *st,
837 enum iio_modifier axis, bool en)
838 {
839 int ret;
840 u32 axis_ctrl;
841
842 switch (axis) {
843 case IIO_MOD_X:
844 axis_ctrl = ADXL345_TAP_X_EN;
845 break;
846 case IIO_MOD_Y:
847 axis_ctrl = ADXL345_TAP_Y_EN;
848 break;
849 case IIO_MOD_Z:
850 axis_ctrl = ADXL345_TAP_Z_EN;
851 break;
852 default:
853 return -EINVAL;
854 }
855
856 if (en)
857 ret = regmap_set_bits(st->regmap, ADXL345_REG_TAP_AXIS,
858 axis_ctrl);
859 else
860 ret = regmap_clear_bits(st->regmap, ADXL345_REG_TAP_AXIS,
861 axis_ctrl);
862 if (ret)
863 return ret;
864
865 return _adxl345_set_tap_int(st, ADXL345_SINGLE_TAP, en);
866 }
867
adxl345_set_doubletap_en(struct adxl345_state * st,bool en)868 static int adxl345_set_doubletap_en(struct adxl345_state *st, bool en)
869 {
870 int ret;
871
872 /*
873 * Generally suppress detection of spikes during the latency period as
874 * double taps here, this is fully optional for double tap detection
875 */
876 ret = regmap_assign_bits(st->regmap, ADXL345_REG_TAP_AXIS,
877 ADXL345_REG_TAP_SUPPRESS, en);
878 if (ret)
879 return ret;
880
881 return _adxl345_set_tap_int(st, ADXL345_DOUBLE_TAP, en);
882 }
883
_adxl345_set_tap_time(struct adxl345_state * st,enum adxl345_tap_time_type type,u32 val_us)884 static int _adxl345_set_tap_time(struct adxl345_state *st,
885 enum adxl345_tap_time_type type, u32 val_us)
886 {
887 unsigned int regval;
888
889 switch (type) {
890 case ADXL345_TAP_TIME_WINDOW:
891 st->tap_window_us = val_us;
892 break;
893 case ADXL345_TAP_TIME_LATENT:
894 st->tap_latent_us = val_us;
895 break;
896 case ADXL345_TAP_TIME_DUR:
897 st->tap_duration_us = val_us;
898 break;
899 }
900
901 /*
902 * The scale factor is 1250us / LSB for tap_window_us and tap_latent_us.
903 * For tap_duration_us the scale factor is 625us / LSB.
904 */
905 if (type == ADXL345_TAP_TIME_DUR)
906 regval = DIV_ROUND_CLOSEST(val_us, 625);
907 else
908 regval = DIV_ROUND_CLOSEST(val_us, 1250);
909
910 return regmap_write(st->regmap, adxl345_tap_time_reg[type], regval);
911 }
912
adxl345_set_tap_duration(struct adxl345_state * st,u32 val_int,u32 val_fract_us)913 static int adxl345_set_tap_duration(struct adxl345_state *st, u32 val_int,
914 u32 val_fract_us)
915 {
916 /*
917 * Max value is 255 * 625 us = 0.159375 seconds
918 *
919 * Note: the scaling is similar to the scaling in the ADXL380
920 */
921 if (val_int || val_fract_us > 159375)
922 return -EINVAL;
923
924 return _adxl345_set_tap_time(st, ADXL345_TAP_TIME_DUR, val_fract_us);
925 }
926
adxl345_set_tap_window(struct adxl345_state * st,u32 val_int,u32 val_fract_us)927 static int adxl345_set_tap_window(struct adxl345_state *st, u32 val_int,
928 u32 val_fract_us)
929 {
930 /*
931 * Max value is 255 * 1250 us = 0.318750 seconds
932 *
933 * Note: the scaling is similar to the scaling in the ADXL380
934 */
935 if (val_int || val_fract_us > 318750)
936 return -EINVAL;
937
938 return _adxl345_set_tap_time(st, ADXL345_TAP_TIME_WINDOW, val_fract_us);
939 }
940
adxl345_set_tap_latent(struct adxl345_state * st,u32 val_int,u32 val_fract_us)941 static int adxl345_set_tap_latent(struct adxl345_state *st, u32 val_int,
942 u32 val_fract_us)
943 {
944 /*
945 * Max value is 255 * 1250 us = 0.318750 seconds
946 *
947 * Note: the scaling is similar to the scaling in the ADXL380
948 */
949 if (val_int || val_fract_us > 318750)
950 return -EINVAL;
951
952 return _adxl345_set_tap_time(st, ADXL345_TAP_TIME_LATENT, val_fract_us);
953 }
954
adxl345_find_odr(struct adxl345_state * st,int val,int val2,enum adxl345_odr * odr)955 static int adxl345_find_odr(struct adxl345_state *st, int val,
956 int val2, enum adxl345_odr *odr)
957 {
958 int i;
959
960 for (i = 0; i < ARRAY_SIZE(adxl345_odr_tbl); i++) {
961 if (val == adxl345_odr_tbl[i][0] &&
962 val2 == adxl345_odr_tbl[i][1]) {
963 *odr = i;
964 return 0;
965 }
966 }
967
968 return -EINVAL;
969 }
970
adxl345_set_odr(struct adxl345_state * st,enum adxl345_odr odr)971 static int adxl345_set_odr(struct adxl345_state *st, enum adxl345_odr odr)
972 {
973 int ret;
974
975 ret = regmap_update_bits(st->regmap, ADXL345_REG_BW_RATE,
976 ADXL345_BW_RATE_MSK,
977 FIELD_PREP(ADXL345_BW_RATE_MSK, odr));
978 if (ret)
979 return ret;
980
981 /* update inactivity time by ODR */
982 return adxl345_set_inact_time(st, 0, 0);
983 }
984
adxl345_find_range(struct adxl345_state * st,int val,int val2,enum adxl345_range * range)985 static int adxl345_find_range(struct adxl345_state *st, int val, int val2,
986 enum adxl345_range *range)
987 {
988 int i;
989
990 for (i = 0; i < ARRAY_SIZE(adxl345_fullres_range_tbl); i++) {
991 if (val == adxl345_fullres_range_tbl[i][0] &&
992 val2 == adxl345_fullres_range_tbl[i][1]) {
993 *range = i;
994 return 0;
995 }
996 }
997
998 return -EINVAL;
999 }
1000
adxl345_set_range(struct adxl345_state * st,enum adxl345_range range)1001 static int adxl345_set_range(struct adxl345_state *st, enum adxl345_range range)
1002 {
1003 unsigned int act_threshold, inact_threshold;
1004 unsigned int range_old;
1005 unsigned int regval;
1006 int ret;
1007
1008 ret = regmap_read(st->regmap, ADXL345_REG_DATA_FORMAT, ®val);
1009 if (ret)
1010 return ret;
1011 range_old = FIELD_GET(ADXL345_DATA_FORMAT_RANGE, regval);
1012
1013 ret = regmap_read(st->regmap,
1014 adxl345_act_thresh_reg[ADXL345_ACTIVITY],
1015 &act_threshold);
1016 if (ret)
1017 return ret;
1018
1019 ret = regmap_update_bits(st->regmap, ADXL345_REG_DATA_FORMAT,
1020 ADXL345_DATA_FORMAT_RANGE,
1021 FIELD_PREP(ADXL345_DATA_FORMAT_RANGE, range));
1022 if (ret)
1023 return ret;
1024
1025 act_threshold = act_threshold * adxl345_range_factor_tbl[range_old]
1026 / adxl345_range_factor_tbl[range];
1027 act_threshold = min(U8_MAX, max(1, act_threshold));
1028
1029 inact_threshold = st->inact_threshold;
1030 inact_threshold = inact_threshold * adxl345_range_factor_tbl[range_old]
1031 / adxl345_range_factor_tbl[range];
1032 inact_threshold = min(U8_MAX, max(1, inact_threshold));
1033
1034 ret = regmap_write(st->regmap, adxl345_act_thresh_reg[ADXL345_ACTIVITY],
1035 act_threshold);
1036 if (ret)
1037 return ret;
1038
1039 return adxl345_set_inact_threshold(st, inact_threshold);
1040 }
1041
adxl345_read_avail(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,const int ** vals,int * type,int * length,long mask)1042 static int adxl345_read_avail(struct iio_dev *indio_dev,
1043 struct iio_chan_spec const *chan,
1044 const int **vals, int *type,
1045 int *length, long mask)
1046 {
1047 switch (mask) {
1048 case IIO_CHAN_INFO_SCALE:
1049 *vals = (int *)adxl345_fullres_range_tbl;
1050 *type = IIO_VAL_INT_PLUS_MICRO;
1051 *length = ARRAY_SIZE(adxl345_fullres_range_tbl) * 2;
1052 return IIO_AVAIL_LIST;
1053 case IIO_CHAN_INFO_SAMP_FREQ:
1054 *vals = (int *)adxl345_odr_tbl;
1055 *type = IIO_VAL_INT_PLUS_MICRO;
1056 *length = ARRAY_SIZE(adxl345_odr_tbl) * 2;
1057 return IIO_AVAIL_LIST;
1058 }
1059
1060 return -EINVAL;
1061 }
1062
adxl345_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)1063 static int adxl345_read_raw(struct iio_dev *indio_dev,
1064 struct iio_chan_spec const *chan,
1065 int *val, int *val2, long mask)
1066 {
1067 struct adxl345_state *st = iio_priv(indio_dev);
1068 __le16 accel;
1069 unsigned int regval;
1070 enum adxl345_odr odr;
1071 enum adxl345_range range;
1072 int ret;
1073
1074 switch (mask) {
1075 case IIO_CHAN_INFO_RAW:
1076 /*
1077 * Data is stored in adjacent registers:
1078 * ADXL345_REG_DATA(X0/Y0/Z0) contain the least significant byte
1079 * and ADXL345_REG_DATA(X0/Y0/Z0) + 1 the most significant byte
1080 */
1081 ret = regmap_bulk_read(st->regmap,
1082 ADXL345_REG_DATA_AXIS(chan->address),
1083 &accel, sizeof(accel));
1084 if (ret)
1085 return ret;
1086
1087 *val = sign_extend32(le16_to_cpu(accel), 12);
1088 return IIO_VAL_INT;
1089 case IIO_CHAN_INFO_SCALE:
1090 ret = regmap_read(st->regmap, ADXL345_REG_DATA_FORMAT, ®val);
1091 if (ret)
1092 return ret;
1093 range = FIELD_GET(ADXL345_DATA_FORMAT_RANGE, regval);
1094 *val = adxl345_fullres_range_tbl[range][0];
1095 *val2 = adxl345_fullres_range_tbl[range][1];
1096 return IIO_VAL_INT_PLUS_MICRO;
1097 case IIO_CHAN_INFO_CALIBBIAS:
1098 ret = regmap_read(st->regmap,
1099 ADXL345_REG_OFS_AXIS(chan->address), ®val);
1100 if (ret)
1101 return ret;
1102 /*
1103 * 8-bit resolution at +/- 2g, that is 4x accel data scale
1104 * factor
1105 */
1106 *val = sign_extend32(regval, 7) * 4;
1107
1108 return IIO_VAL_INT;
1109 case IIO_CHAN_INFO_SAMP_FREQ:
1110 ret = regmap_read(st->regmap, ADXL345_REG_BW_RATE, ®val);
1111 if (ret)
1112 return ret;
1113 odr = FIELD_GET(ADXL345_BW_RATE_MSK, regval);
1114 *val = adxl345_odr_tbl[odr][0];
1115 *val2 = adxl345_odr_tbl[odr][1];
1116 return IIO_VAL_INT_PLUS_MICRO;
1117 }
1118
1119 return -EINVAL;
1120 }
1121
adxl345_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)1122 static int adxl345_write_raw(struct iio_dev *indio_dev,
1123 struct iio_chan_spec const *chan,
1124 int val, int val2, long mask)
1125 {
1126 struct adxl345_state *st = iio_priv(indio_dev);
1127 enum adxl345_range range;
1128 enum adxl345_odr odr;
1129 int ret;
1130
1131 ret = adxl345_set_measure_en(st, false);
1132 if (ret)
1133 return ret;
1134
1135 switch (mask) {
1136 case IIO_CHAN_INFO_CALIBBIAS:
1137 /*
1138 * 8-bit resolution at +/- 2g, that is 4x accel data scale
1139 * factor
1140 */
1141 ret = regmap_write(st->regmap,
1142 ADXL345_REG_OFS_AXIS(chan->address),
1143 val / 4);
1144 if (ret)
1145 return ret;
1146 break;
1147 case IIO_CHAN_INFO_SAMP_FREQ:
1148 ret = adxl345_find_odr(st, val, val2, &odr);
1149 if (ret)
1150 return ret;
1151
1152 ret = adxl345_set_odr(st, odr);
1153 if (ret)
1154 return ret;
1155 break;
1156 case IIO_CHAN_INFO_SCALE:
1157 ret = adxl345_find_range(st, val, val2, &range);
1158 if (ret)
1159 return ret;
1160
1161 ret = adxl345_set_range(st, range);
1162 if (ret)
1163 return ret;
1164 break;
1165 default:
1166 return -EINVAL;
1167 }
1168
1169 return adxl345_set_measure_en(st, true);
1170 }
1171
adxl345_read_mag_config(struct adxl345_state * st,enum iio_event_direction dir,enum adxl345_activity_type type_act,enum adxl345_activity_type type_inact)1172 static int adxl345_read_mag_config(struct adxl345_state *st,
1173 enum iio_event_direction dir,
1174 enum adxl345_activity_type type_act,
1175 enum adxl345_activity_type type_inact)
1176 {
1177 switch (dir) {
1178 case IIO_EV_DIR_RISING:
1179 return !!adxl345_is_act_inact_en(st, type_act);
1180 case IIO_EV_DIR_FALLING:
1181 return !!adxl345_is_act_inact_en(st, type_inact);
1182 default:
1183 return -EINVAL;
1184 }
1185 }
1186
adxl345_write_mag_config(struct adxl345_state * st,enum iio_event_direction dir,enum adxl345_activity_type type_act,enum adxl345_activity_type type_inact,bool state)1187 static int adxl345_write_mag_config(struct adxl345_state *st,
1188 enum iio_event_direction dir,
1189 enum adxl345_activity_type type_act,
1190 enum adxl345_activity_type type_inact,
1191 bool state)
1192 {
1193 switch (dir) {
1194 case IIO_EV_DIR_RISING:
1195 return adxl345_set_act_inact_en(st, type_act, state);
1196 case IIO_EV_DIR_FALLING:
1197 return adxl345_set_act_inact_en(st, type_inact, state);
1198 default:
1199 return -EINVAL;
1200 }
1201 }
1202
adxl345_read_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir)1203 static int adxl345_read_event_config(struct iio_dev *indio_dev,
1204 const struct iio_chan_spec *chan,
1205 enum iio_event_type type,
1206 enum iio_event_direction dir)
1207 {
1208 struct adxl345_state *st = iio_priv(indio_dev);
1209 bool int_en;
1210 int ret;
1211
1212 switch (type) {
1213 case IIO_EV_TYPE_MAG:
1214 return adxl345_read_mag_config(st, dir,
1215 ADXL345_ACTIVITY,
1216 ADXL345_INACTIVITY);
1217 case IIO_EV_TYPE_MAG_ADAPTIVE:
1218 return adxl345_read_mag_config(st, dir,
1219 ADXL345_ACTIVITY_AC,
1220 ADXL345_INACTIVITY_AC);
1221 case IIO_EV_TYPE_GESTURE:
1222 switch (dir) {
1223 case IIO_EV_DIR_SINGLETAP:
1224 ret = adxl345_is_tap_en(st, chan->channel2,
1225 ADXL345_SINGLE_TAP, &int_en);
1226 if (ret)
1227 return ret;
1228 return int_en;
1229 case IIO_EV_DIR_DOUBLETAP:
1230 ret = adxl345_is_tap_en(st, chan->channel2,
1231 ADXL345_DOUBLE_TAP, &int_en);
1232 if (ret)
1233 return ret;
1234 return int_en;
1235 default:
1236 return -EINVAL;
1237 }
1238 default:
1239 return -EINVAL;
1240 }
1241 }
1242
adxl345_write_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,bool state)1243 static int adxl345_write_event_config(struct iio_dev *indio_dev,
1244 const struct iio_chan_spec *chan,
1245 enum iio_event_type type,
1246 enum iio_event_direction dir,
1247 bool state)
1248 {
1249 struct adxl345_state *st = iio_priv(indio_dev);
1250
1251 switch (type) {
1252 case IIO_EV_TYPE_MAG:
1253 return adxl345_write_mag_config(st, dir,
1254 ADXL345_ACTIVITY,
1255 ADXL345_INACTIVITY,
1256 state);
1257 case IIO_EV_TYPE_MAG_ADAPTIVE:
1258 return adxl345_write_mag_config(st, dir,
1259 ADXL345_ACTIVITY_AC,
1260 ADXL345_INACTIVITY_AC,
1261 state);
1262 case IIO_EV_TYPE_GESTURE:
1263 switch (dir) {
1264 case IIO_EV_DIR_SINGLETAP:
1265 return adxl345_set_singletap_en(st, chan->channel2, state);
1266 case IIO_EV_DIR_DOUBLETAP:
1267 return adxl345_set_doubletap_en(st, state);
1268 default:
1269 return -EINVAL;
1270 }
1271 default:
1272 return -EINVAL;
1273 }
1274 }
1275
adxl345_read_mag_value(struct adxl345_state * st,enum iio_event_direction dir,enum iio_event_info info,enum adxl345_activity_type type_act,enum adxl345_activity_type type_inact,int * val,int * val2)1276 static int adxl345_read_mag_value(struct adxl345_state *st,
1277 enum iio_event_direction dir,
1278 enum iio_event_info info,
1279 enum adxl345_activity_type type_act,
1280 enum adxl345_activity_type type_inact,
1281 int *val, int *val2)
1282 {
1283 unsigned int threshold;
1284 int ret;
1285
1286 switch (info) {
1287 case IIO_EV_INFO_VALUE:
1288 switch (dir) {
1289 case IIO_EV_DIR_RISING:
1290 ret = regmap_read(st->regmap,
1291 adxl345_act_thresh_reg[type_act],
1292 &threshold);
1293 if (ret)
1294 return ret;
1295 *val = 62500 * threshold;
1296 *val2 = MICRO;
1297 return IIO_VAL_FRACTIONAL;
1298 case IIO_EV_DIR_FALLING:
1299 *val = 62500 * st->inact_threshold;
1300 *val2 = MICRO;
1301 return IIO_VAL_FRACTIONAL;
1302 default:
1303 return -EINVAL;
1304 }
1305 case IIO_EV_INFO_PERIOD:
1306 *val = st->inact_time_ms;
1307 *val2 = MILLI;
1308 return IIO_VAL_FRACTIONAL;
1309 default:
1310 return -EINVAL;
1311 }
1312 }
1313
adxl345_write_mag_value(struct adxl345_state * st,enum iio_event_direction dir,enum iio_event_info info,enum adxl345_activity_type type_act,enum adxl345_activity_type type_inact,int val,int val2)1314 static int adxl345_write_mag_value(struct adxl345_state *st,
1315 enum iio_event_direction dir,
1316 enum iio_event_info info,
1317 enum adxl345_activity_type type_act,
1318 enum adxl345_activity_type type_inact,
1319 int val, int val2)
1320 {
1321 switch (info) {
1322 case IIO_EV_INFO_VALUE:
1323 /* Scaling factor 62.5mg/LSB, i.e. ~16g corresponds to 0xff */
1324 val = DIV_ROUND_CLOSEST(val * MICRO + val2, 62500);
1325 switch (dir) {
1326 case IIO_EV_DIR_RISING:
1327 return regmap_write(st->regmap,
1328 adxl345_act_thresh_reg[type_act],
1329 val);
1330 case IIO_EV_DIR_FALLING:
1331 return adxl345_set_inact_threshold(st, val);
1332 default:
1333 return -EINVAL;
1334 }
1335 case IIO_EV_INFO_PERIOD:
1336 return adxl345_set_inact_time(st, val, val2);
1337 default:
1338 return -EINVAL;
1339 }
1340 }
1341
adxl345_read_event_value(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int * val,int * val2)1342 static int adxl345_read_event_value(struct iio_dev *indio_dev,
1343 const struct iio_chan_spec *chan,
1344 enum iio_event_type type,
1345 enum iio_event_direction dir,
1346 enum iio_event_info info,
1347 int *val, int *val2)
1348 {
1349 struct adxl345_state *st = iio_priv(indio_dev);
1350 unsigned int tap_threshold;
1351 int ret;
1352
1353 /*
1354 * The event threshold LSB is fixed at 62.5 mg/LSB
1355 * 0.0625 * 9.80665 = 0.612915625 m/s^2
1356 */
1357 if (info == IIO_EV_INFO_SCALE) {
1358 *val = 0;
1359 *val2 = 612915;
1360 return IIO_VAL_INT_PLUS_MICRO;
1361 }
1362
1363 switch (type) {
1364 case IIO_EV_TYPE_MAG:
1365 return adxl345_read_mag_value(st, dir, info,
1366 ADXL345_ACTIVITY,
1367 ADXL345_INACTIVITY,
1368 val, val2);
1369 case IIO_EV_TYPE_MAG_ADAPTIVE:
1370 return adxl345_read_mag_value(st, dir, info,
1371 ADXL345_ACTIVITY_AC,
1372 ADXL345_INACTIVITY_AC,
1373 val, val2);
1374 case IIO_EV_TYPE_GESTURE:
1375 switch (info) {
1376 case IIO_EV_INFO_VALUE:
1377 ret = regmap_read(st->regmap, ADXL345_REG_THRESH_TAP,
1378 &tap_threshold);
1379 if (ret)
1380 return ret;
1381 *val = sign_extend32(tap_threshold, 7);
1382 return IIO_VAL_INT;
1383 case IIO_EV_INFO_TIMEOUT:
1384 *val = st->tap_duration_us;
1385 *val2 = MICRO;
1386 return IIO_VAL_FRACTIONAL;
1387 case IIO_EV_INFO_RESET_TIMEOUT:
1388 *val = st->tap_window_us;
1389 *val2 = MICRO;
1390 return IIO_VAL_FRACTIONAL;
1391 case IIO_EV_INFO_TAP2_MIN_DELAY:
1392 *val = st->tap_latent_us;
1393 *val2 = MICRO;
1394 return IIO_VAL_FRACTIONAL;
1395 default:
1396 return -EINVAL;
1397 }
1398 default:
1399 return -EINVAL;
1400 }
1401 }
1402
adxl345_write_event_value(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int val,int val2)1403 static int adxl345_write_event_value(struct iio_dev *indio_dev,
1404 const struct iio_chan_spec *chan,
1405 enum iio_event_type type,
1406 enum iio_event_direction dir,
1407 enum iio_event_info info,
1408 int val, int val2)
1409 {
1410 struct adxl345_state *st = iio_priv(indio_dev);
1411 int ret;
1412
1413 ret = adxl345_set_measure_en(st, false);
1414 if (ret)
1415 return ret;
1416
1417 if (info == IIO_EV_INFO_SCALE)
1418 return -EINVAL;
1419
1420 switch (type) {
1421 case IIO_EV_TYPE_MAG:
1422 ret = adxl345_write_mag_value(st, dir, info,
1423 ADXL345_ACTIVITY,
1424 ADXL345_INACTIVITY,
1425 val, val2);
1426 if (ret)
1427 return ret;
1428 break;
1429 case IIO_EV_TYPE_MAG_ADAPTIVE:
1430 ret = adxl345_write_mag_value(st, dir, info,
1431 ADXL345_ACTIVITY_AC,
1432 ADXL345_INACTIVITY_AC,
1433 val, val2);
1434 if (ret)
1435 return ret;
1436 break;
1437 case IIO_EV_TYPE_GESTURE:
1438 switch (info) {
1439 case IIO_EV_INFO_VALUE:
1440 ret = regmap_write(st->regmap, ADXL345_REG_THRESH_TAP,
1441 min(val, 0xFF));
1442 if (ret)
1443 return ret;
1444 break;
1445 case IIO_EV_INFO_TIMEOUT:
1446 ret = adxl345_set_tap_duration(st, val, val2);
1447 if (ret)
1448 return ret;
1449 break;
1450 case IIO_EV_INFO_RESET_TIMEOUT:
1451 ret = adxl345_set_tap_window(st, val, val2);
1452 if (ret)
1453 return ret;
1454 break;
1455 case IIO_EV_INFO_TAP2_MIN_DELAY:
1456 ret = adxl345_set_tap_latent(st, val, val2);
1457 if (ret)
1458 return ret;
1459 break;
1460 default:
1461 return -EINVAL;
1462 }
1463 break;
1464 default:
1465 return -EINVAL;
1466 }
1467
1468 return adxl345_set_measure_en(st, true);
1469 }
1470
adxl345_reg_access(struct iio_dev * indio_dev,unsigned int reg,unsigned int writeval,unsigned int * readval)1471 static int adxl345_reg_access(struct iio_dev *indio_dev, unsigned int reg,
1472 unsigned int writeval, unsigned int *readval)
1473 {
1474 struct adxl345_state *st = iio_priv(indio_dev);
1475
1476 if (readval)
1477 return regmap_read(st->regmap, reg, readval);
1478 return regmap_write(st->regmap, reg, writeval);
1479 }
1480
adxl345_set_watermark(struct iio_dev * indio_dev,unsigned int value)1481 static int adxl345_set_watermark(struct iio_dev *indio_dev, unsigned int value)
1482 {
1483 struct adxl345_state *st = iio_priv(indio_dev);
1484 const unsigned int fifo_mask = 0x1F, watermark_mask = 0x02;
1485 int ret;
1486
1487 value = min(value, ADXL345_FIFO_SIZE - 1);
1488
1489 ret = regmap_update_bits(st->regmap, ADXL345_REG_FIFO_CTL, fifo_mask, value);
1490 if (ret)
1491 return ret;
1492
1493 st->watermark = value;
1494 return regmap_update_bits(st->regmap, ADXL345_REG_INT_ENABLE,
1495 watermark_mask, ADXL345_INT_WATERMARK);
1496 }
1497
adxl345_write_raw_get_fmt(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,long mask)1498 static int adxl345_write_raw_get_fmt(struct iio_dev *indio_dev,
1499 struct iio_chan_spec const *chan,
1500 long mask)
1501 {
1502 switch (mask) {
1503 case IIO_CHAN_INFO_CALIBBIAS:
1504 return IIO_VAL_INT;
1505 case IIO_CHAN_INFO_SCALE:
1506 return IIO_VAL_INT_PLUS_MICRO;
1507 case IIO_CHAN_INFO_SAMP_FREQ:
1508 return IIO_VAL_INT_PLUS_MICRO;
1509 default:
1510 return -EINVAL;
1511 }
1512 }
1513
adxl345_powerdown(void * ptr)1514 static void adxl345_powerdown(void *ptr)
1515 {
1516 struct adxl345_state *st = ptr;
1517
1518 adxl345_set_measure_en(st, false);
1519 }
1520
adxl345_set_fifo(struct adxl345_state * st)1521 static int adxl345_set_fifo(struct adxl345_state *st)
1522 {
1523 unsigned int intio;
1524 int ret;
1525
1526 /* FIFO should only be configured while in standby mode */
1527 ret = adxl345_set_measure_en(st, false);
1528 if (ret)
1529 return ret;
1530
1531 ret = regmap_read(st->regmap, ADXL345_REG_INT_MAP, &intio);
1532 if (ret)
1533 return ret;
1534
1535 ret = regmap_write(st->regmap, ADXL345_REG_FIFO_CTL,
1536 FIELD_PREP(ADXL345_FIFO_CTL_SAMPLES_MSK,
1537 st->watermark) |
1538 FIELD_PREP(ADXL345_FIFO_CTL_TRIGGER_MSK, intio) |
1539 FIELD_PREP(ADXL345_FIFO_CTL_MODE_MSK,
1540 st->fifo_mode));
1541 if (ret)
1542 return ret;
1543
1544 return adxl345_set_measure_en(st, true);
1545 }
1546
1547 /**
1548 * adxl345_get_samples() - Read number of FIFO entries.
1549 * @st: The initialized state instance of this driver.
1550 *
1551 * The sensor does not support treating any axis individually, or exclude them
1552 * from measuring.
1553 *
1554 * Return: negative error, or value.
1555 */
adxl345_get_samples(struct adxl345_state * st)1556 static int adxl345_get_samples(struct adxl345_state *st)
1557 {
1558 unsigned int regval = 0;
1559 int ret;
1560
1561 ret = regmap_read(st->regmap, ADXL345_REG_FIFO_STATUS, ®val);
1562 if (ret)
1563 return ret;
1564
1565 return FIELD_GET(ADXL345_REG_FIFO_STATUS_MSK, regval);
1566 }
1567
1568 /**
1569 * adxl345_fifo_transfer() - Read samples number of elements.
1570 * @st: The instance of the state object of this sensor.
1571 * @samples: The number of lines in the FIFO referred to as fifo_entry.
1572 *
1573 * It is recommended that a multiple-byte read of all registers be performed to
1574 * prevent a change in data between reads of sequential registers. That is to
1575 * read out the data registers X0, X1, Y0, Y1, Z0, Z1, i.e. 6 bytes at once.
1576 *
1577 * Return: 0 or error value.
1578 */
adxl345_fifo_transfer(struct adxl345_state * st,int samples)1579 static int adxl345_fifo_transfer(struct adxl345_state *st, int samples)
1580 {
1581 int i, ret = 0;
1582
1583 for (i = 0; i < samples; i++) {
1584 ret = regmap_bulk_read(st->regmap, ADXL345_REG_XYZ_BASE,
1585 st->fifo_buf + (i * ADXL345_DIRS),
1586 sizeof(st->fifo_buf[0]) * ADXL345_DIRS);
1587 if (ret)
1588 return ret;
1589
1590 /*
1591 * To ensure that the FIFO has completely popped, there must be at least 5
1592 * us between the end of reading the data registers, signified by the
1593 * transition to register 0x38 from 0x37 or the CS pin going high, and the
1594 * start of new reads of the FIFO or reading the FIFO_STATUS register. For
1595 * SPI operation at 1.5 MHz or lower, the register addressing portion of the
1596 * transmission is sufficient delay to ensure the FIFO has completely
1597 * popped. It is necessary for SPI operation greater than 1.5 MHz to
1598 * de-assert the CS pin to ensure a total of 5 us, which is at most 3.4 us
1599 * at 5 MHz operation.
1600 */
1601 if (st->fifo_delay && samples > 1)
1602 udelay(3);
1603 }
1604 return ret;
1605 }
1606
1607 /**
1608 * adxl345_fifo_reset() - Empty the FIFO in error condition.
1609 * @st: The instance to the state object of the sensor.
1610 *
1611 * Read all elements of the FIFO. Reading the interrupt source register
1612 * resets the sensor.
1613 */
adxl345_fifo_reset(struct adxl345_state * st)1614 static void adxl345_fifo_reset(struct adxl345_state *st)
1615 {
1616 int regval;
1617 int samples;
1618
1619 adxl345_set_measure_en(st, false);
1620
1621 samples = adxl345_get_samples(st);
1622 if (samples > 0)
1623 adxl345_fifo_transfer(st, samples);
1624
1625 regmap_read(st->regmap, ADXL345_REG_INT_SOURCE, ®val);
1626
1627 adxl345_set_measure_en(st, true);
1628 }
1629
adxl345_buffer_postenable(struct iio_dev * indio_dev)1630 static int adxl345_buffer_postenable(struct iio_dev *indio_dev)
1631 {
1632 struct adxl345_state *st = iio_priv(indio_dev);
1633
1634 st->fifo_mode = ADXL345_FIFO_STREAM;
1635 return adxl345_set_fifo(st);
1636 }
1637
adxl345_buffer_predisable(struct iio_dev * indio_dev)1638 static int adxl345_buffer_predisable(struct iio_dev *indio_dev)
1639 {
1640 struct adxl345_state *st = iio_priv(indio_dev);
1641 int ret;
1642
1643 st->fifo_mode = ADXL345_FIFO_BYPASS;
1644 ret = adxl345_set_fifo(st);
1645 if (ret)
1646 return ret;
1647
1648 return regmap_write(st->regmap, ADXL345_REG_INT_ENABLE, 0x00);
1649 }
1650
1651 static const struct iio_buffer_setup_ops adxl345_buffer_ops = {
1652 .postenable = adxl345_buffer_postenable,
1653 .predisable = adxl345_buffer_predisable,
1654 };
1655
adxl345_fifo_push(struct iio_dev * indio_dev,int samples)1656 static int adxl345_fifo_push(struct iio_dev *indio_dev,
1657 int samples)
1658 {
1659 struct adxl345_state *st = iio_priv(indio_dev);
1660 int i, ret;
1661
1662 if (samples <= 0)
1663 return -EINVAL;
1664
1665 ret = adxl345_fifo_transfer(st, samples);
1666 if (ret)
1667 return ret;
1668
1669 for (i = 0; i < ADXL345_DIRS * samples; i += ADXL345_DIRS)
1670 iio_push_to_buffers(indio_dev, &st->fifo_buf[i]);
1671
1672 return 0;
1673 }
1674
adxl345_push_event(struct iio_dev * indio_dev,int int_stat,enum iio_modifier act_dir,enum iio_modifier tap_dir)1675 static int adxl345_push_event(struct iio_dev *indio_dev, int int_stat,
1676 enum iio_modifier act_dir,
1677 enum iio_modifier tap_dir)
1678 {
1679 s64 ts = iio_get_time_ns(indio_dev);
1680 struct adxl345_state *st = iio_priv(indio_dev);
1681 unsigned int regval;
1682 int samples;
1683 int ret = -ENOENT;
1684
1685 if (FIELD_GET(ADXL345_INT_SINGLE_TAP, int_stat)) {
1686 ret = iio_push_event(indio_dev,
1687 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, tap_dir,
1688 IIO_EV_TYPE_GESTURE,
1689 IIO_EV_DIR_SINGLETAP),
1690 ts);
1691 if (ret)
1692 return ret;
1693 }
1694
1695 if (FIELD_GET(ADXL345_INT_DOUBLE_TAP, int_stat)) {
1696 ret = iio_push_event(indio_dev,
1697 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, tap_dir,
1698 IIO_EV_TYPE_GESTURE,
1699 IIO_EV_DIR_DOUBLETAP),
1700 ts);
1701 if (ret)
1702 return ret;
1703 }
1704
1705 if (FIELD_GET(ADXL345_INT_ACTIVITY, int_stat)) {
1706 ret = regmap_read(st->regmap, ADXL345_REG_ACT_INACT_CTRL, ®val);
1707 if (ret)
1708 return ret;
1709
1710 if (FIELD_GET(ADXL345_REG_ACT_ACDC, regval)) {
1711 /* AC coupled */
1712 ret = iio_push_event(indio_dev,
1713 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, act_dir,
1714 IIO_EV_TYPE_MAG_ADAPTIVE,
1715 IIO_EV_DIR_RISING),
1716 ts);
1717
1718 } else {
1719 /* DC coupled, relying on THRESH */
1720 ret = iio_push_event(indio_dev,
1721 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, act_dir,
1722 IIO_EV_TYPE_MAG,
1723 IIO_EV_DIR_RISING),
1724 ts);
1725 }
1726 if (ret)
1727 return ret;
1728 }
1729
1730 if (FIELD_GET(ADXL345_INT_INACTIVITY, int_stat)) {
1731 ret = regmap_read(st->regmap, ADXL345_REG_ACT_INACT_CTRL, ®val);
1732 if (ret)
1733 return ret;
1734
1735 if (FIELD_GET(ADXL345_REG_INACT_ACDC, regval)) {
1736 /* AC coupled */
1737 ret = iio_push_event(indio_dev,
1738 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0,
1739 IIO_MOD_X_AND_Y_AND_Z,
1740 IIO_EV_TYPE_MAG_ADAPTIVE,
1741 IIO_EV_DIR_FALLING),
1742 ts);
1743 } else {
1744 /* DC coupled, relying on THRESH */
1745 ret = iio_push_event(indio_dev,
1746 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0,
1747 IIO_MOD_X_AND_Y_AND_Z,
1748 IIO_EV_TYPE_MAG,
1749 IIO_EV_DIR_FALLING),
1750 ts);
1751 }
1752 if (ret)
1753 return ret;
1754 }
1755
1756 if (FIELD_GET(ADXL345_INT_FREE_FALL, int_stat)) {
1757 ret = iio_push_event(indio_dev,
1758 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0,
1759 IIO_MOD_X_AND_Y_AND_Z,
1760 IIO_EV_TYPE_MAG,
1761 IIO_EV_DIR_FALLING),
1762 ts);
1763 if (ret)
1764 return ret;
1765 }
1766
1767 if (FIELD_GET(ADXL345_INT_WATERMARK, int_stat)) {
1768 samples = adxl345_get_samples(st);
1769 if (samples < 0)
1770 return -EINVAL;
1771
1772 if (adxl345_fifo_push(indio_dev, samples) < 0)
1773 return -EINVAL;
1774
1775 ret = 0;
1776 }
1777
1778 return ret;
1779 }
1780
1781 /**
1782 * adxl345_irq_handler() - Handle irqs of the ADXL345.
1783 * @irq: The irq being handled.
1784 * @p: The struct iio_device pointer for the device.
1785 *
1786 * Return: The interrupt was handled.
1787 */
adxl345_irq_handler(int irq,void * p)1788 static irqreturn_t adxl345_irq_handler(int irq, void *p)
1789 {
1790 struct iio_dev *indio_dev = p;
1791 struct adxl345_state *st = iio_priv(indio_dev);
1792 unsigned int regval;
1793 enum iio_modifier tap_dir = IIO_NO_MOD;
1794 enum iio_modifier act_dir = IIO_NO_MOD;
1795 u32 axis_ctrl;
1796 int int_stat;
1797 int ret;
1798
1799 ret = regmap_read(st->regmap, ADXL345_REG_TAP_AXIS, &axis_ctrl);
1800 if (ret)
1801 return IRQ_NONE;
1802
1803 if (FIELD_GET(ADXL345_REG_TAP_AXIS_MSK, axis_ctrl) ||
1804 FIELD_GET(ADXL345_ACT_XYZ_EN, axis_ctrl)) {
1805 ret = regmap_read(st->regmap, ADXL345_REG_ACT_TAP_STATUS, ®val);
1806 if (ret)
1807 return IRQ_NONE;
1808
1809 if (FIELD_GET(ADXL345_TAP_Z_EN, regval))
1810 tap_dir = IIO_MOD_Z;
1811 else if (FIELD_GET(ADXL345_TAP_Y_EN, regval))
1812 tap_dir = IIO_MOD_Y;
1813 else if (FIELD_GET(ADXL345_TAP_X_EN, regval))
1814 tap_dir = IIO_MOD_X;
1815
1816 if (FIELD_GET(ADXL345_ACT_Z_EN, regval))
1817 act_dir = IIO_MOD_Z;
1818 else if (FIELD_GET(ADXL345_ACT_Y_EN, regval))
1819 act_dir = IIO_MOD_Y;
1820 else if (FIELD_GET(ADXL345_ACT_X_EN, regval))
1821 act_dir = IIO_MOD_X;
1822 }
1823
1824 if (regmap_read(st->regmap, ADXL345_REG_INT_SOURCE, &int_stat))
1825 return IRQ_NONE;
1826
1827 if (adxl345_push_event(indio_dev, int_stat, act_dir, tap_dir))
1828 goto err;
1829
1830 if (FIELD_GET(ADXL345_INT_OVERRUN, int_stat))
1831 goto err;
1832
1833 return IRQ_HANDLED;
1834
1835 err:
1836 adxl345_fifo_reset(st);
1837
1838 return IRQ_HANDLED;
1839 }
1840
1841 static const struct iio_info adxl345_info = {
1842 .read_raw = adxl345_read_raw,
1843 .write_raw = adxl345_write_raw,
1844 .read_avail = adxl345_read_avail,
1845 .write_raw_get_fmt = adxl345_write_raw_get_fmt,
1846 .read_event_config = adxl345_read_event_config,
1847 .write_event_config = adxl345_write_event_config,
1848 .read_event_value = adxl345_read_event_value,
1849 .write_event_value = adxl345_write_event_value,
1850 .debugfs_reg_access = &adxl345_reg_access,
1851 .hwfifo_set_watermark = adxl345_set_watermark,
1852 };
1853
adxl345_get_int_line(struct device * dev,int * irq)1854 static int adxl345_get_int_line(struct device *dev, int *irq)
1855 {
1856 *irq = fwnode_irq_get_byname(dev_fwnode(dev), "INT1");
1857 if (*irq > 0)
1858 return ADXL345_INT1;
1859
1860 *irq = fwnode_irq_get_byname(dev_fwnode(dev), "INT2");
1861 if (*irq > 0)
1862 return ADXL345_INT2;
1863
1864 return ADXL345_INT_NONE;
1865 }
1866
1867 /**
1868 * adxl345_core_probe() - Probe and setup for the accelerometer.
1869 * @dev: Driver model representation of the device
1870 * @regmap: Regmap instance for the device
1871 * @fifo_delay_default: Using FIFO with SPI needs delay
1872 * @setup: Setup routine to be executed right before the standard device
1873 * setup
1874 *
1875 * For SPI operation greater than 1.6 MHz, it is necessary to deassert the CS
1876 * pin to ensure a total delay of 5 us; otherwise, the delay is not sufficient.
1877 * The total delay necessary for 5 MHz operation is at most 3.4 us. This is not
1878 * a concern when using I2C mode because the communication rate is low enough
1879 * to ensure a sufficient delay between FIFO reads.
1880 * Ref: "Retrieving Data from FIFO", p. 21 of 36, Data Sheet ADXL345 Rev. G
1881 *
1882 * Return: 0 on success, negative errno on error
1883 */
adxl345_core_probe(struct device * dev,struct regmap * regmap,bool fifo_delay_default,int (* setup)(struct device *,struct regmap *))1884 int adxl345_core_probe(struct device *dev, struct regmap *regmap,
1885 bool fifo_delay_default,
1886 int (*setup)(struct device*, struct regmap*))
1887 {
1888 struct adxl345_state *st;
1889 struct iio_dev *indio_dev;
1890 u32 regval;
1891 u8 intio = ADXL345_INT1;
1892 unsigned int data_format_mask = (ADXL345_DATA_FORMAT_RANGE |
1893 ADXL345_DATA_FORMAT_JUSTIFY |
1894 ADXL345_DATA_FORMAT_FULL_RES |
1895 ADXL345_DATA_FORMAT_SELF_TEST);
1896 unsigned int tap_threshold;
1897 int irq;
1898 int ret;
1899
1900 indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
1901 if (!indio_dev)
1902 return -ENOMEM;
1903
1904 st = iio_priv(indio_dev);
1905 st->regmap = regmap;
1906 st->info = device_get_match_data(dev);
1907 if (!st->info)
1908 return -ENODEV;
1909 st->fifo_delay = fifo_delay_default;
1910
1911 /* Init with reasonable values */
1912 tap_threshold = 48; /* 48 [0x30] -> ~3g */
1913 st->tap_duration_us = 16; /* 16 [0x10] -> .010 */
1914 st->tap_window_us = 64; /* 64 [0x40] -> .080 */
1915 st->tap_latent_us = 16; /* 16 [0x10] -> .020 */
1916
1917 indio_dev->name = st->info->name;
1918 indio_dev->info = &adxl345_info;
1919 indio_dev->modes = INDIO_DIRECT_MODE;
1920 indio_dev->channels = adxl345_channels;
1921 indio_dev->num_channels = ARRAY_SIZE(adxl345_channels);
1922 indio_dev->available_scan_masks = adxl345_scan_masks;
1923
1924 /*
1925 * Using I2C at 100kHz would limit the maximum ODR to 200Hz, operation
1926 * at an output rate above the recommended maximum may result in
1927 * undesired behavior.
1928 */
1929 ret = adxl345_set_odr(st, ADXL345_ODR_200HZ);
1930 if (ret)
1931 return ret;
1932
1933 ret = adxl345_set_range(st, ADXL345_16G_RANGE);
1934 if (ret)
1935 return ret;
1936
1937 /* Reset interrupts at start up */
1938 ret = regmap_write(st->regmap, ADXL345_REG_INT_ENABLE, 0x00);
1939 if (ret)
1940 return ret;
1941
1942 if (setup) {
1943 /* Perform optional initial bus specific configuration */
1944 ret = setup(dev, st->regmap);
1945 if (ret)
1946 return ret;
1947
1948 /* Enable full-resolution mode */
1949 ret = regmap_update_bits(st->regmap, ADXL345_REG_DATA_FORMAT,
1950 data_format_mask,
1951 ADXL345_DATA_FORMAT_FULL_RES);
1952 if (ret)
1953 return dev_err_probe(dev, ret,
1954 "Failed to set data range\n");
1955
1956 } else {
1957 /* Enable full-resolution mode (init all data_format bits) */
1958 ret = regmap_write(st->regmap, ADXL345_REG_DATA_FORMAT,
1959 ADXL345_DATA_FORMAT_FULL_RES);
1960 if (ret)
1961 return dev_err_probe(dev, ret,
1962 "Failed to set data range\n");
1963 }
1964
1965 ret = regmap_read(st->regmap, ADXL345_REG_DEVID, ®val);
1966 if (ret)
1967 return dev_err_probe(dev, ret, "Error reading device ID\n");
1968
1969 if (regval != ADXL345_DEVID)
1970 return dev_err_probe(dev, -ENODEV, "Invalid device ID: %x, expected %x\n",
1971 regval, ADXL345_DEVID);
1972
1973 /* Enable measurement mode */
1974 ret = adxl345_set_measure_en(st, true);
1975 if (ret)
1976 return dev_err_probe(dev, ret, "Failed to enable measurement mode\n");
1977
1978 ret = devm_add_action_or_reset(dev, adxl345_powerdown, st);
1979 if (ret)
1980 return ret;
1981
1982 intio = adxl345_get_int_line(dev, &irq);
1983 if (intio != ADXL345_INT_NONE) {
1984 /*
1985 * In the INT map register, bits set to 0 route their
1986 * corresponding interrupts to the INT1 pin, while bits set to 1
1987 * route them to the INT2 pin. The intio should handle this
1988 * mapping accordingly.
1989 */
1990 ret = regmap_assign_bits(st->regmap, ADXL345_REG_INT_MAP,
1991 U8_MAX, intio);
1992 if (ret)
1993 return ret;
1994
1995 /*
1996 * Initialized with sensible default values to streamline
1997 * sensor operation. These defaults are partly derived from
1998 * the previous input driver for the ADXL345 and partly
1999 * based on the recommendations provided in the datasheet.
2000 */
2001 ret = regmap_write(st->regmap, ADXL345_REG_ACT_INACT_CTRL, 0);
2002 if (ret)
2003 return ret;
2004
2005 ret = regmap_write(st->regmap, ADXL345_REG_THRESH_ACT, 6);
2006 if (ret)
2007 return ret;
2008
2009 ret = adxl345_set_inact_threshold(st, 4);
2010 if (ret)
2011 return ret;
2012
2013 ret = regmap_write(st->regmap, ADXL345_REG_THRESH_TAP, tap_threshold);
2014 if (ret)
2015 return ret;
2016
2017 /* FIFO_STREAM mode is going to be activated later */
2018 ret = devm_iio_kfifo_buffer_setup(dev, indio_dev, &adxl345_buffer_ops);
2019 if (ret)
2020 return ret;
2021
2022 ret = devm_request_threaded_irq(dev, irq, NULL,
2023 &adxl345_irq_handler,
2024 IRQF_SHARED | IRQF_ONESHOT,
2025 indio_dev->name, indio_dev);
2026 if (ret)
2027 return ret;
2028 } else {
2029 ret = regmap_write(st->regmap, ADXL345_REG_FIFO_CTL,
2030 FIELD_PREP(ADXL345_FIFO_CTL_MODE_MSK,
2031 ADXL345_FIFO_BYPASS));
2032 if (ret)
2033 return ret;
2034 }
2035
2036 return devm_iio_device_register(dev, indio_dev);
2037 }
2038 EXPORT_SYMBOL_NS_GPL(adxl345_core_probe, "IIO_ADXL345");
2039
2040 MODULE_AUTHOR("Eva Rachel Retuya <eraretuya@gmail.com>");
2041 MODULE_DESCRIPTION("ADXL345 3-Axis Digital Accelerometer core driver");
2042 MODULE_LICENSE("GPL v2");
2043