1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020 Intel Corporation 4 * 5 */ 6 7 #include <drm/drm_print.h> 8 9 #include "intel_alpm.h" 10 #include "intel_crtc.h" 11 #include "intel_de.h" 12 #include "intel_display_regs.h" 13 #include "intel_display_types.h" 14 #include "intel_dmc.h" 15 #include "intel_dmc_regs.h" 16 #include "intel_dp.h" 17 #include "intel_psr.h" 18 #include "intel_vrr.h" 19 #include "intel_vrr_regs.h" 20 #include "skl_prefill.h" 21 #include "skl_watermark.h" 22 23 #define FIXED_POINT_PRECISION 100 24 #define CMRR_PRECISION_TOLERANCE 10 25 26 /* 27 * Tunable parameters for DC Balance correction. 28 * These are captured based on experimentations. 29 */ 30 #define DCB_CORRECTION_SENSITIVITY 30 31 #define DCB_CORRECTION_AGGRESSIVENESS 1000 /* ms × 100; 10 ms */ 32 #define DCB_BLANK_TARGET 50 33 34 bool intel_vrr_is_capable(struct intel_connector *connector) 35 { 36 struct intel_display *display = to_intel_display(connector); 37 const struct drm_display_info *info = &connector->base.display_info; 38 struct intel_dp *intel_dp; 39 40 if (!HAS_VRR(display)) 41 return false; 42 43 /* 44 * DP Sink is capable of VRR video timings if 45 * Ignore MSA bit is set in DPCD. 46 * EDID monitor range also should be atleast 10 for reasonable 47 * Adaptive Sync or Variable Refresh Rate end user experience. 48 */ 49 switch (connector->base.connector_type) { 50 case DRM_MODE_CONNECTOR_eDP: 51 if (!connector->panel.vbt.vrr) 52 return false; 53 fallthrough; 54 case DRM_MODE_CONNECTOR_DisplayPort: 55 if (connector->mst.dp) 56 return false; 57 intel_dp = intel_attached_dp(connector); 58 /* 59 * Among non-MST DP branch devices, only an HDMI 2.1 sink connected 60 * via a PCON could support VRR. However, supporting VRR through a 61 * PCON requires non-trivial changes that are not implemented yet. 62 * Until that support exists, avoid VRR on all DP branch devices. 63 * 64 * TODO: Add support for VRR for DP->HDMI 2.1 PCON. 65 */ 66 if (drm_dp_is_branch(intel_dp->dpcd)) 67 return false; 68 69 if (!drm_dp_sink_can_do_video_without_timing_msa(intel_dp->dpcd)) 70 return false; 71 72 break; 73 default: 74 return false; 75 } 76 77 return info->monitor_range.max_vfreq - info->monitor_range.min_vfreq > 10; 78 } 79 80 bool intel_vrr_is_in_range(struct intel_connector *connector, int vrefresh) 81 { 82 const struct drm_display_info *info = &connector->base.display_info; 83 84 return intel_vrr_is_capable(connector) && 85 vrefresh >= info->monitor_range.min_vfreq && 86 vrefresh <= info->monitor_range.max_vfreq; 87 } 88 89 bool intel_vrr_possible(const struct intel_crtc_state *crtc_state) 90 { 91 return crtc_state->vrr.flipline; 92 } 93 94 void 95 intel_vrr_check_modeset(struct intel_atomic_state *state) 96 { 97 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 98 struct intel_crtc *crtc; 99 100 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state) { 101 if (new_crtc_state->uapi.vrr_enabled != 102 old_crtc_state->uapi.vrr_enabled) 103 new_crtc_state->uapi.mode_changed = true; 104 } 105 } 106 107 static int intel_vrr_extra_vblank_delay(struct intel_display *display) 108 { 109 /* 110 * On ICL/TGL VRR hardware inserts one extra scanline 111 * just after vactive, which pushes the vmin decision 112 * boundary ahead accordingly, and thus reduces the 113 * max guardband length by one scanline. 114 */ 115 return DISPLAY_VER(display) < 13 ? 1 : 0; 116 } 117 118 static int intel_vrr_vmin_flipline_offset(struct intel_display *display) 119 { 120 /* 121 * ICL/TGL hardware imposes flipline>=vmin+1 122 * 123 * We reduce the vmin value to compensate when programming the 124 * hardware. This approach allows flipline to remain set at the 125 * original value, and thus the frame will have the desired 126 * minimum vtotal. 127 */ 128 return DISPLAY_VER(display) < 13 ? 1 : 0; 129 } 130 131 static int intel_vrr_guardband_to_pipeline_full(const struct intel_crtc_state *crtc_state, 132 int guardband) 133 { 134 /* hardware imposes one extra scanline somewhere */ 135 return guardband - crtc_state->framestart_delay - 1; 136 } 137 138 static int intel_vrr_pipeline_full_to_guardband(const struct intel_crtc_state *crtc_state, 139 int pipeline_full) 140 { 141 /* hardware imposes one extra scanline somewhere */ 142 return pipeline_full + crtc_state->framestart_delay + 1; 143 } 144 145 /* 146 * Without VRR registers get latched at: 147 * vblank_start 148 * 149 * With VRR the earliest registers can get latched is: 150 * intel_vrr_vmin_vblank_start(), which if we want to maintain 151 * the correct min vtotal is >=vblank_start+1 152 * 153 * The latest point registers can get latched is the vmax decision boundary: 154 * intel_vrr_vmax_vblank_start() 155 * 156 * Between those two points the vblank exit starts (and hence registers get 157 * latched) ASAP after a push is sent. 158 * 159 * framestart_delay is programmable 1-4. 160 */ 161 162 int intel_vrr_vmin_vtotal(const struct intel_crtc_state *crtc_state) 163 { 164 /* Min vblank actually determined by flipline */ 165 return crtc_state->vrr.vmin; 166 } 167 168 int intel_vrr_vmax_vtotal(const struct intel_crtc_state *crtc_state) 169 { 170 return crtc_state->vrr.vmax; 171 } 172 173 int intel_vrr_vmin_vblank_start(const struct intel_crtc_state *crtc_state) 174 { 175 return intel_vrr_vmin_vtotal(crtc_state) - crtc_state->vrr.guardband; 176 } 177 178 int intel_vrr_vmax_vblank_start(const struct intel_crtc_state *crtc_state) 179 { 180 return intel_vrr_vmax_vtotal(crtc_state) - crtc_state->vrr.guardband; 181 } 182 183 static bool 184 is_cmrr_frac_required(struct intel_crtc_state *crtc_state) 185 { 186 struct intel_display *display = to_intel_display(crtc_state); 187 int calculated_refresh_k, actual_refresh_k, pixel_clock_per_line; 188 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 189 190 /* Avoid CMRR for now till we have VRR with fixed timings working */ 191 if (!HAS_CMRR(display) || true) 192 return false; 193 194 actual_refresh_k = 195 drm_mode_vrefresh(adjusted_mode) * FIXED_POINT_PRECISION; 196 pixel_clock_per_line = 197 adjusted_mode->crtc_clock * 1000 / adjusted_mode->crtc_htotal; 198 calculated_refresh_k = 199 pixel_clock_per_line * FIXED_POINT_PRECISION / adjusted_mode->crtc_vtotal; 200 201 if ((actual_refresh_k - calculated_refresh_k) < CMRR_PRECISION_TOLERANCE) 202 return false; 203 204 return true; 205 } 206 207 static unsigned int 208 cmrr_get_vtotal(struct intel_crtc_state *crtc_state, bool video_mode_required) 209 { 210 int multiplier_m = 1, multiplier_n = 1, vtotal, desired_refresh_rate; 211 u64 adjusted_pixel_rate; 212 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 213 214 desired_refresh_rate = drm_mode_vrefresh(adjusted_mode); 215 216 if (video_mode_required) { 217 multiplier_m = 1001; 218 multiplier_n = 1000; 219 } 220 221 crtc_state->cmrr.cmrr_n = mul_u32_u32(desired_refresh_rate * adjusted_mode->crtc_htotal, 222 multiplier_n); 223 vtotal = DIV_ROUND_UP_ULL(mul_u32_u32(adjusted_mode->crtc_clock * 1000, multiplier_n), 224 crtc_state->cmrr.cmrr_n); 225 adjusted_pixel_rate = mul_u32_u32(adjusted_mode->crtc_clock * 1000, multiplier_m); 226 crtc_state->cmrr.cmrr_m = do_div(adjusted_pixel_rate, crtc_state->cmrr.cmrr_n); 227 228 return vtotal; 229 } 230 231 static 232 void intel_vrr_compute_cmrr_timings(struct intel_crtc_state *crtc_state) 233 { 234 /* 235 * TODO: Compute precise target refresh rate to determine 236 * if video_mode_required should be true. Currently set to 237 * false due to uncertainty about the precise target 238 * refresh Rate. 239 */ 240 crtc_state->vrr.vmax = cmrr_get_vtotal(crtc_state, false); 241 crtc_state->vrr.vmin = crtc_state->vrr.vmax; 242 crtc_state->vrr.flipline = crtc_state->vrr.vmin; 243 244 crtc_state->cmrr.enable = true; 245 crtc_state->mode_flags |= I915_MODE_FLAG_VRR; 246 } 247 248 static 249 void intel_vrr_compute_vrr_timings(struct intel_crtc_state *crtc_state, 250 int vmin, int vmax) 251 { 252 crtc_state->vrr.vmax = vmax; 253 crtc_state->vrr.vmin = vmin; 254 crtc_state->vrr.flipline = crtc_state->vrr.vmin; 255 256 crtc_state->vrr.enable = true; 257 crtc_state->mode_flags |= I915_MODE_FLAG_VRR; 258 } 259 260 static 261 void intel_vrr_compute_fixed_rr_timings(struct intel_crtc_state *crtc_state) 262 { 263 /* For fixed rr, vmin = vmax = flipline */ 264 crtc_state->vrr.vmax = crtc_state->hw.adjusted_mode.crtc_vtotal; 265 crtc_state->vrr.vmin = crtc_state->vrr.vmax; 266 crtc_state->vrr.flipline = crtc_state->vrr.vmin; 267 } 268 269 static int intel_vrr_hw_value(const struct intel_crtc_state *crtc_state, 270 int value) 271 { 272 struct intel_display *display = to_intel_display(crtc_state); 273 274 /* 275 * On TGL vmin/vmax/flipline also need to be 276 * adjusted by the SCL to maintain correct vtotals. 277 */ 278 if (DISPLAY_VER(display) >= 13) 279 return value; 280 else 281 return value - crtc_state->set_context_latency; 282 } 283 284 static int intel_vrr_vblank_start(const struct intel_crtc_state *crtc_state, 285 int vmin_vmax) 286 { 287 return intel_vrr_hw_value(crtc_state, vmin_vmax) - crtc_state->vrr.guardband; 288 } 289 290 /* 291 * For fixed refresh rate mode Vmin, Vmax and Flipline all are set to 292 * Vtotal value. 293 */ 294 static 295 int intel_vrr_fixed_rr_hw_vtotal(const struct intel_crtc_state *crtc_state) 296 { 297 return intel_vrr_hw_value(crtc_state, crtc_state->hw.adjusted_mode.crtc_vtotal); 298 } 299 300 static 301 int intel_vrr_fixed_rr_hw_vmax(const struct intel_crtc_state *crtc_state) 302 { 303 return intel_vrr_fixed_rr_hw_vtotal(crtc_state); 304 } 305 306 static 307 int intel_vrr_fixed_rr_hw_vmin(const struct intel_crtc_state *crtc_state) 308 { 309 struct intel_display *display = to_intel_display(crtc_state); 310 311 return intel_vrr_fixed_rr_hw_vtotal(crtc_state) - 312 intel_vrr_vmin_flipline_offset(display); 313 } 314 315 static 316 int intel_vrr_fixed_rr_hw_flipline(const struct intel_crtc_state *crtc_state) 317 { 318 return intel_vrr_fixed_rr_hw_vtotal(crtc_state); 319 } 320 321 void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state) 322 { 323 struct intel_display *display = to_intel_display(crtc_state); 324 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 325 326 if (!intel_vrr_possible(crtc_state)) 327 return; 328 329 intel_de_write(display, TRANS_VRR_VMIN(display, cpu_transcoder), 330 intel_vrr_fixed_rr_hw_vmin(crtc_state) - 1); 331 intel_de_write(display, TRANS_VRR_VMAX(display, cpu_transcoder), 332 intel_vrr_fixed_rr_hw_vmax(crtc_state) - 1); 333 intel_de_write(display, TRANS_VRR_FLIPLINE(display, cpu_transcoder), 334 intel_vrr_fixed_rr_hw_flipline(crtc_state) - 1); 335 } 336 337 static 338 int intel_vrr_compute_vmin(struct intel_crtc_state *crtc_state) 339 { 340 /* 341 * To make fixed rr and vrr work seamless the guardband/pipeline full 342 * should be set such that it satisfies both the fixed and variable 343 * timings. 344 * For this set the vmin as crtc_vtotal. With this we never need to 345 * change anything to do with the guardband. 346 */ 347 return crtc_state->hw.adjusted_mode.crtc_vtotal; 348 } 349 350 static 351 int intel_vrr_compute_vmax(struct intel_connector *connector, 352 const struct drm_display_mode *adjusted_mode) 353 { 354 const struct drm_display_info *info = &connector->base.display_info; 355 int vmax; 356 357 vmax = adjusted_mode->crtc_clock * 1000 / 358 (adjusted_mode->crtc_htotal * info->monitor_range.min_vfreq); 359 vmax = max_t(int, vmax, adjusted_mode->crtc_vtotal); 360 361 return vmax; 362 } 363 364 static bool intel_vrr_dc_balance_possible(const struct intel_crtc_state *crtc_state) 365 { 366 struct intel_display *display = to_intel_display(crtc_state); 367 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 368 enum pipe pipe = crtc->pipe; 369 370 /* 371 * FIXME: Currently Firmware supports DC Balancing on PIPE A 372 * and PIPE B. Account those limitation while computing DC 373 * Balance parameters. 374 */ 375 return (HAS_VRR_DC_BALANCE(display) && 376 ((pipe == PIPE_A) || (pipe == PIPE_B))); 377 } 378 379 static void 380 intel_vrr_dc_balance_compute_config(struct intel_crtc_state *crtc_state) 381 { 382 int guardband_usec, adjustment_usec; 383 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 384 385 if (!intel_vrr_dc_balance_possible(crtc_state) || !crtc_state->vrr.enable) 386 return; 387 388 crtc_state->vrr.dc_balance.vmax = crtc_state->vrr.vmax; 389 crtc_state->vrr.dc_balance.vmin = crtc_state->vrr.vmin; 390 crtc_state->vrr.dc_balance.max_increase = 391 crtc_state->vrr.vmax - crtc_state->vrr.vmin; 392 crtc_state->vrr.dc_balance.max_decrease = 393 crtc_state->vrr.vmax - crtc_state->vrr.vmin; 394 crtc_state->vrr.dc_balance.guardband = 395 DIV_ROUND_UP(crtc_state->vrr.dc_balance.vmax * 396 DCB_CORRECTION_SENSITIVITY, 100); 397 guardband_usec = 398 intel_scanlines_to_usecs(adjusted_mode, 399 crtc_state->vrr.dc_balance.guardband); 400 /* 401 * The correction_aggressiveness/100 is the number of milliseconds to 402 * adjust by when the balance is at twice the guardband. 403 * guardband_slope = correction_aggressiveness / (guardband * 100) 404 */ 405 adjustment_usec = DCB_CORRECTION_AGGRESSIVENESS * 10; 406 crtc_state->vrr.dc_balance.slope = 407 DIV_ROUND_UP(adjustment_usec, guardband_usec); 408 crtc_state->vrr.dc_balance.vblank_target = 409 DIV_ROUND_UP((crtc_state->vrr.vmax - crtc_state->vrr.vmin) * 410 DCB_BLANK_TARGET, 100); 411 crtc_state->vrr.dc_balance.enable = true; 412 } 413 414 void 415 intel_vrr_compute_config(struct intel_crtc_state *crtc_state, 416 struct drm_connector_state *conn_state) 417 { 418 struct intel_display *display = to_intel_display(crtc_state); 419 struct intel_connector *connector = 420 to_intel_connector(conn_state->connector); 421 struct intel_dp *intel_dp = intel_attached_dp(connector); 422 bool is_edp = intel_dp_is_edp(intel_dp); 423 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 424 int vmin, vmax; 425 426 if (!HAS_VRR(display)) 427 return; 428 429 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) 430 return; 431 432 crtc_state->vrr.in_range = 433 intel_vrr_is_in_range(connector, drm_mode_vrefresh(adjusted_mode)); 434 435 /* 436 * Allow fixed refresh rate with VRR Timing Generator. 437 * For now set the vrr.in_range to 0, to allow fixed_rr but skip actual 438 * VRR and LRR. 439 * #TODO For actual VRR with joiner, we need to figure out how to 440 * correctly sequence transcoder level stuff vs. pipe level stuff 441 * in the commit. 442 */ 443 if (crtc_state->joiner_pipes) 444 crtc_state->vrr.in_range = false; 445 446 vmin = intel_vrr_compute_vmin(crtc_state); 447 448 if (crtc_state->vrr.in_range) { 449 if (HAS_LRR(display)) 450 crtc_state->update_lrr = true; 451 vmax = intel_vrr_compute_vmax(connector, adjusted_mode); 452 } else { 453 vmax = vmin; 454 } 455 456 if (crtc_state->uapi.vrr_enabled && vmin < vmax) 457 intel_vrr_compute_vrr_timings(crtc_state, vmin, vmax); 458 else if (is_cmrr_frac_required(crtc_state) && is_edp) 459 intel_vrr_compute_cmrr_timings(crtc_state); 460 else 461 intel_vrr_compute_fixed_rr_timings(crtc_state); 462 463 if (HAS_AS_SDP(display)) { 464 crtc_state->vrr.vsync_start = 465 (crtc_state->hw.adjusted_mode.crtc_vtotal - 466 crtc_state->hw.adjusted_mode.crtc_vsync_start); 467 crtc_state->vrr.vsync_end = 468 (crtc_state->hw.adjusted_mode.crtc_vtotal - 469 crtc_state->hw.adjusted_mode.crtc_vsync_end); 470 } 471 472 intel_vrr_dc_balance_compute_config(crtc_state); 473 } 474 475 static int 476 intel_vrr_max_hw_guardband(const struct intel_crtc_state *crtc_state) 477 { 478 struct intel_display *display = to_intel_display(crtc_state); 479 int max_pipeline_full = REG_FIELD_MAX(VRR_CTL_PIPELINE_FULL_MASK); 480 481 if (DISPLAY_VER(display) >= 13) 482 return REG_FIELD_MAX(XELPD_VRR_CTL_VRR_GUARDBAND_MASK); 483 else 484 return intel_vrr_pipeline_full_to_guardband(crtc_state, 485 max_pipeline_full); 486 } 487 488 static int 489 intel_vrr_max_vblank_guardband(const struct intel_crtc_state *crtc_state) 490 { 491 struct intel_display *display = to_intel_display(crtc_state); 492 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 493 494 return crtc_state->vrr.vmin - 495 adjusted_mode->crtc_vdisplay - 496 crtc_state->set_context_latency - 497 intel_vrr_extra_vblank_delay(display); 498 } 499 500 static int 501 intel_vrr_max_guardband(struct intel_crtc_state *crtc_state) 502 { 503 return min(intel_vrr_max_hw_guardband(crtc_state), 504 intel_vrr_max_vblank_guardband(crtc_state)); 505 } 506 507 static 508 int intel_vrr_compute_optimized_guardband(struct intel_crtc_state *crtc_state) 509 { 510 struct intel_display *display = to_intel_display(crtc_state); 511 struct skl_prefill_ctx prefill_ctx; 512 int prefill_latency_us; 513 int guardband = 0; 514 515 skl_prefill_init_worst(&prefill_ctx, crtc_state); 516 517 /* 518 * The SoC power controller runs SAGV mutually exclusive with package C states, 519 * so the max of package C and SAGV latencies is used to compute the min prefill guardband. 520 * PM delay = max(sagv_latency, pkgc_max_latency (highest enabled wm level 1 and up)) 521 */ 522 prefill_latency_us = max(display->sagv.block_time_us, 523 skl_watermark_max_latency(display, 1)); 524 525 guardband = skl_prefill_min_guardband(&prefill_ctx, 526 crtc_state, 527 prefill_latency_us); 528 529 if (intel_crtc_has_dp_encoder(crtc_state)) { 530 guardband = max(guardband, intel_psr_min_guardband(crtc_state)); 531 guardband = max(guardband, intel_dp_sdp_min_guardband(crtc_state, true)); 532 guardband = max(guardband, intel_alpm_lobf_min_guardband(crtc_state)); 533 } 534 535 return guardband; 536 } 537 538 static bool intel_vrr_use_optimized_guardband(const struct intel_crtc_state *crtc_state) 539 { 540 /* 541 * #TODO: Enable optimized guardband for HDMI 542 * For HDMI lot of infoframes are transmitted a line or two after vsync. 543 * Since with optimized guardband the double bufferring point is at delayed vblank, 544 * we need to ensure that vsync happens after delayed vblank for the HDMI case. 545 */ 546 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 547 return false; 548 549 return true; 550 } 551 552 void intel_vrr_compute_guardband(struct intel_crtc_state *crtc_state) 553 { 554 struct intel_display *display = to_intel_display(crtc_state); 555 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 556 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; 557 int guardband; 558 559 if (!intel_vrr_possible(crtc_state)) 560 return; 561 562 if (intel_vrr_use_optimized_guardband(crtc_state)) 563 guardband = intel_vrr_compute_optimized_guardband(crtc_state); 564 else 565 guardband = crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay; 566 567 crtc_state->vrr.guardband = min(guardband, intel_vrr_max_guardband(crtc_state)); 568 569 if (intel_vrr_always_use_vrr_tg(display)) { 570 adjusted_mode->crtc_vblank_start = 571 adjusted_mode->crtc_vtotal - crtc_state->vrr.guardband; 572 /* 573 * pipe_mode has already been derived from the 574 * original adjusted_mode, keep the two in sync. 575 */ 576 pipe_mode->crtc_vblank_start = 577 adjusted_mode->crtc_vblank_start; 578 } 579 580 if (DISPLAY_VER(display) < 13) 581 crtc_state->vrr.pipeline_full = 582 intel_vrr_guardband_to_pipeline_full(crtc_state, 583 crtc_state->vrr.guardband); 584 } 585 586 static u32 trans_vrr_ctl(const struct intel_crtc_state *crtc_state) 587 { 588 struct intel_display *display = to_intel_display(crtc_state); 589 590 if (DISPLAY_VER(display) >= 14) 591 return VRR_CTL_FLIP_LINE_EN | 592 XELPD_VRR_CTL_VRR_GUARDBAND(crtc_state->vrr.guardband); 593 else if (DISPLAY_VER(display) >= 13) 594 return VRR_CTL_IGN_MAX_SHIFT | VRR_CTL_FLIP_LINE_EN | 595 XELPD_VRR_CTL_VRR_GUARDBAND(crtc_state->vrr.guardband); 596 else 597 return VRR_CTL_IGN_MAX_SHIFT | VRR_CTL_FLIP_LINE_EN | 598 VRR_CTL_PIPELINE_FULL(crtc_state->vrr.pipeline_full) | 599 VRR_CTL_PIPELINE_FULL_OVERRIDE; 600 } 601 602 void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state) 603 { 604 struct intel_display *display = to_intel_display(crtc_state); 605 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 606 607 if (!HAS_VRR(display)) 608 return; 609 610 /* 611 * Bspec says: 612 * "(note: VRR needs to be programmed after 613 * TRANS_DDI_FUNC_CTL and before TRANS_CONF)." 614 * 615 * In practice it turns out that ICL can hang if 616 * TRANS_VRR_VMAX/FLIPLINE are written before 617 * enabling TRANS_DDI_FUNC_CTL. 618 */ 619 drm_WARN_ON(display->drm, 620 !(intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)) & TRANS_DDI_FUNC_ENABLE)); 621 622 /* 623 * This bit seems to have two meanings depending on the platform: 624 * TGL: generate VRR "safe window" for DSB vblank waits 625 * ADL/DG2: make TRANS_SET_CONTEXT_LATENCY effective with VRR 626 */ 627 if (IS_DISPLAY_VER(display, 12, 13)) 628 intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder), 629 0, PIPE_VBLANK_WITH_DELAY); 630 631 if (!intel_vrr_possible(crtc_state)) { 632 intel_de_write(display, 633 TRANS_VRR_CTL(display, cpu_transcoder), 0); 634 return; 635 } 636 637 if (crtc_state->cmrr.enable) { 638 intel_de_write(display, TRANS_CMRR_M_HI(display, cpu_transcoder), 639 upper_32_bits(crtc_state->cmrr.cmrr_m)); 640 intel_de_write(display, TRANS_CMRR_M_LO(display, cpu_transcoder), 641 lower_32_bits(crtc_state->cmrr.cmrr_m)); 642 intel_de_write(display, TRANS_CMRR_N_HI(display, cpu_transcoder), 643 upper_32_bits(crtc_state->cmrr.cmrr_n)); 644 intel_de_write(display, TRANS_CMRR_N_LO(display, cpu_transcoder), 645 lower_32_bits(crtc_state->cmrr.cmrr_n)); 646 } 647 648 intel_vrr_set_fixed_rr_timings(crtc_state); 649 650 if (!intel_vrr_always_use_vrr_tg(display)) 651 intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), 652 trans_vrr_ctl(crtc_state)); 653 654 if (HAS_AS_SDP(display)) 655 intel_de_write(display, 656 TRANS_VRR_VSYNC(display, cpu_transcoder), 657 VRR_VSYNC_END(crtc_state->vrr.vsync_end) | 658 VRR_VSYNC_START(crtc_state->vrr.vsync_start)); 659 660 /* 661 * For BMG and LNL+ onwards the EMP_AS_SDP_TL is used for programming 662 * double buffering point and transmission line for VRR packets for 663 * HDMI2.1/DP/eDP/DP->HDMI2.1 PCON. 664 * Since currently we support VRR only for DP/eDP, so this is programmed 665 * to for Adaptive Sync SDP to Vsync start. 666 */ 667 if (DISPLAY_VERx100(display) == 1401 || DISPLAY_VER(display) >= 20) 668 intel_de_write(display, 669 EMP_AS_SDP_TL(display, cpu_transcoder), 670 EMP_AS_SDP_DB_TL(crtc_state->vrr.vsync_start)); 671 } 672 673 void 674 intel_vrr_dcb_increment_flip_count(struct intel_crtc_state *crtc_state, 675 struct intel_crtc *crtc) 676 { 677 struct intel_display *display = to_intel_display(crtc_state); 678 enum pipe pipe = crtc->pipe; 679 680 if (!crtc_state->vrr.dc_balance.enable) 681 return; 682 683 intel_de_write(display, PIPEDMC_DCB_FLIP_COUNT(pipe), 684 ++crtc->dc_balance.flip_count); 685 } 686 687 void 688 intel_vrr_dcb_reset(const struct intel_crtc_state *old_crtc_state, 689 struct intel_crtc *crtc) 690 { 691 struct intel_display *display = to_intel_display(old_crtc_state); 692 enum pipe pipe = crtc->pipe; 693 694 if (!old_crtc_state->vrr.dc_balance.enable) 695 return; 696 697 intel_de_write(display, PIPEDMC_DCB_FLIP_COUNT(pipe), 0); 698 intel_de_write(display, PIPEDMC_DCB_BALANCE_RESET(pipe), 0); 699 } 700 701 static u32 trans_vrr_push(const struct intel_crtc_state *crtc_state, 702 bool send_push) 703 { 704 struct intel_display *display = to_intel_display(crtc_state); 705 u32 trans_vrr_push = 0; 706 707 if (intel_vrr_always_use_vrr_tg(display) || 708 crtc_state->vrr.enable) 709 trans_vrr_push |= TRANS_PUSH_EN; 710 711 if (send_push) 712 trans_vrr_push |= TRANS_PUSH_SEND; 713 714 if (HAS_PSR_TRANS_PUSH_FRAME_CHANGE(display)) 715 trans_vrr_push |= LNL_TRANS_PUSH_PSR_PR_EN; 716 717 return trans_vrr_push; 718 } 719 720 void intel_vrr_send_push(struct intel_dsb *dsb, 721 const struct intel_crtc_state *crtc_state) 722 { 723 struct intel_display *display = to_intel_display(crtc_state); 724 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 725 726 if (!crtc_state->vrr.enable && !intel_psr_use_trans_push(crtc_state)) 727 return; 728 729 if (dsb) 730 intel_dsb_nonpost_start(dsb); 731 732 intel_de_write_dsb(display, dsb, 733 TRANS_PUSH(display, cpu_transcoder), 734 trans_vrr_push(crtc_state, true)); 735 if (dsb) 736 intel_dsb_nonpost_end(dsb); 737 } 738 739 void intel_vrr_check_push_sent(struct intel_dsb *dsb, 740 const struct intel_crtc_state *crtc_state) 741 { 742 struct intel_display *display = to_intel_display(crtc_state); 743 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 744 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 745 746 if (!crtc_state->vrr.enable) 747 return; 748 749 /* 750 * Make sure the push send bit has cleared. This should 751 * already be the case as long as the caller makes sure 752 * this is called after the delayed vblank has occurred. 753 */ 754 if (dsb) { 755 int wait_us, count; 756 757 wait_us = 2; 758 count = 1; 759 760 /* 761 * If the bit hasn't cleared the DSB will 762 * raise the poll error interrupt. 763 */ 764 intel_dsb_poll(dsb, TRANS_PUSH(display, cpu_transcoder), 765 TRANS_PUSH_SEND, 0, wait_us, count); 766 } else { 767 if (intel_vrr_is_push_sent(crtc_state)) 768 drm_err(display->drm, "[CRTC:%d:%s] VRR push send still pending\n", 769 crtc->base.base.id, crtc->base.name); 770 } 771 } 772 773 bool intel_vrr_is_push_sent(const struct intel_crtc_state *crtc_state) 774 { 775 struct intel_display *display = to_intel_display(crtc_state); 776 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 777 778 if (!crtc_state->vrr.enable) 779 return false; 780 781 return intel_de_read(display, TRANS_PUSH(display, cpu_transcoder)) & TRANS_PUSH_SEND; 782 } 783 784 bool intel_vrr_always_use_vrr_tg(struct intel_display *display) 785 { 786 if (!HAS_VRR(display)) 787 return false; 788 789 if (DISPLAY_VER(display) >= 30) 790 return true; 791 792 return false; 793 } 794 795 static int intel_vrr_hw_vmin(const struct intel_crtc_state *crtc_state) 796 { 797 struct intel_display *display = to_intel_display(crtc_state); 798 799 return intel_vrr_hw_value(crtc_state, crtc_state->vrr.vmin) - 800 intel_vrr_vmin_flipline_offset(display); 801 } 802 803 static int intel_vrr_hw_vmax(const struct intel_crtc_state *crtc_state) 804 { 805 return intel_vrr_hw_value(crtc_state, crtc_state->vrr.vmax); 806 } 807 808 static int intel_vrr_hw_flipline(const struct intel_crtc_state *crtc_state) 809 { 810 return intel_vrr_hw_value(crtc_state, crtc_state->vrr.flipline); 811 } 812 813 static void intel_vrr_set_vrr_timings(const struct intel_crtc_state *crtc_state) 814 { 815 struct intel_display *display = to_intel_display(crtc_state); 816 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 817 818 intel_de_write(display, TRANS_VRR_VMIN(display, cpu_transcoder), 819 intel_vrr_hw_vmin(crtc_state) - 1); 820 intel_de_write(display, TRANS_VRR_VMAX(display, cpu_transcoder), 821 intel_vrr_hw_vmax(crtc_state) - 1); 822 intel_de_write(display, TRANS_VRR_FLIPLINE(display, cpu_transcoder), 823 intel_vrr_hw_flipline(crtc_state) - 1); 824 } 825 826 static void 827 intel_vrr_enable_dc_balancing(const struct intel_crtc_state *crtc_state) 828 { 829 struct intel_display *display = to_intel_display(crtc_state); 830 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 831 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 832 enum pipe pipe = crtc->pipe; 833 u32 vrr_ctl = intel_de_read(display, TRANS_VRR_CTL(display, cpu_transcoder)); 834 835 if (!crtc_state->vrr.dc_balance.enable) 836 return; 837 838 intel_de_write(display, TRANS_VRR_DCB_ADJ_VMAX_CFG(cpu_transcoder), 839 VRR_DCB_ADJ_VMAX(crtc_state->vrr.vmax - 1)); 840 intel_de_write(display, TRANS_VRR_DCB_ADJ_VMAX_CFG_LIVE(cpu_transcoder), 841 VRR_DCB_ADJ_VMAX(crtc_state->vrr.vmax - 1)); 842 intel_de_write(display, TRANS_VRR_DCB_VMAX(cpu_transcoder), 843 VRR_DCB_VMAX(crtc_state->vrr.vmax - 1)); 844 intel_de_write(display, TRANS_VRR_DCB_VMAX_LIVE(cpu_transcoder), 845 VRR_DCB_VMAX(crtc_state->vrr.vmax - 1)); 846 intel_de_write(display, TRANS_VRR_DCB_FLIPLINE(cpu_transcoder), 847 VRR_DCB_FLIPLINE(crtc_state->vrr.flipline - 1)); 848 intel_de_write(display, TRANS_VRR_DCB_FLIPLINE_LIVE(cpu_transcoder), 849 VRR_DCB_FLIPLINE(crtc_state->vrr.flipline - 1)); 850 intel_de_write(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE(cpu_transcoder), 851 VRR_DCB_ADJ_FLIPLINE(crtc_state->vrr.flipline - 1)); 852 intel_de_write(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(cpu_transcoder), 853 VRR_DCB_ADJ_FLIPLINE(crtc_state->vrr.flipline - 1)); 854 intel_de_write(display, PIPEDMC_DCB_VMIN(pipe), 855 crtc_state->vrr.dc_balance.vmin - 1); 856 intel_de_write(display, PIPEDMC_DCB_VMAX(pipe), 857 crtc_state->vrr.dc_balance.vmax - 1); 858 intel_de_write(display, PIPEDMC_DCB_MAX_INCREASE(pipe), 859 crtc_state->vrr.dc_balance.max_increase); 860 intel_de_write(display, PIPEDMC_DCB_MAX_DECREASE(pipe), 861 crtc_state->vrr.dc_balance.max_decrease); 862 intel_de_write(display, PIPEDMC_DCB_GUARDBAND(pipe), 863 crtc_state->vrr.dc_balance.guardband); 864 intel_de_write(display, PIPEDMC_DCB_SLOPE(pipe), 865 crtc_state->vrr.dc_balance.slope); 866 intel_de_write(display, PIPEDMC_DCB_VBLANK(pipe), 867 crtc_state->vrr.dc_balance.vblank_target); 868 intel_dmc_configure_dc_balance_event(display, pipe, true); 869 intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder), 870 ADAPTIVE_SYNC_COUNTER_EN); 871 intel_pipedmc_dcb_enable(NULL, crtc); 872 873 vrr_ctl |= VRR_CTL_DCB_ADJ_ENABLE; 874 intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), vrr_ctl); 875 } 876 877 static void 878 intel_vrr_disable_dc_balancing(const struct intel_crtc_state *old_crtc_state) 879 { 880 struct intel_display *display = to_intel_display(old_crtc_state); 881 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 882 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 883 enum pipe pipe = crtc->pipe; 884 u32 vrr_ctl = intel_de_read(display, TRANS_VRR_CTL(display, cpu_transcoder)); 885 886 if (!old_crtc_state->vrr.dc_balance.enable) 887 return; 888 889 intel_pipedmc_dcb_disable(NULL, crtc); 890 intel_dmc_configure_dc_balance_event(display, pipe, false); 891 intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder), 0); 892 intel_de_write(display, PIPEDMC_DCB_VMIN(pipe), 0); 893 intel_de_write(display, PIPEDMC_DCB_VMAX(pipe), 0); 894 intel_de_write(display, PIPEDMC_DCB_MAX_INCREASE(pipe), 0); 895 intel_de_write(display, PIPEDMC_DCB_MAX_DECREASE(pipe), 0); 896 intel_de_write(display, PIPEDMC_DCB_GUARDBAND(pipe), 0); 897 intel_de_write(display, PIPEDMC_DCB_SLOPE(pipe), 0); 898 intel_de_write(display, PIPEDMC_DCB_VBLANK(pipe), 0); 899 intel_de_write(display, TRANS_VRR_DCB_ADJ_VMAX_CFG_LIVE(cpu_transcoder), 0); 900 intel_de_write(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE(cpu_transcoder), 0); 901 intel_de_write(display, TRANS_VRR_DCB_VMAX_LIVE(cpu_transcoder), 0); 902 intel_de_write(display, TRANS_VRR_DCB_FLIPLINE_LIVE(cpu_transcoder), 0); 903 intel_de_write(display, TRANS_VRR_DCB_ADJ_VMAX_CFG(cpu_transcoder), 0); 904 intel_de_write(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(cpu_transcoder), 0); 905 intel_de_write(display, TRANS_VRR_DCB_VMAX(cpu_transcoder), 0); 906 intel_de_write(display, TRANS_VRR_DCB_FLIPLINE(cpu_transcoder), 0); 907 908 vrr_ctl &= ~VRR_CTL_DCB_ADJ_ENABLE; 909 intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), vrr_ctl); 910 } 911 912 static void intel_vrr_tg_enable(const struct intel_crtc_state *crtc_state, 913 bool cmrr_enable) 914 { 915 struct intel_display *display = to_intel_display(crtc_state); 916 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 917 u32 vrr_ctl; 918 919 intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), 920 trans_vrr_push(crtc_state, false)); 921 922 vrr_ctl = VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state); 923 924 /* 925 * FIXME this might be broken as bspec seems to imply that 926 * even VRR_CTL_CMRR_ENABLE is armed by TRANS_CMRR_N_HI 927 * when enabling CMRR (but not when disabling CMRR?). 928 */ 929 if (cmrr_enable) 930 vrr_ctl |= VRR_CTL_CMRR_ENABLE; 931 932 intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), vrr_ctl); 933 } 934 935 static void intel_vrr_tg_disable(const struct intel_crtc_state *old_crtc_state) 936 { 937 struct intel_display *display = to_intel_display(old_crtc_state); 938 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 939 940 intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), 941 trans_vrr_ctl(old_crtc_state)); 942 943 if (intel_de_wait_for_clear_ms(display, 944 TRANS_VRR_STATUS(display, cpu_transcoder), 945 VRR_STATUS_VRR_EN_LIVE, 1000)) 946 drm_err(display->drm, "Timed out waiting for VRR live status to clear\n"); 947 948 intel_de_rmw(display, TRANS_PUSH(display, cpu_transcoder), 949 TRANS_PUSH_EN, 0); 950 } 951 952 void intel_vrr_enable(const struct intel_crtc_state *crtc_state) 953 { 954 struct intel_display *display = to_intel_display(crtc_state); 955 956 if (!crtc_state->vrr.enable) 957 return; 958 959 intel_vrr_set_vrr_timings(crtc_state); 960 intel_vrr_enable_dc_balancing(crtc_state); 961 962 if (!intel_vrr_always_use_vrr_tg(display)) 963 intel_vrr_tg_enable(crtc_state, crtc_state->cmrr.enable); 964 } 965 966 void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state) 967 { 968 struct intel_display *display = to_intel_display(old_crtc_state); 969 970 if (!old_crtc_state->vrr.enable) 971 return; 972 973 if (!intel_vrr_always_use_vrr_tg(display)) 974 intel_vrr_tg_disable(old_crtc_state); 975 976 intel_vrr_disable_dc_balancing(old_crtc_state); 977 intel_vrr_set_fixed_rr_timings(old_crtc_state); 978 } 979 980 void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state) 981 { 982 struct intel_display *display = to_intel_display(crtc_state); 983 984 intel_vrr_set_transcoder_timings(crtc_state); 985 986 if (!intel_vrr_possible(crtc_state)) 987 return; 988 989 if (intel_vrr_always_use_vrr_tg(display)) 990 intel_vrr_tg_enable(crtc_state, false); 991 } 992 993 void intel_vrr_transcoder_disable(const struct intel_crtc_state *old_crtc_state) 994 { 995 struct intel_display *display = to_intel_display(old_crtc_state); 996 997 if (!intel_vrr_possible(old_crtc_state)) 998 return; 999 1000 if (intel_vrr_always_use_vrr_tg(display)) 1001 intel_vrr_tg_disable(old_crtc_state); 1002 } 1003 1004 void intel_vrr_psr_frame_change_enable(const struct intel_crtc_state *crtc_state) 1005 { 1006 struct intel_display *display = to_intel_display(crtc_state); 1007 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1008 1009 intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), 1010 trans_vrr_push(crtc_state, false)); 1011 } 1012 1013 bool intel_vrr_is_fixed_rr(const struct intel_crtc_state *crtc_state) 1014 { 1015 return crtc_state->vrr.flipline && 1016 crtc_state->vrr.flipline == crtc_state->vrr.vmax && 1017 crtc_state->vrr.flipline == crtc_state->vrr.vmin; 1018 } 1019 1020 static 1021 void intel_vrr_get_dc_balance_config(struct intel_crtc_state *crtc_state) 1022 { 1023 u32 reg_val; 1024 struct intel_display *display = to_intel_display(crtc_state); 1025 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1026 enum pipe pipe = crtc->pipe; 1027 1028 if (!intel_vrr_dc_balance_possible(crtc_state)) 1029 return; 1030 1031 reg_val = intel_de_read(display, PIPEDMC_DCB_VMIN(pipe)); 1032 crtc_state->vrr.dc_balance.vmin = reg_val ? reg_val + 1 : 0; 1033 1034 reg_val = intel_de_read(display, PIPEDMC_DCB_VMAX(pipe)); 1035 crtc_state->vrr.dc_balance.vmax = reg_val ? reg_val + 1 : 0; 1036 1037 crtc_state->vrr.dc_balance.guardband = 1038 intel_de_read(display, PIPEDMC_DCB_GUARDBAND(pipe)); 1039 crtc_state->vrr.dc_balance.max_increase = 1040 intel_de_read(display, PIPEDMC_DCB_MAX_INCREASE(pipe)); 1041 crtc_state->vrr.dc_balance.max_decrease = 1042 intel_de_read(display, PIPEDMC_DCB_MAX_DECREASE(pipe)); 1043 crtc_state->vrr.dc_balance.slope = 1044 intel_de_read(display, PIPEDMC_DCB_SLOPE(pipe)); 1045 crtc_state->vrr.dc_balance.vblank_target = 1046 intel_de_read(display, PIPEDMC_DCB_VBLANK(pipe)); 1047 } 1048 1049 void intel_vrr_get_config(struct intel_crtc_state *crtc_state) 1050 { 1051 struct intel_display *display = to_intel_display(crtc_state); 1052 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1053 u32 trans_vrr_ctl, trans_vrr_vsync; 1054 bool vrr_enable; 1055 1056 trans_vrr_ctl = intel_de_read(display, 1057 TRANS_VRR_CTL(display, cpu_transcoder)); 1058 1059 if (HAS_CMRR(display)) 1060 crtc_state->cmrr.enable = (trans_vrr_ctl & VRR_CTL_CMRR_ENABLE); 1061 1062 if (crtc_state->cmrr.enable) { 1063 crtc_state->cmrr.cmrr_n = 1064 intel_de_read64_2x32(display, TRANS_CMRR_N_LO(display, cpu_transcoder)); 1065 crtc_state->cmrr.cmrr_m = 1066 intel_de_read64_2x32(display, TRANS_CMRR_M_LO(display, cpu_transcoder)); 1067 } 1068 1069 if (DISPLAY_VER(display) >= 13) { 1070 crtc_state->vrr.guardband = 1071 REG_FIELD_GET(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, trans_vrr_ctl); 1072 } else { 1073 if (trans_vrr_ctl & VRR_CTL_PIPELINE_FULL_OVERRIDE) { 1074 crtc_state->vrr.pipeline_full = 1075 REG_FIELD_GET(VRR_CTL_PIPELINE_FULL_MASK, trans_vrr_ctl); 1076 1077 crtc_state->vrr.guardband = 1078 intel_vrr_pipeline_full_to_guardband(crtc_state, 1079 crtc_state->vrr.pipeline_full); 1080 } 1081 } 1082 1083 if (trans_vrr_ctl & VRR_CTL_FLIP_LINE_EN) { 1084 crtc_state->vrr.flipline = intel_de_read(display, 1085 TRANS_VRR_FLIPLINE(display, cpu_transcoder)) + 1; 1086 crtc_state->vrr.vmax = intel_de_read(display, 1087 TRANS_VRR_VMAX(display, cpu_transcoder)) + 1; 1088 crtc_state->vrr.vmin = intel_de_read(display, 1089 TRANS_VRR_VMIN(display, cpu_transcoder)) + 1; 1090 1091 if (DISPLAY_VER(display) < 13) { 1092 /* undo what intel_vrr_hw_value() does when writing the values */ 1093 crtc_state->vrr.flipline += crtc_state->set_context_latency; 1094 crtc_state->vrr.vmax += crtc_state->set_context_latency; 1095 crtc_state->vrr.vmin += crtc_state->set_context_latency; 1096 1097 crtc_state->vrr.vmin += intel_vrr_vmin_flipline_offset(display); 1098 } 1099 1100 /* 1101 * For platforms that always use VRR Timing Generator, the VTOTAL.Vtotal 1102 * bits are not filled. Since for these platforms TRAN_VMIN is always 1103 * filled with crtc_vtotal, use TRAN_VRR_VMIN to get the vtotal for 1104 * adjusted_mode. 1105 */ 1106 if (intel_vrr_always_use_vrr_tg(display)) 1107 crtc_state->hw.adjusted_mode.crtc_vtotal = 1108 intel_vrr_vmin_vtotal(crtc_state); 1109 1110 if (HAS_AS_SDP(display)) { 1111 trans_vrr_vsync = 1112 intel_de_read(display, 1113 TRANS_VRR_VSYNC(display, cpu_transcoder)); 1114 crtc_state->vrr.vsync_start = 1115 REG_FIELD_GET(VRR_VSYNC_START_MASK, trans_vrr_vsync); 1116 crtc_state->vrr.vsync_end = 1117 REG_FIELD_GET(VRR_VSYNC_END_MASK, trans_vrr_vsync); 1118 } 1119 } 1120 1121 vrr_enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE; 1122 1123 if (intel_vrr_always_use_vrr_tg(display)) 1124 crtc_state->vrr.enable = vrr_enable && !intel_vrr_is_fixed_rr(crtc_state); 1125 else 1126 crtc_state->vrr.enable = vrr_enable; 1127 1128 intel_vrr_get_dc_balance_config(crtc_state); 1129 1130 /* 1131 * #TODO: For Both VRR and CMRR the flag I915_MODE_FLAG_VRR is set for mode_flags. 1132 * Since CMRR is currently disabled, set this flag for VRR for now. 1133 * Need to keep this in mind while re-enabling CMRR. 1134 */ 1135 if (crtc_state->vrr.enable) 1136 crtc_state->mode_flags |= I915_MODE_FLAG_VRR; 1137 1138 /* 1139 * For platforms that always use the VRR timing generator, we overwrite 1140 * crtc_vblank_start with vtotal - guardband to reflect the delayed 1141 * vblank start. This works for both default and optimized guardband values. 1142 * On other platforms, we keep the original value from 1143 * intel_get_transcoder_timings() and apply adjustments only in VRR-specific 1144 * paths as needed. 1145 */ 1146 if (intel_vrr_always_use_vrr_tg(display)) 1147 crtc_state->hw.adjusted_mode.crtc_vblank_start = 1148 crtc_state->hw.adjusted_mode.crtc_vtotal - 1149 crtc_state->vrr.guardband; 1150 } 1151 1152 int intel_vrr_safe_window_start(const struct intel_crtc_state *crtc_state) 1153 { 1154 struct intel_display *display = to_intel_display(crtc_state); 1155 1156 if (DISPLAY_VER(display) >= 30) 1157 return crtc_state->hw.adjusted_mode.crtc_vdisplay - 1158 crtc_state->set_context_latency; 1159 else 1160 return crtc_state->hw.adjusted_mode.crtc_vdisplay; 1161 } 1162 1163 static int 1164 intel_vrr_dcb_vmin_vblank_start(const struct intel_crtc_state *crtc_state) 1165 { 1166 return (intel_vrr_dcb_vmin_vblank_start_next(crtc_state) < 0) ? 1167 intel_vrr_dcb_vmin_vblank_start_final(crtc_state) : 1168 intel_vrr_dcb_vmin_vblank_start_next(crtc_state); 1169 } 1170 1171 int intel_vrr_vmin_safe_window_end(const struct intel_crtc_state *crtc_state) 1172 { 1173 int vmin_vblank_start = crtc_state->vrr.dc_balance.enable ? 1174 intel_vrr_dcb_vmin_vblank_start(crtc_state) : 1175 intel_vrr_vmin_vblank_start(crtc_state); 1176 1177 return vmin_vblank_start - crtc_state->set_context_latency; 1178 } 1179 1180 int intel_vrr_dcb_vmin_vblank_start_next(const struct intel_crtc_state *crtc_state) 1181 { 1182 struct intel_display *display = to_intel_display(crtc_state); 1183 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1184 u32 tmp = 0; 1185 1186 tmp = intel_de_read(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE(cpu_transcoder)); 1187 1188 if (REG_FIELD_GET(VRR_DCB_ADJ_FLIPLINE_CNT_MASK, tmp) == 0) 1189 return -EINVAL; 1190 1191 return intel_vrr_vblank_start(crtc_state, VRR_DCB_ADJ_FLIPLINE(tmp) + 1); 1192 } 1193 1194 int intel_vrr_dcb_vmax_vblank_start_next(const struct intel_crtc_state *crtc_state) 1195 { 1196 struct intel_display *display = to_intel_display(crtc_state); 1197 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1198 u32 tmp = 0; 1199 1200 tmp = intel_de_read(display, TRANS_VRR_DCB_ADJ_VMAX_CFG_LIVE(cpu_transcoder)); 1201 1202 if (REG_FIELD_GET(VRR_DCB_ADJ_VMAX_CNT_MASK, tmp) == 0) 1203 return -EINVAL; 1204 1205 return intel_vrr_vblank_start(crtc_state, VRR_DCB_ADJ_VMAX(tmp) + 1); 1206 } 1207 1208 int intel_vrr_dcb_vmin_vblank_start_final(const struct intel_crtc_state *crtc_state) 1209 { 1210 struct intel_display *display = to_intel_display(crtc_state); 1211 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1212 u32 tmp = 0; 1213 1214 tmp = intel_de_read(display, TRANS_VRR_DCB_FLIPLINE_LIVE(cpu_transcoder)); 1215 1216 return intel_vrr_vblank_start(crtc_state, VRR_DCB_FLIPLINE(tmp) + 1); 1217 } 1218 1219 int intel_vrr_dcb_vmax_vblank_start_final(const struct intel_crtc_state *crtc_state) 1220 { 1221 struct intel_display *display = to_intel_display(crtc_state); 1222 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1223 u32 tmp = 0; 1224 1225 tmp = intel_de_read(display, TRANS_VRR_DCB_VMAX_LIVE(cpu_transcoder)); 1226 1227 return intel_vrr_vblank_start(crtc_state, VRR_DCB_VMAX(tmp) + 1); 1228 } 1229