1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * linux/arch/arm/mm/fault-armv.c
4 *
5 * Copyright (C) 1995 Linus Torvalds
6 * Modifications for ARM processor (c) 1995-2002 Russell King
7 */
8 #include <linux/sched.h>
9 #include <linux/kernel.h>
10 #include <linux/mm.h>
11 #include <linux/bitops.h>
12 #include <linux/vmalloc.h>
13 #include <linux/init.h>
14 #include <linux/pagemap.h>
15 #include <linux/gfp.h>
16
17 #include <asm/bugs.h>
18 #include <asm/cacheflush.h>
19 #include <asm/cachetype.h>
20 #include <asm/tlbflush.h>
21
22 #include "mm.h"
23
24 static pteval_t shared_pte_mask = L_PTE_MT_BUFFERABLE;
25
26 #if __LINUX_ARM_ARCH__ < 6
27 /*
28 * We take the easy way out of this problem - we make the
29 * PTE uncacheable. However, we leave the write buffer on.
30 *
31 * Note that the pte lock held when calling update_mmu_cache must also
32 * guard the pte (somewhere else in the same mm) that we modify here.
33 * Therefore those configurations which might call adjust_pte (those
34 * without CONFIG_CPU_CACHE_VIPT) cannot support split page_table_lock.
35 */
do_adjust_pte(struct vm_area_struct * vma,unsigned long address,unsigned long pfn,pte_t * ptep)36 static int do_adjust_pte(struct vm_area_struct *vma, unsigned long address,
37 unsigned long pfn, pte_t *ptep)
38 {
39 pte_t entry = *ptep;
40 int ret;
41
42 /*
43 * If this page is present, it's actually being shared.
44 */
45 ret = pte_present(entry);
46
47 /*
48 * If this page isn't present, or is already setup to
49 * fault (ie, is old), we can safely ignore any issues.
50 */
51 if (ret && (pte_val(entry) & L_PTE_MT_MASK) != shared_pte_mask) {
52 flush_cache_page(vma, address, pfn);
53 outer_flush_range((pfn << PAGE_SHIFT),
54 (pfn << PAGE_SHIFT) + PAGE_SIZE);
55 pte_val(entry) &= ~L_PTE_MT_MASK;
56 pte_val(entry) |= shared_pte_mask;
57 set_pte_at(vma->vm_mm, address, ptep, entry);
58 flush_tlb_page(vma, address);
59 }
60
61 return ret;
62 }
63
adjust_pte(struct vm_area_struct * vma,unsigned long address,unsigned long pfn,bool need_lock)64 static int adjust_pte(struct vm_area_struct *vma, unsigned long address,
65 unsigned long pfn, bool need_lock)
66 {
67 spinlock_t *ptl;
68 pgd_t *pgd;
69 p4d_t *p4d;
70 pud_t *pud;
71 pmd_t *pmd;
72 pte_t *pte;
73 pmd_t pmdval;
74 int ret;
75
76 pgd = pgd_offset(vma->vm_mm, address);
77 if (pgd_none_or_clear_bad(pgd))
78 return 0;
79
80 p4d = p4d_offset(pgd, address);
81 if (p4d_none_or_clear_bad(p4d))
82 return 0;
83
84 pud = pud_offset(p4d, address);
85 if (pud_none_or_clear_bad(pud))
86 return 0;
87
88 pmd = pmd_offset(pud, address);
89 if (pmd_none_or_clear_bad(pmd))
90 return 0;
91
92 again:
93 /*
94 * This is called while another page table is mapped, so we
95 * must use the nested version. This also means we need to
96 * open-code the spin-locking.
97 */
98 pte = pte_offset_map_rw_nolock(vma->vm_mm, pmd, address, &pmdval, &ptl);
99 if (!pte)
100 return 0;
101
102 if (need_lock) {
103 /*
104 * Use nested version here to indicate that we are already
105 * holding one similar spinlock.
106 */
107 spin_lock_nested(ptl, SINGLE_DEPTH_NESTING);
108 if (unlikely(!pmd_same(pmdval, pmdp_get_lockless(pmd)))) {
109 pte_unmap_unlock(pte, ptl);
110 goto again;
111 }
112 }
113
114 ret = do_adjust_pte(vma, address, pfn, pte);
115
116 if (need_lock)
117 spin_unlock(ptl);
118 pte_unmap(pte);
119
120 return ret;
121 }
122
123 static void
make_coherent(struct address_space * mapping,struct vm_area_struct * vma,unsigned long addr,pte_t * ptep,unsigned long pfn)124 make_coherent(struct address_space *mapping, struct vm_area_struct *vma,
125 unsigned long addr, pte_t *ptep, unsigned long pfn)
126 {
127 const unsigned long pmd_start_addr = ALIGN_DOWN(addr, PMD_SIZE);
128 const unsigned long pmd_end_addr = pmd_start_addr + PMD_SIZE;
129 struct mm_struct *mm = vma->vm_mm;
130 struct vm_area_struct *mpnt;
131 unsigned long offset;
132 pgoff_t pgoff;
133 int aliases = 0;
134
135 pgoff = vma->vm_pgoff + ((addr - vma->vm_start) >> PAGE_SHIFT);
136
137 /*
138 * If we have any shared mappings that are in the same mm
139 * space, then we need to handle them specially to maintain
140 * cache coherency.
141 */
142 flush_dcache_mmap_lock(mapping);
143 vma_interval_tree_foreach(mpnt, &mapping->i_mmap, pgoff, pgoff) {
144 /*
145 * If we are using split PTE locks, then we need to take the pte
146 * lock. Otherwise we are using shared mm->page_table_lock which
147 * is already locked, thus cannot take it.
148 */
149 bool need_lock = IS_ENABLED(CONFIG_SPLIT_PTE_PTLOCKS);
150 unsigned long mpnt_addr;
151
152 /*
153 * If this VMA is not in our MM, we can ignore it.
154 * Note that we intentionally mask out the VMA
155 * that we are fixing up.
156 */
157 if (mpnt->vm_mm != mm || mpnt == vma)
158 continue;
159 if (!(mpnt->vm_flags & VM_MAYSHARE))
160 continue;
161 offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT;
162 mpnt_addr = mpnt->vm_start + offset;
163
164 /* Avoid deadlocks by not grabbing the same PTE lock again. */
165 if (mpnt_addr >= pmd_start_addr && mpnt_addr < pmd_end_addr)
166 need_lock = false;
167 aliases += adjust_pte(mpnt, mpnt_addr, pfn, need_lock);
168 }
169 flush_dcache_mmap_unlock(mapping);
170 if (aliases)
171 do_adjust_pte(vma, addr, pfn, ptep);
172 }
173
174 /*
175 * Take care of architecture specific things when placing a new PTE into
176 * a page table, or changing an existing PTE. Basically, there are two
177 * things that we need to take care of:
178 *
179 * 1. If PG_dcache_clean is not set for the page, we need to ensure
180 * that any cache entries for the kernels virtual memory
181 * range are written back to the page.
182 * 2. If we have multiple shared mappings of the same space in
183 * an object, we need to deal with the cache aliasing issues.
184 *
185 * Note that the pte lock will be held.
186 */
update_mmu_cache_range(struct vm_fault * vmf,struct vm_area_struct * vma,unsigned long addr,pte_t * ptep,unsigned int nr)187 void update_mmu_cache_range(struct vm_fault *vmf, struct vm_area_struct *vma,
188 unsigned long addr, pte_t *ptep, unsigned int nr)
189 {
190 unsigned long pfn = pte_pfn(*ptep);
191 struct address_space *mapping;
192 struct folio *folio;
193
194 if (!pfn_valid(pfn))
195 return;
196
197 /*
198 * The zero page is never written to, so never has any dirty
199 * cache lines, and therefore never needs to be flushed.
200 */
201 if (is_zero_pfn(pfn))
202 return;
203
204 folio = page_folio(pfn_to_page(pfn));
205 mapping = folio_flush_mapping(folio);
206 if (!test_and_set_bit(PG_dcache_clean, &folio->flags))
207 __flush_dcache_folio(mapping, folio);
208 if (mapping) {
209 if (cache_is_vivt())
210 make_coherent(mapping, vma, addr, ptep, pfn);
211 else if (vma->vm_flags & VM_EXEC)
212 __flush_icache_all();
213 }
214 }
215 #endif /* __LINUX_ARM_ARCH__ < 6 */
216
217 /*
218 * Check whether the write buffer has physical address aliasing
219 * issues. If it has, we need to avoid them for the case where
220 * we have several shared mappings of the same object in user
221 * space.
222 */
check_writebuffer(unsigned long * p1,unsigned long * p2)223 static int __init check_writebuffer(unsigned long *p1, unsigned long *p2)
224 {
225 register unsigned long zero = 0, one = 1, val;
226
227 local_irq_disable();
228 mb();
229 *p1 = one;
230 mb();
231 *p2 = zero;
232 mb();
233 val = *p1;
234 mb();
235 local_irq_enable();
236 return val != zero;
237 }
238
check_writebuffer_bugs(void)239 void __init check_writebuffer_bugs(void)
240 {
241 struct page *page;
242 const char *reason;
243 unsigned long v = 1;
244
245 pr_info("CPU: Testing write buffer coherency: ");
246
247 page = alloc_page(GFP_KERNEL);
248 if (page) {
249 unsigned long *p1, *p2;
250 pgprot_t prot = __pgprot_modify(PAGE_KERNEL,
251 L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE);
252
253 p1 = vmap(&page, 1, VM_IOREMAP, prot);
254 p2 = vmap(&page, 1, VM_IOREMAP, prot);
255
256 if (p1 && p2) {
257 v = check_writebuffer(p1, p2);
258 reason = "enabling work-around";
259 } else {
260 reason = "unable to map memory\n";
261 }
262
263 vunmap(p1);
264 vunmap(p2);
265 put_page(page);
266 } else {
267 reason = "unable to grab page\n";
268 }
269
270 if (v) {
271 pr_cont("failed, %s\n", reason);
272 shared_pte_mask = L_PTE_MT_UNCACHED;
273 } else {
274 pr_cont("ok\n");
275 }
276 }
277