1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * omap-mcbsp.c -- OMAP ALSA SoC DAI driver using McBSP port 4 * 5 * Copyright (C) 2008 Nokia Corporation 6 * 7 * Contact: Jarkko Nikula <jarkko.nikula@bitmer.com> 8 * Peter Ujfalusi <peter.ujfalusi@ti.com> 9 */ 10 11 #include <linux/init.h> 12 #include <linux/module.h> 13 #include <linux/device.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/of.h> 16 #include <sound/core.h> 17 #include <sound/pcm.h> 18 #include <sound/pcm_params.h> 19 #include <sound/initval.h> 20 #include <sound/soc.h> 21 #include <sound/dmaengine_pcm.h> 22 23 #include "omap-mcbsp-priv.h" 24 #include "omap-mcbsp.h" 25 #include "sdma-pcm.h" 26 27 #define OMAP_MCBSP_RATES (SNDRV_PCM_RATE_8000_96000) 28 29 enum { 30 OMAP_MCBSP_WORD_8 = 0, 31 OMAP_MCBSP_WORD_12, 32 OMAP_MCBSP_WORD_16, 33 OMAP_MCBSP_WORD_20, 34 OMAP_MCBSP_WORD_24, 35 OMAP_MCBSP_WORD_32, 36 }; 37 38 static void omap_mcbsp_dump_reg(struct omap_mcbsp *mcbsp) 39 { 40 dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id); 41 dev_dbg(mcbsp->dev, "DRR2: 0x%04x\n", MCBSP_READ(mcbsp, DRR2)); 42 dev_dbg(mcbsp->dev, "DRR1: 0x%04x\n", MCBSP_READ(mcbsp, DRR1)); 43 dev_dbg(mcbsp->dev, "DXR2: 0x%04x\n", MCBSP_READ(mcbsp, DXR2)); 44 dev_dbg(mcbsp->dev, "DXR1: 0x%04x\n", MCBSP_READ(mcbsp, DXR1)); 45 dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n", MCBSP_READ(mcbsp, SPCR2)); 46 dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n", MCBSP_READ(mcbsp, SPCR1)); 47 dev_dbg(mcbsp->dev, "RCR2: 0x%04x\n", MCBSP_READ(mcbsp, RCR2)); 48 dev_dbg(mcbsp->dev, "RCR1: 0x%04x\n", MCBSP_READ(mcbsp, RCR1)); 49 dev_dbg(mcbsp->dev, "XCR2: 0x%04x\n", MCBSP_READ(mcbsp, XCR2)); 50 dev_dbg(mcbsp->dev, "XCR1: 0x%04x\n", MCBSP_READ(mcbsp, XCR1)); 51 dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n", MCBSP_READ(mcbsp, SRGR2)); 52 dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n", MCBSP_READ(mcbsp, SRGR1)); 53 dev_dbg(mcbsp->dev, "PCR0: 0x%04x\n", MCBSP_READ(mcbsp, PCR0)); 54 dev_dbg(mcbsp->dev, "***********************\n"); 55 } 56 57 static int omap2_mcbsp_set_clks_src(struct omap_mcbsp *mcbsp, u8 fck_src_id) 58 { 59 struct clk *fck_src; 60 const char *src; 61 int r; 62 63 if (fck_src_id == MCBSP_CLKS_PAD_SRC) 64 src = "pad_fck"; 65 else if (fck_src_id == MCBSP_CLKS_PRCM_SRC) 66 src = "prcm_fck"; 67 else 68 return -EINVAL; 69 70 fck_src = clk_get(mcbsp->dev, src); 71 if (IS_ERR(fck_src)) { 72 dev_info(mcbsp->dev, "CLKS: could not clk_get() %s\n", src); 73 return 0; 74 } 75 76 if (mcbsp->active) 77 pm_runtime_put_sync(mcbsp->dev); 78 79 r = clk_set_parent(mcbsp->fclk, fck_src); 80 if (r) 81 dev_err(mcbsp->dev, "CLKS: could not clk_set_parent() to %s\n", 82 src); 83 84 if (mcbsp->active) 85 pm_runtime_get_sync(mcbsp->dev); 86 87 clk_put(fck_src); 88 89 return r; 90 } 91 92 static irqreturn_t omap_mcbsp_irq_handler(int irq, void *data) 93 { 94 struct omap_mcbsp *mcbsp = data; 95 u16 irqst; 96 97 irqst = MCBSP_READ(mcbsp, IRQST); 98 dev_dbg(mcbsp->dev, "IRQ callback : 0x%x\n", irqst); 99 100 if (irqst & RSYNCERREN) 101 dev_err(mcbsp->dev, "RX Frame Sync Error!\n"); 102 if (irqst & RFSREN) 103 dev_dbg(mcbsp->dev, "RX Frame Sync\n"); 104 if (irqst & REOFEN) 105 dev_dbg(mcbsp->dev, "RX End Of Frame\n"); 106 if (irqst & RRDYEN) 107 dev_dbg(mcbsp->dev, "RX Buffer Threshold Reached\n"); 108 if (irqst & RUNDFLEN) 109 dev_err(mcbsp->dev, "RX Buffer Underflow!\n"); 110 if (irqst & ROVFLEN) 111 dev_err(mcbsp->dev, "RX Buffer Overflow!\n"); 112 113 if (irqst & XSYNCERREN) 114 dev_err(mcbsp->dev, "TX Frame Sync Error!\n"); 115 if (irqst & XFSXEN) 116 dev_dbg(mcbsp->dev, "TX Frame Sync\n"); 117 if (irqst & XEOFEN) 118 dev_dbg(mcbsp->dev, "TX End Of Frame\n"); 119 if (irqst & XRDYEN) 120 dev_dbg(mcbsp->dev, "TX Buffer threshold Reached\n"); 121 if (irqst & XUNDFLEN) 122 dev_err(mcbsp->dev, "TX Buffer Underflow!\n"); 123 if (irqst & XOVFLEN) 124 dev_err(mcbsp->dev, "TX Buffer Overflow!\n"); 125 if (irqst & XEMPTYEOFEN) 126 dev_dbg(mcbsp->dev, "TX Buffer empty at end of frame\n"); 127 128 MCBSP_WRITE(mcbsp, IRQST, irqst); 129 130 return IRQ_HANDLED; 131 } 132 133 static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *data) 134 { 135 struct omap_mcbsp *mcbsp = data; 136 u16 irqst_spcr2; 137 138 irqst_spcr2 = MCBSP_READ(mcbsp, SPCR2); 139 dev_dbg(mcbsp->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2); 140 141 if (irqst_spcr2 & XSYNC_ERR) { 142 dev_err(mcbsp->dev, "TX Frame Sync Error! : 0x%x\n", 143 irqst_spcr2); 144 /* Writing zero to XSYNC_ERR clears the IRQ */ 145 MCBSP_WRITE(mcbsp, SPCR2, MCBSP_READ_CACHE(mcbsp, SPCR2)); 146 } 147 148 return IRQ_HANDLED; 149 } 150 151 static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *data) 152 { 153 struct omap_mcbsp *mcbsp = data; 154 u16 irqst_spcr1; 155 156 irqst_spcr1 = MCBSP_READ(mcbsp, SPCR1); 157 dev_dbg(mcbsp->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1); 158 159 if (irqst_spcr1 & RSYNC_ERR) { 160 dev_err(mcbsp->dev, "RX Frame Sync Error! : 0x%x\n", 161 irqst_spcr1); 162 /* Writing zero to RSYNC_ERR clears the IRQ */ 163 MCBSP_WRITE(mcbsp, SPCR1, MCBSP_READ_CACHE(mcbsp, SPCR1)); 164 } 165 166 return IRQ_HANDLED; 167 } 168 169 /* 170 * omap_mcbsp_config simply write a config to the 171 * appropriate McBSP. 172 * You either call this function or set the McBSP registers 173 * by yourself before calling omap_mcbsp_start(). 174 */ 175 static void omap_mcbsp_config(struct omap_mcbsp *mcbsp, 176 const struct omap_mcbsp_reg_cfg *config) 177 { 178 dev_dbg(mcbsp->dev, "Configuring McBSP%d phys_base: 0x%08lx\n", 179 mcbsp->id, mcbsp->phys_base); 180 181 /* We write the given config */ 182 MCBSP_WRITE(mcbsp, SPCR2, config->spcr2); 183 MCBSP_WRITE(mcbsp, SPCR1, config->spcr1); 184 MCBSP_WRITE(mcbsp, RCR2, config->rcr2); 185 MCBSP_WRITE(mcbsp, RCR1, config->rcr1); 186 MCBSP_WRITE(mcbsp, XCR2, config->xcr2); 187 MCBSP_WRITE(mcbsp, XCR1, config->xcr1); 188 MCBSP_WRITE(mcbsp, SRGR2, config->srgr2); 189 MCBSP_WRITE(mcbsp, SRGR1, config->srgr1); 190 MCBSP_WRITE(mcbsp, MCR2, config->mcr2); 191 MCBSP_WRITE(mcbsp, MCR1, config->mcr1); 192 MCBSP_WRITE(mcbsp, PCR0, config->pcr0); 193 if (mcbsp->pdata->has_ccr) { 194 MCBSP_WRITE(mcbsp, XCCR, config->xccr); 195 MCBSP_WRITE(mcbsp, RCCR, config->rccr); 196 } 197 /* Enable wakeup behavior */ 198 if (mcbsp->pdata->has_wakeup) 199 MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN); 200 201 /* Enable TX/RX sync error interrupts by default */ 202 if (mcbsp->irq) 203 MCBSP_WRITE(mcbsp, IRQEN, RSYNCERREN | XSYNCERREN | 204 RUNDFLEN | ROVFLEN | XUNDFLEN | XOVFLEN); 205 } 206 207 /** 208 * omap_mcbsp_dma_reg_params - returns the address of mcbsp data register 209 * @mcbsp: omap_mcbsp struct for the McBSP instance 210 * @stream: Stream direction (playback/capture) 211 * 212 * Returns the address of mcbsp data transmit register or data receive register 213 * to be used by DMA for transferring/receiving data 214 */ 215 static int omap_mcbsp_dma_reg_params(struct omap_mcbsp *mcbsp, 216 unsigned int stream) 217 { 218 int data_reg; 219 220 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 221 if (mcbsp->pdata->reg_size == 2) 222 data_reg = OMAP_MCBSP_REG_DXR1; 223 else 224 data_reg = OMAP_MCBSP_REG_DXR; 225 } else { 226 if (mcbsp->pdata->reg_size == 2) 227 data_reg = OMAP_MCBSP_REG_DRR1; 228 else 229 data_reg = OMAP_MCBSP_REG_DRR; 230 } 231 232 return mcbsp->phys_dma_base + data_reg * mcbsp->pdata->reg_step; 233 } 234 235 /* 236 * omap_mcbsp_set_rx_threshold configures the transmit threshold in words. 237 * The threshold parameter is 1 based, and it is converted (threshold - 1) 238 * for the THRSH2 register. 239 */ 240 static void omap_mcbsp_set_tx_threshold(struct omap_mcbsp *mcbsp, u16 threshold) 241 { 242 if (threshold && threshold <= mcbsp->max_tx_thres) 243 MCBSP_WRITE(mcbsp, THRSH2, threshold - 1); 244 } 245 246 /* 247 * omap_mcbsp_set_rx_threshold configures the receive threshold in words. 248 * The threshold parameter is 1 based, and it is converted (threshold - 1) 249 * for the THRSH1 register. 250 */ 251 static void omap_mcbsp_set_rx_threshold(struct omap_mcbsp *mcbsp, u16 threshold) 252 { 253 if (threshold && threshold <= mcbsp->max_rx_thres) 254 MCBSP_WRITE(mcbsp, THRSH1, threshold - 1); 255 } 256 257 /* 258 * omap_mcbsp_get_tx_delay returns the number of used slots in the McBSP FIFO 259 */ 260 static u16 omap_mcbsp_get_tx_delay(struct omap_mcbsp *mcbsp) 261 { 262 u16 buffstat; 263 264 /* Returns the number of free locations in the buffer */ 265 buffstat = MCBSP_READ(mcbsp, XBUFFSTAT); 266 267 /* Number of slots are different in McBSP ports */ 268 return mcbsp->pdata->buffer_size - buffstat; 269 } 270 271 /* 272 * omap_mcbsp_get_rx_delay returns the number of free slots in the McBSP FIFO 273 * to reach the threshold value (when the DMA will be triggered to read it) 274 */ 275 static u16 omap_mcbsp_get_rx_delay(struct omap_mcbsp *mcbsp) 276 { 277 u16 buffstat, threshold; 278 279 /* Returns the number of used locations in the buffer */ 280 buffstat = MCBSP_READ(mcbsp, RBUFFSTAT); 281 /* RX threshold */ 282 threshold = MCBSP_READ(mcbsp, THRSH1); 283 284 /* Return the number of location till we reach the threshold limit */ 285 if (threshold <= buffstat) 286 return 0; 287 else 288 return threshold - buffstat; 289 } 290 291 static int omap_mcbsp_request(struct omap_mcbsp *mcbsp) 292 { 293 void *reg_cache __free(kfree) = kzalloc(mcbsp->reg_cache_size, GFP_KERNEL); 294 int err; 295 296 if (!reg_cache) 297 return -ENOMEM; 298 299 scoped_guard(spinlock, &mcbsp->lock) { 300 if (!mcbsp->free) { 301 dev_err(mcbsp->dev, "McBSP%d is currently in use\n", mcbsp->id); 302 return -EBUSY; 303 } 304 305 mcbsp->free = false; 306 mcbsp->reg_cache = reg_cache; 307 reg_cache = NULL; 308 } 309 310 if (mcbsp->pdata->ops && mcbsp->pdata->ops->request) 311 mcbsp->pdata->ops->request(mcbsp->id - 1); 312 313 /* 314 * Make sure that transmitter, receiver and sample-rate generator are 315 * not running before activating IRQs. 316 */ 317 MCBSP_WRITE(mcbsp, SPCR1, 0); 318 MCBSP_WRITE(mcbsp, SPCR2, 0); 319 320 if (mcbsp->irq) { 321 err = request_irq(mcbsp->irq, omap_mcbsp_irq_handler, 0, 322 "McBSP", (void *)mcbsp); 323 if (err != 0) { 324 dev_err(mcbsp->dev, "Unable to request IRQ\n"); 325 } 326 } else { 327 err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler, 0, 328 "McBSP TX", (void *)mcbsp); 329 if (err != 0) { 330 dev_err(mcbsp->dev, "Unable to request TX IRQ\n"); 331 } else { 332 err = request_irq(mcbsp->rx_irq, omap_mcbsp_rx_irq_handler, 0, 333 "McBSP RX", (void *)mcbsp); 334 if (err != 0) { 335 dev_err(mcbsp->dev, "Unable to request RX IRQ\n"); 336 free_irq(mcbsp->tx_irq, (void *)mcbsp); 337 } 338 } 339 } 340 341 if (err != 0) { 342 if (mcbsp->pdata->ops && mcbsp->pdata->ops->free) 343 mcbsp->pdata->ops->free(mcbsp->id - 1); 344 345 /* Disable wakeup behavior */ 346 if (mcbsp->pdata->has_wakeup) 347 MCBSP_WRITE(mcbsp, WAKEUPEN, 0); 348 349 scoped_guard(spinlock, &mcbsp->lock) { 350 reg_cache = mcbsp->reg_cache; 351 mcbsp->free = true; 352 mcbsp->reg_cache = NULL; 353 } 354 355 return err; 356 } 357 358 return 0; 359 } 360 361 static void omap_mcbsp_free(struct omap_mcbsp *mcbsp) 362 { 363 void *reg_cache; 364 365 if(mcbsp->pdata->ops && mcbsp->pdata->ops->free) 366 mcbsp->pdata->ops->free(mcbsp->id - 1); 367 368 /* Disable wakeup behavior */ 369 if (mcbsp->pdata->has_wakeup) 370 MCBSP_WRITE(mcbsp, WAKEUPEN, 0); 371 372 /* Disable interrupt requests */ 373 if (mcbsp->irq) { 374 MCBSP_WRITE(mcbsp, IRQEN, 0); 375 376 free_irq(mcbsp->irq, (void *)mcbsp); 377 } else { 378 free_irq(mcbsp->rx_irq, (void *)mcbsp); 379 free_irq(mcbsp->tx_irq, (void *)mcbsp); 380 } 381 382 reg_cache = mcbsp->reg_cache; 383 384 /* 385 * Select CLKS source from internal source unconditionally before 386 * marking the McBSP port as free. 387 * If the external clock source via MCBSP_CLKS pin has been selected the 388 * system will refuse to enter idle if the CLKS pin source is not reset 389 * back to internal source. 390 */ 391 if (!mcbsp_omap1()) 392 omap2_mcbsp_set_clks_src(mcbsp, MCBSP_CLKS_PRCM_SRC); 393 394 scoped_guard(spinlock, &mcbsp->lock) { 395 if (mcbsp->free) 396 dev_err(mcbsp->dev, "McBSP%d was not reserved\n", mcbsp->id); 397 else 398 mcbsp->free = true; 399 mcbsp->reg_cache = NULL; 400 } 401 402 kfree(reg_cache); 403 } 404 405 /* 406 * Here we start the McBSP, by enabling transmitter, receiver or both. 407 * If no transmitter or receiver is active prior calling, then sample-rate 408 * generator and frame sync are started. 409 */ 410 static void omap_mcbsp_start(struct omap_mcbsp *mcbsp, int stream) 411 { 412 int tx = (stream == SNDRV_PCM_STREAM_PLAYBACK); 413 int rx = !tx; 414 int enable_srg = 0; 415 u16 w; 416 417 if (mcbsp->st_data) 418 omap_mcbsp_st_start(mcbsp); 419 420 /* Only enable SRG, if McBSP is master */ 421 w = MCBSP_READ_CACHE(mcbsp, PCR0); 422 if (w & (FSXM | FSRM | CLKXM | CLKRM)) 423 enable_srg = !((MCBSP_READ_CACHE(mcbsp, SPCR2) | 424 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1); 425 426 if (enable_srg) { 427 /* Start the sample generator */ 428 w = MCBSP_READ_CACHE(mcbsp, SPCR2); 429 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6)); 430 } 431 432 /* Enable transmitter and receiver */ 433 tx &= 1; 434 w = MCBSP_READ_CACHE(mcbsp, SPCR2); 435 MCBSP_WRITE(mcbsp, SPCR2, w | tx); 436 437 rx &= 1; 438 w = MCBSP_READ_CACHE(mcbsp, SPCR1); 439 MCBSP_WRITE(mcbsp, SPCR1, w | rx); 440 441 /* 442 * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec 443 * REVISIT: 100us may give enough time for two CLKSRG, however 444 * due to some unknown PM related, clock gating etc. reason it 445 * is now at 500us. 446 */ 447 udelay(500); 448 449 if (enable_srg) { 450 /* Start frame sync */ 451 w = MCBSP_READ_CACHE(mcbsp, SPCR2); 452 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7)); 453 } 454 455 if (mcbsp->pdata->has_ccr) { 456 /* Release the transmitter and receiver */ 457 w = MCBSP_READ_CACHE(mcbsp, XCCR); 458 w &= ~(tx ? XDISABLE : 0); 459 MCBSP_WRITE(mcbsp, XCCR, w); 460 w = MCBSP_READ_CACHE(mcbsp, RCCR); 461 w &= ~(rx ? RDISABLE : 0); 462 MCBSP_WRITE(mcbsp, RCCR, w); 463 } 464 465 /* Dump McBSP Regs */ 466 omap_mcbsp_dump_reg(mcbsp); 467 } 468 469 static void omap_mcbsp_stop(struct omap_mcbsp *mcbsp, int stream) 470 { 471 int tx = (stream == SNDRV_PCM_STREAM_PLAYBACK); 472 int rx = !tx; 473 int idle; 474 u16 w; 475 476 /* Reset transmitter */ 477 tx &= 1; 478 if (mcbsp->pdata->has_ccr) { 479 w = MCBSP_READ_CACHE(mcbsp, XCCR); 480 w |= (tx ? XDISABLE : 0); 481 MCBSP_WRITE(mcbsp, XCCR, w); 482 } 483 w = MCBSP_READ_CACHE(mcbsp, SPCR2); 484 MCBSP_WRITE(mcbsp, SPCR2, w & ~tx); 485 486 /* Reset receiver */ 487 rx &= 1; 488 if (mcbsp->pdata->has_ccr) { 489 w = MCBSP_READ_CACHE(mcbsp, RCCR); 490 w |= (rx ? RDISABLE : 0); 491 MCBSP_WRITE(mcbsp, RCCR, w); 492 } 493 w = MCBSP_READ_CACHE(mcbsp, SPCR1); 494 MCBSP_WRITE(mcbsp, SPCR1, w & ~rx); 495 496 idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) | 497 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1); 498 499 if (idle) { 500 /* Reset the sample rate generator */ 501 w = MCBSP_READ_CACHE(mcbsp, SPCR2); 502 MCBSP_WRITE(mcbsp, SPCR2, w & ~(1 << 6)); 503 } 504 505 if (mcbsp->st_data) 506 omap_mcbsp_st_stop(mcbsp); 507 } 508 509 #define max_thres(m) (mcbsp->pdata->buffer_size) 510 #define valid_threshold(m, val) ((val) <= max_thres(m)) 511 #define THRESHOLD_PROP_BUILDER(prop) \ 512 static ssize_t prop##_show(struct device *dev, \ 513 struct device_attribute *attr, char *buf) \ 514 { \ 515 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \ 516 \ 517 return sysfs_emit(buf, "%u\n", mcbsp->prop); \ 518 } \ 519 \ 520 static ssize_t prop##_store(struct device *dev, \ 521 struct device_attribute *attr, \ 522 const char *buf, size_t size) \ 523 { \ 524 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \ 525 unsigned long val; \ 526 int status; \ 527 \ 528 status = kstrtoul(buf, 0, &val); \ 529 if (status) \ 530 return status; \ 531 \ 532 if (!valid_threshold(mcbsp, val)) \ 533 return -EDOM; \ 534 \ 535 mcbsp->prop = val; \ 536 return size; \ 537 } \ 538 \ 539 static DEVICE_ATTR_RW(prop) 540 541 THRESHOLD_PROP_BUILDER(max_tx_thres); 542 THRESHOLD_PROP_BUILDER(max_rx_thres); 543 544 static const char * const dma_op_modes[] = { 545 "element", "threshold", 546 }; 547 548 static ssize_t dma_op_mode_show(struct device *dev, 549 struct device_attribute *attr, char *buf) 550 { 551 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); 552 int dma_op_mode, i = 0; 553 ssize_t len = 0; 554 const char * const *s; 555 556 dma_op_mode = mcbsp->dma_op_mode; 557 558 for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++) { 559 if (dma_op_mode == i) 560 len += sysfs_emit_at(buf, len, "[%s] ", *s); 561 else 562 len += sysfs_emit_at(buf, len, "%s ", *s); 563 } 564 len += sysfs_emit_at(buf, len, "\n"); 565 566 return len; 567 } 568 569 static ssize_t dma_op_mode_store(struct device *dev, 570 struct device_attribute *attr, const char *buf, 571 size_t size) 572 { 573 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); 574 int i; 575 576 i = sysfs_match_string(dma_op_modes, buf); 577 if (i < 0) 578 return i; 579 580 guard(spinlock_irq)(&mcbsp->lock); 581 if (!mcbsp->free) { 582 return -EBUSY; 583 } 584 mcbsp->dma_op_mode = i; 585 586 return size; 587 } 588 589 static DEVICE_ATTR_RW(dma_op_mode); 590 591 static const struct attribute *additional_attrs[] = { 592 &dev_attr_max_tx_thres.attr, 593 &dev_attr_max_rx_thres.attr, 594 &dev_attr_dma_op_mode.attr, 595 NULL, 596 }; 597 598 static const struct attribute_group additional_attr_group = { 599 .attrs = (struct attribute **)additional_attrs, 600 }; 601 602 /* 603 * McBSP1 and McBSP3 are directly mapped on 1610 and 1510. 604 * 730 has only 2 McBSP, and both of them are MPU peripherals. 605 */ 606 static int omap_mcbsp_init(struct platform_device *pdev) 607 { 608 struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev); 609 struct resource *res; 610 int ret; 611 612 spin_lock_init(&mcbsp->lock); 613 mcbsp->free = true; 614 615 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu"); 616 if (!res) 617 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 618 619 mcbsp->io_base = devm_ioremap_resource(&pdev->dev, res); 620 if (IS_ERR(mcbsp->io_base)) 621 return PTR_ERR(mcbsp->io_base); 622 623 mcbsp->phys_base = res->start; 624 mcbsp->reg_cache_size = resource_size(res); 625 626 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma"); 627 if (!res) 628 mcbsp->phys_dma_base = mcbsp->phys_base; 629 else 630 mcbsp->phys_dma_base = res->start; 631 632 /* 633 * OMAP1, 2 uses two interrupt lines: TX, RX 634 * OMAP2430, OMAP3 SoC have combined IRQ line as well. 635 * OMAP4 and newer SoC only have the combined IRQ line. 636 * Use the combined IRQ if available since it gives better debugging 637 * possibilities. 638 */ 639 mcbsp->irq = platform_get_irq_byname(pdev, "common"); 640 if (mcbsp->irq == -ENXIO) { 641 mcbsp->tx_irq = platform_get_irq_byname(pdev, "tx"); 642 643 if (mcbsp->tx_irq == -ENXIO) { 644 mcbsp->irq = platform_get_irq(pdev, 0); 645 mcbsp->tx_irq = 0; 646 } else { 647 mcbsp->rx_irq = platform_get_irq_byname(pdev, "rx"); 648 mcbsp->irq = 0; 649 } 650 } 651 652 if (!pdev->dev.of_node) { 653 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx"); 654 if (!res) { 655 dev_err(&pdev->dev, "invalid tx DMA channel\n"); 656 return -ENODEV; 657 } 658 mcbsp->dma_req[0] = res->start; 659 mcbsp->dma_data[0].filter_data = &mcbsp->dma_req[0]; 660 661 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx"); 662 if (!res) { 663 dev_err(&pdev->dev, "invalid rx DMA channel\n"); 664 return -ENODEV; 665 } 666 mcbsp->dma_req[1] = res->start; 667 mcbsp->dma_data[1].filter_data = &mcbsp->dma_req[1]; 668 } else { 669 mcbsp->dma_data[0].filter_data = "tx"; 670 mcbsp->dma_data[1].filter_data = "rx"; 671 } 672 673 mcbsp->dma_data[0].addr = omap_mcbsp_dma_reg_params(mcbsp, 674 SNDRV_PCM_STREAM_PLAYBACK); 675 mcbsp->dma_data[1].addr = omap_mcbsp_dma_reg_params(mcbsp, 676 SNDRV_PCM_STREAM_CAPTURE); 677 678 mcbsp->fclk = devm_clk_get(&pdev->dev, "fck"); 679 if (IS_ERR(mcbsp->fclk)) { 680 ret = PTR_ERR(mcbsp->fclk); 681 dev_err(mcbsp->dev, "unable to get fck: %d\n", ret); 682 return ret; 683 } 684 685 mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT; 686 if (mcbsp->pdata->buffer_size) { 687 /* 688 * Initially configure the maximum thresholds to a safe value. 689 * The McBSP FIFO usage with these values should not go under 690 * 16 locations. 691 * If the whole FIFO without safety buffer is used, than there 692 * is a possibility that the DMA will be not able to push the 693 * new data on time, causing channel shifts in runtime. 694 */ 695 mcbsp->max_tx_thres = max_thres(mcbsp) - 0x10; 696 mcbsp->max_rx_thres = max_thres(mcbsp) - 0x10; 697 698 ret = devm_device_add_group(mcbsp->dev, &additional_attr_group); 699 if (ret) { 700 dev_err(mcbsp->dev, 701 "Unable to create additional controls\n"); 702 return ret; 703 } 704 } 705 706 return omap_mcbsp_st_init(pdev); 707 } 708 709 /* 710 * Stream DMA parameters. DMA request line and port address are set runtime 711 * since they are different between OMAP1 and later OMAPs 712 */ 713 static void omap_mcbsp_set_threshold(struct snd_pcm_substream *substream, 714 unsigned int packet_size) 715 { 716 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); 717 struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0); 718 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); 719 int words; 720 721 /* No need to proceed further if McBSP does not have FIFO */ 722 if (mcbsp->pdata->buffer_size == 0) 723 return; 724 725 /* 726 * Configure McBSP threshold based on either: 727 * packet_size, when the sDMA is in packet mode, or based on the 728 * period size in THRESHOLD mode, otherwise use McBSP threshold = 1 729 * for mono streams. 730 */ 731 if (packet_size) 732 words = packet_size; 733 else 734 words = 1; 735 736 /* Configure McBSP internal buffer usage */ 737 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 738 omap_mcbsp_set_tx_threshold(mcbsp, words); 739 else 740 omap_mcbsp_set_rx_threshold(mcbsp, words); 741 } 742 743 static int omap_mcbsp_hwrule_min_buffersize(struct snd_pcm_hw_params *params, 744 struct snd_pcm_hw_rule *rule) 745 { 746 struct snd_interval *buffer_size = hw_param_interval(params, 747 SNDRV_PCM_HW_PARAM_BUFFER_SIZE); 748 struct snd_interval *channels = hw_param_interval(params, 749 SNDRV_PCM_HW_PARAM_CHANNELS); 750 struct omap_mcbsp *mcbsp = rule->private; 751 struct snd_interval frames; 752 int size; 753 754 snd_interval_any(&frames); 755 size = mcbsp->pdata->buffer_size; 756 757 frames.min = size / channels->min; 758 frames.integer = 1; 759 return snd_interval_refine(buffer_size, &frames); 760 } 761 762 static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream, 763 struct snd_soc_dai *cpu_dai) 764 { 765 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); 766 int err = 0; 767 768 if (!snd_soc_dai_active(cpu_dai)) 769 err = omap_mcbsp_request(mcbsp); 770 771 /* 772 * OMAP3 McBSP FIFO is word structured. 773 * McBSP2 has 1024 + 256 = 1280 word long buffer, 774 * McBSP1,3,4,5 has 128 word long buffer 775 * This means that the size of the FIFO depends on the sample format. 776 * For example on McBSP3: 777 * 16bit samples: size is 128 * 2 = 256 bytes 778 * 32bit samples: size is 128 * 4 = 512 bytes 779 * It is simpler to place constraint for buffer and period based on 780 * channels. 781 * McBSP3 as example again (16 or 32 bit samples): 782 * 1 channel (mono): size is 128 frames (128 words) 783 * 2 channels (stereo): size is 128 / 2 = 64 frames (2 * 64 words) 784 * 4 channels: size is 128 / 4 = 32 frames (4 * 32 words) 785 */ 786 if (mcbsp->pdata->buffer_size) { 787 /* 788 * Rule for the buffer size. We should not allow 789 * smaller buffer than the FIFO size to avoid underruns. 790 * This applies only for the playback stream. 791 */ 792 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 793 snd_pcm_hw_rule_add(substream->runtime, 0, 794 SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 795 omap_mcbsp_hwrule_min_buffersize, 796 mcbsp, 797 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 798 799 /* Make sure, that the period size is always even */ 800 snd_pcm_hw_constraint_step(substream->runtime, 0, 801 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2); 802 } 803 804 return err; 805 } 806 807 static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream, 808 struct snd_soc_dai *cpu_dai) 809 { 810 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); 811 int tx = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); 812 int stream1 = tx ? SNDRV_PCM_STREAM_PLAYBACK : SNDRV_PCM_STREAM_CAPTURE; 813 int stream2 = tx ? SNDRV_PCM_STREAM_CAPTURE : SNDRV_PCM_STREAM_PLAYBACK; 814 815 if (mcbsp->latency[stream2]) 816 cpu_latency_qos_update_request(&mcbsp->pm_qos_req, 817 mcbsp->latency[stream2]); 818 else if (mcbsp->latency[stream1]) 819 cpu_latency_qos_remove_request(&mcbsp->pm_qos_req); 820 821 mcbsp->latency[stream1] = 0; 822 823 if (!snd_soc_dai_active(cpu_dai)) { 824 omap_mcbsp_free(mcbsp); 825 mcbsp->configured = 0; 826 } 827 } 828 829 static int omap_mcbsp_dai_prepare(struct snd_pcm_substream *substream, 830 struct snd_soc_dai *cpu_dai) 831 { 832 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); 833 struct pm_qos_request *pm_qos_req = &mcbsp->pm_qos_req; 834 int tx = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); 835 int stream1 = tx ? SNDRV_PCM_STREAM_PLAYBACK : SNDRV_PCM_STREAM_CAPTURE; 836 int stream2 = tx ? SNDRV_PCM_STREAM_CAPTURE : SNDRV_PCM_STREAM_PLAYBACK; 837 int latency = mcbsp->latency[stream2]; 838 839 /* Prevent omap hardware from hitting off between FIFO fills */ 840 if (!latency || mcbsp->latency[stream1] < latency) 841 latency = mcbsp->latency[stream1]; 842 843 if (cpu_latency_qos_request_active(pm_qos_req)) 844 cpu_latency_qos_update_request(pm_qos_req, latency); 845 else if (latency) 846 cpu_latency_qos_add_request(pm_qos_req, latency); 847 848 return 0; 849 } 850 851 static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd, 852 struct snd_soc_dai *cpu_dai) 853 { 854 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); 855 856 switch (cmd) { 857 case SNDRV_PCM_TRIGGER_START: 858 case SNDRV_PCM_TRIGGER_RESUME: 859 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 860 mcbsp->active++; 861 omap_mcbsp_start(mcbsp, substream->stream); 862 break; 863 864 case SNDRV_PCM_TRIGGER_STOP: 865 case SNDRV_PCM_TRIGGER_SUSPEND: 866 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 867 omap_mcbsp_stop(mcbsp, substream->stream); 868 mcbsp->active--; 869 break; 870 default: 871 return -EINVAL; 872 } 873 874 return 0; 875 } 876 877 static snd_pcm_sframes_t omap_mcbsp_dai_delay( 878 struct snd_pcm_substream *substream, 879 struct snd_soc_dai *dai) 880 { 881 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); 882 struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0); 883 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); 884 u16 fifo_use; 885 snd_pcm_sframes_t delay; 886 887 /* No need to proceed further if McBSP does not have FIFO */ 888 if (mcbsp->pdata->buffer_size == 0) 889 return 0; 890 891 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 892 fifo_use = omap_mcbsp_get_tx_delay(mcbsp); 893 else 894 fifo_use = omap_mcbsp_get_rx_delay(mcbsp); 895 896 /* 897 * Divide the used locations with the channel count to get the 898 * FIFO usage in samples (don't care about partial samples in the 899 * buffer). 900 */ 901 delay = fifo_use / substream->runtime->channels; 902 903 return delay; 904 } 905 906 static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream, 907 struct snd_pcm_hw_params *params, 908 struct snd_soc_dai *cpu_dai) 909 { 910 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); 911 struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs; 912 struct snd_dmaengine_dai_dma_data *dma_data; 913 int wlen, channels, wpf; 914 int pkt_size = 0; 915 unsigned int format, div, framesize, master; 916 unsigned int buffer_size = mcbsp->pdata->buffer_size; 917 918 dma_data = snd_soc_dai_get_dma_data(cpu_dai, substream); 919 channels = params_channels(params); 920 921 switch (params_format(params)) { 922 case SNDRV_PCM_FORMAT_S16_LE: 923 wlen = 16; 924 break; 925 case SNDRV_PCM_FORMAT_S32_LE: 926 wlen = 32; 927 break; 928 default: 929 return -EINVAL; 930 } 931 if (buffer_size) { 932 int latency; 933 934 if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) { 935 int period_words, max_thrsh; 936 int divider = 0; 937 938 period_words = params_period_bytes(params) / (wlen / 8); 939 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 940 max_thrsh = mcbsp->max_tx_thres; 941 else 942 max_thrsh = mcbsp->max_rx_thres; 943 /* 944 * Use sDMA packet mode if McBSP is in threshold mode: 945 * If period words less than the FIFO size the packet 946 * size is set to the number of period words, otherwise 947 * Look for the biggest threshold value which divides 948 * the period size evenly. 949 */ 950 divider = period_words / max_thrsh; 951 if (period_words % max_thrsh) 952 divider++; 953 while (period_words % divider && 954 divider < period_words) 955 divider++; 956 if (divider == period_words) 957 return -EINVAL; 958 959 pkt_size = period_words / divider; 960 } else if (channels > 1) { 961 /* Use packet mode for non mono streams */ 962 pkt_size = channels; 963 } 964 965 latency = (buffer_size - pkt_size) / channels; 966 latency = latency * USEC_PER_SEC / 967 (params->rate_num / params->rate_den); 968 mcbsp->latency[substream->stream] = latency; 969 970 omap_mcbsp_set_threshold(substream, pkt_size); 971 } 972 973 dma_data->maxburst = pkt_size; 974 975 if (mcbsp->configured) { 976 /* McBSP already configured by another stream */ 977 return 0; 978 } 979 980 regs->rcr2 &= ~(RPHASE | RFRLEN2(0x7f) | RWDLEN2(7)); 981 regs->xcr2 &= ~(RPHASE | XFRLEN2(0x7f) | XWDLEN2(7)); 982 regs->rcr1 &= ~(RFRLEN1(0x7f) | RWDLEN1(7)); 983 regs->xcr1 &= ~(XFRLEN1(0x7f) | XWDLEN1(7)); 984 format = mcbsp->fmt & SND_SOC_DAIFMT_FORMAT_MASK; 985 wpf = channels; 986 if (channels == 2 && (format == SND_SOC_DAIFMT_I2S || 987 format == SND_SOC_DAIFMT_LEFT_J)) { 988 /* Use dual-phase frames */ 989 regs->rcr2 |= RPHASE; 990 regs->xcr2 |= XPHASE; 991 /* Set 1 word per (McBSP) frame for phase1 and phase2 */ 992 wpf--; 993 regs->rcr2 |= RFRLEN2(wpf - 1); 994 regs->xcr2 |= XFRLEN2(wpf - 1); 995 } 996 997 regs->rcr1 |= RFRLEN1(wpf - 1); 998 regs->xcr1 |= XFRLEN1(wpf - 1); 999 1000 switch (params_format(params)) { 1001 case SNDRV_PCM_FORMAT_S16_LE: 1002 /* Set word lengths */ 1003 regs->rcr2 |= RWDLEN2(OMAP_MCBSP_WORD_16); 1004 regs->rcr1 |= RWDLEN1(OMAP_MCBSP_WORD_16); 1005 regs->xcr2 |= XWDLEN2(OMAP_MCBSP_WORD_16); 1006 regs->xcr1 |= XWDLEN1(OMAP_MCBSP_WORD_16); 1007 break; 1008 case SNDRV_PCM_FORMAT_S32_LE: 1009 /* Set word lengths */ 1010 regs->rcr2 |= RWDLEN2(OMAP_MCBSP_WORD_32); 1011 regs->rcr1 |= RWDLEN1(OMAP_MCBSP_WORD_32); 1012 regs->xcr2 |= XWDLEN2(OMAP_MCBSP_WORD_32); 1013 regs->xcr1 |= XWDLEN1(OMAP_MCBSP_WORD_32); 1014 break; 1015 default: 1016 /* Unsupported PCM format */ 1017 return -EINVAL; 1018 } 1019 1020 /* In McBSP master modes, FRAME (i.e. sample rate) is generated 1021 * by _counting_ BCLKs. Calculate frame size in BCLKs */ 1022 master = mcbsp->fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK; 1023 if (master == SND_SOC_DAIFMT_BP_FP) { 1024 div = mcbsp->clk_div ? mcbsp->clk_div : 1; 1025 framesize = (mcbsp->in_freq / div) / params_rate(params); 1026 1027 if (framesize < wlen * channels) { 1028 printk(KERN_ERR "%s: not enough bandwidth for desired rate and " 1029 "channels\n", __func__); 1030 return -EINVAL; 1031 } 1032 } else 1033 framesize = wlen * channels; 1034 1035 /* Set FS period and length in terms of bit clock periods */ 1036 regs->srgr2 &= ~FPER(0xfff); 1037 regs->srgr1 &= ~FWID(0xff); 1038 switch (format) { 1039 case SND_SOC_DAIFMT_I2S: 1040 case SND_SOC_DAIFMT_LEFT_J: 1041 regs->srgr2 |= FPER(framesize - 1); 1042 regs->srgr1 |= FWID((framesize >> 1) - 1); 1043 break; 1044 case SND_SOC_DAIFMT_DSP_A: 1045 case SND_SOC_DAIFMT_DSP_B: 1046 regs->srgr2 |= FPER(framesize - 1); 1047 regs->srgr1 |= FWID(0); 1048 break; 1049 } 1050 1051 omap_mcbsp_config(mcbsp, &mcbsp->cfg_regs); 1052 mcbsp->wlen = wlen; 1053 mcbsp->configured = 1; 1054 1055 return 0; 1056 } 1057 1058 /* 1059 * This must be called before _set_clkdiv and _set_sysclk since McBSP register 1060 * cache is initialized here 1061 */ 1062 static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai, 1063 unsigned int fmt) 1064 { 1065 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); 1066 struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs; 1067 bool inv_fs = false; 1068 1069 if (mcbsp->configured) 1070 return 0; 1071 1072 mcbsp->fmt = fmt; 1073 memset(regs, 0, sizeof(*regs)); 1074 /* Generic McBSP register settings */ 1075 regs->spcr2 |= XINTM(3) | FREE; 1076 regs->spcr1 |= RINTM(3); 1077 /* RFIG and XFIG are not defined in 2430 and on OMAP3+ */ 1078 if (!mcbsp->pdata->has_ccr) { 1079 regs->rcr2 |= RFIG; 1080 regs->xcr2 |= XFIG; 1081 } 1082 1083 /* Configure XCCR/RCCR only for revisions which have ccr registers */ 1084 if (mcbsp->pdata->has_ccr) { 1085 regs->xccr = DXENDLY(1) | XDMAEN | XDISABLE; 1086 regs->rccr = RFULL_CYCLE | RDMAEN | RDISABLE; 1087 } 1088 1089 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1090 case SND_SOC_DAIFMT_I2S: 1091 /* 1-bit data delay */ 1092 regs->rcr2 |= RDATDLY(1); 1093 regs->xcr2 |= XDATDLY(1); 1094 break; 1095 case SND_SOC_DAIFMT_LEFT_J: 1096 /* 0-bit data delay */ 1097 regs->rcr2 |= RDATDLY(0); 1098 regs->xcr2 |= XDATDLY(0); 1099 regs->spcr1 |= RJUST(2); 1100 /* Invert FS polarity configuration */ 1101 inv_fs = true; 1102 break; 1103 case SND_SOC_DAIFMT_DSP_A: 1104 /* 1-bit data delay */ 1105 regs->rcr2 |= RDATDLY(1); 1106 regs->xcr2 |= XDATDLY(1); 1107 /* Invert FS polarity configuration */ 1108 inv_fs = true; 1109 break; 1110 case SND_SOC_DAIFMT_DSP_B: 1111 /* 0-bit data delay */ 1112 regs->rcr2 |= RDATDLY(0); 1113 regs->xcr2 |= XDATDLY(0); 1114 /* Invert FS polarity configuration */ 1115 inv_fs = true; 1116 break; 1117 default: 1118 /* Unsupported data format */ 1119 return -EINVAL; 1120 } 1121 1122 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 1123 case SND_SOC_DAIFMT_BP_FP: 1124 /* McBSP master. Set FS and bit clocks as outputs */ 1125 regs->pcr0 |= FSXM | FSRM | 1126 CLKXM | CLKRM; 1127 /* Sample rate generator drives the FS */ 1128 regs->srgr2 |= FSGM; 1129 break; 1130 case SND_SOC_DAIFMT_BC_FP: 1131 /* McBSP slave. FS clock as output */ 1132 regs->srgr2 |= FSGM; 1133 regs->pcr0 |= FSXM | FSRM; 1134 break; 1135 case SND_SOC_DAIFMT_BC_FC: 1136 /* McBSP slave */ 1137 break; 1138 default: 1139 /* Unsupported master/slave configuration */ 1140 return -EINVAL; 1141 } 1142 1143 /* Set bit clock (CLKX/CLKR) and FS polarities */ 1144 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1145 case SND_SOC_DAIFMT_NB_NF: 1146 /* 1147 * Normal BCLK + FS. 1148 * FS active low. TX data driven on falling edge of bit clock 1149 * and RX data sampled on rising edge of bit clock. 1150 */ 1151 regs->pcr0 |= FSXP | FSRP | 1152 CLKXP | CLKRP; 1153 break; 1154 case SND_SOC_DAIFMT_NB_IF: 1155 regs->pcr0 |= CLKXP | CLKRP; 1156 break; 1157 case SND_SOC_DAIFMT_IB_NF: 1158 regs->pcr0 |= FSXP | FSRP; 1159 break; 1160 case SND_SOC_DAIFMT_IB_IF: 1161 break; 1162 default: 1163 return -EINVAL; 1164 } 1165 if (inv_fs) 1166 regs->pcr0 ^= FSXP | FSRP; 1167 1168 return 0; 1169 } 1170 1171 static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai, 1172 int div_id, int div) 1173 { 1174 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); 1175 struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs; 1176 1177 if (div_id != OMAP_MCBSP_CLKGDV) 1178 return -ENODEV; 1179 1180 mcbsp->clk_div = div; 1181 regs->srgr1 &= ~CLKGDV(0xff); 1182 regs->srgr1 |= CLKGDV(div - 1); 1183 1184 return 0; 1185 } 1186 1187 static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai, 1188 int clk_id, unsigned int freq, 1189 int dir) 1190 { 1191 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); 1192 struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs; 1193 int err = 0; 1194 1195 if (mcbsp->active) { 1196 if (freq == mcbsp->in_freq) 1197 return 0; 1198 else 1199 return -EBUSY; 1200 } 1201 1202 mcbsp->in_freq = freq; 1203 regs->srgr2 &= ~CLKSM; 1204 regs->pcr0 &= ~SCLKME; 1205 1206 switch (clk_id) { 1207 case OMAP_MCBSP_SYSCLK_CLK: 1208 regs->srgr2 |= CLKSM; 1209 break; 1210 case OMAP_MCBSP_SYSCLK_CLKS_FCLK: 1211 if (mcbsp_omap1()) { 1212 err = -EINVAL; 1213 break; 1214 } 1215 err = omap2_mcbsp_set_clks_src(mcbsp, 1216 MCBSP_CLKS_PRCM_SRC); 1217 break; 1218 case OMAP_MCBSP_SYSCLK_CLKS_EXT: 1219 if (mcbsp_omap1()) { 1220 err = 0; 1221 break; 1222 } 1223 err = omap2_mcbsp_set_clks_src(mcbsp, 1224 MCBSP_CLKS_PAD_SRC); 1225 break; 1226 1227 case OMAP_MCBSP_SYSCLK_CLKX_EXT: 1228 regs->srgr2 |= CLKSM; 1229 regs->pcr0 |= SCLKME; 1230 /* 1231 * If McBSP is master but yet the CLKX/CLKR pin drives the SRG, 1232 * disable output on those pins. This enables to inject the 1233 * reference clock through CLKX/CLKR. For this to work 1234 * set_dai_sysclk() _needs_ to be called after set_dai_fmt(). 1235 */ 1236 regs->pcr0 &= ~CLKXM; 1237 break; 1238 case OMAP_MCBSP_SYSCLK_CLKR_EXT: 1239 regs->pcr0 |= SCLKME; 1240 /* Disable ouput on CLKR pin in master mode */ 1241 regs->pcr0 &= ~CLKRM; 1242 break; 1243 default: 1244 err = -ENODEV; 1245 } 1246 1247 return err; 1248 } 1249 1250 static int omap_mcbsp_probe(struct snd_soc_dai *dai) 1251 { 1252 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(dai); 1253 1254 pm_runtime_enable(mcbsp->dev); 1255 1256 snd_soc_dai_init_dma_data(dai, 1257 &mcbsp->dma_data[SNDRV_PCM_STREAM_PLAYBACK], 1258 &mcbsp->dma_data[SNDRV_PCM_STREAM_CAPTURE]); 1259 1260 return 0; 1261 } 1262 1263 static int omap_mcbsp_remove(struct snd_soc_dai *dai) 1264 { 1265 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(dai); 1266 1267 pm_runtime_disable(mcbsp->dev); 1268 1269 return 0; 1270 } 1271 1272 static const struct snd_soc_dai_ops mcbsp_dai_ops = { 1273 .probe = omap_mcbsp_probe, 1274 .remove = omap_mcbsp_remove, 1275 .startup = omap_mcbsp_dai_startup, 1276 .shutdown = omap_mcbsp_dai_shutdown, 1277 .prepare = omap_mcbsp_dai_prepare, 1278 .trigger = omap_mcbsp_dai_trigger, 1279 .delay = omap_mcbsp_dai_delay, 1280 .hw_params = omap_mcbsp_dai_hw_params, 1281 .set_fmt = omap_mcbsp_dai_set_dai_fmt, 1282 .set_clkdiv = omap_mcbsp_dai_set_clkdiv, 1283 .set_sysclk = omap_mcbsp_dai_set_dai_sysclk, 1284 }; 1285 1286 static struct snd_soc_dai_driver omap_mcbsp_dai = { 1287 .playback = { 1288 .channels_min = 1, 1289 .channels_max = 16, 1290 .rates = OMAP_MCBSP_RATES, 1291 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE, 1292 }, 1293 .capture = { 1294 .channels_min = 1, 1295 .channels_max = 16, 1296 .rates = OMAP_MCBSP_RATES, 1297 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE, 1298 }, 1299 .ops = &mcbsp_dai_ops, 1300 }; 1301 1302 static const struct snd_soc_component_driver omap_mcbsp_component = { 1303 .name = "omap-mcbsp", 1304 .legacy_dai_naming = 1, 1305 }; 1306 1307 static struct omap_mcbsp_platform_data omap2420_pdata = { 1308 .reg_step = 4, 1309 .reg_size = 2, 1310 }; 1311 1312 static struct omap_mcbsp_platform_data omap2430_pdata = { 1313 .reg_step = 4, 1314 .reg_size = 4, 1315 .has_ccr = true, 1316 }; 1317 1318 static struct omap_mcbsp_platform_data omap3_pdata = { 1319 .reg_step = 4, 1320 .reg_size = 4, 1321 .has_ccr = true, 1322 .has_wakeup = true, 1323 }; 1324 1325 static struct omap_mcbsp_platform_data omap4_pdata = { 1326 .reg_step = 4, 1327 .reg_size = 4, 1328 .has_ccr = true, 1329 .has_wakeup = true, 1330 }; 1331 1332 static const struct of_device_id omap_mcbsp_of_match[] = { 1333 { 1334 .compatible = "ti,omap2420-mcbsp", 1335 .data = &omap2420_pdata, 1336 }, 1337 { 1338 .compatible = "ti,omap2430-mcbsp", 1339 .data = &omap2430_pdata, 1340 }, 1341 { 1342 .compatible = "ti,omap3-mcbsp", 1343 .data = &omap3_pdata, 1344 }, 1345 { 1346 .compatible = "ti,omap4-mcbsp", 1347 .data = &omap4_pdata, 1348 }, 1349 { }, 1350 }; 1351 MODULE_DEVICE_TABLE(of, omap_mcbsp_of_match); 1352 1353 static int asoc_mcbsp_probe(struct platform_device *pdev) 1354 { 1355 struct omap_mcbsp_platform_data *pdata = dev_get_platdata(&pdev->dev); 1356 const struct omap_mcbsp_platform_data *match_pdata = 1357 device_get_match_data(&pdev->dev); 1358 struct omap_mcbsp *mcbsp; 1359 int ret; 1360 1361 if (match_pdata) { 1362 struct device_node *node = pdev->dev.of_node; 1363 struct omap_mcbsp_platform_data *pdata_quirk = pdata; 1364 int buffer_size; 1365 1366 pdata = devm_kmemdup(&pdev->dev, match_pdata, 1367 sizeof(struct omap_mcbsp_platform_data), 1368 GFP_KERNEL); 1369 if (!pdata) 1370 return -ENOMEM; 1371 1372 if (!of_property_read_u32(node, "ti,buffer-size", &buffer_size)) 1373 pdata->buffer_size = buffer_size; 1374 if (pdata_quirk) 1375 pdata->force_ick_on = pdata_quirk->force_ick_on; 1376 } else if (!pdata) { 1377 dev_err(&pdev->dev, "missing platform data.\n"); 1378 return -EINVAL; 1379 } 1380 mcbsp = devm_kzalloc(&pdev->dev, sizeof(struct omap_mcbsp), GFP_KERNEL); 1381 if (!mcbsp) 1382 return -ENOMEM; 1383 1384 mcbsp->id = pdev->id; 1385 mcbsp->pdata = pdata; 1386 mcbsp->dev = &pdev->dev; 1387 platform_set_drvdata(pdev, mcbsp); 1388 1389 ret = omap_mcbsp_init(pdev); 1390 if (ret) 1391 return ret; 1392 1393 if (mcbsp->pdata->reg_size == 2) { 1394 omap_mcbsp_dai.playback.formats = SNDRV_PCM_FMTBIT_S16_LE; 1395 omap_mcbsp_dai.capture.formats = SNDRV_PCM_FMTBIT_S16_LE; 1396 } 1397 1398 ret = devm_snd_soc_register_component(&pdev->dev, 1399 &omap_mcbsp_component, 1400 &omap_mcbsp_dai, 1); 1401 if (ret) 1402 return ret; 1403 1404 return sdma_pcm_platform_register(&pdev->dev, "tx", "rx"); 1405 } 1406 1407 static void asoc_mcbsp_remove(struct platform_device *pdev) 1408 { 1409 struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev); 1410 1411 if (mcbsp->pdata->ops && mcbsp->pdata->ops->free) 1412 mcbsp->pdata->ops->free(mcbsp->id); 1413 1414 if (cpu_latency_qos_request_active(&mcbsp->pm_qos_req)) 1415 cpu_latency_qos_remove_request(&mcbsp->pm_qos_req); 1416 } 1417 1418 static struct platform_driver asoc_mcbsp_driver = { 1419 .driver = { 1420 .name = "omap-mcbsp", 1421 .of_match_table = omap_mcbsp_of_match, 1422 }, 1423 1424 .probe = asoc_mcbsp_probe, 1425 .remove = asoc_mcbsp_remove, 1426 }; 1427 1428 module_platform_driver(asoc_mcbsp_driver); 1429 1430 MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@bitmer.com>"); 1431 MODULE_DESCRIPTION("OMAP I2S SoC Interface"); 1432 MODULE_LICENSE("GPL"); 1433 MODULE_ALIAS("platform:omap-mcbsp"); 1434