1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Analog Devices AD9739a SPI DAC driver
4 *
5 * Copyright 2015-2024 Analog Devices Inc.
6 */
7 #include <linux/bitfield.h>
8 #include <linux/bits.h>
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/device.h>
12 #include <linux/err.h>
13 #include <linux/errno.h>
14 #include <linux/gpio/consumer.h>
15 #include <linux/minmax.h>
16 #include <linux/module.h>
17 #include <linux/property.h>
18 #include <linux/regmap.h>
19 #include <linux/spi/spi.h>
20 #include <linux/units.h>
21
22 #include <linux/iio/backend.h>
23 #include <linux/iio/iio.h>
24 #include <linux/iio/types.h>
25
26 #define AD9739A_REG_MODE 0
27 #define AD9739A_RESET_MASK BIT(5)
28 #define AD9739A_REG_FSC_1 0x06
29 #define AD9739A_REG_FSC_2 0x07
30 #define AD9739A_FSC_MSB GENMASK(1, 0)
31 #define AD9739A_REG_DEC_CNT 0x8
32 #define AD9739A_NORMAL_MODE 0
33 #define AD9739A_MIXED_MODE 2
34 #define AD9739A_DAC_DEC GENMASK(1, 0)
35 #define AD9739A_REG_LVDS_REC_CNT1 0x10
36 #define AD9739A_RCVR_LOOP_EN_MASK GENMASK(1, 0)
37 #define AD9739A_REG_LVDS_REC_CNT4 0x13
38 #define AD9739A_FINE_DEL_SKW_MASK GENMASK(3, 0)
39 #define AD9739A_REG_LVDS_REC_STAT9 0x21
40 #define AD9739A_RCVR_TRACK_AND_LOCK (BIT(3) | BIT(0))
41 #define AD9739A_REG_CROSS_CNT1 0x22
42 #define AD9739A_REG_CROSS_CNT2 0x23
43 #define AD9739A_REG_PHS_DET 0x24
44 #define AD9739A_REG_MU_DUTY 0x25
45 #define AD9739A_REG_MU_CNT1 0x26
46 #define AD9739A_MU_EN_MASK BIT(0)
47 #define AD9739A_MU_GAIN_MASK BIT(1)
48 #define AD9739A_REG_MU_CNT2 0x27
49 #define AD9739A_REG_MU_CNT3 0x28
50 #define AD9739A_REG_MU_CNT4 0x29
51 #define AD9739A_MU_CNT4_DEFAULT 0xcb
52 #define AD9739A_REG_MU_STAT1 0x2A
53 #define AD9739A_MU_LOCK_MASK BIT(0)
54 #define AD9739A_REG_ANA_CNT_1 0x32
55 #define AD9739A_REG_ID 0x35
56
57 #define AD9739A_ID 0x24
58 #define AD9739A_REG_IS_RESERVED(reg) \
59 ((reg) == 0x5 || (reg) == 0x9 || (reg) == 0x0E || (reg) == 0x0D || \
60 (reg) == 0x2B || (reg) == 0x2C || (reg) == 0x34)
61
62 #define AD9739A_FSC_MIN 8580
63 #define AD9739A_FSC_MAX 31700
64 #define AD9739A_FSC_RANGE (AD9739A_FSC_MAX - AD9739A_FSC_MIN + 1)
65
66 #define AD9739A_MIN_DAC_CLK (1600 * MEGA)
67 #define AD9739A_MAX_DAC_CLK (2500 * MEGA)
68 #define AD9739A_DAC_CLK_RANGE (AD9739A_MAX_DAC_CLK - AD9739A_MIN_DAC_CLK + 1)
69 /* as recommended by the datasheet */
70 #define AD9739A_LOCK_N_TRIES 3
71
72 struct ad9739a_state {
73 struct iio_backend *back;
74 struct regmap *regmap;
75 unsigned long sample_rate;
76 };
77
ad9739a_oper_mode_get(struct iio_dev * indio_dev,const struct iio_chan_spec * chan)78 static int ad9739a_oper_mode_get(struct iio_dev *indio_dev,
79 const struct iio_chan_spec *chan)
80 {
81 struct ad9739a_state *st = iio_priv(indio_dev);
82 u32 mode;
83 int ret;
84
85 ret = regmap_read(st->regmap, AD9739A_REG_DEC_CNT, &mode);
86 if (ret)
87 return ret;
88
89 mode = FIELD_GET(AD9739A_DAC_DEC, mode);
90 /* sanity check we get valid values from the HW */
91 if (mode != AD9739A_NORMAL_MODE && mode != AD9739A_MIXED_MODE)
92 return -EIO;
93 if (!mode)
94 return AD9739A_NORMAL_MODE;
95
96 /*
97 * We get 2 from the device but for IIO modes, that means 1. Hence the
98 * minus 1.
99 */
100 return AD9739A_MIXED_MODE - 1;
101 }
102
ad9739a_oper_mode_set(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,u32 mode)103 static int ad9739a_oper_mode_set(struct iio_dev *indio_dev,
104 const struct iio_chan_spec *chan, u32 mode)
105 {
106 struct ad9739a_state *st = iio_priv(indio_dev);
107
108 /*
109 * On the IIO interface we have 0 and 1 for mode. But for mixed_mode, we
110 * need to write 2 in the device. That's what the below check is about.
111 */
112 if (mode == AD9739A_MIXED_MODE - 1)
113 mode = AD9739A_MIXED_MODE;
114
115 return regmap_update_bits(st->regmap, AD9739A_REG_DEC_CNT,
116 AD9739A_DAC_DEC, mode);
117 }
118
ad9739a_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)119 static int ad9739a_read_raw(struct iio_dev *indio_dev,
120 struct iio_chan_spec const *chan,
121 int *val, int *val2, long mask)
122 {
123 struct ad9739a_state *st = iio_priv(indio_dev);
124
125 switch (mask) {
126 case IIO_CHAN_INFO_SAMP_FREQ:
127 *val = st->sample_rate;
128 *val2 = 0;
129 return IIO_VAL_INT_64;
130 default:
131 return -EINVAL;
132 }
133 }
134
ad9739a_buffer_preenable(struct iio_dev * indio_dev)135 static int ad9739a_buffer_preenable(struct iio_dev *indio_dev)
136 {
137 struct ad9739a_state *st = iio_priv(indio_dev);
138
139 return iio_backend_data_source_set(st->back, 0, IIO_BACKEND_EXTERNAL);
140 }
141
ad9739a_buffer_postdisable(struct iio_dev * indio_dev)142 static int ad9739a_buffer_postdisable(struct iio_dev *indio_dev)
143 {
144 struct ad9739a_state *st = iio_priv(indio_dev);
145
146 return iio_backend_data_source_set(st->back, 0,
147 IIO_BACKEND_INTERNAL_CONTINUOUS_WAVE);
148 }
149
ad9739a_reg_accessible(struct device * dev,unsigned int reg)150 static bool ad9739a_reg_accessible(struct device *dev, unsigned int reg)
151 {
152 if (AD9739A_REG_IS_RESERVED(reg))
153 return false;
154 if (reg > AD9739A_REG_MU_STAT1 && reg < AD9739A_REG_ANA_CNT_1)
155 return false;
156
157 return true;
158 }
159
ad9739a_reset(struct device * dev,const struct ad9739a_state * st)160 static int ad9739a_reset(struct device *dev, const struct ad9739a_state *st)
161 {
162 struct gpio_desc *gpio;
163 int ret;
164
165 gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
166 if (IS_ERR(gpio))
167 return PTR_ERR(gpio);
168 if (gpio) {
169 /* minimum pulse width of 40ns */
170 ndelay(40);
171 gpiod_set_value_cansleep(gpio, 0);
172 return 0;
173 }
174
175 /* bring all registers to their default state */
176 ret = regmap_set_bits(st->regmap, AD9739A_REG_MODE, AD9739A_RESET_MASK);
177 if (ret)
178 return ret;
179
180 ndelay(40);
181
182 return regmap_clear_bits(st->regmap, AD9739A_REG_MODE,
183 AD9739A_RESET_MASK);
184 }
185
186 /*
187 * Recommended values (as per datasheet) for the dac clk common mode voltage
188 * and Mu controller. Look at table 29.
189 */
190 static const struct reg_sequence ad9739a_clk_mu_ctrl[] = {
191 /* DAC clk common mode voltage */
192 { AD9739A_REG_CROSS_CNT1, 0x0f },
193 { AD9739A_REG_CROSS_CNT2, 0x0f },
194 /* Mu controller configuration */
195 { AD9739A_REG_PHS_DET, 0x30 },
196 { AD9739A_REG_MU_DUTY, 0x80 },
197 { AD9739A_REG_MU_CNT2, 0x44 },
198 { AD9739A_REG_MU_CNT3, 0x6c },
199 };
200
ad9739a_init(struct device * dev,const struct ad9739a_state * st)201 static int ad9739a_init(struct device *dev, const struct ad9739a_state *st)
202 {
203 unsigned int i = 0, lock, fsc;
204 u32 fsc_raw;
205 int ret;
206
207 ret = regmap_multi_reg_write(st->regmap, ad9739a_clk_mu_ctrl,
208 ARRAY_SIZE(ad9739a_clk_mu_ctrl));
209 if (ret)
210 return ret;
211
212 /*
213 * Try to get the Mu lock. Repeat the below steps AD9739A_LOCK_N_TRIES
214 * (as specified by the datasheet) until we get the lock.
215 */
216 do {
217 ret = regmap_write(st->regmap, AD9739A_REG_MU_CNT4,
218 AD9739A_MU_CNT4_DEFAULT);
219 if (ret)
220 return ret;
221
222 /* Enable the Mu controller search and track mode. */
223 ret = regmap_write(st->regmap, AD9739A_REG_MU_CNT1,
224 AD9739A_MU_EN_MASK | AD9739A_MU_GAIN_MASK);
225 if (ret)
226 return ret;
227
228 /* Ensure the DLL loop is locked */
229 ret = regmap_read_poll_timeout(st->regmap, AD9739A_REG_MU_STAT1,
230 lock, lock & AD9739A_MU_LOCK_MASK,
231 0, 1000);
232 if (ret && ret != -ETIMEDOUT)
233 return ret;
234 } while (ret && ++i < AD9739A_LOCK_N_TRIES);
235
236 if (i == AD9739A_LOCK_N_TRIES)
237 return dev_err_probe(dev, ret, "Mu lock timeout\n");
238
239 /* Receiver tracking and lock. Same deal as the Mu controller */
240 i = 0;
241 do {
242 ret = regmap_update_bits(st->regmap, AD9739A_REG_LVDS_REC_CNT4,
243 AD9739A_FINE_DEL_SKW_MASK,
244 FIELD_PREP(AD9739A_FINE_DEL_SKW_MASK, 2));
245 if (ret)
246 return ret;
247
248 /* Disable the receiver and the loop. */
249 ret = regmap_write(st->regmap, AD9739A_REG_LVDS_REC_CNT1, 0);
250 if (ret)
251 return ret;
252
253 /*
254 * Re-enable the loop so it falls out of lock and begins the
255 * search/track routine again.
256 */
257 ret = regmap_set_bits(st->regmap, AD9739A_REG_LVDS_REC_CNT1,
258 AD9739A_RCVR_LOOP_EN_MASK);
259 if (ret)
260 return ret;
261
262 /* Ensure the DLL loop is locked */
263 ret = regmap_read_poll_timeout(st->regmap,
264 AD9739A_REG_LVDS_REC_STAT9, lock,
265 lock == AD9739A_RCVR_TRACK_AND_LOCK,
266 0, 1000);
267 if (ret && ret != -ETIMEDOUT)
268 return ret;
269 } while (ret && ++i < AD9739A_LOCK_N_TRIES);
270
271 if (i == AD9739A_LOCK_N_TRIES)
272 return dev_err_probe(dev, ret, "Receiver lock timeout\n");
273
274 ret = device_property_read_u32(dev, "adi,full-scale-microamp", &fsc);
275 if (ret && ret == -EINVAL)
276 return 0;
277 if (ret)
278 return ret;
279 if (!in_range(fsc, AD9739A_FSC_MIN, AD9739A_FSC_RANGE))
280 return dev_err_probe(dev, -EINVAL,
281 "Invalid full scale current(%u) [%u %u]\n",
282 fsc, AD9739A_FSC_MIN, AD9739A_FSC_MAX);
283 /*
284 * IOUTFS is given by
285 * Ioutfs = 0.0226 * FSC + 8.58
286 * and is given in mA. Hence we'll have to multiply by 10 * MILLI in
287 * order to get rid of the fractional.
288 */
289 fsc_raw = DIV_ROUND_CLOSEST(fsc * 10 - 85800, 226);
290
291 ret = regmap_write(st->regmap, AD9739A_REG_FSC_1, fsc_raw & 0xff);
292 if (ret)
293 return ret;
294
295 return regmap_update_bits(st->regmap, AD9739A_REG_FSC_2,
296 AD9739A_FSC_MSB, fsc_raw >> 8);
297 }
298
299 static const char * const ad9739a_modes_avail[] = { "normal", "mixed-mode" };
300
301 static const struct iio_enum ad9739a_modes = {
302 .items = ad9739a_modes_avail,
303 .num_items = ARRAY_SIZE(ad9739a_modes_avail),
304 .get = ad9739a_oper_mode_get,
305 .set = ad9739a_oper_mode_set,
306 };
307
308 static const struct iio_chan_spec_ext_info ad9739a_ext_info[] = {
309 IIO_ENUM_AVAILABLE("operating_mode", IIO_SEPARATE, &ad9739a_modes),
310 IIO_ENUM("operating_mode", IIO_SEPARATE, &ad9739a_modes),
311 { }
312 };
313
314 /*
315 * The reason for having two different channels is because we have, in reality,
316 * two sources of data:
317 * ALTVOLTAGE: It's a Continuous Wave that's internally generated by the
318 * backend device.
319 * VOLTAGE: It's the typical data we can have in a DAC device and the source
320 * of it has nothing to do with the backend. The backend will only
321 * forward it into our data interface to be sent out.
322 */
323 static struct iio_chan_spec ad9739a_channels[] = {
324 {
325 .type = IIO_ALTVOLTAGE,
326 .indexed = 1,
327 .output = 1,
328 .scan_index = -1,
329 },
330 {
331 .type = IIO_VOLTAGE,
332 .indexed = 1,
333 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
334 .output = 1,
335 .ext_info = ad9739a_ext_info,
336 .scan_type = {
337 .sign = 's',
338 .storagebits = 16,
339 .realbits = 16,
340 },
341 }
342 };
343
344 static const struct iio_info ad9739a_info = {
345 .read_raw = ad9739a_read_raw,
346 };
347
348 static const struct iio_buffer_setup_ops ad9739a_buffer_setup_ops = {
349 .preenable = &ad9739a_buffer_preenable,
350 .postdisable = &ad9739a_buffer_postdisable,
351 };
352
353 static const struct regmap_config ad9739a_regmap_config = {
354 .reg_bits = 8,
355 .val_bits = 8,
356 .readable_reg = ad9739a_reg_accessible,
357 .writeable_reg = ad9739a_reg_accessible,
358 .max_register = AD9739A_REG_ID,
359 };
360
ad9739a_probe(struct spi_device * spi)361 static int ad9739a_probe(struct spi_device *spi)
362 {
363 struct device *dev = &spi->dev;
364 struct iio_dev *indio_dev;
365 struct ad9739a_state *st;
366 unsigned int id;
367 struct clk *clk;
368 int ret;
369
370 indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
371 if (!indio_dev)
372 return -ENOMEM;
373
374 st = iio_priv(indio_dev);
375
376 clk = devm_clk_get_enabled(dev, NULL);
377 if (IS_ERR(clk))
378 return dev_err_probe(dev, PTR_ERR(clk), "Could not get clkin\n");
379
380 st->sample_rate = clk_get_rate(clk);
381 if (!in_range(st->sample_rate, AD9739A_MIN_DAC_CLK,
382 AD9739A_DAC_CLK_RANGE))
383 return dev_err_probe(dev, -EINVAL,
384 "Invalid dac clk range(%lu) [%lu %lu]\n",
385 st->sample_rate, AD9739A_MIN_DAC_CLK,
386 AD9739A_MAX_DAC_CLK);
387
388 st->regmap = devm_regmap_init_spi(spi, &ad9739a_regmap_config);
389 if (IS_ERR(st->regmap))
390 return PTR_ERR(st->regmap);
391
392 ret = regmap_read(st->regmap, AD9739A_REG_ID, &id);
393 if (ret)
394 return ret;
395
396 if (id != AD9739A_ID)
397 dev_warn(dev, "Unrecognized CHIP_ID 0x%X", id);
398
399 ret = ad9739a_reset(dev, st);
400 if (ret)
401 return ret;
402
403 ret = ad9739a_init(dev, st);
404 if (ret)
405 return ret;
406
407 st->back = devm_iio_backend_get(dev, NULL);
408 if (IS_ERR(st->back))
409 return PTR_ERR(st->back);
410
411 ret = devm_iio_backend_request_buffer(dev, st->back, indio_dev);
412 if (ret)
413 return ret;
414
415 ret = iio_backend_extend_chan_spec(st->back, &ad9739a_channels[0]);
416 if (ret)
417 return ret;
418
419 ret = iio_backend_set_sampling_freq(st->back, 0, st->sample_rate);
420 if (ret)
421 return ret;
422
423 ret = devm_iio_backend_enable(dev, st->back);
424 if (ret)
425 return ret;
426
427 indio_dev->name = "ad9739a";
428 indio_dev->info = &ad9739a_info;
429 indio_dev->channels = ad9739a_channels;
430 indio_dev->num_channels = ARRAY_SIZE(ad9739a_channels);
431 indio_dev->setup_ops = &ad9739a_buffer_setup_ops;
432
433 ret = devm_iio_device_register(&spi->dev, indio_dev);
434 if (ret)
435 return ret;
436
437 iio_backend_debugfs_add(st->back, indio_dev);
438
439 return 0;
440 }
441
442 static const struct of_device_id ad9739a_of_match[] = {
443 { .compatible = "adi,ad9739a" },
444 { }
445 };
446 MODULE_DEVICE_TABLE(of, ad9739a_of_match);
447
448 static const struct spi_device_id ad9739a_id[] = {
449 { .name = "ad9739a" },
450 { }
451 };
452 MODULE_DEVICE_TABLE(spi, ad9739a_id);
453
454 static struct spi_driver ad9739a_driver = {
455 .driver = {
456 .name = "ad9739a",
457 .of_match_table = ad9739a_of_match,
458 },
459 .probe = ad9739a_probe,
460 .id_table = ad9739a_id,
461 };
462 module_spi_driver(ad9739a_driver);
463
464 MODULE_AUTHOR("Dragos Bogdan <dragos.bogdan@analog.com>");
465 MODULE_AUTHOR("Nuno Sa <nuno.sa@analog.com>");
466 MODULE_DESCRIPTION("Analog Devices AD9739 DAC");
467 MODULE_LICENSE("GPL");
468 MODULE_IMPORT_NS("IIO_BACKEND");
469