1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * AD7606 SPI ADC driver
4 *
5 * Copyright 2011 Analog Devices Inc.
6 */
7
8 #include <linux/cleanup.h>
9 #include <linux/delay.h>
10 #include <linux/device.h>
11 #include <linux/err.h>
12 #include <linux/gpio/consumer.h>
13 #include <linux/interrupt.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/mutex.h>
17 #include <linux/property.h>
18 #include <linux/pwm.h>
19 #include <linux/regulator/consumer.h>
20 #include <linux/sched.h>
21 #include <linux/slab.h>
22 #include <linux/sysfs.h>
23 #include <linux/units.h>
24 #include <linux/util_macros.h>
25
26 #include <linux/iio/backend.h>
27 #include <linux/iio/buffer.h>
28 #include <linux/iio/iio.h>
29 #include <linux/iio/sysfs.h>
30 #include <linux/iio/trigger.h>
31 #include <linux/iio/triggered_buffer.h>
32 #include <linux/iio/trigger_consumer.h>
33
34 #include "ad7606.h"
35
36 /*
37 * Scales are computed as 5000/32768 and 10000/32768 respectively,
38 * so that when applied to the raw values they provide mV values.
39 * The scale arrays are kept as IIO_VAL_INT_PLUS_MICRO, so index
40 * X is the integer part and X + 1 is the fractional part.
41 */
42 static const unsigned int ad7606_16bit_hw_scale_avail[2][2] = {
43 { 0, 152588 }, { 0, 305176 }
44 };
45
46 static const unsigned int ad7606_18bit_hw_scale_avail[2][2] = {
47 { 0, 38147 }, { 0, 76294 }
48 };
49
50 static const unsigned int ad7606c_16bit_single_ended_unipolar_scale_avail[3][2] = {
51 { 0, 76294 }, { 0, 152588 }, { 0, 190735 }
52 };
53
54 static const unsigned int ad7606c_16bit_single_ended_bipolar_scale_avail[5][2] = {
55 { 0, 76294 }, { 0, 152588 }, { 0, 190735 }, { 0, 305176 }, { 0, 381470 }
56 };
57
58 static const unsigned int ad7606c_16bit_differential_bipolar_scale_avail[4][2] = {
59 { 0, 152588 }, { 0, 305176 }, { 0, 381470 }, { 0, 610352 }
60 };
61
62 static const unsigned int ad7606c_18bit_single_ended_unipolar_scale_avail[3][2] = {
63 { 0, 19073 }, { 0, 38147 }, { 0, 47684 }
64 };
65
66 static const unsigned int ad7606c_18bit_single_ended_bipolar_scale_avail[5][2] = {
67 { 0, 19073 }, { 0, 38147 }, { 0, 47684 }, { 0, 76294 }, { 0, 95367 }
68 };
69
70 static const unsigned int ad7606c_18bit_differential_bipolar_scale_avail[4][2] = {
71 { 0, 38147 }, { 0, 76294 }, { 0, 95367 }, { 0, 152588 }
72 };
73
74 static const unsigned int ad7606_16bit_sw_scale_avail[3][2] = {
75 { 0, 76293 }, { 0, 152588 }, { 0, 305176 }
76 };
77
78 static const unsigned int ad7607_hw_scale_avail[2][2] = {
79 { 0, 610352 }, { 1, 220703 }
80 };
81
82 static const unsigned int ad7609_hw_scale_avail[2][2] = {
83 { 0, 152588 }, { 0, 305176 }
84 };
85
86 static const unsigned int ad7606_oversampling_avail[7] = {
87 1, 2, 4, 8, 16, 32, 64,
88 };
89
90 static const unsigned int ad7606b_oversampling_avail[9] = {
91 1, 2, 4, 8, 16, 32, 64, 128, 256,
92 };
93
94 static const unsigned int ad7616_oversampling_avail[8] = {
95 1, 2, 4, 8, 16, 32, 64, 128,
96 };
97
98 static int ad7606c_18bit_chan_scale_setup(struct iio_dev *indio_dev,
99 struct iio_chan_spec *chan);
100 static int ad7606c_16bit_chan_scale_setup(struct iio_dev *indio_dev,
101 struct iio_chan_spec *chan);
102 static int ad7606_16bit_chan_scale_setup(struct iio_dev *indio_dev,
103 struct iio_chan_spec *chan);
104 static int ad7607_chan_scale_setup(struct iio_dev *indio_dev,
105 struct iio_chan_spec *chan);
106 static int ad7608_chan_scale_setup(struct iio_dev *indio_dev,
107 struct iio_chan_spec *chan);
108 static int ad7609_chan_scale_setup(struct iio_dev *indio_dev,
109 struct iio_chan_spec *chan);
110 static int ad7616_sw_mode_setup(struct iio_dev *indio_dev);
111 static int ad7606b_sw_mode_setup(struct iio_dev *indio_dev);
112
113 const struct ad7606_chip_info ad7605_4_info = {
114 .max_samplerate = 300 * KILO,
115 .name = "ad7605-4",
116 .bits = 16,
117 .num_adc_channels = 4,
118 .scale_setup_cb = ad7606_16bit_chan_scale_setup,
119 };
120 EXPORT_SYMBOL_NS_GPL(ad7605_4_info, "IIO_AD7606");
121
122 const struct ad7606_chip_info ad7606_8_info = {
123 .max_samplerate = 200 * KILO,
124 .name = "ad7606-8",
125 .bits = 16,
126 .num_adc_channels = 8,
127 .oversampling_avail = ad7606_oversampling_avail,
128 .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail),
129 .scale_setup_cb = ad7606_16bit_chan_scale_setup,
130 };
131 EXPORT_SYMBOL_NS_GPL(ad7606_8_info, "IIO_AD7606");
132
133 const struct ad7606_chip_info ad7606_6_info = {
134 .max_samplerate = 200 * KILO,
135 .name = "ad7606-6",
136 .bits = 16,
137 .num_adc_channels = 6,
138 .oversampling_avail = ad7606_oversampling_avail,
139 .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail),
140 .scale_setup_cb = ad7606_16bit_chan_scale_setup,
141 .offload_storagebits = 32,
142 };
143 EXPORT_SYMBOL_NS_GPL(ad7606_6_info, "IIO_AD7606");
144
145 const struct ad7606_chip_info ad7606_4_info = {
146 .max_samplerate = 200 * KILO,
147 .name = "ad7606-4",
148 .bits = 16,
149 .num_adc_channels = 4,
150 .oversampling_avail = ad7606_oversampling_avail,
151 .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail),
152 .scale_setup_cb = ad7606_16bit_chan_scale_setup,
153 .offload_storagebits = 32,
154 };
155 EXPORT_SYMBOL_NS_GPL(ad7606_4_info, "IIO_AD7606");
156
157 const struct ad7606_chip_info ad7606b_info = {
158 .max_samplerate = 800 * KILO,
159 .name = "ad7606b",
160 .bits = 16,
161 .num_adc_channels = 8,
162 .oversampling_avail = ad7606_oversampling_avail,
163 .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail),
164 .scale_setup_cb = ad7606_16bit_chan_scale_setup,
165 .sw_setup_cb = ad7606b_sw_mode_setup,
166 .offload_storagebits = 32,
167 };
168 EXPORT_SYMBOL_NS_GPL(ad7606b_info, "IIO_AD7606");
169
170 const struct ad7606_chip_info ad7606c_16_info = {
171 .max_samplerate = 1 * MEGA,
172 .name = "ad7606c16",
173 .bits = 16,
174 .num_adc_channels = 8,
175 .oversampling_avail = ad7606_oversampling_avail,
176 .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail),
177 .scale_setup_cb = ad7606c_16bit_chan_scale_setup,
178 .sw_setup_cb = ad7606b_sw_mode_setup,
179 .offload_storagebits = 32,
180 };
181 EXPORT_SYMBOL_NS_GPL(ad7606c_16_info, "IIO_AD7606");
182
183 const struct ad7606_chip_info ad7607_info = {
184 .max_samplerate = 200 * KILO,
185 .name = "ad7607",
186 .bits = 14,
187 .num_adc_channels = 8,
188 .oversampling_avail = ad7606_oversampling_avail,
189 .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail),
190 .scale_setup_cb = ad7607_chan_scale_setup,
191 .offload_storagebits = 32,
192 };
193 EXPORT_SYMBOL_NS_GPL(ad7607_info, "IIO_AD7606");
194
195 const struct ad7606_chip_info ad7608_info = {
196 .max_samplerate = 200 * KILO,
197 .name = "ad7608",
198 .bits = 18,
199 .num_adc_channels = 8,
200 .oversampling_avail = ad7606_oversampling_avail,
201 .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail),
202 .scale_setup_cb = ad7608_chan_scale_setup,
203 .offload_storagebits = 32,
204 };
205 EXPORT_SYMBOL_NS_GPL(ad7608_info, "IIO_AD7606");
206
207 const struct ad7606_chip_info ad7609_info = {
208 .max_samplerate = 200 * KILO,
209 .name = "ad7609",
210 .bits = 18,
211 .num_adc_channels = 8,
212 .oversampling_avail = ad7606_oversampling_avail,
213 .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail),
214 .scale_setup_cb = ad7609_chan_scale_setup,
215 .offload_storagebits = 32,
216 };
217 EXPORT_SYMBOL_NS_GPL(ad7609_info, "IIO_AD7606");
218
219 const struct ad7606_chip_info ad7606c_18_info = {
220 .max_samplerate = 1 * MEGA,
221 .name = "ad7606c18",
222 .bits = 18,
223 .num_adc_channels = 8,
224 .oversampling_avail = ad7606_oversampling_avail,
225 .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail),
226 .scale_setup_cb = ad7606c_18bit_chan_scale_setup,
227 .sw_setup_cb = ad7606b_sw_mode_setup,
228 .offload_storagebits = 32,
229 };
230 EXPORT_SYMBOL_NS_GPL(ad7606c_18_info, "IIO_AD7606");
231
232 const struct ad7606_chip_info ad7616_info = {
233 .max_samplerate = 1 * MEGA,
234 .init_delay_ms = 15,
235 .name = "ad7616",
236 .bits = 16,
237 .num_adc_channels = 16,
238 .oversampling_avail = ad7616_oversampling_avail,
239 .oversampling_num = ARRAY_SIZE(ad7616_oversampling_avail),
240 .os_req_reset = true,
241 .scale_setup_cb = ad7606_16bit_chan_scale_setup,
242 .sw_setup_cb = ad7616_sw_mode_setup,
243 .offload_storagebits = 16,
244 };
245 EXPORT_SYMBOL_NS_GPL(ad7616_info, "IIO_AD7606");
246
ad7606_reset(struct ad7606_state * st)247 int ad7606_reset(struct ad7606_state *st)
248 {
249 if (st->gpio_reset) {
250 gpiod_set_value(st->gpio_reset, 1);
251 ndelay(100); /* t_reset >= 100ns */
252 gpiod_set_value(st->gpio_reset, 0);
253 return 0;
254 }
255
256 return -ENODEV;
257 }
258 EXPORT_SYMBOL_NS_GPL(ad7606_reset, "IIO_AD7606");
259
ad7606_16bit_chan_scale_setup(struct iio_dev * indio_dev,struct iio_chan_spec * chan)260 static int ad7606_16bit_chan_scale_setup(struct iio_dev *indio_dev,
261 struct iio_chan_spec *chan)
262 {
263 struct ad7606_state *st = iio_priv(indio_dev);
264 struct ad7606_chan_scale *cs = &st->chan_scales[chan->scan_index];
265
266 if (!st->sw_mode_en) {
267 /* tied to logic low, analog input range is +/- 5V */
268 cs->range = 0;
269 cs->scale_avail = ad7606_16bit_hw_scale_avail;
270 cs->num_scales = ARRAY_SIZE(ad7606_16bit_hw_scale_avail);
271 return 0;
272 }
273
274 /* Scale of 0.076293 is only available in sw mode */
275 /* After reset, in software mode, ±10 V is set by default */
276 cs->range = 2;
277 cs->scale_avail = ad7606_16bit_sw_scale_avail;
278 cs->num_scales = ARRAY_SIZE(ad7606_16bit_sw_scale_avail);
279
280 return 0;
281 }
282
ad7606_get_chan_config(struct iio_dev * indio_dev,int ch,bool * bipolar,bool * differential)283 static int ad7606_get_chan_config(struct iio_dev *indio_dev, int ch,
284 bool *bipolar, bool *differential)
285 {
286 struct ad7606_state *st = iio_priv(indio_dev);
287 unsigned int num_channels = st->chip_info->num_adc_channels;
288 struct device *dev = st->dev;
289 int ret;
290
291 *bipolar = false;
292 *differential = false;
293
294 device_for_each_child_node_scoped(dev, child) {
295 u32 pins[2];
296 int reg;
297
298 ret = fwnode_property_read_u32(child, "reg", ®);
299 if (ret)
300 continue;
301
302 /* channel number (here) is from 1 to num_channels */
303 if (reg < 1 || reg > num_channels) {
304 dev_warn(dev,
305 "Invalid channel number (ignoring): %d\n", reg);
306 continue;
307 }
308
309 if (reg != (ch + 1))
310 continue;
311
312 *bipolar = fwnode_property_read_bool(child, "bipolar");
313
314 ret = fwnode_property_read_u32_array(child, "diff-channels",
315 pins, ARRAY_SIZE(pins));
316 /* Channel is differential, if pins are the same as 'reg' */
317 if (ret == 0 && (pins[0] != reg || pins[1] != reg)) {
318 dev_err(dev,
319 "Differential pins must be the same as 'reg'");
320 return -EINVAL;
321 }
322
323 *differential = (ret == 0);
324
325 if (*differential && !*bipolar) {
326 dev_err(dev,
327 "'bipolar' must be added for diff channel %d\n",
328 reg);
329 return -EINVAL;
330 }
331
332 return 0;
333 }
334
335 return 0;
336 }
337
ad7606c_18bit_chan_scale_setup(struct iio_dev * indio_dev,struct iio_chan_spec * chan)338 static int ad7606c_18bit_chan_scale_setup(struct iio_dev *indio_dev,
339 struct iio_chan_spec *chan)
340 {
341 struct ad7606_state *st = iio_priv(indio_dev);
342 struct ad7606_chan_scale *cs = &st->chan_scales[chan->scan_index];
343 bool bipolar, differential;
344 int ret;
345
346 if (!st->sw_mode_en) {
347 cs->range = 0;
348 cs->scale_avail = ad7606_18bit_hw_scale_avail;
349 cs->num_scales = ARRAY_SIZE(ad7606_18bit_hw_scale_avail);
350 return 0;
351 }
352
353 ret = ad7606_get_chan_config(indio_dev, chan->scan_index, &bipolar,
354 &differential);
355 if (ret)
356 return ret;
357
358 if (differential) {
359 cs->scale_avail = ad7606c_18bit_differential_bipolar_scale_avail;
360 cs->num_scales =
361 ARRAY_SIZE(ad7606c_18bit_differential_bipolar_scale_avail);
362 /* Bipolar differential ranges start at 8 (b1000) */
363 cs->reg_offset = 8;
364 cs->range = 1;
365 chan->differential = 1;
366 chan->channel2 = chan->channel;
367
368 return 0;
369 }
370
371 chan->differential = 0;
372
373 if (bipolar) {
374 cs->scale_avail = ad7606c_18bit_single_ended_bipolar_scale_avail;
375 cs->num_scales =
376 ARRAY_SIZE(ad7606c_18bit_single_ended_bipolar_scale_avail);
377 /* Bipolar single-ended ranges start at 0 (b0000) */
378 cs->reg_offset = 0;
379 cs->range = 3;
380 chan->scan_type.sign = 's';
381
382 return 0;
383 }
384
385 cs->scale_avail = ad7606c_18bit_single_ended_unipolar_scale_avail;
386 cs->num_scales =
387 ARRAY_SIZE(ad7606c_18bit_single_ended_unipolar_scale_avail);
388 /* Unipolar single-ended ranges start at 5 (b0101) */
389 cs->reg_offset = 5;
390 cs->range = 1;
391 chan->scan_type.sign = 'u';
392
393 return 0;
394 }
395
ad7606c_16bit_chan_scale_setup(struct iio_dev * indio_dev,struct iio_chan_spec * chan)396 static int ad7606c_16bit_chan_scale_setup(struct iio_dev *indio_dev,
397 struct iio_chan_spec *chan)
398 {
399 struct ad7606_state *st = iio_priv(indio_dev);
400 struct ad7606_chan_scale *cs = &st->chan_scales[chan->scan_index];
401 bool bipolar, differential;
402 int ret;
403
404 if (!st->sw_mode_en) {
405 cs->range = 0;
406 cs->scale_avail = ad7606_16bit_hw_scale_avail;
407 cs->num_scales = ARRAY_SIZE(ad7606_16bit_hw_scale_avail);
408 return 0;
409 }
410
411 ret = ad7606_get_chan_config(indio_dev, chan->scan_index, &bipolar,
412 &differential);
413 if (ret)
414 return ret;
415
416 if (differential) {
417 cs->scale_avail = ad7606c_16bit_differential_bipolar_scale_avail;
418 cs->num_scales =
419 ARRAY_SIZE(ad7606c_16bit_differential_bipolar_scale_avail);
420 /* Bipolar differential ranges start at 8 (b1000) */
421 cs->reg_offset = 8;
422 cs->range = 1;
423 chan->differential = 1;
424 chan->channel2 = chan->channel;
425 chan->scan_type.sign = 's';
426
427 return 0;
428 }
429
430 chan->differential = 0;
431
432 if (bipolar) {
433 cs->scale_avail = ad7606c_16bit_single_ended_bipolar_scale_avail;
434 cs->num_scales =
435 ARRAY_SIZE(ad7606c_16bit_single_ended_bipolar_scale_avail);
436 /* Bipolar single-ended ranges start at 0 (b0000) */
437 cs->reg_offset = 0;
438 cs->range = 3;
439 chan->scan_type.sign = 's';
440
441 return 0;
442 }
443
444 cs->scale_avail = ad7606c_16bit_single_ended_unipolar_scale_avail;
445 cs->num_scales =
446 ARRAY_SIZE(ad7606c_16bit_single_ended_unipolar_scale_avail);
447 /* Unipolar single-ended ranges start at 5 (b0101) */
448 cs->reg_offset = 5;
449 cs->range = 1;
450 chan->scan_type.sign = 'u';
451
452 return 0;
453 }
454
ad7607_chan_scale_setup(struct iio_dev * indio_dev,struct iio_chan_spec * chan)455 static int ad7607_chan_scale_setup(struct iio_dev *indio_dev,
456 struct iio_chan_spec *chan)
457 {
458 struct ad7606_state *st = iio_priv(indio_dev);
459 struct ad7606_chan_scale *cs = &st->chan_scales[chan->scan_index];
460
461 cs->range = 0;
462 cs->scale_avail = ad7607_hw_scale_avail;
463 cs->num_scales = ARRAY_SIZE(ad7607_hw_scale_avail);
464 return 0;
465 }
466
ad7608_chan_scale_setup(struct iio_dev * indio_dev,struct iio_chan_spec * chan)467 static int ad7608_chan_scale_setup(struct iio_dev *indio_dev,
468 struct iio_chan_spec *chan)
469 {
470 struct ad7606_state *st = iio_priv(indio_dev);
471 struct ad7606_chan_scale *cs = &st->chan_scales[chan->scan_index];
472
473 cs->range = 0;
474 cs->scale_avail = ad7606_18bit_hw_scale_avail;
475 cs->num_scales = ARRAY_SIZE(ad7606_18bit_hw_scale_avail);
476 return 0;
477 }
478
ad7609_chan_scale_setup(struct iio_dev * indio_dev,struct iio_chan_spec * chan)479 static int ad7609_chan_scale_setup(struct iio_dev *indio_dev,
480 struct iio_chan_spec *chan)
481 {
482 struct ad7606_state *st = iio_priv(indio_dev);
483 struct ad7606_chan_scale *cs = &st->chan_scales[chan->scan_index];
484
485 cs->range = 0;
486 cs->scale_avail = ad7609_hw_scale_avail;
487 cs->num_scales = ARRAY_SIZE(ad7609_hw_scale_avail);
488 return 0;
489 }
490
ad7606_reg_access(struct iio_dev * indio_dev,unsigned int reg,unsigned int writeval,unsigned int * readval)491 static int ad7606_reg_access(struct iio_dev *indio_dev,
492 unsigned int reg,
493 unsigned int writeval,
494 unsigned int *readval)
495 {
496 struct ad7606_state *st = iio_priv(indio_dev);
497 int ret;
498
499 guard(mutex)(&st->lock);
500
501 if (readval) {
502 ret = st->bops->reg_read(st, reg);
503 if (ret < 0)
504 return ret;
505 *readval = ret;
506 return 0;
507 } else {
508 return st->bops->reg_write(st, reg, writeval);
509 }
510 }
511
ad7606_pwm_set_high(struct ad7606_state * st)512 static int ad7606_pwm_set_high(struct ad7606_state *st)
513 {
514 struct pwm_state cnvst_pwm_state;
515 int ret;
516
517 pwm_get_state(st->cnvst_pwm, &cnvst_pwm_state);
518 cnvst_pwm_state.enabled = true;
519 cnvst_pwm_state.duty_cycle = cnvst_pwm_state.period;
520
521 ret = pwm_apply_might_sleep(st->cnvst_pwm, &cnvst_pwm_state);
522
523 return ret;
524 }
525
ad7606_pwm_set_low(struct ad7606_state * st)526 int ad7606_pwm_set_low(struct ad7606_state *st)
527 {
528 struct pwm_state cnvst_pwm_state;
529 int ret;
530
531 pwm_get_state(st->cnvst_pwm, &cnvst_pwm_state);
532 cnvst_pwm_state.enabled = true;
533 cnvst_pwm_state.duty_cycle = 0;
534
535 ret = pwm_apply_might_sleep(st->cnvst_pwm, &cnvst_pwm_state);
536
537 return ret;
538 }
539 EXPORT_SYMBOL_NS_GPL(ad7606_pwm_set_low, "IIO_AD7606");
540
ad7606_pwm_set_swing(struct ad7606_state * st)541 int ad7606_pwm_set_swing(struct ad7606_state *st)
542 {
543 struct pwm_state cnvst_pwm_state;
544
545 pwm_get_state(st->cnvst_pwm, &cnvst_pwm_state);
546 cnvst_pwm_state.enabled = true;
547 cnvst_pwm_state.duty_cycle = cnvst_pwm_state.period / 2;
548
549 return pwm_apply_might_sleep(st->cnvst_pwm, &cnvst_pwm_state);
550 }
551 EXPORT_SYMBOL_NS_GPL(ad7606_pwm_set_swing, "IIO_AD7606");
552
ad7606_pwm_is_swinging(struct ad7606_state * st)553 static bool ad7606_pwm_is_swinging(struct ad7606_state *st)
554 {
555 struct pwm_state cnvst_pwm_state;
556
557 pwm_get_state(st->cnvst_pwm, &cnvst_pwm_state);
558
559 return cnvst_pwm_state.duty_cycle != cnvst_pwm_state.period &&
560 cnvst_pwm_state.duty_cycle != 0;
561 }
562
ad7606_set_sampling_freq(struct ad7606_state * st,unsigned long freq)563 static int ad7606_set_sampling_freq(struct ad7606_state *st, unsigned long freq)
564 {
565 struct pwm_state cnvst_pwm_state;
566 bool is_swinging = ad7606_pwm_is_swinging(st);
567 bool is_high;
568
569 if (freq == 0)
570 return -EINVAL;
571
572 /* Retrieve the previous state. */
573 pwm_get_state(st->cnvst_pwm, &cnvst_pwm_state);
574 is_high = cnvst_pwm_state.duty_cycle == cnvst_pwm_state.period;
575
576 cnvst_pwm_state.period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, freq);
577 cnvst_pwm_state.polarity = PWM_POLARITY_NORMAL;
578 if (is_high)
579 cnvst_pwm_state.duty_cycle = cnvst_pwm_state.period;
580 else if (is_swinging)
581 cnvst_pwm_state.duty_cycle = cnvst_pwm_state.period / 2;
582 else
583 cnvst_pwm_state.duty_cycle = 0;
584
585 return pwm_apply_might_sleep(st->cnvst_pwm, &cnvst_pwm_state);
586 }
587
ad7606_read_samples(struct ad7606_state * st)588 static int ad7606_read_samples(struct ad7606_state *st)
589 {
590 unsigned int num = st->chip_info->num_adc_channels;
591
592 return st->bops->read_block(st->dev, num, &st->data);
593 }
594
ad7606_trigger_handler(int irq,void * p)595 static irqreturn_t ad7606_trigger_handler(int irq, void *p)
596 {
597 struct iio_poll_func *pf = p;
598 struct iio_dev *indio_dev = pf->indio_dev;
599 struct ad7606_state *st = iio_priv(indio_dev);
600 int ret;
601
602 guard(mutex)(&st->lock);
603
604 ret = ad7606_read_samples(st);
605 if (ret)
606 goto error_ret;
607
608 iio_push_to_buffers_with_ts(indio_dev, &st->data, sizeof(st->data),
609 iio_get_time_ns(indio_dev));
610 error_ret:
611 iio_trigger_notify_done(indio_dev->trig);
612 /* The rising edge of the CONVST signal starts a new conversion. */
613 gpiod_set_value(st->gpio_convst, 1);
614
615 return IRQ_HANDLED;
616 }
617
ad7606_scan_direct(struct iio_dev * indio_dev,unsigned int ch,int * val)618 static int ad7606_scan_direct(struct iio_dev *indio_dev, unsigned int ch,
619 int *val)
620 {
621 struct ad7606_state *st = iio_priv(indio_dev);
622 const struct iio_chan_spec *chan;
623 unsigned int realbits;
624 int ret;
625
626 if (st->gpio_convst) {
627 gpiod_set_value(st->gpio_convst, 1);
628 } else {
629 ret = ad7606_pwm_set_high(st);
630 if (ret < 0)
631 return ret;
632 }
633
634 /*
635 * If no backend, wait for the interruption on busy pin, otherwise just add
636 * a delay to leave time for the data to be available. For now, the latter
637 * will not happen because IIO_CHAN_INFO_RAW is not supported for the backend.
638 * TODO: Add support for reading a single value when the backend is used.
639 */
640 if (st->trig) {
641 ret = wait_for_completion_timeout(&st->completion,
642 msecs_to_jiffies(1000));
643 if (!ret) {
644 ret = -ETIMEDOUT;
645 goto error_ret;
646 }
647 } else {
648 /*
649 * If the BUSY interrupt is not available, wait enough time for
650 * the longest possible conversion (max for the whole family is
651 * around 350us).
652 */
653 fsleep(400);
654 }
655
656 ret = ad7606_read_samples(st);
657 if (ret)
658 goto error_ret;
659
660 chan = &indio_dev->channels[ch];
661 realbits = chan->scan_type.realbits;
662
663 if (realbits > 16)
664 *val = st->data.buf32[ch];
665 else
666 *val = st->data.buf16[ch];
667
668 *val &= GENMASK(realbits - 1, 0);
669
670 if (chan->scan_type.sign == 's')
671 *val = sign_extend32(*val, realbits - 1);
672
673 error_ret:
674 if (!st->gpio_convst) {
675 ret = ad7606_pwm_set_low(st);
676 if (ret < 0)
677 return ret;
678 }
679 gpiod_set_value(st->gpio_convst, 0);
680
681 return ret;
682 }
683
ad7606_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long m)684 static int ad7606_read_raw(struct iio_dev *indio_dev,
685 struct iio_chan_spec const *chan,
686 int *val,
687 int *val2,
688 long m)
689 {
690 int ret, ch = 0;
691 struct ad7606_state *st = iio_priv(indio_dev);
692 struct ad7606_chan_scale *cs;
693 struct pwm_state cnvst_pwm_state;
694
695 switch (m) {
696 case IIO_CHAN_INFO_RAW:
697 if (!iio_device_claim_direct(indio_dev))
698 return -EBUSY;
699 ret = ad7606_scan_direct(indio_dev, chan->scan_index, val);
700 iio_device_release_direct(indio_dev);
701 if (ret < 0)
702 return ret;
703 return IIO_VAL_INT;
704 case IIO_CHAN_INFO_SCALE:
705 if (st->sw_mode_en)
706 ch = chan->scan_index;
707 cs = &st->chan_scales[ch];
708 *val = cs->scale_avail[cs->range][0];
709 *val2 = cs->scale_avail[cs->range][1];
710 return IIO_VAL_INT_PLUS_MICRO;
711 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
712 *val = st->oversampling;
713 return IIO_VAL_INT;
714 case IIO_CHAN_INFO_SAMP_FREQ:
715 pwm_get_state(st->cnvst_pwm, &cnvst_pwm_state);
716 *val = DIV_ROUND_CLOSEST_ULL(NSEC_PER_SEC, cnvst_pwm_state.period);
717 return IIO_VAL_INT;
718 }
719 return -EINVAL;
720 }
721
in_voltage_scale_available_show(struct device * dev,struct device_attribute * attr,char * buf)722 static ssize_t in_voltage_scale_available_show(struct device *dev,
723 struct device_attribute *attr,
724 char *buf)
725 {
726 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
727 struct ad7606_state *st = iio_priv(indio_dev);
728 struct ad7606_chan_scale *cs = &st->chan_scales[0];
729 const unsigned int (*vals)[2] = cs->scale_avail;
730 unsigned int i;
731 size_t len = 0;
732
733 for (i = 0; i < cs->num_scales; i++)
734 len += scnprintf(buf + len, PAGE_SIZE - len, "%u.%06u ",
735 vals[i][0], vals[i][1]);
736 buf[len - 1] = '\n';
737
738 return len;
739 }
740
741 static IIO_DEVICE_ATTR_RO(in_voltage_scale_available, 0);
742
ad7606_write_scale_hw(struct iio_dev * indio_dev,int ch,int val)743 static int ad7606_write_scale_hw(struct iio_dev *indio_dev, int ch, int val)
744 {
745 struct ad7606_state *st = iio_priv(indio_dev);
746
747 gpiod_set_value(st->gpio_range, val);
748
749 return 0;
750 }
751
ad7606_write_os_hw(struct iio_dev * indio_dev,int val)752 static int ad7606_write_os_hw(struct iio_dev *indio_dev, int val)
753 {
754 struct ad7606_state *st = iio_priv(indio_dev);
755 DECLARE_BITMAP(values, 3);
756
757 values[0] = val & GENMASK(2, 0);
758
759 gpiod_multi_set_value_cansleep(st->gpio_os, values);
760
761 /* AD7616 requires a reset to update value */
762 if (st->chip_info->os_req_reset)
763 ad7606_reset(st);
764
765 return 0;
766 }
767
ad7606_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)768 static int ad7606_write_raw(struct iio_dev *indio_dev,
769 struct iio_chan_spec const *chan,
770 int val,
771 int val2,
772 long mask)
773 {
774 struct ad7606_state *st = iio_priv(indio_dev);
775 unsigned int scale_avail_uv[AD760X_MAX_SCALES];
776 struct ad7606_chan_scale *cs;
777 int i, ret, ch = 0;
778
779 guard(mutex)(&st->lock);
780
781 switch (mask) {
782 case IIO_CHAN_INFO_SCALE:
783 if (st->sw_mode_en)
784 ch = chan->scan_index;
785 cs = &st->chan_scales[ch];
786 for (i = 0; i < cs->num_scales; i++) {
787 scale_avail_uv[i] = cs->scale_avail[i][0] * MICRO +
788 cs->scale_avail[i][1];
789 }
790 val = (val * MICRO) + val2;
791 i = find_closest(val, scale_avail_uv, cs->num_scales);
792
793 if (!iio_device_claim_direct(indio_dev))
794 return -EBUSY;
795 ret = st->write_scale(indio_dev, ch, i + cs->reg_offset);
796 iio_device_release_direct(indio_dev);
797 if (ret < 0)
798 return ret;
799 cs->range = i;
800
801 return 0;
802 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
803 if (val2)
804 return -EINVAL;
805 i = find_closest(val, st->oversampling_avail,
806 st->num_os_ratios);
807
808 if (!iio_device_claim_direct(indio_dev))
809 return -EBUSY;
810 ret = st->write_os(indio_dev, i);
811 iio_device_release_direct(indio_dev);
812 if (ret < 0)
813 return ret;
814 st->oversampling = st->oversampling_avail[i];
815
816 return 0;
817 case IIO_CHAN_INFO_SAMP_FREQ:
818 if (val < 0 && val2 != 0)
819 return -EINVAL;
820 return ad7606_set_sampling_freq(st, val);
821 default:
822 return -EINVAL;
823 }
824 }
825
ad7606_oversampling_ratio_avail(struct device * dev,struct device_attribute * attr,char * buf)826 static ssize_t ad7606_oversampling_ratio_avail(struct device *dev,
827 struct device_attribute *attr,
828 char *buf)
829 {
830 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
831 struct ad7606_state *st = iio_priv(indio_dev);
832 const unsigned int *vals = st->oversampling_avail;
833 unsigned int i;
834 size_t len = 0;
835
836 for (i = 0; i < st->num_os_ratios; i++)
837 len += scnprintf(buf + len, PAGE_SIZE - len, "%u ", vals[i]);
838 buf[len - 1] = '\n';
839
840 return len;
841 }
842
843 static IIO_DEVICE_ATTR(oversampling_ratio_available, 0444,
844 ad7606_oversampling_ratio_avail, NULL, 0);
845
846 static struct attribute *ad7606_attributes_os_and_range[] = {
847 &iio_dev_attr_in_voltage_scale_available.dev_attr.attr,
848 &iio_dev_attr_oversampling_ratio_available.dev_attr.attr,
849 NULL,
850 };
851
852 static const struct attribute_group ad7606_attribute_group_os_and_range = {
853 .attrs = ad7606_attributes_os_and_range,
854 };
855
856 static struct attribute *ad7606_attributes_os[] = {
857 &iio_dev_attr_oversampling_ratio_available.dev_attr.attr,
858 NULL,
859 };
860
861 static const struct attribute_group ad7606_attribute_group_os = {
862 .attrs = ad7606_attributes_os,
863 };
864
865 static struct attribute *ad7606_attributes_range[] = {
866 &iio_dev_attr_in_voltage_scale_available.dev_attr.attr,
867 NULL,
868 };
869
870 static const struct attribute_group ad7606_attribute_group_range = {
871 .attrs = ad7606_attributes_range,
872 };
873
ad7606_request_gpios(struct ad7606_state * st)874 static int ad7606_request_gpios(struct ad7606_state *st)
875 {
876 struct device *dev = st->dev;
877
878 st->gpio_convst = devm_gpiod_get_optional(dev, "adi,conversion-start",
879 GPIOD_OUT_LOW);
880
881 if (IS_ERR(st->gpio_convst))
882 return PTR_ERR(st->gpio_convst);
883
884 st->gpio_reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
885 if (IS_ERR(st->gpio_reset))
886 return PTR_ERR(st->gpio_reset);
887
888 st->gpio_range = devm_gpiod_get_optional(dev, "adi,range",
889 GPIOD_OUT_LOW);
890 if (IS_ERR(st->gpio_range))
891 return PTR_ERR(st->gpio_range);
892
893 st->gpio_standby = devm_gpiod_get_optional(dev, "standby",
894 GPIOD_OUT_LOW);
895 if (IS_ERR(st->gpio_standby))
896 return PTR_ERR(st->gpio_standby);
897
898 st->gpio_frstdata = devm_gpiod_get_optional(dev, "adi,first-data",
899 GPIOD_IN);
900 if (IS_ERR(st->gpio_frstdata))
901 return PTR_ERR(st->gpio_frstdata);
902
903 if (!st->chip_info->oversampling_num)
904 return 0;
905
906 st->gpio_os = devm_gpiod_get_array_optional(dev,
907 "adi,oversampling-ratio",
908 GPIOD_OUT_LOW);
909 return PTR_ERR_OR_ZERO(st->gpio_os);
910 }
911
912 /*
913 * The BUSY signal indicates when conversions are in progress, so when a rising
914 * edge of CONVST is applied, BUSY goes logic high and transitions low at the
915 * end of the entire conversion process. The falling edge of the BUSY signal
916 * triggers this interrupt.
917 */
ad7606_interrupt(int irq,void * dev_id)918 static irqreturn_t ad7606_interrupt(int irq, void *dev_id)
919 {
920 struct iio_dev *indio_dev = dev_id;
921 struct ad7606_state *st = iio_priv(indio_dev);
922 int ret;
923
924 if (iio_buffer_enabled(indio_dev)) {
925 if (st->gpio_convst) {
926 gpiod_set_value(st->gpio_convst, 0);
927 } else {
928 ret = ad7606_pwm_set_low(st);
929 if (ret < 0) {
930 dev_err(st->dev, "PWM set low failed");
931 goto done;
932 }
933 }
934 iio_trigger_poll_nested(st->trig);
935 } else {
936 complete(&st->completion);
937 }
938
939 done:
940 return IRQ_HANDLED;
941 };
942
ad7606_validate_trigger(struct iio_dev * indio_dev,struct iio_trigger * trig)943 static int ad7606_validate_trigger(struct iio_dev *indio_dev,
944 struct iio_trigger *trig)
945 {
946 struct ad7606_state *st = iio_priv(indio_dev);
947
948 if (st->trig != trig)
949 return -EINVAL;
950
951 return 0;
952 }
953
ad7606_buffer_postenable(struct iio_dev * indio_dev)954 static int ad7606_buffer_postenable(struct iio_dev *indio_dev)
955 {
956 struct ad7606_state *st = iio_priv(indio_dev);
957
958 gpiod_set_value(st->gpio_convst, 1);
959
960 return 0;
961 }
962
ad7606_buffer_predisable(struct iio_dev * indio_dev)963 static int ad7606_buffer_predisable(struct iio_dev *indio_dev)
964 {
965 struct ad7606_state *st = iio_priv(indio_dev);
966
967 gpiod_set_value(st->gpio_convst, 0);
968
969 return 0;
970 }
971
ad7606_read_avail(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,const int ** vals,int * type,int * length,long info)972 static int ad7606_read_avail(struct iio_dev *indio_dev,
973 struct iio_chan_spec const *chan,
974 const int **vals, int *type, int *length,
975 long info)
976 {
977 struct ad7606_state *st = iio_priv(indio_dev);
978 struct ad7606_chan_scale *cs;
979 unsigned int ch = 0;
980
981 switch (info) {
982 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
983 *vals = st->oversampling_avail;
984 *length = st->num_os_ratios;
985 *type = IIO_VAL_INT;
986
987 return IIO_AVAIL_LIST;
988
989 case IIO_CHAN_INFO_SCALE:
990 if (st->sw_mode_en)
991 ch = chan->scan_index;
992
993 cs = &st->chan_scales[ch];
994 *vals = (int *)cs->scale_avail;
995 *length = cs->num_scales * 2;
996 *type = IIO_VAL_INT_PLUS_MICRO;
997
998 return IIO_AVAIL_LIST;
999 }
1000 return -EINVAL;
1001 }
1002
ad7606_backend_buffer_postenable(struct iio_dev * indio_dev)1003 static int ad7606_backend_buffer_postenable(struct iio_dev *indio_dev)
1004 {
1005 struct ad7606_state *st = iio_priv(indio_dev);
1006
1007 return ad7606_pwm_set_swing(st);
1008 }
1009
ad7606_backend_buffer_predisable(struct iio_dev * indio_dev)1010 static int ad7606_backend_buffer_predisable(struct iio_dev *indio_dev)
1011 {
1012 struct ad7606_state *st = iio_priv(indio_dev);
1013
1014 return ad7606_pwm_set_low(st);
1015 }
1016
ad7606_update_scan_mode(struct iio_dev * indio_dev,const unsigned long * scan_mask)1017 static int ad7606_update_scan_mode(struct iio_dev *indio_dev,
1018 const unsigned long *scan_mask)
1019 {
1020 struct ad7606_state *st = iio_priv(indio_dev);
1021
1022 /*
1023 * The update scan mode is only for iio backend compatible drivers.
1024 * If the specific update_scan_mode is not defined in the bus ops,
1025 * just do nothing and return 0.
1026 */
1027 if (!st->bops->update_scan_mode)
1028 return 0;
1029
1030 return st->bops->update_scan_mode(indio_dev, scan_mask);
1031 }
1032
1033 static const struct iio_buffer_setup_ops ad7606_buffer_ops = {
1034 .postenable = &ad7606_buffer_postenable,
1035 .predisable = &ad7606_buffer_predisable,
1036 };
1037
1038 static const struct iio_buffer_setup_ops ad7606_backend_buffer_ops = {
1039 .postenable = &ad7606_backend_buffer_postenable,
1040 .predisable = &ad7606_backend_buffer_predisable,
1041 };
1042
1043 static const struct iio_info ad7606_info_no_os_or_range = {
1044 .read_raw = &ad7606_read_raw,
1045 .validate_trigger = &ad7606_validate_trigger,
1046 .update_scan_mode = &ad7606_update_scan_mode,
1047 };
1048
1049 static const struct iio_info ad7606_info_os_and_range = {
1050 .read_raw = &ad7606_read_raw,
1051 .write_raw = &ad7606_write_raw,
1052 .attrs = &ad7606_attribute_group_os_and_range,
1053 .validate_trigger = &ad7606_validate_trigger,
1054 .update_scan_mode = &ad7606_update_scan_mode,
1055 };
1056
1057 static const struct iio_info ad7606_info_sw_mode = {
1058 .read_raw = &ad7606_read_raw,
1059 .write_raw = &ad7606_write_raw,
1060 .read_avail = &ad7606_read_avail,
1061 .debugfs_reg_access = &ad7606_reg_access,
1062 .validate_trigger = &ad7606_validate_trigger,
1063 .update_scan_mode = &ad7606_update_scan_mode,
1064 };
1065
1066 static const struct iio_info ad7606_info_os = {
1067 .read_raw = &ad7606_read_raw,
1068 .write_raw = &ad7606_write_raw,
1069 .attrs = &ad7606_attribute_group_os,
1070 .validate_trigger = &ad7606_validate_trigger,
1071 .update_scan_mode = &ad7606_update_scan_mode,
1072 };
1073
1074 static const struct iio_info ad7606_info_range = {
1075 .read_raw = &ad7606_read_raw,
1076 .write_raw = &ad7606_write_raw,
1077 .attrs = &ad7606_attribute_group_range,
1078 .validate_trigger = &ad7606_validate_trigger,
1079 .update_scan_mode = &ad7606_update_scan_mode,
1080 };
1081
1082 static const struct iio_trigger_ops ad7606_trigger_ops = {
1083 .validate_device = iio_trigger_validate_own_device,
1084 };
1085
ad7606_write_mask(struct ad7606_state * st,unsigned int addr,unsigned long mask,unsigned int val)1086 static int ad7606_write_mask(struct ad7606_state *st, unsigned int addr,
1087 unsigned long mask, unsigned int val)
1088 {
1089 int readval;
1090
1091 readval = st->bops->reg_read(st, addr);
1092 if (readval < 0)
1093 return readval;
1094
1095 readval &= ~mask;
1096 readval |= val;
1097
1098 return st->bops->reg_write(st, addr, readval);
1099 }
1100
ad7616_write_scale_sw(struct iio_dev * indio_dev,int ch,int val)1101 static int ad7616_write_scale_sw(struct iio_dev *indio_dev, int ch, int val)
1102 {
1103 struct ad7606_state *st = iio_priv(indio_dev);
1104 unsigned int ch_addr, mode, ch_index;
1105
1106 /*
1107 * Ad7616 has 16 channels divided in group A and group B.
1108 * The range of channels from A are stored in registers with address 4
1109 * while channels from B are stored in register with address 6.
1110 * The last bit from channels determines if it is from group A or B
1111 * because the order of channels in iio is 0A, 0B, 1A, 1B...
1112 */
1113 ch_index = ch >> 1;
1114
1115 ch_addr = AD7616_RANGE_CH_ADDR(ch_index);
1116
1117 if ((ch & 0x1) == 0) /* channel A */
1118 ch_addr += AD7616_RANGE_CH_A_ADDR_OFF;
1119 else /* channel B */
1120 ch_addr += AD7616_RANGE_CH_B_ADDR_OFF;
1121
1122 /* 0b01 for 2.5v, 0b10 for 5v and 0b11 for 10v */
1123 mode = AD7616_RANGE_CH_MODE(ch_index, ((val + 1) & 0b11));
1124
1125 return ad7606_write_mask(st, ch_addr, AD7616_RANGE_CH_MSK(ch_index),
1126 mode);
1127 }
1128
ad7616_write_os_sw(struct iio_dev * indio_dev,int val)1129 static int ad7616_write_os_sw(struct iio_dev *indio_dev, int val)
1130 {
1131 struct ad7606_state *st = iio_priv(indio_dev);
1132
1133 return ad7606_write_mask(st, AD7616_CONFIGURATION_REGISTER,
1134 AD7616_OS_MASK, val << 2);
1135 }
1136
ad7606_write_scale_sw(struct iio_dev * indio_dev,int ch,int val)1137 static int ad7606_write_scale_sw(struct iio_dev *indio_dev, int ch, int val)
1138 {
1139 struct ad7606_state *st = iio_priv(indio_dev);
1140
1141 return ad7606_write_mask(st, AD7606_RANGE_CH_ADDR(ch),
1142 AD7606_RANGE_CH_MSK(ch),
1143 AD7606_RANGE_CH_MODE(ch, val));
1144 }
1145
ad7606_write_os_sw(struct iio_dev * indio_dev,int val)1146 static int ad7606_write_os_sw(struct iio_dev *indio_dev, int val)
1147 {
1148 struct ad7606_state *st = iio_priv(indio_dev);
1149
1150 return st->bops->reg_write(st, AD7606_OS_MODE, val);
1151 }
1152
ad7616_sw_mode_setup(struct iio_dev * indio_dev)1153 static int ad7616_sw_mode_setup(struct iio_dev *indio_dev)
1154 {
1155 struct ad7606_state *st = iio_priv(indio_dev);
1156 int ret;
1157
1158 /*
1159 * Scale can be configured individually for each channel
1160 * in software mode.
1161 */
1162
1163 st->write_scale = ad7616_write_scale_sw;
1164 st->write_os = &ad7616_write_os_sw;
1165
1166 if (st->bops->sw_mode_config) {
1167 ret = st->bops->sw_mode_config(indio_dev);
1168 if (ret)
1169 return ret;
1170 }
1171
1172 /* Activate Burst mode and SEQEN MODE */
1173 return ad7606_write_mask(st, AD7616_CONFIGURATION_REGISTER,
1174 AD7616_BURST_MODE | AD7616_SEQEN_MODE,
1175 AD7616_BURST_MODE | AD7616_SEQEN_MODE);
1176 }
1177
ad7606b_sw_mode_setup(struct iio_dev * indio_dev)1178 static int ad7606b_sw_mode_setup(struct iio_dev *indio_dev)
1179 {
1180 struct ad7606_state *st = iio_priv(indio_dev);
1181 DECLARE_BITMAP(os, 3);
1182
1183 bitmap_fill(os, 3);
1184 /*
1185 * Software mode is enabled when all three oversampling
1186 * pins are set to high. If oversampling gpios are defined
1187 * in the device tree, then they need to be set to high,
1188 * otherwise, they must be hardwired to VDD
1189 */
1190 if (st->gpio_os)
1191 gpiod_multi_set_value_cansleep(st->gpio_os, os);
1192
1193 /* OS of 128 and 256 are available only in software mode */
1194 st->oversampling_avail = ad7606b_oversampling_avail;
1195 st->num_os_ratios = ARRAY_SIZE(ad7606b_oversampling_avail);
1196
1197 st->write_scale = ad7606_write_scale_sw;
1198 st->write_os = &ad7606_write_os_sw;
1199
1200 if (!st->bops->sw_mode_config)
1201 return 0;
1202
1203 return st->bops->sw_mode_config(indio_dev);
1204 }
1205
ad7606_probe_channels(struct iio_dev * indio_dev)1206 static int ad7606_probe_channels(struct iio_dev *indio_dev)
1207 {
1208 struct ad7606_state *st = iio_priv(indio_dev);
1209 struct device *dev = indio_dev->dev.parent;
1210 struct iio_chan_spec *channels;
1211 bool slow_bus;
1212 int ret, i;
1213
1214 slow_bus = !(st->bops->iio_backend_config || st->offload_en);
1215 indio_dev->num_channels = st->chip_info->num_adc_channels;
1216
1217 /* Slow buses also get 1 more channel for soft timestamp */
1218 if (slow_bus)
1219 indio_dev->num_channels++;
1220
1221 channels = devm_kcalloc(dev, indio_dev->num_channels, sizeof(*channels),
1222 GFP_KERNEL);
1223 if (!channels)
1224 return -ENOMEM;
1225
1226 for (i = 0; i < st->chip_info->num_adc_channels; i++) {
1227 struct iio_chan_spec *chan = &channels[i];
1228
1229 chan->type = IIO_VOLTAGE;
1230 chan->indexed = 1;
1231 chan->channel = i;
1232 chan->scan_index = i;
1233 chan->scan_type.sign = 's';
1234 chan->scan_type.realbits = st->chip_info->bits;
1235 /*
1236 * If in SPI offload mode, storagebits are set based
1237 * on the spi-engine hw implementation.
1238 */
1239 chan->scan_type.storagebits = st->offload_en ?
1240 st->chip_info->offload_storagebits :
1241 (st->chip_info->bits > 16 ? 32 : 16);
1242
1243 chan->scan_type.endianness = IIO_CPU;
1244
1245 if (indio_dev->modes & INDIO_DIRECT_MODE)
1246 chan->info_mask_separate |= BIT(IIO_CHAN_INFO_RAW);
1247
1248 if (st->sw_mode_en) {
1249 chan->info_mask_separate |= BIT(IIO_CHAN_INFO_SCALE);
1250 chan->info_mask_separate_available |=
1251 BIT(IIO_CHAN_INFO_SCALE);
1252
1253 /*
1254 * All chips with software mode support oversampling,
1255 * so we skip the oversampling_available check. And the
1256 * shared_by_type instead of shared_by_all on slow
1257 * buses is for backward compatibility.
1258 */
1259 if (slow_bus)
1260 chan->info_mask_shared_by_type |=
1261 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO);
1262 else
1263 chan->info_mask_shared_by_all |=
1264 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO);
1265
1266 chan->info_mask_shared_by_all_available |=
1267 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO);
1268 } else {
1269 chan->info_mask_shared_by_type |=
1270 BIT(IIO_CHAN_INFO_SCALE);
1271
1272 if (st->chip_info->oversampling_avail)
1273 chan->info_mask_shared_by_all |=
1274 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO);
1275 }
1276
1277 if (!slow_bus)
1278 chan->info_mask_shared_by_all |=
1279 BIT(IIO_CHAN_INFO_SAMP_FREQ);
1280
1281 ret = st->chip_info->scale_setup_cb(indio_dev, chan);
1282 if (ret)
1283 return ret;
1284 }
1285
1286 if (slow_bus)
1287 channels[i] = (struct iio_chan_spec)IIO_CHAN_SOFT_TIMESTAMP(i);
1288
1289 indio_dev->channels = channels;
1290
1291 return 0;
1292 }
1293
ad7606_pwm_disable(void * data)1294 static void ad7606_pwm_disable(void *data)
1295 {
1296 pwm_disable(data);
1297 }
1298
ad7606_probe(struct device * dev,int irq,void __iomem * base_address,const struct ad7606_chip_info * chip_info,const struct ad7606_bus_ops * bops)1299 int ad7606_probe(struct device *dev, int irq, void __iomem *base_address,
1300 const struct ad7606_chip_info *chip_info,
1301 const struct ad7606_bus_ops *bops)
1302 {
1303 struct ad7606_state *st;
1304 int ret;
1305 struct iio_dev *indio_dev;
1306
1307 indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
1308 if (!indio_dev)
1309 return -ENOMEM;
1310
1311 st = iio_priv(indio_dev);
1312 dev_set_drvdata(dev, indio_dev);
1313
1314 ret = devm_mutex_init(dev, &st->lock);
1315 if (ret)
1316 return ret;
1317
1318 st->dev = dev;
1319 st->bops = bops;
1320 st->base_address = base_address;
1321 st->oversampling = 1;
1322 st->sw_mode_en = device_property_read_bool(dev, "adi,sw-mode");
1323
1324 if (st->sw_mode_en && !chip_info->sw_setup_cb)
1325 return dev_err_probe(dev, -EINVAL,
1326 "Software mode is not supported for this chip\n");
1327
1328 ret = devm_regulator_get_enable(dev, "avcc");
1329 if (ret)
1330 return dev_err_probe(dev, ret,
1331 "Failed to enable specified AVcc supply\n");
1332
1333 st->chip_info = chip_info;
1334
1335 if (st->chip_info->oversampling_num) {
1336 st->oversampling_avail = st->chip_info->oversampling_avail;
1337 st->num_os_ratios = st->chip_info->oversampling_num;
1338 }
1339
1340 ret = ad7606_request_gpios(st);
1341 if (ret)
1342 return ret;
1343
1344 if (st->gpio_os) {
1345 if (st->gpio_range)
1346 indio_dev->info = &ad7606_info_os_and_range;
1347 else
1348 indio_dev->info = &ad7606_info_os;
1349 } else {
1350 if (st->gpio_range)
1351 indio_dev->info = &ad7606_info_range;
1352 else
1353 indio_dev->info = &ad7606_info_no_os_or_range;
1354 }
1355
1356 /* AXI ADC backend doesn't support single read. */
1357 indio_dev->modes = st->bops->iio_backend_config ? 0 : INDIO_DIRECT_MODE;
1358 indio_dev->name = chip_info->name;
1359
1360 /* Using spi-engine with offload support ? */
1361 if (st->bops->offload_config) {
1362 ret = st->bops->offload_config(dev, indio_dev);
1363 if (ret)
1364 return ret;
1365 }
1366
1367 ret = ad7606_probe_channels(indio_dev);
1368 if (ret)
1369 return ret;
1370
1371 ret = ad7606_reset(st);
1372 if (ret)
1373 dev_warn(st->dev, "failed to RESET: no RESET GPIO specified\n");
1374
1375 /* AD7616 requires al least 15ms to reconfigure after a reset */
1376 if (st->chip_info->init_delay_ms) {
1377 if (msleep_interruptible(st->chip_info->init_delay_ms))
1378 return -ERESTARTSYS;
1379 }
1380
1381 /* If convst pin is not defined, setup PWM. */
1382 if (!st->gpio_convst || st->offload_en) {
1383 st->cnvst_pwm = devm_pwm_get(dev, NULL);
1384 if (IS_ERR(st->cnvst_pwm))
1385 return PTR_ERR(st->cnvst_pwm);
1386
1387 /* The PWM is initialized at 1MHz to have a fast enough GPIO emulation. */
1388 ret = ad7606_set_sampling_freq(st, 1 * MEGA);
1389 if (ret)
1390 return ret;
1391
1392 ret = ad7606_pwm_set_low(st);
1393 if (ret)
1394 return ret;
1395
1396 /*
1397 * PWM is not disabled when sampling stops, but instead its duty cycle is set
1398 * to 0% to be sure we have a "low" state. After we unload the driver, let's
1399 * disable the PWM.
1400 */
1401 ret = devm_add_action_or_reset(dev, ad7606_pwm_disable,
1402 st->cnvst_pwm);
1403 if (ret)
1404 return ret;
1405 }
1406
1407 if (st->bops->iio_backend_config) {
1408 /*
1409 * If there is a backend, the PWM should not overpass the maximum sampling
1410 * frequency the chip supports.
1411 */
1412 ret = ad7606_set_sampling_freq(st, chip_info->max_samplerate);
1413 if (ret)
1414 return ret;
1415
1416 ret = st->bops->iio_backend_config(dev, indio_dev);
1417 if (ret)
1418 return ret;
1419
1420 indio_dev->setup_ops = &ad7606_backend_buffer_ops;
1421 } else if (!st->offload_en) {
1422 /* Reserve the PWM use only for backend (force gpio_convst definition) */
1423 if (!st->gpio_convst)
1424 return dev_err_probe(dev, -EINVAL,
1425 "No backend, connect convst to a GPIO");
1426
1427 init_completion(&st->completion);
1428 st->trig = devm_iio_trigger_alloc(dev, "%s-dev%d",
1429 indio_dev->name,
1430 iio_device_id(indio_dev));
1431 if (!st->trig)
1432 return -ENOMEM;
1433
1434 st->trig->ops = &ad7606_trigger_ops;
1435 iio_trigger_set_drvdata(st->trig, indio_dev);
1436 ret = devm_iio_trigger_register(dev, st->trig);
1437 if (ret)
1438 return ret;
1439
1440 indio_dev->trig = iio_trigger_get(st->trig);
1441
1442 ret = devm_request_threaded_irq(dev, irq, NULL, &ad7606_interrupt,
1443 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
1444 chip_info->name, indio_dev);
1445 if (ret)
1446 return ret;
1447
1448 ret = devm_iio_triggered_buffer_setup(dev, indio_dev,
1449 &iio_pollfunc_store_time,
1450 &ad7606_trigger_handler,
1451 &ad7606_buffer_ops);
1452 if (ret)
1453 return ret;
1454 }
1455
1456 st->write_scale = ad7606_write_scale_hw;
1457 st->write_os = ad7606_write_os_hw;
1458
1459 /* Offload needs 1 DOUT line, applying this setting in sw_setup_cb. */
1460 if (st->sw_mode_en || st->offload_en) {
1461 indio_dev->info = &ad7606_info_sw_mode;
1462 st->chip_info->sw_setup_cb(indio_dev);
1463 }
1464
1465 return devm_iio_device_register(dev, indio_dev);
1466 }
1467 EXPORT_SYMBOL_NS_GPL(ad7606_probe, "IIO_AD7606");
1468
1469 #ifdef CONFIG_PM_SLEEP
1470
ad7606_suspend(struct device * dev)1471 static int ad7606_suspend(struct device *dev)
1472 {
1473 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1474 struct ad7606_state *st = iio_priv(indio_dev);
1475
1476 if (st->gpio_standby) {
1477 gpiod_set_value(st->gpio_range, 1);
1478 gpiod_set_value(st->gpio_standby, 1);
1479 }
1480
1481 return 0;
1482 }
1483
ad7606_resume(struct device * dev)1484 static int ad7606_resume(struct device *dev)
1485 {
1486 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1487 struct ad7606_state *st = iio_priv(indio_dev);
1488
1489 if (st->gpio_standby) {
1490 gpiod_set_value(st->gpio_range, st->chan_scales[0].range);
1491 gpiod_set_value(st->gpio_standby, 1);
1492 ad7606_reset(st);
1493 }
1494
1495 return 0;
1496 }
1497
1498 SIMPLE_DEV_PM_OPS(ad7606_pm_ops, ad7606_suspend, ad7606_resume);
1499 EXPORT_SYMBOL_NS_GPL(ad7606_pm_ops, "IIO_AD7606");
1500
1501 #endif
1502
1503 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
1504 MODULE_DESCRIPTION("Analog Devices AD7606 ADC");
1505 MODULE_LICENSE("GPL v2");
1506