1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * AD7606 SPI ADC driver
4 *
5 * Copyright 2011 Analog Devices Inc.
6 */
7
8 #include <linux/bitmap.h>
9 #include <linux/err.h>
10 #include <linux/math.h>
11 #include <linux/module.h>
12 #include <linux/pwm.h>
13 #include <linux/spi/offload/consumer.h>
14 #include <linux/spi/offload/provider.h>
15 #include <linux/spi/spi.h>
16 #include <linux/types.h>
17 #include <linux/units.h>
18
19 #include <linux/iio/buffer-dmaengine.h>
20 #include <linux/iio/iio.h>
21
22 #include <dt-bindings/iio/adc/adi,ad7606.h>
23
24 #include "ad7606.h"
25
26 #define MAX_SPI_FREQ_HZ 23500000 /* VDRIVE above 4.75 V */
27
28 struct spi_bus_data {
29 struct spi_offload *offload;
30 struct spi_offload_trigger *offload_trigger;
31 struct spi_transfer offload_xfer;
32 struct spi_message offload_msg;
33 };
34
ad7616_spi_rd_wr_cmd(int addr,char is_write_op)35 static u16 ad7616_spi_rd_wr_cmd(int addr, char is_write_op)
36 {
37 /*
38 * The address of register consist of one w/r bit
39 * 6 bits of address followed by one reserved bit.
40 */
41 return ((addr & 0x7F) << 1) | ((is_write_op & 0x1) << 7);
42 }
43
ad7606b_spi_rd_wr_cmd(int addr,char is_write_op)44 static u16 ad7606b_spi_rd_wr_cmd(int addr, char is_write_op)
45 {
46 /*
47 * The address of register consists of one bit which
48 * specifies a read command placed in bit 6, followed by
49 * 6 bits of address.
50 */
51 return (addr & 0x3F) | (((~is_write_op) & 0x1) << 6);
52 }
53
ad7606_spi_read_block(struct device * dev,int count,void * buf)54 static int ad7606_spi_read_block(struct device *dev,
55 int count, void *buf)
56 {
57 struct spi_device *spi = to_spi_device(dev);
58 int i, ret;
59 unsigned short *data = buf;
60 __be16 *bdata = buf;
61
62 ret = spi_read(spi, buf, count * 2);
63 if (ret < 0) {
64 dev_err(&spi->dev, "SPI read error\n");
65 return ret;
66 }
67
68 for (i = 0; i < count; i++)
69 data[i] = be16_to_cpu(bdata[i]);
70
71 return 0;
72 }
73
ad7606_spi_read_block14to16(struct device * dev,int count,void * buf)74 static int ad7606_spi_read_block14to16(struct device *dev,
75 int count, void *buf)
76 {
77 struct spi_device *spi = to_spi_device(dev);
78 struct spi_transfer xfer = {
79 .bits_per_word = 14,
80 .len = count * sizeof(u16),
81 .rx_buf = buf,
82 };
83
84 return spi_sync_transfer(spi, &xfer, 1);
85 }
86
ad7606_spi_read_block18to32(struct device * dev,int count,void * buf)87 static int ad7606_spi_read_block18to32(struct device *dev,
88 int count, void *buf)
89 {
90 struct spi_device *spi = to_spi_device(dev);
91 struct spi_transfer xfer = {
92 .bits_per_word = 18,
93 .len = count * sizeof(u32),
94 .rx_buf = buf,
95 };
96
97 return spi_sync_transfer(spi, &xfer, 1);
98 }
99
ad7606_spi_reg_read(struct ad7606_state * st,unsigned int addr)100 static int ad7606_spi_reg_read(struct ad7606_state *st, unsigned int addr)
101 {
102 struct spi_device *spi = to_spi_device(st->dev);
103 struct spi_transfer t[] = {
104 {
105 .tx_buf = &st->d16[0],
106 .len = 2,
107 .cs_change = 1,
108 }, {
109 .rx_buf = &st->d16[1],
110 .len = 2,
111 },
112 };
113 int ret;
114
115 st->d16[0] = cpu_to_be16(st->bops->rd_wr_cmd(addr, 0) << 8);
116
117 ret = spi_sync_transfer(spi, t, ARRAY_SIZE(t));
118 if (ret < 0)
119 return ret;
120
121 return be16_to_cpu(st->d16[1]);
122 }
123
ad7606_spi_reg_write(struct ad7606_state * st,unsigned int addr,unsigned int val)124 static int ad7606_spi_reg_write(struct ad7606_state *st,
125 unsigned int addr,
126 unsigned int val)
127 {
128 struct spi_device *spi = to_spi_device(st->dev);
129
130 st->d16[0] = cpu_to_be16((st->bops->rd_wr_cmd(addr, 1) << 8) |
131 (val & 0xFF));
132
133 return spi_write(spi, &st->d16[0], sizeof(st->d16[0]));
134 }
135
ad7606b_sw_mode_config(struct iio_dev * indio_dev)136 static int ad7606b_sw_mode_config(struct iio_dev *indio_dev)
137 {
138 struct ad7606_state *st = iio_priv(indio_dev);
139
140 /* Configure device spi to output on a single channel */
141 return st->bops->reg_write(st, AD7606_CONFIGURATION_REGISTER,
142 AD7606_SINGLE_DOUT);
143 }
144
145 static const struct spi_offload_config ad7606_spi_offload_config = {
146 .capability_flags = SPI_OFFLOAD_CAP_TRIGGER |
147 SPI_OFFLOAD_CAP_RX_STREAM_DMA,
148 };
149
ad7606_spi_offload_buffer_postenable(struct iio_dev * indio_dev)150 static int ad7606_spi_offload_buffer_postenable(struct iio_dev *indio_dev)
151 {
152 const struct iio_scan_type *scan_type;
153 struct ad7606_state *st = iio_priv(indio_dev);
154 struct spi_bus_data *bus_data = st->bus_data;
155 struct spi_transfer *xfer = &bus_data->offload_xfer;
156 struct spi_device *spi = to_spi_device(st->dev);
157 struct spi_offload_trigger_config config = {
158 .type = SPI_OFFLOAD_TRIGGER_DATA_READY,
159 };
160 int ret;
161
162 scan_type = &indio_dev->channels[0].scan_type;
163
164 xfer->bits_per_word = scan_type->realbits;
165 xfer->offload_flags = SPI_OFFLOAD_XFER_RX_STREAM;
166 /*
167 * Using SPI offload, storagebits are related to the spi-engine
168 * hw implementation, can be 16 or 32, so can't be used to compute
169 * struct spi_transfer.len. Using realbits instead.
170 */
171 xfer->len = (scan_type->realbits > 16 ? 4 : 2) *
172 st->chip_info->num_adc_channels;
173
174 spi_message_init_with_transfers(&bus_data->offload_msg, xfer, 1);
175 bus_data->offload_msg.offload = bus_data->offload;
176
177 ret = spi_optimize_message(spi, &bus_data->offload_msg);
178 if (ret) {
179 dev_err(st->dev, "failed to prepare offload, err: %d\n", ret);
180 return ret;
181 }
182
183 ret = spi_offload_trigger_enable(bus_data->offload,
184 bus_data->offload_trigger,
185 &config);
186 if (ret)
187 goto err_unoptimize_message;
188
189 ret = ad7606_pwm_set_swing(st);
190 if (ret)
191 goto err_offload_exit_conversion_mode;
192
193 return 0;
194
195 err_offload_exit_conversion_mode:
196 spi_offload_trigger_disable(bus_data->offload,
197 bus_data->offload_trigger);
198
199 err_unoptimize_message:
200 spi_unoptimize_message(&bus_data->offload_msg);
201
202 return ret;
203 }
204
ad7606_spi_offload_buffer_predisable(struct iio_dev * indio_dev)205 static int ad7606_spi_offload_buffer_predisable(struct iio_dev *indio_dev)
206 {
207 struct ad7606_state *st = iio_priv(indio_dev);
208 struct spi_bus_data *bus_data = st->bus_data;
209 int ret;
210
211 ret = ad7606_pwm_set_low(st);
212 if (ret)
213 return ret;
214
215 spi_offload_trigger_disable(bus_data->offload,
216 bus_data->offload_trigger);
217 spi_unoptimize_message(&bus_data->offload_msg);
218
219 return 0;
220 }
221
222 static const struct iio_buffer_setup_ops ad7606_offload_buffer_setup_ops = {
223 .postenable = ad7606_spi_offload_buffer_postenable,
224 .predisable = ad7606_spi_offload_buffer_predisable,
225 };
226
ad7606_spi_offload_trigger_match(struct spi_offload_trigger * trigger,enum spi_offload_trigger_type type,u64 * args,u32 nargs)227 static bool ad7606_spi_offload_trigger_match(
228 struct spi_offload_trigger *trigger,
229 enum spi_offload_trigger_type type,
230 u64 *args, u32 nargs)
231 {
232 if (type != SPI_OFFLOAD_TRIGGER_DATA_READY)
233 return false;
234
235 /*
236 * Requires 1 arg:
237 * args[0] is the trigger event.
238 */
239 if (nargs != 1 || args[0] != AD7606_TRIGGER_EVENT_BUSY)
240 return false;
241
242 return true;
243 }
244
ad7606_spi_offload_trigger_request(struct spi_offload_trigger * trigger,enum spi_offload_trigger_type type,u64 * args,u32 nargs)245 static int ad7606_spi_offload_trigger_request(
246 struct spi_offload_trigger *trigger,
247 enum spi_offload_trigger_type type,
248 u64 *args, u32 nargs)
249 {
250 /* Should already be validated by match, but just in case. */
251 if (nargs != 1)
252 return -EINVAL;
253
254 return 0;
255 }
256
ad7606_spi_offload_trigger_validate(struct spi_offload_trigger * trigger,struct spi_offload_trigger_config * config)257 static int ad7606_spi_offload_trigger_validate(
258 struct spi_offload_trigger *trigger,
259 struct spi_offload_trigger_config *config)
260 {
261 if (config->type != SPI_OFFLOAD_TRIGGER_DATA_READY)
262 return -EINVAL;
263
264 return 0;
265 }
266
267 static const struct spi_offload_trigger_ops ad7606_offload_trigger_ops = {
268 .match = ad7606_spi_offload_trigger_match,
269 .request = ad7606_spi_offload_trigger_request,
270 .validate = ad7606_spi_offload_trigger_validate,
271 };
272
ad7606_spi_offload_probe(struct device * dev,struct iio_dev * indio_dev)273 static int ad7606_spi_offload_probe(struct device *dev,
274 struct iio_dev *indio_dev)
275 {
276 struct ad7606_state *st = iio_priv(indio_dev);
277 struct spi_device *spi = to_spi_device(dev);
278 struct spi_bus_data *bus_data;
279 struct dma_chan *rx_dma;
280 struct spi_offload_trigger_info trigger_info = {
281 .fwnode = dev_fwnode(dev),
282 .ops = &ad7606_offload_trigger_ops,
283 .priv = st,
284 };
285 int ret;
286
287 bus_data = devm_kzalloc(dev, sizeof(*bus_data), GFP_KERNEL);
288 if (!bus_data)
289 return -ENOMEM;
290 st->bus_data = bus_data;
291
292 bus_data->offload = devm_spi_offload_get(dev, spi,
293 &ad7606_spi_offload_config);
294 ret = PTR_ERR_OR_ZERO(bus_data->offload);
295 if (ret && ret != -ENODEV)
296 return dev_err_probe(dev, ret, "failed to get SPI offload\n");
297 /* Allow main ad7606_probe function to continue. */
298 if (ret == -ENODEV)
299 return 0;
300
301 ret = devm_spi_offload_trigger_register(dev, &trigger_info);
302 if (ret)
303 return dev_err_probe(dev, ret,
304 "failed to register offload trigger\n");
305
306 bus_data->offload_trigger = devm_spi_offload_trigger_get(dev,
307 bus_data->offload, SPI_OFFLOAD_TRIGGER_DATA_READY);
308 if (IS_ERR(bus_data->offload_trigger))
309 return dev_err_probe(dev, PTR_ERR(bus_data->offload_trigger),
310 "failed to get offload trigger\n");
311
312 /* TODO: PWM setup should be ok, done for the backend. PWM mutex ? */
313 rx_dma = devm_spi_offload_rx_stream_request_dma_chan(dev,
314 bus_data->offload);
315 if (IS_ERR(rx_dma))
316 return dev_err_probe(dev, PTR_ERR(rx_dma),
317 "failed to get offload RX DMA\n");
318
319 ret = devm_iio_dmaengine_buffer_setup_with_handle(dev, indio_dev,
320 rx_dma, IIO_BUFFER_DIRECTION_IN);
321 if (ret)
322 return dev_err_probe(dev, ret,
323 "failed to setup offload RX DMA\n");
324
325 /* Use offload ops. */
326 indio_dev->setup_ops = &ad7606_offload_buffer_setup_ops;
327
328 st->offload_en = true;
329
330 return 0;
331 }
332
ad7606_spi_update_scan_mode(struct iio_dev * indio_dev,const unsigned long * scan_mask)333 static int ad7606_spi_update_scan_mode(struct iio_dev *indio_dev,
334 const unsigned long *scan_mask)
335 {
336 struct ad7606_state *st = iio_priv(indio_dev);
337
338 if (st->offload_en) {
339 unsigned int num_adc_ch = st->chip_info->num_adc_channels;
340
341 /*
342 * SPI offload requires that all channels are enabled since
343 * there isn't a way to selectively disable channels that get
344 * read (this is simultaneous sampling ADC) and the DMA buffer
345 * has no way of demuxing the data to filter out unwanted
346 * channels.
347 */
348 if (bitmap_weight(scan_mask, num_adc_ch) != num_adc_ch)
349 return -EINVAL;
350 }
351
352 return 0;
353 }
354
355 static const struct ad7606_bus_ops ad7606_spi_bops = {
356 .offload_config = ad7606_spi_offload_probe,
357 .read_block = ad7606_spi_read_block,
358 .update_scan_mode = ad7606_spi_update_scan_mode,
359 };
360
361 static const struct ad7606_bus_ops ad7607_spi_bops = {
362 .offload_config = ad7606_spi_offload_probe,
363 .read_block = ad7606_spi_read_block14to16,
364 .update_scan_mode = ad7606_spi_update_scan_mode,
365 };
366
367 static const struct ad7606_bus_ops ad7608_spi_bops = {
368 .offload_config = ad7606_spi_offload_probe,
369 .read_block = ad7606_spi_read_block18to32,
370 .update_scan_mode = ad7606_spi_update_scan_mode,
371 };
372
373 static const struct ad7606_bus_ops ad7616_spi_bops = {
374 .offload_config = ad7606_spi_offload_probe,
375 .read_block = ad7606_spi_read_block,
376 .reg_read = ad7606_spi_reg_read,
377 .reg_write = ad7606_spi_reg_write,
378 .rd_wr_cmd = ad7616_spi_rd_wr_cmd,
379 .update_scan_mode = ad7606_spi_update_scan_mode,
380 };
381
382 static const struct ad7606_bus_ops ad7606b_spi_bops = {
383 .offload_config = ad7606_spi_offload_probe,
384 .read_block = ad7606_spi_read_block,
385 .reg_read = ad7606_spi_reg_read,
386 .reg_write = ad7606_spi_reg_write,
387 .rd_wr_cmd = ad7606b_spi_rd_wr_cmd,
388 .sw_mode_config = ad7606b_sw_mode_config,
389 .update_scan_mode = ad7606_spi_update_scan_mode,
390 };
391
392 static const struct ad7606_bus_ops ad7606c_18_spi_bops = {
393 .offload_config = ad7606_spi_offload_probe,
394 .read_block = ad7606_spi_read_block18to32,
395 .reg_read = ad7606_spi_reg_read,
396 .reg_write = ad7606_spi_reg_write,
397 .rd_wr_cmd = ad7606b_spi_rd_wr_cmd,
398 .sw_mode_config = ad7606b_sw_mode_config,
399 .update_scan_mode = ad7606_spi_update_scan_mode,
400 };
401
402 static const struct ad7606_bus_info ad7605_4_bus_info = {
403 .chip_info = &ad7605_4_info,
404 .bops = &ad7606_spi_bops,
405 };
406
407 static const struct ad7606_bus_info ad7606_8_bus_info = {
408 .chip_info = &ad7606_8_info,
409 .bops = &ad7606_spi_bops,
410 };
411
412 static const struct ad7606_bus_info ad7606_6_bus_info = {
413 .chip_info = &ad7606_6_info,
414 .bops = &ad7606_spi_bops,
415 };
416
417 static const struct ad7606_bus_info ad7606_4_bus_info = {
418 .chip_info = &ad7606_4_info,
419 .bops = &ad7606_spi_bops,
420 };
421
422 static const struct ad7606_bus_info ad7606b_bus_info = {
423 .chip_info = &ad7606b_info,
424 .bops = &ad7606b_spi_bops,
425 };
426
427 static const struct ad7606_bus_info ad7606c_16_bus_info = {
428 .chip_info = &ad7606c_16_info,
429 .bops = &ad7606b_spi_bops,
430 };
431
432 static const struct ad7606_bus_info ad7606c_18_bus_info = {
433 .chip_info = &ad7606c_18_info,
434 .bops = &ad7606c_18_spi_bops,
435 };
436
437 static const struct ad7606_bus_info ad7607_bus_info = {
438 .chip_info = &ad7607_info,
439 .bops = &ad7607_spi_bops,
440 };
441
442 static const struct ad7606_bus_info ad7608_bus_info = {
443 .chip_info = &ad7608_info,
444 .bops = &ad7608_spi_bops,
445 };
446
447 static const struct ad7606_bus_info ad7609_bus_info = {
448 .chip_info = &ad7609_info,
449 .bops = &ad7608_spi_bops,
450 };
451
452 static const struct ad7606_bus_info ad7616_bus_info = {
453 .chip_info = &ad7616_info,
454 .bops = &ad7616_spi_bops,
455 };
456
ad7606_spi_probe(struct spi_device * spi)457 static int ad7606_spi_probe(struct spi_device *spi)
458 {
459 const struct ad7606_bus_info *bus_info = spi_get_device_match_data(spi);
460
461 return ad7606_probe(&spi->dev, spi->irq, NULL,
462 bus_info->chip_info, bus_info->bops);
463 }
464
465 static const struct spi_device_id ad7606_id_table[] = {
466 { "ad7605-4", (kernel_ulong_t)&ad7605_4_bus_info },
467 { "ad7606-4", (kernel_ulong_t)&ad7606_4_bus_info },
468 { "ad7606-6", (kernel_ulong_t)&ad7606_6_bus_info },
469 { "ad7606-8", (kernel_ulong_t)&ad7606_8_bus_info },
470 { "ad7606b", (kernel_ulong_t)&ad7606b_bus_info },
471 { "ad7606c-16", (kernel_ulong_t)&ad7606c_16_bus_info },
472 { "ad7606c-18", (kernel_ulong_t)&ad7606c_18_bus_info },
473 { "ad7607", (kernel_ulong_t)&ad7607_bus_info },
474 { "ad7608", (kernel_ulong_t)&ad7608_bus_info },
475 { "ad7609", (kernel_ulong_t)&ad7609_bus_info },
476 { "ad7616", (kernel_ulong_t)&ad7616_bus_info },
477 { }
478 };
479 MODULE_DEVICE_TABLE(spi, ad7606_id_table);
480
481 static const struct of_device_id ad7606_of_match[] = {
482 { .compatible = "adi,ad7605-4", .data = &ad7605_4_bus_info },
483 { .compatible = "adi,ad7606-4", .data = &ad7606_4_bus_info },
484 { .compatible = "adi,ad7606-6", .data = &ad7606_6_bus_info },
485 { .compatible = "adi,ad7606-8", .data = &ad7606_8_bus_info },
486 { .compatible = "adi,ad7606b", .data = &ad7606b_bus_info },
487 { .compatible = "adi,ad7606c-16", .data = &ad7606c_16_bus_info },
488 { .compatible = "adi,ad7606c-18", .data = &ad7606c_18_bus_info },
489 { .compatible = "adi,ad7607", .data = &ad7607_bus_info },
490 { .compatible = "adi,ad7608", .data = &ad7608_bus_info },
491 { .compatible = "adi,ad7609", .data = &ad7609_bus_info },
492 { .compatible = "adi,ad7616", .data = &ad7616_bus_info },
493 { }
494 };
495 MODULE_DEVICE_TABLE(of, ad7606_of_match);
496
497 static struct spi_driver ad7606_driver = {
498 .driver = {
499 .name = "ad7606",
500 .of_match_table = ad7606_of_match,
501 .pm = AD7606_PM_OPS,
502 },
503 .probe = ad7606_spi_probe,
504 .id_table = ad7606_id_table,
505 };
506 module_spi_driver(ad7606_driver);
507
508 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
509 MODULE_DESCRIPTION("Analog Devices AD7606 ADC");
510 MODULE_LICENSE("GPL v2");
511 MODULE_IMPORT_NS("IIO_AD7606");
512 MODULE_IMPORT_NS("IIO_DMAENGINE_BUFFER");
513