1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Analog Devices AD738x Simultaneous Sampling SAR ADCs
4 *
5 * Copyright 2017 Analog Devices Inc.
6 * Copyright 2024 BayLibre, SAS
7 *
8 * Datasheets of supported parts:
9 * ad7380/1 : https://www.analog.com/media/en/technical-documentation/data-sheets/AD7380-7381.pdf
10 * ad7383/4 : https://www.analog.com/media/en/technical-documentation/data-sheets/ad7383-7384.pdf
11 * ad7386/7/8 : https://www.analog.com/media/en/technical-documentation/data-sheets/AD7386-7387-7388.pdf
12 * ad7380-4 : https://www.analog.com/media/en/technical-documentation/data-sheets/ad7380-4.pdf
13 * ad7381-4 : https://www.analog.com/media/en/technical-documentation/data-sheets/ad7381-4.pdf
14 * ad7383/4-4 : https://www.analog.com/media/en/technical-documentation/data-sheets/ad7383-4-ad7384-4.pdf
15 * ad7386/7/8-4 : https://www.analog.com/media/en/technical-documentation/data-sheets/ad7386-4-7387-4-7388-4.pdf
16 * ad7389-4 : https://www.analog.com/media/en/technical-documentation/data-sheets/ad7389-4.pdf
17 * adaq4370-4 : https://www.analog.com/media/en/technical-documentation/data-sheets/adaq4370-4.pdf
18 * adaq4380-4 : https://www.analog.com/media/en/technical-documentation/data-sheets/adaq4380-4.pdf
19 * adaq4381-4 : https://www.analog.com/media/en/technical-documentation/data-sheets/adaq4381-4.pdf
20 *
21 * HDL ad738x_fmc: https://analogdevicesinc.github.io/hdl/projects/ad738x_fmc/index.html
22 *
23 */
24
25 #include <linux/align.h>
26 #include <linux/bitfield.h>
27 #include <linux/bitops.h>
28 #include <linux/cleanup.h>
29 #include <linux/device.h>
30 #include <linux/err.h>
31 #include <linux/kernel.h>
32 #include <linux/math.h>
33 #include <linux/module.h>
34 #include <linux/regmap.h>
35 #include <linux/regulator/consumer.h>
36 #include <linux/slab.h>
37 #include <linux/spi/offload/consumer.h>
38 #include <linux/spi/spi.h>
39 #include <linux/units.h>
40 #include <linux/util_macros.h>
41
42 #include <linux/iio/buffer.h>
43 #include <linux/iio/buffer-dmaengine.h>
44 #include <linux/iio/events.h>
45 #include <linux/iio/iio.h>
46 #include <linux/iio/trigger_consumer.h>
47 #include <linux/iio/triggered_buffer.h>
48
49 #define MAX_NUM_CHANNELS 8
50 /* 2.5V internal reference voltage */
51 #define AD7380_INTERNAL_REF_MV 2500
52 /* 3.3V internal reference voltage for ADAQ */
53 #define ADAQ4380_INTERNAL_REF_MV 3300
54
55 /* reading and writing registers is more reliable at lower than max speed */
56 #define AD7380_REG_WR_SPEED_HZ 10000000
57
58 #define AD7380_REG_WR BIT(15)
59 #define AD7380_REG_REGADDR GENMASK(14, 12)
60 #define AD7380_REG_DATA GENMASK(11, 0)
61
62 #define AD7380_REG_ADDR_NOP 0x0
63 #define AD7380_REG_ADDR_CONFIG1 0x1
64 #define AD7380_REG_ADDR_CONFIG2 0x2
65 #define AD7380_REG_ADDR_ALERT 0x3
66 #define AD7380_REG_ADDR_ALERT_LOW_TH 0x4
67 #define AD7380_REG_ADDR_ALERT_HIGH_TH 0x5
68
69 #define AD7380_CONFIG1_CH BIT(11)
70 #define AD7380_CONFIG1_SEQ BIT(10)
71 #define AD7380_CONFIG1_OS_MODE BIT(9)
72 #define AD7380_CONFIG1_OSR GENMASK(8, 6)
73 #define AD7380_CONFIG1_CRC_W BIT(5)
74 #define AD7380_CONFIG1_CRC_R BIT(4)
75 #define AD7380_CONFIG1_ALERTEN BIT(3)
76 #define AD7380_CONFIG1_RES BIT(2)
77 #define AD7380_CONFIG1_REFSEL BIT(1)
78 #define AD7380_CONFIG1_PMODE BIT(0)
79
80 #define AD7380_CONFIG2_SDO2 GENMASK(9, 8)
81 #define AD7380_CONFIG2_SDO BIT(8)
82 #define AD7380_CONFIG2_RESET GENMASK(7, 0)
83
84 #define AD7380_CONFIG2_RESET_SOFT 0x3C
85 #define AD7380_CONFIG2_RESET_HARD 0xFF
86
87 #define AD7380_ALERT_LOW_TH GENMASK(11, 0)
88 #define AD7380_ALERT_HIGH_TH GENMASK(11, 0)
89
90 #define T_CONVERT_NS 190 /* conversion time */
91 #define T_CONVERT_0_NS 10 /* 1st conversion start time (oversampling) */
92 #define T_CONVERT_X_NS 500 /* xth conversion start time (oversampling) */
93 #define T_POWERUP_US 5000 /* Power up */
94
95 /*
96 * AD738x support several SDO lines to increase throughput, but driver currently
97 * supports only 1 SDO line (standard SPI transaction)
98 */
99 #define AD7380_NUM_SDO_LINES 1
100 #define AD7380_DEFAULT_GAIN_MILLI 1000
101
102 /*
103 * Using SPI offload, storagebits is always 32, so can't be used to compute struct
104 * spi_transfer.len. Using realbits instead.
105 */
106 #define AD7380_SPI_BYTES(scan_type) ((scan_type)->realbits > 16 ? 4 : 2)
107
108 struct ad7380_timing_specs {
109 const unsigned int t_csh_ns; /* CS minimum high time */
110 };
111
112 struct ad7380_chip_info {
113 const char *name;
114 const struct iio_chan_spec *channels;
115 const struct iio_chan_spec *offload_channels;
116 unsigned int num_channels;
117 unsigned int num_simult_channels;
118 bool has_hardware_gain;
119 bool has_mux;
120 const char * const *supplies;
121 unsigned int num_supplies;
122 bool external_ref_only;
123 bool internal_ref_only;
124 unsigned int internal_ref_mv;
125 const char * const *vcm_supplies;
126 unsigned int num_vcm_supplies;
127 const unsigned long *available_scan_masks;
128 const struct ad7380_timing_specs *timing_specs;
129 u32 max_conversion_rate_hz;
130 };
131
132 static const struct iio_event_spec ad7380_events[] = {
133 {
134 .type = IIO_EV_TYPE_THRESH,
135 .dir = IIO_EV_DIR_RISING,
136 .mask_shared_by_dir = BIT(IIO_EV_INFO_VALUE),
137 },
138 {
139 .type = IIO_EV_TYPE_THRESH,
140 .dir = IIO_EV_DIR_FALLING,
141 .mask_shared_by_dir = BIT(IIO_EV_INFO_VALUE),
142 },
143 {
144 .type = IIO_EV_TYPE_THRESH,
145 .dir = IIO_EV_DIR_EITHER,
146 .mask_shared_by_all = BIT(IIO_EV_INFO_ENABLE),
147 },
148 };
149
150 enum {
151 AD7380_SCAN_TYPE_NORMAL,
152 AD7380_SCAN_TYPE_RESOLUTION_BOOST,
153 };
154
155 /* Extended scan types for 12-bit unsigned chips. */
156 static const struct iio_scan_type ad7380_scan_type_12_u[] = {
157 [AD7380_SCAN_TYPE_NORMAL] = {
158 .sign = 'u',
159 .realbits = 12,
160 .storagebits = 16,
161 .endianness = IIO_CPU,
162 },
163 [AD7380_SCAN_TYPE_RESOLUTION_BOOST] = {
164 .sign = 'u',
165 .realbits = 14,
166 .storagebits = 16,
167 .endianness = IIO_CPU,
168 },
169 };
170
171 /* Extended scan types for 14-bit signed chips. */
172 static const struct iio_scan_type ad7380_scan_type_14_s[] = {
173 [AD7380_SCAN_TYPE_NORMAL] = {
174 .sign = 's',
175 .realbits = 14,
176 .storagebits = 16,
177 .endianness = IIO_CPU,
178 },
179 [AD7380_SCAN_TYPE_RESOLUTION_BOOST] = {
180 .sign = 's',
181 .realbits = 16,
182 .storagebits = 16,
183 .endianness = IIO_CPU,
184 },
185 };
186
187 /* Extended scan types for 14-bit unsigned chips. */
188 static const struct iio_scan_type ad7380_scan_type_14_u[] = {
189 [AD7380_SCAN_TYPE_NORMAL] = {
190 .sign = 'u',
191 .realbits = 14,
192 .storagebits = 16,
193 .endianness = IIO_CPU,
194 },
195 [AD7380_SCAN_TYPE_RESOLUTION_BOOST] = {
196 .sign = 'u',
197 .realbits = 16,
198 .storagebits = 16,
199 .endianness = IIO_CPU,
200 },
201 };
202
203 /* Extended scan types for 16-bit signed_chips. */
204 static const struct iio_scan_type ad7380_scan_type_16_s[] = {
205 [AD7380_SCAN_TYPE_NORMAL] = {
206 .sign = 's',
207 .realbits = 16,
208 .storagebits = 16,
209 .endianness = IIO_CPU,
210 },
211 [AD7380_SCAN_TYPE_RESOLUTION_BOOST] = {
212 .sign = 's',
213 .realbits = 18,
214 .storagebits = 32,
215 .endianness = IIO_CPU,
216 },
217 };
218
219 /* Extended scan types for 16-bit unsigned chips. */
220 static const struct iio_scan_type ad7380_scan_type_16_u[] = {
221 [AD7380_SCAN_TYPE_NORMAL] = {
222 .sign = 'u',
223 .realbits = 16,
224 .storagebits = 16,
225 .endianness = IIO_CPU,
226 },
227 [AD7380_SCAN_TYPE_RESOLUTION_BOOST] = {
228 .sign = 'u',
229 .realbits = 18,
230 .storagebits = 32,
231 .endianness = IIO_CPU,
232 },
233 };
234
235 /*
236 * Defining here scan types for offload mode, since with current available HDL
237 * only a value of 32 for storagebits is supported.
238 */
239
240 /* Extended scan types for 12-bit unsigned chips, offload support. */
241 static const struct iio_scan_type ad7380_scan_type_12_u_offload[] = {
242 [AD7380_SCAN_TYPE_NORMAL] = {
243 .sign = 'u',
244 .realbits = 12,
245 .storagebits = 32,
246 .endianness = IIO_CPU,
247 },
248 [AD7380_SCAN_TYPE_RESOLUTION_BOOST] = {
249 .sign = 'u',
250 .realbits = 14,
251 .storagebits = 32,
252 .endianness = IIO_CPU,
253 },
254 };
255
256 /* Extended scan types for 14-bit signed chips, offload support. */
257 static const struct iio_scan_type ad7380_scan_type_14_s_offload[] = {
258 [AD7380_SCAN_TYPE_NORMAL] = {
259 .sign = 's',
260 .realbits = 14,
261 .storagebits = 32,
262 .endianness = IIO_CPU,
263 },
264 [AD7380_SCAN_TYPE_RESOLUTION_BOOST] = {
265 .sign = 's',
266 .realbits = 16,
267 .storagebits = 32,
268 .endianness = IIO_CPU,
269 },
270 };
271
272 /* Extended scan types for 14-bit unsigned chips, offload support. */
273 static const struct iio_scan_type ad7380_scan_type_14_u_offload[] = {
274 [AD7380_SCAN_TYPE_NORMAL] = {
275 .sign = 'u',
276 .realbits = 14,
277 .storagebits = 32,
278 .endianness = IIO_CPU,
279 },
280 [AD7380_SCAN_TYPE_RESOLUTION_BOOST] = {
281 .sign = 'u',
282 .realbits = 16,
283 .storagebits = 32,
284 .endianness = IIO_CPU,
285 },
286 };
287
288 /* Extended scan types for 16-bit signed_chips, offload support. */
289 static const struct iio_scan_type ad7380_scan_type_16_s_offload[] = {
290 [AD7380_SCAN_TYPE_NORMAL] = {
291 .sign = 's',
292 .realbits = 16,
293 .storagebits = 32,
294 .endianness = IIO_CPU,
295 },
296 [AD7380_SCAN_TYPE_RESOLUTION_BOOST] = {
297 .sign = 's',
298 .realbits = 18,
299 .storagebits = 32,
300 .endianness = IIO_CPU,
301 },
302 };
303
304 /* Extended scan types for 16-bit unsigned chips, offload support. */
305 static const struct iio_scan_type ad7380_scan_type_16_u_offload[] = {
306 [AD7380_SCAN_TYPE_NORMAL] = {
307 .sign = 'u',
308 .realbits = 16,
309 .storagebits = 32,
310 .endianness = IIO_CPU,
311 },
312 [AD7380_SCAN_TYPE_RESOLUTION_BOOST] = {
313 .sign = 'u',
314 .realbits = 18,
315 .storagebits = 32,
316 .endianness = IIO_CPU,
317 },
318 };
319
320 #define _AD7380_CHANNEL(index, bits, diff, sign, gain) { \
321 .type = IIO_VOLTAGE, \
322 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
323 ((gain) ? BIT(IIO_CHAN_INFO_SCALE) : 0) | \
324 ((diff) ? 0 : BIT(IIO_CHAN_INFO_OFFSET)), \
325 .info_mask_shared_by_type = ((gain) ? 0 : BIT(IIO_CHAN_INFO_SCALE)) | \
326 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
327 .info_mask_shared_by_type_available = \
328 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
329 .indexed = 1, \
330 .differential = (diff), \
331 .channel = (diff) ? (2 * (index)) : (index), \
332 .channel2 = (diff) ? (2 * (index) + 1) : 0, \
333 .scan_index = (index), \
334 .has_ext_scan_type = 1, \
335 .ext_scan_type = ad7380_scan_type_##bits##_##sign, \
336 .num_ext_scan_type = ARRAY_SIZE(ad7380_scan_type_##bits##_##sign), \
337 .event_spec = ad7380_events, \
338 .num_event_specs = ARRAY_SIZE(ad7380_events), \
339 }
340
341 #define _AD7380_OFFLOAD_CHANNEL(index, bits, diff, sign, gain) { \
342 .type = IIO_VOLTAGE, \
343 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
344 ((gain) ? BIT(IIO_CHAN_INFO_SCALE) : 0) | \
345 ((diff) ? 0 : BIT(IIO_CHAN_INFO_OFFSET)), \
346 .info_mask_shared_by_type = ((gain) ? 0 : BIT(IIO_CHAN_INFO_SCALE)) | \
347 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO) | \
348 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
349 .info_mask_shared_by_type_available = \
350 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO) | \
351 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
352 .indexed = 1, \
353 .differential = (diff), \
354 .channel = (diff) ? (2 * (index)) : (index), \
355 .channel2 = (diff) ? (2 * (index) + 1) : 0, \
356 .scan_index = (index), \
357 .has_ext_scan_type = 1, \
358 .ext_scan_type = ad7380_scan_type_##bits##_##sign##_offload, \
359 .num_ext_scan_type = \
360 ARRAY_SIZE(ad7380_scan_type_##bits##_##sign##_offload), \
361 .event_spec = ad7380_events, \
362 .num_event_specs = ARRAY_SIZE(ad7380_events), \
363 }
364
365 /*
366 * Notes on the offload channels:
367 * - There is no soft timestamp since everything is done in hardware.
368 * - There is a sampling frequency attribute added. This controls the SPI
369 * offload trigger.
370 * - The storagebits value depends on the SPI offload provider. Currently there
371 * is only one supported provider, namely the ADI PULSAR ADC HDL project,
372 * which always uses 32-bit words for data values, even for <= 16-bit ADCs.
373 * So the value is just hardcoded to 32 for now.
374 */
375
376 #define AD7380_CHANNEL(index, bits, diff, sign) \
377 _AD7380_CHANNEL(index, bits, diff, sign, false)
378
379 #define ADAQ4380_CHANNEL(index, bits, diff, sign) \
380 _AD7380_CHANNEL(index, bits, diff, sign, true)
381
382 #define DEFINE_AD7380_2_CHANNEL(name, bits, diff, sign) \
383 static const struct iio_chan_spec name[] = { \
384 AD7380_CHANNEL(0, bits, diff, sign), \
385 AD7380_CHANNEL(1, bits, diff, sign), \
386 IIO_CHAN_SOFT_TIMESTAMP(2), \
387 }
388
389 #define DEFINE_AD7380_4_CHANNEL(name, bits, diff, sign) \
390 static const struct iio_chan_spec name[] = { \
391 AD7380_CHANNEL(0, bits, diff, sign), \
392 AD7380_CHANNEL(1, bits, diff, sign), \
393 AD7380_CHANNEL(2, bits, diff, sign), \
394 AD7380_CHANNEL(3, bits, diff, sign), \
395 IIO_CHAN_SOFT_TIMESTAMP(4), \
396 }
397
398 #define DEFINE_ADAQ4380_4_CHANNEL(name, bits, diff, sign) \
399 static const struct iio_chan_spec name[] = { \
400 ADAQ4380_CHANNEL(0, bits, diff, sign), \
401 ADAQ4380_CHANNEL(1, bits, diff, sign), \
402 ADAQ4380_CHANNEL(2, bits, diff, sign), \
403 ADAQ4380_CHANNEL(3, bits, diff, sign), \
404 IIO_CHAN_SOFT_TIMESTAMP(4), \
405 }
406
407 #define DEFINE_AD7380_8_CHANNEL(name, bits, diff, sign) \
408 static const struct iio_chan_spec name[] = { \
409 AD7380_CHANNEL(0, bits, diff, sign), \
410 AD7380_CHANNEL(1, bits, diff, sign), \
411 AD7380_CHANNEL(2, bits, diff, sign), \
412 AD7380_CHANNEL(3, bits, diff, sign), \
413 AD7380_CHANNEL(4, bits, diff, sign), \
414 AD7380_CHANNEL(5, bits, diff, sign), \
415 AD7380_CHANNEL(6, bits, diff, sign), \
416 AD7380_CHANNEL(7, bits, diff, sign), \
417 IIO_CHAN_SOFT_TIMESTAMP(8), \
418 }
419
420 #define AD7380_OFFLOAD_CHANNEL(index, bits, diff, sign) \
421 _AD7380_OFFLOAD_CHANNEL(index, bits, diff, sign, false)
422
423 #define ADAQ4380_OFFLOAD_CHANNEL(index, bits, diff, sign) \
424 _AD7380_OFFLOAD_CHANNEL(index, bits, diff, sign, true)
425
426 #define DEFINE_AD7380_2_OFFLOAD_CHANNEL(name, bits, diff, sign) \
427 static const struct iio_chan_spec name[] = { \
428 AD7380_OFFLOAD_CHANNEL(0, bits, diff, sign), \
429 AD7380_OFFLOAD_CHANNEL(1, bits, diff, sign), \
430 }
431
432 #define DEFINE_AD7380_4_OFFLOAD_CHANNEL(name, bits, diff, sign) \
433 static const struct iio_chan_spec name[] = { \
434 AD7380_OFFLOAD_CHANNEL(0, bits, diff, sign), \
435 AD7380_OFFLOAD_CHANNEL(1, bits, diff, sign), \
436 AD7380_OFFLOAD_CHANNEL(2, bits, diff, sign), \
437 AD7380_OFFLOAD_CHANNEL(3, bits, diff, sign), \
438 }
439
440 #define DEFINE_ADAQ4380_4_OFFLOAD_CHANNEL(name, bits, diff, sign) \
441 static const struct iio_chan_spec name[] = { \
442 AD7380_OFFLOAD_CHANNEL(0, bits, diff, sign), \
443 AD7380_OFFLOAD_CHANNEL(1, bits, diff, sign), \
444 AD7380_OFFLOAD_CHANNEL(2, bits, diff, sign), \
445 AD7380_OFFLOAD_CHANNEL(3, bits, diff, sign), \
446 }
447
448 #define DEFINE_AD7380_8_OFFLOAD_CHANNEL(name, bits, diff, sign) \
449 static const struct iio_chan_spec name[] = { \
450 AD7380_OFFLOAD_CHANNEL(0, bits, diff, sign), \
451 AD7380_OFFLOAD_CHANNEL(1, bits, diff, sign), \
452 AD7380_OFFLOAD_CHANNEL(2, bits, diff, sign), \
453 AD7380_OFFLOAD_CHANNEL(3, bits, diff, sign), \
454 AD7380_OFFLOAD_CHANNEL(4, bits, diff, sign), \
455 AD7380_OFFLOAD_CHANNEL(5, bits, diff, sign), \
456 AD7380_OFFLOAD_CHANNEL(6, bits, diff, sign), \
457 AD7380_OFFLOAD_CHANNEL(7, bits, diff, sign), \
458 }
459
460 /* fully differential */
461 DEFINE_AD7380_2_CHANNEL(ad7380_channels, 16, 1, s);
462 DEFINE_AD7380_2_CHANNEL(ad7381_channels, 14, 1, s);
463 DEFINE_AD7380_4_CHANNEL(ad7380_4_channels, 16, 1, s);
464 DEFINE_AD7380_4_CHANNEL(ad7381_4_channels, 14, 1, s);
465 DEFINE_ADAQ4380_4_CHANNEL(adaq4380_4_channels, 16, 1, s);
466 DEFINE_ADAQ4380_4_CHANNEL(adaq4381_4_channels, 14, 1, s);
467 /* pseudo differential */
468 DEFINE_AD7380_2_CHANNEL(ad7383_channels, 16, 0, s);
469 DEFINE_AD7380_2_CHANNEL(ad7384_channels, 14, 0, s);
470 DEFINE_AD7380_4_CHANNEL(ad7383_4_channels, 16, 0, s);
471 DEFINE_AD7380_4_CHANNEL(ad7384_4_channels, 14, 0, s);
472
473 /* Single ended */
474 DEFINE_AD7380_4_CHANNEL(ad7386_channels, 16, 0, u);
475 DEFINE_AD7380_4_CHANNEL(ad7387_channels, 14, 0, u);
476 DEFINE_AD7380_4_CHANNEL(ad7388_channels, 12, 0, u);
477 DEFINE_AD7380_8_CHANNEL(ad7386_4_channels, 16, 0, u);
478 DEFINE_AD7380_8_CHANNEL(ad7387_4_channels, 14, 0, u);
479 DEFINE_AD7380_8_CHANNEL(ad7388_4_channels, 12, 0, u);
480
481 /* offload channels */
482 DEFINE_AD7380_2_OFFLOAD_CHANNEL(ad7380_offload_channels, 16, 1, s);
483 DEFINE_AD7380_2_OFFLOAD_CHANNEL(ad7381_offload_channels, 14, 1, s);
484 DEFINE_AD7380_4_OFFLOAD_CHANNEL(ad7380_4_offload_channels, 16, 1, s);
485 DEFINE_AD7380_4_OFFLOAD_CHANNEL(ad7381_4_offload_channels, 14, 1, s);
486 DEFINE_ADAQ4380_4_OFFLOAD_CHANNEL(adaq4380_4_offload_channels, 16, 1, s);
487 DEFINE_ADAQ4380_4_OFFLOAD_CHANNEL(adaq4381_4_offload_channels, 14, 1, s);
488
489 /* pseudo differential */
490 DEFINE_AD7380_2_OFFLOAD_CHANNEL(ad7383_offload_channels, 16, 0, s);
491 DEFINE_AD7380_2_OFFLOAD_CHANNEL(ad7384_offload_channels, 14, 0, s);
492 DEFINE_AD7380_4_OFFLOAD_CHANNEL(ad7383_4_offload_channels, 16, 0, s);
493 DEFINE_AD7380_4_OFFLOAD_CHANNEL(ad7384_4_offload_channels, 14, 0, s);
494
495 /* Single ended */
496 DEFINE_AD7380_4_OFFLOAD_CHANNEL(ad7386_offload_channels, 16, 0, u);
497 DEFINE_AD7380_4_OFFLOAD_CHANNEL(ad7387_offload_channels, 14, 0, u);
498 DEFINE_AD7380_4_OFFLOAD_CHANNEL(ad7388_offload_channels, 12, 0, u);
499 DEFINE_AD7380_8_OFFLOAD_CHANNEL(ad7386_4_offload_channels, 16, 0, u);
500 DEFINE_AD7380_8_OFFLOAD_CHANNEL(ad7387_4_offload_channels, 14, 0, u);
501 DEFINE_AD7380_8_OFFLOAD_CHANNEL(ad7388_4_offload_channels, 12, 0, u);
502
503 static const char * const ad7380_supplies[] = {
504 "vcc", "vlogic",
505 };
506
507 static const char * const adaq4380_supplies[] = {
508 "ldo", "vcc", "vlogic", "vs-p", "vs-n", "refin",
509 };
510
511 static const char * const ad7380_2_channel_vcm_supplies[] = {
512 "aina", "ainb",
513 };
514
515 static const char * const ad7380_4_channel_vcm_supplies[] = {
516 "aina", "ainb", "ainc", "aind",
517 };
518
519 /* Since this is simultaneous sampling, we don't allow individual channels. */
520 static const unsigned long ad7380_2_channel_scan_masks[] = {
521 GENMASK(1, 0),
522 0
523 };
524
525 static const unsigned long ad7380_4_channel_scan_masks[] = {
526 GENMASK(3, 0),
527 0
528 };
529
530 /*
531 * Single ended parts have a 2:1 multiplexer in front of each ADC.
532 *
533 * From an IIO point of view, all inputs are exported, i.e ad7386/7/8
534 * export 4 channels and ad7386-4/7-4/8-4 export 8 channels.
535 *
536 * Inputs AinX0 of multiplexers correspond to the first half of IIO channels
537 * (i.e 0-1 or 0-3) and inputs AinX1 correspond to second half (i.e 2-3 or
538 * 4-7). Example for AD7386/7/8 (2 channels parts):
539 *
540 * IIO | AD7386/7/8
541 * | +----------------------------
542 * | | _____ ______
543 * | | | | | |
544 * voltage0 | AinA0 --|--->| | | |
545 * | | | mux |----->| ADCA |---
546 * voltage2 | AinA1 --|--->| | | |
547 * | | |_____| |_____ |
548 * | | _____ ______
549 * | | | | | |
550 * voltage1 | AinB0 --|--->| | | |
551 * | | | mux |----->| ADCB |---
552 * voltage3 | AinB1 --|--->| | | |
553 * | | |_____| |______|
554 * | |
555 * | +----------------------------
556 *
557 * Since this is simultaneous sampling for AinX0 OR AinX1 we have two separate
558 * scan masks.
559 * When sequencer mode is enabled, chip automatically cycles through
560 * AinX0 and AinX1 channels. From an IIO point of view, we ca enable all
561 * channels, at the cost of an extra read, thus dividing the maximum rate by
562 * two.
563 */
564 enum {
565 AD7380_SCAN_MASK_CH_0,
566 AD7380_SCAN_MASK_CH_1,
567 AD7380_SCAN_MASK_SEQ,
568 };
569
570 static const unsigned long ad7380_2x2_channel_scan_masks[] = {
571 [AD7380_SCAN_MASK_CH_0] = GENMASK(1, 0),
572 [AD7380_SCAN_MASK_CH_1] = GENMASK(3, 2),
573 [AD7380_SCAN_MASK_SEQ] = GENMASK(3, 0),
574 0
575 };
576
577 static const unsigned long ad7380_2x4_channel_scan_masks[] = {
578 [AD7380_SCAN_MASK_CH_0] = GENMASK(3, 0),
579 [AD7380_SCAN_MASK_CH_1] = GENMASK(7, 4),
580 [AD7380_SCAN_MASK_SEQ] = GENMASK(7, 0),
581 0
582 };
583
584 static const struct ad7380_timing_specs ad7380_timing = {
585 .t_csh_ns = 10,
586 };
587
588 static const struct ad7380_timing_specs ad7380_4_timing = {
589 .t_csh_ns = 20,
590 };
591
592 /*
593 * Available oversampling ratios. The indices correspond with the bit value
594 * expected by the chip. The available ratios depend on the averaging mode,
595 * only normal averaging is supported for now.
596 */
597 static const int ad7380_oversampling_ratios[] = {
598 1, 2, 4, 8, 16, 32,
599 };
600
601 /* Gains stored as fractions of 1000 so they can be expressed by integers. */
602 static const int ad7380_gains[] = {
603 300, 600, 1000, 1600,
604 };
605
606 static const struct ad7380_chip_info ad7380_chip_info = {
607 .name = "ad7380",
608 .channels = ad7380_channels,
609 .offload_channels = ad7380_offload_channels,
610 .num_channels = ARRAY_SIZE(ad7380_channels),
611 .num_simult_channels = 2,
612 .supplies = ad7380_supplies,
613 .num_supplies = ARRAY_SIZE(ad7380_supplies),
614 .internal_ref_mv = AD7380_INTERNAL_REF_MV,
615 .available_scan_masks = ad7380_2_channel_scan_masks,
616 .timing_specs = &ad7380_timing,
617 .max_conversion_rate_hz = 4 * MEGA,
618 };
619
620 static const struct ad7380_chip_info ad7381_chip_info = {
621 .name = "ad7381",
622 .channels = ad7381_channels,
623 .offload_channels = ad7381_offload_channels,
624 .num_channels = ARRAY_SIZE(ad7381_channels),
625 .num_simult_channels = 2,
626 .supplies = ad7380_supplies,
627 .num_supplies = ARRAY_SIZE(ad7380_supplies),
628 .internal_ref_mv = AD7380_INTERNAL_REF_MV,
629 .available_scan_masks = ad7380_2_channel_scan_masks,
630 .timing_specs = &ad7380_timing,
631 .max_conversion_rate_hz = 4 * MEGA,
632 };
633
634 static const struct ad7380_chip_info ad7383_chip_info = {
635 .name = "ad7383",
636 .channels = ad7383_channels,
637 .offload_channels = ad7383_offload_channels,
638 .num_channels = ARRAY_SIZE(ad7383_channels),
639 .num_simult_channels = 2,
640 .supplies = ad7380_supplies,
641 .num_supplies = ARRAY_SIZE(ad7380_supplies),
642 .vcm_supplies = ad7380_2_channel_vcm_supplies,
643 .num_vcm_supplies = ARRAY_SIZE(ad7380_2_channel_vcm_supplies),
644 .internal_ref_mv = AD7380_INTERNAL_REF_MV,
645 .available_scan_masks = ad7380_2_channel_scan_masks,
646 .timing_specs = &ad7380_timing,
647 .max_conversion_rate_hz = 4 * MEGA,
648 };
649
650 static const struct ad7380_chip_info ad7384_chip_info = {
651 .name = "ad7384",
652 .channels = ad7384_channels,
653 .offload_channels = ad7384_offload_channels,
654 .num_channels = ARRAY_SIZE(ad7384_channels),
655 .num_simult_channels = 2,
656 .supplies = ad7380_supplies,
657 .num_supplies = ARRAY_SIZE(ad7380_supplies),
658 .vcm_supplies = ad7380_2_channel_vcm_supplies,
659 .num_vcm_supplies = ARRAY_SIZE(ad7380_2_channel_vcm_supplies),
660 .internal_ref_mv = AD7380_INTERNAL_REF_MV,
661 .available_scan_masks = ad7380_2_channel_scan_masks,
662 .timing_specs = &ad7380_timing,
663 .max_conversion_rate_hz = 4 * MEGA,
664 };
665
666 static const struct ad7380_chip_info ad7386_chip_info = {
667 .name = "ad7386",
668 .channels = ad7386_channels,
669 .offload_channels = ad7386_offload_channels,
670 .num_channels = ARRAY_SIZE(ad7386_channels),
671 .num_simult_channels = 2,
672 .supplies = ad7380_supplies,
673 .num_supplies = ARRAY_SIZE(ad7380_supplies),
674 .internal_ref_mv = AD7380_INTERNAL_REF_MV,
675 .has_mux = true,
676 .available_scan_masks = ad7380_2x2_channel_scan_masks,
677 .timing_specs = &ad7380_timing,
678 .max_conversion_rate_hz = 4 * MEGA,
679 };
680
681 static const struct ad7380_chip_info ad7387_chip_info = {
682 .name = "ad7387",
683 .channels = ad7387_channels,
684 .offload_channels = ad7387_offload_channels,
685 .num_channels = ARRAY_SIZE(ad7387_channels),
686 .num_simult_channels = 2,
687 .supplies = ad7380_supplies,
688 .num_supplies = ARRAY_SIZE(ad7380_supplies),
689 .internal_ref_mv = AD7380_INTERNAL_REF_MV,
690 .has_mux = true,
691 .available_scan_masks = ad7380_2x2_channel_scan_masks,
692 .timing_specs = &ad7380_timing,
693 .max_conversion_rate_hz = 4 * MEGA,
694 };
695
696 static const struct ad7380_chip_info ad7388_chip_info = {
697 .name = "ad7388",
698 .channels = ad7388_channels,
699 .offload_channels = ad7388_offload_channels,
700 .num_channels = ARRAY_SIZE(ad7388_channels),
701 .num_simult_channels = 2,
702 .supplies = ad7380_supplies,
703 .num_supplies = ARRAY_SIZE(ad7380_supplies),
704 .internal_ref_mv = AD7380_INTERNAL_REF_MV,
705 .has_mux = true,
706 .available_scan_masks = ad7380_2x2_channel_scan_masks,
707 .timing_specs = &ad7380_timing,
708 .max_conversion_rate_hz = 4 * MEGA,
709 };
710
711 static const struct ad7380_chip_info ad7380_4_chip_info = {
712 .name = "ad7380-4",
713 .channels = ad7380_4_channels,
714 .offload_channels = ad7380_4_offload_channels,
715 .num_channels = ARRAY_SIZE(ad7380_4_channels),
716 .num_simult_channels = 4,
717 .supplies = ad7380_supplies,
718 .num_supplies = ARRAY_SIZE(ad7380_supplies),
719 .external_ref_only = true,
720 .available_scan_masks = ad7380_4_channel_scan_masks,
721 .timing_specs = &ad7380_4_timing,
722 .max_conversion_rate_hz = 4 * MEGA,
723 };
724
725 static const struct ad7380_chip_info ad7381_4_chip_info = {
726 .name = "ad7381-4",
727 .channels = ad7381_4_channels,
728 .offload_channels = ad7381_4_offload_channels,
729 .num_channels = ARRAY_SIZE(ad7381_4_channels),
730 .num_simult_channels = 4,
731 .supplies = ad7380_supplies,
732 .num_supplies = ARRAY_SIZE(ad7380_supplies),
733 .internal_ref_mv = AD7380_INTERNAL_REF_MV,
734 .available_scan_masks = ad7380_4_channel_scan_masks,
735 .timing_specs = &ad7380_4_timing,
736 .max_conversion_rate_hz = 4 * MEGA,
737 };
738
739 static const struct ad7380_chip_info ad7383_4_chip_info = {
740 .name = "ad7383-4",
741 .channels = ad7383_4_channels,
742 .offload_channels = ad7383_4_offload_channels,
743 .num_channels = ARRAY_SIZE(ad7383_4_channels),
744 .num_simult_channels = 4,
745 .supplies = ad7380_supplies,
746 .num_supplies = ARRAY_SIZE(ad7380_supplies),
747 .internal_ref_mv = AD7380_INTERNAL_REF_MV,
748 .vcm_supplies = ad7380_4_channel_vcm_supplies,
749 .num_vcm_supplies = ARRAY_SIZE(ad7380_4_channel_vcm_supplies),
750 .available_scan_masks = ad7380_4_channel_scan_masks,
751 .timing_specs = &ad7380_4_timing,
752 .max_conversion_rate_hz = 4 * MEGA,
753 };
754
755 static const struct ad7380_chip_info ad7384_4_chip_info = {
756 .name = "ad7384-4",
757 .channels = ad7384_4_channels,
758 .offload_channels = ad7384_4_offload_channels,
759 .num_channels = ARRAY_SIZE(ad7384_4_channels),
760 .num_simult_channels = 4,
761 .supplies = ad7380_supplies,
762 .num_supplies = ARRAY_SIZE(ad7380_supplies),
763 .internal_ref_mv = AD7380_INTERNAL_REF_MV,
764 .vcm_supplies = ad7380_4_channel_vcm_supplies,
765 .num_vcm_supplies = ARRAY_SIZE(ad7380_4_channel_vcm_supplies),
766 .available_scan_masks = ad7380_4_channel_scan_masks,
767 .timing_specs = &ad7380_4_timing,
768 .max_conversion_rate_hz = 4 * MEGA,
769 };
770
771 static const struct ad7380_chip_info ad7386_4_chip_info = {
772 .name = "ad7386-4",
773 .channels = ad7386_4_channels,
774 .offload_channels = ad7386_4_offload_channels,
775 .num_channels = ARRAY_SIZE(ad7386_4_channels),
776 .num_simult_channels = 4,
777 .supplies = ad7380_supplies,
778 .num_supplies = ARRAY_SIZE(ad7380_supplies),
779 .internal_ref_mv = AD7380_INTERNAL_REF_MV,
780 .has_mux = true,
781 .available_scan_masks = ad7380_2x4_channel_scan_masks,
782 .timing_specs = &ad7380_4_timing,
783 .max_conversion_rate_hz = 4 * MEGA,
784 };
785
786 static const struct ad7380_chip_info ad7387_4_chip_info = {
787 .name = "ad7387-4",
788 .channels = ad7387_4_channels,
789 .offload_channels = ad7387_4_offload_channels,
790 .num_channels = ARRAY_SIZE(ad7387_4_channels),
791 .num_simult_channels = 4,
792 .supplies = ad7380_supplies,
793 .num_supplies = ARRAY_SIZE(ad7380_supplies),
794 .internal_ref_mv = AD7380_INTERNAL_REF_MV,
795 .has_mux = true,
796 .available_scan_masks = ad7380_2x4_channel_scan_masks,
797 .timing_specs = &ad7380_4_timing,
798 .max_conversion_rate_hz = 4 * MEGA,
799 };
800
801 static const struct ad7380_chip_info ad7388_4_chip_info = {
802 .name = "ad7388-4",
803 .channels = ad7388_4_channels,
804 .offload_channels = ad7388_4_offload_channels,
805 .num_channels = ARRAY_SIZE(ad7388_4_channels),
806 .num_simult_channels = 4,
807 .supplies = ad7380_supplies,
808 .num_supplies = ARRAY_SIZE(ad7380_supplies),
809 .internal_ref_mv = AD7380_INTERNAL_REF_MV,
810 .has_mux = true,
811 .available_scan_masks = ad7380_2x4_channel_scan_masks,
812 .timing_specs = &ad7380_4_timing,
813 .max_conversion_rate_hz = 4 * MEGA,
814 };
815
816 static const struct ad7380_chip_info ad7389_4_chip_info = {
817 .name = "ad7389-4",
818 .channels = ad7380_4_channels,
819 .offload_channels = ad7380_4_offload_channels,
820 .num_channels = ARRAY_SIZE(ad7380_4_channels),
821 .num_simult_channels = 4,
822 .supplies = ad7380_supplies,
823 .num_supplies = ARRAY_SIZE(ad7380_supplies),
824 .internal_ref_only = true,
825 .internal_ref_mv = AD7380_INTERNAL_REF_MV,
826 .available_scan_masks = ad7380_4_channel_scan_masks,
827 .timing_specs = &ad7380_4_timing,
828 .max_conversion_rate_hz = 4 * MEGA,
829 };
830
831 static const struct ad7380_chip_info adaq4370_4_chip_info = {
832 .name = "adaq4370-4",
833 .channels = adaq4380_4_channels,
834 .offload_channels = adaq4380_4_offload_channels,
835 .num_channels = ARRAY_SIZE(adaq4380_4_channels),
836 .num_simult_channels = 4,
837 .supplies = adaq4380_supplies,
838 .num_supplies = ARRAY_SIZE(adaq4380_supplies),
839 .internal_ref_only = true,
840 .internal_ref_mv = ADAQ4380_INTERNAL_REF_MV,
841 .has_hardware_gain = true,
842 .available_scan_masks = ad7380_4_channel_scan_masks,
843 .timing_specs = &ad7380_4_timing,
844 .max_conversion_rate_hz = 2 * MEGA,
845 };
846
847 static const struct ad7380_chip_info adaq4380_4_chip_info = {
848 .name = "adaq4380-4",
849 .channels = adaq4380_4_channels,
850 .offload_channels = adaq4380_4_offload_channels,
851 .num_channels = ARRAY_SIZE(adaq4380_4_channels),
852 .num_simult_channels = 4,
853 .supplies = adaq4380_supplies,
854 .num_supplies = ARRAY_SIZE(adaq4380_supplies),
855 .internal_ref_only = true,
856 .internal_ref_mv = ADAQ4380_INTERNAL_REF_MV,
857 .has_hardware_gain = true,
858 .available_scan_masks = ad7380_4_channel_scan_masks,
859 .timing_specs = &ad7380_4_timing,
860 .max_conversion_rate_hz = 4 * MEGA,
861 };
862
863 static const struct ad7380_chip_info adaq4381_4_chip_info = {
864 .name = "adaq4381-4",
865 .channels = adaq4381_4_channels,
866 .offload_channels = adaq4381_4_offload_channels,
867 .num_channels = ARRAY_SIZE(adaq4381_4_channels),
868 .num_simult_channels = 4,
869 .supplies = adaq4380_supplies,
870 .num_supplies = ARRAY_SIZE(adaq4380_supplies),
871 .internal_ref_only = true,
872 .internal_ref_mv = ADAQ4380_INTERNAL_REF_MV,
873 .has_hardware_gain = true,
874 .available_scan_masks = ad7380_4_channel_scan_masks,
875 .timing_specs = &ad7380_4_timing,
876 .max_conversion_rate_hz = 4 * MEGA,
877 };
878
879 static const struct spi_offload_config ad7380_offload_config = {
880 .capability_flags = SPI_OFFLOAD_CAP_TRIGGER |
881 SPI_OFFLOAD_CAP_RX_STREAM_DMA,
882 };
883
884 struct ad7380_state {
885 const struct ad7380_chip_info *chip_info;
886 struct spi_device *spi;
887 struct regmap *regmap;
888 bool resolution_boost_enabled;
889 unsigned int ch;
890 bool seq;
891 unsigned int vref_mv;
892 unsigned int vcm_mv[MAX_NUM_CHANNELS];
893 unsigned int gain_milli[MAX_NUM_CHANNELS];
894 /* xfers, message an buffer for reading sample data */
895 struct spi_transfer normal_xfer[2];
896 struct spi_message normal_msg;
897 struct spi_transfer seq_xfer[4];
898 struct spi_message seq_msg;
899 struct spi_transfer offload_xfer;
900 struct spi_message offload_msg;
901 struct spi_offload *offload;
902 struct spi_offload_trigger *offload_trigger;
903 unsigned long offload_trigger_hz;
904
905 int sample_freq_range[3];
906 /*
907 * DMA (thus cache coherency maintenance) requires the transfer buffers
908 * to live in their own cache lines.
909 *
910 * Make the buffer large enough for MAX_NUM_CHANNELS 32-bit samples and
911 * one 64-bit aligned 64-bit timestamp.
912 */
913 IIO_DECLARE_DMA_BUFFER_WITH_TS(u8, scan_data, MAX_NUM_CHANNELS * sizeof(u32));
914 /* buffers for reading/writing registers */
915 u16 tx;
916 u16 rx;
917 };
918
ad7380_regmap_reg_write(void * context,unsigned int reg,unsigned int val)919 static int ad7380_regmap_reg_write(void *context, unsigned int reg,
920 unsigned int val)
921 {
922 struct ad7380_state *st = context;
923 struct spi_transfer xfer = {
924 .speed_hz = AD7380_REG_WR_SPEED_HZ,
925 .bits_per_word = 16,
926 .len = 2,
927 .tx_buf = &st->tx,
928 };
929
930 st->tx = FIELD_PREP(AD7380_REG_WR, 1) |
931 FIELD_PREP(AD7380_REG_REGADDR, reg) |
932 FIELD_PREP(AD7380_REG_DATA, val);
933
934 return spi_sync_transfer(st->spi, &xfer, 1);
935 }
936
ad7380_regmap_reg_read(void * context,unsigned int reg,unsigned int * val)937 static int ad7380_regmap_reg_read(void *context, unsigned int reg,
938 unsigned int *val)
939 {
940 struct ad7380_state *st = context;
941 struct spi_transfer xfers[] = {
942 {
943 .speed_hz = AD7380_REG_WR_SPEED_HZ,
944 .bits_per_word = 16,
945 .len = 2,
946 .tx_buf = &st->tx,
947 .cs_change = 1,
948 .cs_change_delay = {
949 .value = st->chip_info->timing_specs->t_csh_ns,
950 .unit = SPI_DELAY_UNIT_NSECS,
951 },
952 }, {
953 .speed_hz = AD7380_REG_WR_SPEED_HZ,
954 .bits_per_word = 16,
955 .len = 2,
956 .rx_buf = &st->rx,
957 },
958 };
959 int ret;
960
961 st->tx = FIELD_PREP(AD7380_REG_WR, 0) |
962 FIELD_PREP(AD7380_REG_REGADDR, reg) |
963 FIELD_PREP(AD7380_REG_DATA, 0);
964
965 ret = spi_sync_transfer(st->spi, xfers, ARRAY_SIZE(xfers));
966 if (ret < 0)
967 return ret;
968
969 *val = FIELD_GET(AD7380_REG_DATA, st->rx);
970
971 return 0;
972 }
973
974 static const struct reg_default ad7380_reg_defaults[] = {
975 { AD7380_REG_ADDR_ALERT_LOW_TH, 0x800 },
976 { AD7380_REG_ADDR_ALERT_HIGH_TH, 0x7FF },
977 };
978
979 static const struct regmap_range ad7380_volatile_reg_ranges[] = {
980 regmap_reg_range(AD7380_REG_ADDR_CONFIG2, AD7380_REG_ADDR_ALERT),
981 };
982
983 static const struct regmap_access_table ad7380_volatile_regs = {
984 .yes_ranges = ad7380_volatile_reg_ranges,
985 .n_yes_ranges = ARRAY_SIZE(ad7380_volatile_reg_ranges),
986 };
987
988 static const struct regmap_config ad7380_regmap_config = {
989 .reg_bits = 3,
990 .val_bits = 12,
991 .reg_read = ad7380_regmap_reg_read,
992 .reg_write = ad7380_regmap_reg_write,
993 .max_register = AD7380_REG_ADDR_ALERT_HIGH_TH,
994 .can_sleep = true,
995 .reg_defaults = ad7380_reg_defaults,
996 .num_reg_defaults = ARRAY_SIZE(ad7380_reg_defaults),
997 .volatile_table = &ad7380_volatile_regs,
998 .cache_type = REGCACHE_MAPLE,
999 };
1000
ad7380_debugfs_reg_access(struct iio_dev * indio_dev,u32 reg,u32 writeval,u32 * readval)1001 static int ad7380_debugfs_reg_access(struct iio_dev *indio_dev, u32 reg,
1002 u32 writeval, u32 *readval)
1003 {
1004 struct ad7380_state *st = iio_priv(indio_dev);
1005 int ret;
1006
1007 if (!iio_device_claim_direct(indio_dev))
1008 return -EBUSY;
1009
1010 if (readval)
1011 ret = regmap_read(st->regmap, reg, readval);
1012 else
1013 ret = regmap_write(st->regmap, reg, writeval);
1014
1015 iio_device_release_direct(indio_dev);
1016
1017 return ret;
1018 }
1019
1020 /**
1021 * ad7380_regval_to_osr - convert OSR register value to ratio
1022 * @regval: register value to check
1023 *
1024 * Returns: the ratio corresponding to the OSR register. If regval is not in
1025 * bound, return 1 (oversampling disabled)
1026 *
1027 */
ad7380_regval_to_osr(unsigned int regval)1028 static int ad7380_regval_to_osr(unsigned int regval)
1029 {
1030 if (regval >= ARRAY_SIZE(ad7380_oversampling_ratios))
1031 return 1;
1032
1033 return ad7380_oversampling_ratios[regval];
1034 }
1035
ad7380_get_osr(struct ad7380_state * st,int * val)1036 static int ad7380_get_osr(struct ad7380_state *st, int *val)
1037 {
1038 u32 tmp;
1039 int ret;
1040
1041 ret = regmap_read(st->regmap, AD7380_REG_ADDR_CONFIG1, &tmp);
1042 if (ret)
1043 return ret;
1044
1045 *val = ad7380_regval_to_osr(FIELD_GET(AD7380_CONFIG1_OSR, tmp));
1046
1047 return 0;
1048 }
1049
1050 /*
1051 * When switching channel, the ADC require an additional settling time.
1052 * According to the datasheet, data is value on the third CS low. We already
1053 * have an extra toggle before each read (either direct reads or buffered reads)
1054 * to sample correct data, so we just add a single CS toggle at the end of the
1055 * register write.
1056 */
ad7380_set_ch(struct ad7380_state * st,unsigned int ch)1057 static int ad7380_set_ch(struct ad7380_state *st, unsigned int ch)
1058 {
1059 struct spi_transfer xfer = {
1060 .delay = {
1061 .value = T_CONVERT_NS,
1062 .unit = SPI_DELAY_UNIT_NSECS,
1063 }
1064 };
1065 int oversampling_ratio, ret;
1066
1067 if (st->ch == ch)
1068 return 0;
1069
1070 ret = ad7380_get_osr(st, &oversampling_ratio);
1071 if (ret)
1072 return ret;
1073
1074 ret = regmap_update_bits(st->regmap,
1075 AD7380_REG_ADDR_CONFIG1,
1076 AD7380_CONFIG1_CH,
1077 FIELD_PREP(AD7380_CONFIG1_CH, ch));
1078
1079 if (ret)
1080 return ret;
1081
1082 st->ch = ch;
1083
1084 if (oversampling_ratio > 1)
1085 xfer.delay.value = T_CONVERT_0_NS +
1086 T_CONVERT_X_NS * (oversampling_ratio - 1) *
1087 st->chip_info->num_simult_channels / AD7380_NUM_SDO_LINES;
1088
1089 return spi_sync_transfer(st->spi, &xfer, 1);
1090 }
1091
1092 /**
1093 * ad7380_update_xfers - update the SPI transfers base on the current scan type
1094 * @st: device instance specific state
1095 * @scan_type: current scan type
1096 */
ad7380_update_xfers(struct ad7380_state * st,const struct iio_scan_type * scan_type)1097 static int ad7380_update_xfers(struct ad7380_state *st,
1098 const struct iio_scan_type *scan_type)
1099 {
1100 struct spi_transfer *xfer = st->seq ? st->seq_xfer : st->normal_xfer;
1101 unsigned int t_convert = T_CONVERT_NS;
1102 int oversampling_ratio, ret;
1103
1104 /*
1105 * In the case of oversampling, conversion time is higher than in normal
1106 * mode. Technically T_CONVERT_X_NS is lower for some chips, but we use
1107 * the maximum value for simplicity for now.
1108 */
1109 ret = ad7380_get_osr(st, &oversampling_ratio);
1110 if (ret)
1111 return ret;
1112
1113 if (oversampling_ratio > 1)
1114 t_convert = T_CONVERT_0_NS + T_CONVERT_X_NS *
1115 (oversampling_ratio - 1) *
1116 st->chip_info->num_simult_channels / AD7380_NUM_SDO_LINES;
1117
1118 if (st->seq) {
1119 xfer[0].delay.value = xfer[1].delay.value = t_convert;
1120 xfer[0].delay.unit = xfer[1].delay.unit = SPI_DELAY_UNIT_NSECS;
1121 xfer[2].bits_per_word = xfer[3].bits_per_word =
1122 scan_type->realbits;
1123 xfer[2].len = xfer[3].len =
1124 AD7380_SPI_BYTES(scan_type) *
1125 st->chip_info->num_simult_channels;
1126 xfer[3].rx_buf = xfer[2].rx_buf + xfer[2].len;
1127 /* Additional delay required here when oversampling is enabled */
1128 if (oversampling_ratio > 1)
1129 xfer[2].delay.value = t_convert;
1130 else
1131 xfer[2].delay.value = 0;
1132 xfer[2].delay.unit = SPI_DELAY_UNIT_NSECS;
1133 } else {
1134 xfer[0].delay.value = t_convert;
1135 xfer[0].delay.unit = SPI_DELAY_UNIT_NSECS;
1136 xfer[1].bits_per_word = scan_type->realbits;
1137 xfer[1].len = AD7380_SPI_BYTES(scan_type) *
1138 st->chip_info->num_simult_channels;
1139 }
1140
1141 return 0;
1142 }
1143
ad7380_set_sample_freq(struct ad7380_state * st,int val)1144 static int ad7380_set_sample_freq(struct ad7380_state *st, int val)
1145 {
1146 struct spi_offload_trigger_config config = {
1147 .type = SPI_OFFLOAD_TRIGGER_PERIODIC,
1148 .periodic = {
1149 .frequency_hz = val,
1150 },
1151 };
1152 int ret;
1153
1154 ret = spi_offload_trigger_validate(st->offload_trigger, &config);
1155 if (ret)
1156 return ret;
1157
1158 st->offload_trigger_hz = config.periodic.frequency_hz;
1159
1160 return 0;
1161 }
1162
ad7380_init_offload_msg(struct ad7380_state * st,struct iio_dev * indio_dev)1163 static int ad7380_init_offload_msg(struct ad7380_state *st,
1164 struct iio_dev *indio_dev)
1165 {
1166 struct spi_transfer *xfer = &st->offload_xfer;
1167 struct device *dev = &st->spi->dev;
1168 const struct iio_scan_type *scan_type;
1169 int ret;
1170
1171 scan_type = iio_get_current_scan_type(indio_dev,
1172 &indio_dev->channels[0]);
1173 if (IS_ERR(scan_type))
1174 return PTR_ERR(scan_type);
1175
1176 if (st->chip_info->has_mux) {
1177 int index;
1178
1179 ret = iio_active_scan_mask_index(indio_dev);
1180 if (ret < 0)
1181 return ret;
1182
1183 index = ret;
1184 if (index == AD7380_SCAN_MASK_SEQ) {
1185 ret = regmap_set_bits(st->regmap, AD7380_REG_ADDR_CONFIG1,
1186 AD7380_CONFIG1_SEQ);
1187 if (ret)
1188 return ret;
1189
1190 st->seq = true;
1191 } else {
1192 ret = ad7380_set_ch(st, index);
1193 if (ret)
1194 return ret;
1195 }
1196 }
1197
1198 xfer->bits_per_word = scan_type->realbits;
1199 xfer->offload_flags = SPI_OFFLOAD_XFER_RX_STREAM;
1200 xfer->len = AD7380_SPI_BYTES(scan_type) * st->chip_info->num_simult_channels;
1201
1202 spi_message_init_with_transfers(&st->offload_msg, xfer, 1);
1203 st->offload_msg.offload = st->offload;
1204
1205 ret = spi_optimize_message(st->spi, &st->offload_msg);
1206 if (ret) {
1207 dev_err(dev, "failed to prepare offload msg, err: %d\n",
1208 ret);
1209 return ret;
1210 }
1211
1212 return 0;
1213 }
1214
ad7380_offload_buffer_postenable(struct iio_dev * indio_dev)1215 static int ad7380_offload_buffer_postenable(struct iio_dev *indio_dev)
1216 {
1217 struct ad7380_state *st = iio_priv(indio_dev);
1218 struct spi_offload_trigger_config config = {
1219 .type = SPI_OFFLOAD_TRIGGER_PERIODIC,
1220 .periodic = {
1221 .frequency_hz = st->offload_trigger_hz,
1222 },
1223 };
1224 int ret;
1225
1226 ret = ad7380_init_offload_msg(st, indio_dev);
1227 if (ret)
1228 return ret;
1229
1230 /*
1231 * When the sequencer is required to read all channels, we need to
1232 * trigger twice per sample period in order to read one complete set
1233 * of samples.
1234 */
1235 if (st->seq)
1236 config.periodic.frequency_hz *= 2;
1237
1238 ret = spi_offload_trigger_enable(st->offload, st->offload_trigger, &config);
1239 if (ret)
1240 spi_unoptimize_message(&st->offload_msg);
1241
1242 return ret;
1243 }
1244
ad7380_offload_buffer_predisable(struct iio_dev * indio_dev)1245 static int ad7380_offload_buffer_predisable(struct iio_dev *indio_dev)
1246 {
1247 struct ad7380_state *st = iio_priv(indio_dev);
1248 int ret;
1249
1250 spi_offload_trigger_disable(st->offload, st->offload_trigger);
1251 spi_unoptimize_message(&st->offload_msg);
1252
1253 if (st->seq) {
1254 ret = regmap_update_bits(st->regmap,
1255 AD7380_REG_ADDR_CONFIG1,
1256 AD7380_CONFIG1_SEQ,
1257 FIELD_PREP(AD7380_CONFIG1_SEQ, 0));
1258 if (ret)
1259 return ret;
1260
1261 st->seq = false;
1262 }
1263
1264 return 0;
1265 }
1266
1267 static const struct iio_buffer_setup_ops ad7380_offload_buffer_setup_ops = {
1268 .postenable = ad7380_offload_buffer_postenable,
1269 .predisable = ad7380_offload_buffer_predisable,
1270 };
1271
ad7380_triggered_buffer_preenable(struct iio_dev * indio_dev)1272 static int ad7380_triggered_buffer_preenable(struct iio_dev *indio_dev)
1273 {
1274 struct ad7380_state *st = iio_priv(indio_dev);
1275 const struct iio_scan_type *scan_type;
1276 struct spi_message *msg = &st->normal_msg;
1277 int ret;
1278
1279 /*
1280 * Currently, we always read all channels at the same time. The scan_type
1281 * is the same for all channels, so we just pass the first channel.
1282 */
1283 scan_type = iio_get_current_scan_type(indio_dev, &indio_dev->channels[0]);
1284 if (IS_ERR(scan_type))
1285 return PTR_ERR(scan_type);
1286
1287 if (st->chip_info->has_mux) {
1288 unsigned int index;
1289
1290 /*
1291 * Depending on the requested scan_mask and current state,
1292 * we need to either change CH bit, or enable sequencer mode
1293 * to sample correct data.
1294 * Sequencer mode is enabled if active mask corresponds to all
1295 * IIO channels enabled. Otherwise, CH bit is set.
1296 */
1297 ret = iio_active_scan_mask_index(indio_dev);
1298 if (ret < 0)
1299 return ret;
1300
1301 index = ret;
1302 if (index == AD7380_SCAN_MASK_SEQ) {
1303 ret = regmap_update_bits(st->regmap,
1304 AD7380_REG_ADDR_CONFIG1,
1305 AD7380_CONFIG1_SEQ,
1306 FIELD_PREP(AD7380_CONFIG1_SEQ, 1));
1307 if (ret)
1308 return ret;
1309 msg = &st->seq_msg;
1310 st->seq = true;
1311 } else {
1312 ret = ad7380_set_ch(st, index);
1313 if (ret)
1314 return ret;
1315 }
1316
1317 }
1318
1319 ret = ad7380_update_xfers(st, scan_type);
1320 if (ret)
1321 return ret;
1322
1323 return spi_optimize_message(st->spi, msg);
1324 }
1325
ad7380_triggered_buffer_postdisable(struct iio_dev * indio_dev)1326 static int ad7380_triggered_buffer_postdisable(struct iio_dev *indio_dev)
1327 {
1328 struct ad7380_state *st = iio_priv(indio_dev);
1329 struct spi_message *msg = &st->normal_msg;
1330 int ret;
1331
1332 if (st->seq) {
1333 ret = regmap_update_bits(st->regmap,
1334 AD7380_REG_ADDR_CONFIG1,
1335 AD7380_CONFIG1_SEQ,
1336 FIELD_PREP(AD7380_CONFIG1_SEQ, 0));
1337 if (ret)
1338 return ret;
1339
1340 msg = &st->seq_msg;
1341 st->seq = false;
1342 }
1343
1344 spi_unoptimize_message(msg);
1345
1346 return 0;
1347 }
1348
1349 static const struct iio_buffer_setup_ops ad7380_buffer_setup_ops = {
1350 .preenable = ad7380_triggered_buffer_preenable,
1351 .postdisable = ad7380_triggered_buffer_postdisable,
1352 };
1353
ad7380_trigger_handler(int irq,void * p)1354 static irqreturn_t ad7380_trigger_handler(int irq, void *p)
1355 {
1356 struct iio_poll_func *pf = p;
1357 struct iio_dev *indio_dev = pf->indio_dev;
1358 struct ad7380_state *st = iio_priv(indio_dev);
1359 struct spi_message *msg = st->seq ? &st->seq_msg : &st->normal_msg;
1360 int ret;
1361
1362 ret = spi_sync(st->spi, msg);
1363 if (ret)
1364 goto out;
1365
1366 iio_push_to_buffers_with_ts(indio_dev, &st->scan_data, sizeof(st->scan_data),
1367 pf->timestamp);
1368
1369 out:
1370 iio_trigger_notify_done(indio_dev->trig);
1371
1372 return IRQ_HANDLED;
1373 }
1374
ad7380_read_direct(struct ad7380_state * st,unsigned int scan_index,const struct iio_scan_type * scan_type,int * val)1375 static int ad7380_read_direct(struct ad7380_state *st, unsigned int scan_index,
1376 const struct iio_scan_type *scan_type, int *val)
1377 {
1378 unsigned int index = scan_index;
1379 int ret;
1380
1381 if (st->chip_info->has_mux) {
1382 unsigned int ch = 0;
1383
1384 if (index >= st->chip_info->num_simult_channels) {
1385 index -= st->chip_info->num_simult_channels;
1386 ch = 1;
1387 }
1388
1389 ret = ad7380_set_ch(st, ch);
1390 if (ret)
1391 return ret;
1392 }
1393
1394 ret = ad7380_update_xfers(st, scan_type);
1395 if (ret)
1396 return ret;
1397
1398 ret = spi_sync(st->spi, &st->normal_msg);
1399 if (ret < 0)
1400 return ret;
1401
1402 if (scan_type->realbits > 16) {
1403 if (scan_type->sign == 's')
1404 *val = sign_extend32(*(u32 *)(st->scan_data + 4 * index),
1405 scan_type->realbits - 1);
1406 else
1407 *val = *(u32 *)(st->scan_data + 4 * index) &
1408 GENMASK(scan_type->realbits - 1, 0);
1409 } else {
1410 if (scan_type->sign == 's')
1411 *val = sign_extend32(*(u16 *)(st->scan_data + 2 * index),
1412 scan_type->realbits - 1);
1413 else
1414 *val = *(u16 *)(st->scan_data + 2 * index) &
1415 GENMASK(scan_type->realbits - 1, 0);
1416 }
1417
1418 return IIO_VAL_INT;
1419 }
1420
ad7380_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long info)1421 static int ad7380_read_raw(struct iio_dev *indio_dev,
1422 struct iio_chan_spec const *chan,
1423 int *val, int *val2, long info)
1424 {
1425 struct ad7380_state *st = iio_priv(indio_dev);
1426 const struct iio_scan_type *scan_type;
1427 int ret;
1428
1429 scan_type = iio_get_current_scan_type(indio_dev, chan);
1430
1431 if (IS_ERR(scan_type))
1432 return PTR_ERR(scan_type);
1433
1434 switch (info) {
1435 case IIO_CHAN_INFO_RAW:
1436 if (!iio_device_claim_direct(indio_dev))
1437 return -EBUSY;
1438
1439 ret = ad7380_read_direct(st, chan->scan_index,
1440 scan_type, val);
1441
1442 iio_device_release_direct(indio_dev);
1443
1444 return ret;
1445 case IIO_CHAN_INFO_SCALE:
1446 /*
1447 * According to the datasheet, the LSB size is:
1448 * * (2 × VREF) / 2^N, for differential chips
1449 * * VREF / 2^N, for pseudo-differential chips
1450 * where N is the ADC resolution (i.e realbits)
1451 *
1452 * The gain is stored as a fraction of 1000 and, as we need to
1453 * divide vref_mv by the gain, we invert the gain/1000 fraction.
1454 */
1455 if (st->chip_info->has_hardware_gain)
1456 *val = mult_frac(st->vref_mv, MILLI,
1457 st->gain_milli[chan->scan_index]);
1458 else
1459 *val = st->vref_mv;
1460 *val2 = scan_type->realbits - chan->differential;
1461
1462 return IIO_VAL_FRACTIONAL_LOG2;
1463 case IIO_CHAN_INFO_OFFSET:
1464 /*
1465 * According to IIO ABI, offset is applied before scale,
1466 * so offset is: vcm_mv / scale
1467 */
1468 *val = st->vcm_mv[chan->channel] * (1 << scan_type->realbits)
1469 / st->vref_mv;
1470
1471 return IIO_VAL_INT;
1472 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
1473 if (!iio_device_claim_direct(indio_dev))
1474 return -EBUSY;
1475
1476 ret = ad7380_get_osr(st, val);
1477
1478 iio_device_release_direct(indio_dev);
1479
1480 if (ret)
1481 return ret;
1482
1483 return IIO_VAL_INT;
1484 case IIO_CHAN_INFO_SAMP_FREQ:
1485 *val = st->offload_trigger_hz;
1486 return IIO_VAL_INT;
1487 default:
1488 return -EINVAL;
1489 }
1490 }
1491
ad7380_read_avail(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,const int ** vals,int * type,int * length,long mask)1492 static int ad7380_read_avail(struct iio_dev *indio_dev,
1493 struct iio_chan_spec const *chan,
1494 const int **vals, int *type, int *length,
1495 long mask)
1496 {
1497 struct ad7380_state *st = iio_priv(indio_dev);
1498
1499 switch (mask) {
1500 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
1501 *vals = ad7380_oversampling_ratios;
1502 *length = ARRAY_SIZE(ad7380_oversampling_ratios);
1503 *type = IIO_VAL_INT;
1504
1505 return IIO_AVAIL_LIST;
1506 case IIO_CHAN_INFO_SAMP_FREQ:
1507 *vals = st->sample_freq_range;
1508 *type = IIO_VAL_INT;
1509 return IIO_AVAIL_RANGE;
1510 default:
1511 return -EINVAL;
1512 }
1513 }
1514
1515 /**
1516 * ad7380_osr_to_regval - convert ratio to OSR register value
1517 * @ratio: ratio to check
1518 *
1519 * Check if ratio is present in the list of available ratios and return the
1520 * corresponding value that needs to be written to the register to select that
1521 * ratio.
1522 *
1523 * Returns: register value (0 to 7) or -EINVAL if there is not an exact match
1524 */
ad7380_osr_to_regval(int ratio)1525 static int ad7380_osr_to_regval(int ratio)
1526 {
1527 int i;
1528
1529 for (i = 0; i < ARRAY_SIZE(ad7380_oversampling_ratios); i++) {
1530 if (ratio == ad7380_oversampling_ratios[i])
1531 return i;
1532 }
1533
1534 return -EINVAL;
1535 }
1536
ad7380_set_oversampling_ratio(struct ad7380_state * st,int val)1537 static int ad7380_set_oversampling_ratio(struct ad7380_state *st, int val)
1538 {
1539 int ret, osr, boost;
1540
1541 osr = ad7380_osr_to_regval(val);
1542 if (osr < 0)
1543 return osr;
1544
1545 /* always enable resolution boost when oversampling is enabled */
1546 boost = osr > 0 ? 1 : 0;
1547
1548 ret = regmap_update_bits(st->regmap,
1549 AD7380_REG_ADDR_CONFIG1,
1550 AD7380_CONFIG1_OSR | AD7380_CONFIG1_RES,
1551 FIELD_PREP(AD7380_CONFIG1_OSR, osr) |
1552 FIELD_PREP(AD7380_CONFIG1_RES, boost));
1553
1554 if (ret)
1555 return ret;
1556
1557 st->resolution_boost_enabled = boost;
1558
1559 /*
1560 * Perform a soft reset. This will flush the oversampling
1561 * block and FIFO but will maintain the content of the
1562 * configurable registers.
1563 */
1564 ret = regmap_update_bits(st->regmap,
1565 AD7380_REG_ADDR_CONFIG2,
1566 AD7380_CONFIG2_RESET,
1567 FIELD_PREP(AD7380_CONFIG2_RESET,
1568 AD7380_CONFIG2_RESET_SOFT));
1569 return ret;
1570 }
ad7380_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)1571 static int ad7380_write_raw(struct iio_dev *indio_dev,
1572 struct iio_chan_spec const *chan, int val,
1573 int val2, long mask)
1574 {
1575 struct ad7380_state *st = iio_priv(indio_dev);
1576 int ret;
1577
1578 switch (mask) {
1579 case IIO_CHAN_INFO_SAMP_FREQ:
1580 if (val < 1)
1581 return -EINVAL;
1582 return ad7380_set_sample_freq(st, val);
1583 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
1584 if (!iio_device_claim_direct(indio_dev))
1585 return -EBUSY;
1586
1587 ret = ad7380_set_oversampling_ratio(st, val);
1588
1589 iio_device_release_direct(indio_dev);
1590
1591 return ret;
1592 default:
1593 return -EINVAL;
1594 }
1595 }
1596
ad7380_get_current_scan_type(const struct iio_dev * indio_dev,const struct iio_chan_spec * chan)1597 static int ad7380_get_current_scan_type(const struct iio_dev *indio_dev,
1598 const struct iio_chan_spec *chan)
1599 {
1600 struct ad7380_state *st = iio_priv(indio_dev);
1601
1602 return st->resolution_boost_enabled ? AD7380_SCAN_TYPE_RESOLUTION_BOOST
1603 : AD7380_SCAN_TYPE_NORMAL;
1604 }
1605
ad7380_read_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir)1606 static int ad7380_read_event_config(struct iio_dev *indio_dev,
1607 const struct iio_chan_spec *chan,
1608 enum iio_event_type type,
1609 enum iio_event_direction dir)
1610 {
1611 struct ad7380_state *st = iio_priv(indio_dev);
1612 int tmp, ret;
1613
1614 if (!iio_device_claim_direct(indio_dev))
1615 return -EBUSY;
1616
1617 ret = regmap_read(st->regmap, AD7380_REG_ADDR_CONFIG1, &tmp);
1618
1619 iio_device_release_direct(indio_dev);
1620
1621 if (ret)
1622 return ret;
1623
1624 return FIELD_GET(AD7380_CONFIG1_ALERTEN, tmp);
1625 }
1626
ad7380_write_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,bool state)1627 static int ad7380_write_event_config(struct iio_dev *indio_dev,
1628 const struct iio_chan_spec *chan,
1629 enum iio_event_type type,
1630 enum iio_event_direction dir,
1631 bool state)
1632 {
1633 struct ad7380_state *st = iio_priv(indio_dev);
1634 int ret;
1635
1636 if (!iio_device_claim_direct(indio_dev))
1637 return -EBUSY;
1638
1639 ret = regmap_update_bits(st->regmap,
1640 AD7380_REG_ADDR_CONFIG1,
1641 AD7380_CONFIG1_ALERTEN,
1642 FIELD_PREP(AD7380_CONFIG1_ALERTEN, state));
1643
1644 iio_device_release_direct(indio_dev);
1645
1646 return ret;
1647 }
1648
ad7380_get_alert_th(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_direction dir,int * val)1649 static int ad7380_get_alert_th(struct iio_dev *indio_dev,
1650 const struct iio_chan_spec *chan,
1651 enum iio_event_direction dir,
1652 int *val)
1653 {
1654 struct ad7380_state *st = iio_priv(indio_dev);
1655 const struct iio_scan_type *scan_type;
1656 int ret, tmp, shift;
1657
1658 scan_type = iio_get_current_scan_type(indio_dev, chan);
1659 if (IS_ERR(scan_type))
1660 return PTR_ERR(scan_type);
1661
1662 /*
1663 * The register value is 12-bits and is compared to the most significant
1664 * bits of raw value, therefore a shift is required to convert this to
1665 * the same scale as the raw value.
1666 */
1667 shift = scan_type->realbits - 12;
1668
1669 switch (dir) {
1670 case IIO_EV_DIR_RISING:
1671 ret = regmap_read(st->regmap,
1672 AD7380_REG_ADDR_ALERT_HIGH_TH,
1673 &tmp);
1674 if (ret)
1675 return ret;
1676
1677 *val = FIELD_GET(AD7380_ALERT_HIGH_TH, tmp) << shift;
1678 return IIO_VAL_INT;
1679 case IIO_EV_DIR_FALLING:
1680 ret = regmap_read(st->regmap,
1681 AD7380_REG_ADDR_ALERT_LOW_TH,
1682 &tmp);
1683 if (ret)
1684 return ret;
1685
1686 *val = FIELD_GET(AD7380_ALERT_LOW_TH, tmp) << shift;
1687 return IIO_VAL_INT;
1688 default:
1689 return -EINVAL;
1690 }
1691 }
1692
ad7380_read_event_value(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int * val,int * val2)1693 static int ad7380_read_event_value(struct iio_dev *indio_dev,
1694 const struct iio_chan_spec *chan,
1695 enum iio_event_type type,
1696 enum iio_event_direction dir,
1697 enum iio_event_info info,
1698 int *val, int *val2)
1699 {
1700 int ret;
1701
1702 switch (info) {
1703 case IIO_EV_INFO_VALUE:
1704 if (!iio_device_claim_direct(indio_dev))
1705 return -EBUSY;
1706
1707 ret = ad7380_get_alert_th(indio_dev, chan, dir, val);
1708
1709 iio_device_release_direct(indio_dev);
1710 return ret;
1711 default:
1712 return -EINVAL;
1713 }
1714 }
1715
ad7380_set_alert_th(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_direction dir,int val)1716 static int ad7380_set_alert_th(struct iio_dev *indio_dev,
1717 const struct iio_chan_spec *chan,
1718 enum iio_event_direction dir,
1719 int val)
1720 {
1721 struct ad7380_state *st = iio_priv(indio_dev);
1722 const struct iio_scan_type *scan_type;
1723 u16 th;
1724
1725 /*
1726 * According to the datasheet,
1727 * AD7380_REG_ADDR_ALERT_HIGH_TH[11:0] are the 12 MSB of the
1728 * 16-bits internal alert high register. LSB are set to 0xf.
1729 * AD7380_REG_ADDR_ALERT_LOW_TH[11:0] are the 12 MSB of the
1730 * 16 bits internal alert low register. LSB are set to 0x0.
1731 *
1732 * When alert is enabled the conversion from the adc is compared
1733 * immediately to the alert high/low thresholds, before any
1734 * oversampling. This means that the thresholds are the same for
1735 * normal mode and oversampling mode.
1736 */
1737
1738 /* Extract the 12 MSB of val */
1739 scan_type = iio_get_current_scan_type(indio_dev, chan);
1740 if (IS_ERR(scan_type))
1741 return PTR_ERR(scan_type);
1742
1743 th = val >> (scan_type->realbits - 12);
1744
1745 switch (dir) {
1746 case IIO_EV_DIR_RISING:
1747 return regmap_write(st->regmap,
1748 AD7380_REG_ADDR_ALERT_HIGH_TH,
1749 th);
1750 case IIO_EV_DIR_FALLING:
1751 return regmap_write(st->regmap,
1752 AD7380_REG_ADDR_ALERT_LOW_TH,
1753 th);
1754 default:
1755 return -EINVAL;
1756 }
1757 }
1758
ad7380_write_event_value(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int val,int val2)1759 static int ad7380_write_event_value(struct iio_dev *indio_dev,
1760 const struct iio_chan_spec *chan,
1761 enum iio_event_type type,
1762 enum iio_event_direction dir,
1763 enum iio_event_info info,
1764 int val, int val2)
1765 {
1766 int ret;
1767
1768 switch (info) {
1769 case IIO_EV_INFO_VALUE:
1770 if (!iio_device_claim_direct(indio_dev))
1771 return -EBUSY;
1772
1773 ret = ad7380_set_alert_th(indio_dev, chan, dir, val);
1774
1775 iio_device_release_direct(indio_dev);
1776 return ret;
1777 default:
1778 return -EINVAL;
1779 }
1780 }
1781
1782 static const struct iio_info ad7380_info = {
1783 .read_raw = &ad7380_read_raw,
1784 .read_avail = &ad7380_read_avail,
1785 .write_raw = &ad7380_write_raw,
1786 .get_current_scan_type = &ad7380_get_current_scan_type,
1787 .debugfs_reg_access = &ad7380_debugfs_reg_access,
1788 .read_event_config = &ad7380_read_event_config,
1789 .write_event_config = &ad7380_write_event_config,
1790 .read_event_value = &ad7380_read_event_value,
1791 .write_event_value = &ad7380_write_event_value,
1792 };
1793
ad7380_init(struct ad7380_state * st,bool external_ref_en)1794 static int ad7380_init(struct ad7380_state *st, bool external_ref_en)
1795 {
1796 int ret;
1797
1798 /* perform hard reset */
1799 ret = regmap_update_bits(st->regmap, AD7380_REG_ADDR_CONFIG2,
1800 AD7380_CONFIG2_RESET,
1801 FIELD_PREP(AD7380_CONFIG2_RESET,
1802 AD7380_CONFIG2_RESET_HARD));
1803 if (ret < 0)
1804 return ret;
1805
1806 if (external_ref_en) {
1807 /* select external reference voltage */
1808 ret = regmap_set_bits(st->regmap, AD7380_REG_ADDR_CONFIG1,
1809 AD7380_CONFIG1_REFSEL);
1810 if (ret < 0)
1811 return ret;
1812 }
1813
1814 /* This is the default value after reset. */
1815 st->ch = 0;
1816 st->seq = false;
1817
1818 /* SPI 1-wire mode */
1819 return regmap_update_bits(st->regmap, AD7380_REG_ADDR_CONFIG2,
1820 AD7380_CONFIG2_SDO,
1821 FIELD_PREP(AD7380_CONFIG2_SDO,
1822 AD7380_NUM_SDO_LINES));
1823 }
1824
ad7380_probe_spi_offload(struct iio_dev * indio_dev,struct ad7380_state * st)1825 static int ad7380_probe_spi_offload(struct iio_dev *indio_dev,
1826 struct ad7380_state *st)
1827 {
1828 struct spi_device *spi = st->spi;
1829 struct device *dev = &spi->dev;
1830 struct dma_chan *rx_dma;
1831 int sample_rate, ret;
1832
1833 indio_dev->setup_ops = &ad7380_offload_buffer_setup_ops;
1834 indio_dev->channels = st->chip_info->offload_channels;
1835 /* Just removing the timestamp channel. */
1836 indio_dev->num_channels--;
1837
1838 st->offload_trigger = devm_spi_offload_trigger_get(dev, st->offload,
1839 SPI_OFFLOAD_TRIGGER_PERIODIC);
1840 if (IS_ERR(st->offload_trigger))
1841 return dev_err_probe(dev, PTR_ERR(st->offload_trigger),
1842 "failed to get offload trigger\n");
1843
1844 sample_rate = st->chip_info->max_conversion_rate_hz *
1845 AD7380_NUM_SDO_LINES / st->chip_info->num_simult_channels;
1846
1847 st->sample_freq_range[0] = 1; /* min */
1848 st->sample_freq_range[1] = 1; /* step */
1849 st->sample_freq_range[2] = sample_rate; /* max */
1850
1851 /*
1852 * Starting with a quite low frequency, to allow oversampling x32,
1853 * user is then reponsible to adjust the frequency for the specific case.
1854 */
1855 ret = ad7380_set_sample_freq(st, sample_rate / 32);
1856 if (ret)
1857 return ret;
1858
1859 rx_dma = devm_spi_offload_rx_stream_request_dma_chan(dev, st->offload);
1860 if (IS_ERR(rx_dma))
1861 return dev_err_probe(dev, PTR_ERR(rx_dma),
1862 "failed to get offload RX DMA\n");
1863
1864 ret = devm_iio_dmaengine_buffer_setup_with_handle(dev, indio_dev,
1865 rx_dma, IIO_BUFFER_DIRECTION_IN);
1866 if (ret)
1867 return dev_err_probe(dev, ret, "cannot setup dma buffer\n");
1868
1869 return 0;
1870 }
1871
ad7380_probe(struct spi_device * spi)1872 static int ad7380_probe(struct spi_device *spi)
1873 {
1874 struct device *dev = &spi->dev;
1875 struct iio_dev *indio_dev;
1876 struct ad7380_state *st;
1877 bool external_ref_en;
1878 int ret, i;
1879
1880 indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
1881 if (!indio_dev)
1882 return -ENOMEM;
1883
1884 st = iio_priv(indio_dev);
1885 st->spi = spi;
1886 st->chip_info = spi_get_device_match_data(spi);
1887 if (!st->chip_info)
1888 return dev_err_probe(dev, -EINVAL, "missing match data\n");
1889
1890 ret = devm_regulator_bulk_get_enable(dev, st->chip_info->num_supplies,
1891 st->chip_info->supplies);
1892
1893 if (ret)
1894 return dev_err_probe(dev, ret,
1895 "Failed to enable power supplies\n");
1896 fsleep(T_POWERUP_US);
1897
1898 if (st->chip_info->internal_ref_only) {
1899 /*
1900 * ADAQ chips use fixed internal reference but still
1901 * require a specific reference supply to power it.
1902 * "refin" is already enabled with other power supplies
1903 * in bulk_get_enable().
1904 */
1905
1906 st->vref_mv = st->chip_info->internal_ref_mv;
1907
1908 /* these chips don't have a register bit for this */
1909 external_ref_en = false;
1910 } else if (st->chip_info->external_ref_only) {
1911 ret = devm_regulator_get_enable_read_voltage(dev, "refin");
1912 if (ret < 0)
1913 return dev_err_probe(dev, ret,
1914 "Failed to get refin regulator\n");
1915
1916 st->vref_mv = ret / 1000;
1917
1918 /* these chips don't have a register bit for this */
1919 external_ref_en = false;
1920 } else {
1921 /*
1922 * If there is no REFIO supply, then it means that we are using
1923 * the internal reference, otherwise REFIO is reference voltage.
1924 */
1925 ret = devm_regulator_get_enable_read_voltage(dev, "refio");
1926 if (ret < 0 && ret != -ENODEV)
1927 return dev_err_probe(dev, ret,
1928 "Failed to get refio regulator\n");
1929
1930 external_ref_en = ret != -ENODEV;
1931 st->vref_mv = external_ref_en ? ret / 1000
1932 : st->chip_info->internal_ref_mv;
1933 }
1934
1935 if (st->chip_info->num_vcm_supplies > ARRAY_SIZE(st->vcm_mv))
1936 return dev_err_probe(dev, -EINVAL,
1937 "invalid number of VCM supplies\n");
1938
1939 /*
1940 * pseudo-differential chips have common mode supplies for the negative
1941 * input pin.
1942 */
1943 for (i = 0; i < st->chip_info->num_vcm_supplies; i++) {
1944 const char *vcm = st->chip_info->vcm_supplies[i];
1945
1946 ret = devm_regulator_get_enable_read_voltage(dev, vcm);
1947 if (ret < 0)
1948 return dev_err_probe(dev, ret,
1949 "Failed to get %s regulator\n",
1950 vcm);
1951
1952 st->vcm_mv[i] = ret / 1000;
1953 }
1954
1955 for (i = 0; i < MAX_NUM_CHANNELS; i++)
1956 st->gain_milli[i] = AD7380_DEFAULT_GAIN_MILLI;
1957
1958 if (st->chip_info->has_hardware_gain) {
1959 device_for_each_child_node_scoped(dev, node) {
1960 unsigned int channel;
1961 int gain_idx;
1962 u16 gain;
1963
1964 ret = fwnode_property_read_u32(node, "reg", &channel);
1965 if (ret)
1966 return dev_err_probe(dev, ret,
1967 "Failed to read reg property\n");
1968
1969 if (channel >= st->chip_info->num_channels - 1)
1970 return dev_err_probe(dev, -EINVAL,
1971 "Invalid channel number %i\n",
1972 channel);
1973
1974 ret = fwnode_property_read_u16(node, "adi,gain-milli",
1975 &gain);
1976 if (ret && ret != -EINVAL)
1977 return dev_err_probe(dev, ret,
1978 "Failed to read gain for channel %i\n",
1979 channel);
1980 if (ret != -EINVAL) {
1981 /*
1982 * Match gain value from dt to one of supported
1983 * gains
1984 */
1985 gain_idx = find_closest(gain, ad7380_gains,
1986 ARRAY_SIZE(ad7380_gains));
1987 st->gain_milli[channel] = ad7380_gains[gain_idx];
1988 }
1989 }
1990 }
1991
1992 st->regmap = devm_regmap_init(dev, NULL, st, &ad7380_regmap_config);
1993 if (IS_ERR(st->regmap))
1994 return dev_err_probe(dev, PTR_ERR(st->regmap),
1995 "failed to allocate register map\n");
1996
1997 /*
1998 * Setting up xfer structures for both normal and sequence mode. These
1999 * struct are used for both direct read and triggered buffer. Additional
2000 * fields will be set up in ad7380_update_xfers() based on the current
2001 * state of the driver at the time of the read.
2002 */
2003
2004 /*
2005 * In normal mode a read is composed of two steps:
2006 * - first, toggle CS (no data xfer) to trigger a conversion
2007 * - then, read data
2008 */
2009 st->normal_xfer[0].cs_change = 1;
2010 st->normal_xfer[0].cs_change_delay.value = st->chip_info->timing_specs->t_csh_ns;
2011 st->normal_xfer[0].cs_change_delay.unit = SPI_DELAY_UNIT_NSECS;
2012 st->normal_xfer[1].rx_buf = st->scan_data;
2013
2014 spi_message_init_with_transfers(&st->normal_msg, st->normal_xfer,
2015 ARRAY_SIZE(st->normal_xfer));
2016 /*
2017 * In sequencer mode a read is composed of four steps:
2018 * - CS toggle (no data xfer) to get the right point in the sequence
2019 * - CS toggle (no data xfer) to trigger a conversion of AinX0 and
2020 * acquisition of AinX1
2021 * - 2 data reads, to read AinX0 and AinX1
2022 */
2023 st->seq_xfer[0].cs_change = 1;
2024 st->seq_xfer[0].cs_change_delay.value = st->chip_info->timing_specs->t_csh_ns;
2025 st->seq_xfer[0].cs_change_delay.unit = SPI_DELAY_UNIT_NSECS;
2026 st->seq_xfer[1].cs_change = 1;
2027 st->seq_xfer[1].cs_change_delay.value = st->chip_info->timing_specs->t_csh_ns;
2028 st->seq_xfer[1].cs_change_delay.unit = SPI_DELAY_UNIT_NSECS;
2029
2030 st->seq_xfer[2].rx_buf = st->scan_data;
2031 st->seq_xfer[2].cs_change = 1;
2032 st->seq_xfer[2].cs_change_delay.value = st->chip_info->timing_specs->t_csh_ns;
2033 st->seq_xfer[2].cs_change_delay.unit = SPI_DELAY_UNIT_NSECS;
2034
2035 spi_message_init_with_transfers(&st->seq_msg, st->seq_xfer,
2036 ARRAY_SIZE(st->seq_xfer));
2037
2038 indio_dev->channels = st->chip_info->channels;
2039 indio_dev->num_channels = st->chip_info->num_channels;
2040 indio_dev->name = st->chip_info->name;
2041 indio_dev->info = &ad7380_info;
2042 indio_dev->modes = INDIO_DIRECT_MODE;
2043 indio_dev->available_scan_masks = st->chip_info->available_scan_masks;
2044
2045 st->offload = devm_spi_offload_get(dev, spi, &ad7380_offload_config);
2046 ret = PTR_ERR_OR_ZERO(st->offload);
2047 if (ret && ret != -ENODEV)
2048 return dev_err_probe(dev, ret, "failed to get offload\n");
2049
2050 /* If no SPI offload, fall back to low speed usage. */
2051 if (ret == -ENODEV) {
2052 ret = devm_iio_triggered_buffer_setup(dev, indio_dev,
2053 iio_pollfunc_store_time,
2054 ad7380_trigger_handler,
2055 &ad7380_buffer_setup_ops);
2056 if (ret)
2057 return ret;
2058 } else {
2059 ret = ad7380_probe_spi_offload(indio_dev, st);
2060 if (ret)
2061 return ret;
2062 }
2063
2064 ret = ad7380_init(st, external_ref_en);
2065 if (ret)
2066 return ret;
2067
2068 return devm_iio_device_register(dev, indio_dev);
2069 }
2070
2071 static const struct of_device_id ad7380_of_match_table[] = {
2072 { .compatible = "adi,ad7380", .data = &ad7380_chip_info },
2073 { .compatible = "adi,ad7381", .data = &ad7381_chip_info },
2074 { .compatible = "adi,ad7383", .data = &ad7383_chip_info },
2075 { .compatible = "adi,ad7384", .data = &ad7384_chip_info },
2076 { .compatible = "adi,ad7386", .data = &ad7386_chip_info },
2077 { .compatible = "adi,ad7387", .data = &ad7387_chip_info },
2078 { .compatible = "adi,ad7388", .data = &ad7388_chip_info },
2079 { .compatible = "adi,ad7380-4", .data = &ad7380_4_chip_info },
2080 { .compatible = "adi,ad7381-4", .data = &ad7381_4_chip_info },
2081 { .compatible = "adi,ad7383-4", .data = &ad7383_4_chip_info },
2082 { .compatible = "adi,ad7384-4", .data = &ad7384_4_chip_info },
2083 { .compatible = "adi,ad7386-4", .data = &ad7386_4_chip_info },
2084 { .compatible = "adi,ad7387-4", .data = &ad7387_4_chip_info },
2085 { .compatible = "adi,ad7388-4", .data = &ad7388_4_chip_info },
2086 { .compatible = "adi,ad7389-4", .data = &ad7389_4_chip_info },
2087 { .compatible = "adi,adaq4370-4", .data = &adaq4370_4_chip_info },
2088 { .compatible = "adi,adaq4380-4", .data = &adaq4380_4_chip_info },
2089 { .compatible = "adi,adaq4381-4", .data = &adaq4381_4_chip_info },
2090 { }
2091 };
2092
2093 static const struct spi_device_id ad7380_id_table[] = {
2094 { "ad7380", (kernel_ulong_t)&ad7380_chip_info },
2095 { "ad7381", (kernel_ulong_t)&ad7381_chip_info },
2096 { "ad7383", (kernel_ulong_t)&ad7383_chip_info },
2097 { "ad7384", (kernel_ulong_t)&ad7384_chip_info },
2098 { "ad7386", (kernel_ulong_t)&ad7386_chip_info },
2099 { "ad7387", (kernel_ulong_t)&ad7387_chip_info },
2100 { "ad7388", (kernel_ulong_t)&ad7388_chip_info },
2101 { "ad7380-4", (kernel_ulong_t)&ad7380_4_chip_info },
2102 { "ad7381-4", (kernel_ulong_t)&ad7381_4_chip_info },
2103 { "ad7383-4", (kernel_ulong_t)&ad7383_4_chip_info },
2104 { "ad7384-4", (kernel_ulong_t)&ad7384_4_chip_info },
2105 { "ad7386-4", (kernel_ulong_t)&ad7386_4_chip_info },
2106 { "ad7387-4", (kernel_ulong_t)&ad7387_4_chip_info },
2107 { "ad7388-4", (kernel_ulong_t)&ad7388_4_chip_info },
2108 { "ad7389-4", (kernel_ulong_t)&ad7389_4_chip_info },
2109 { "adaq4370-4", (kernel_ulong_t)&adaq4370_4_chip_info },
2110 { "adaq4380-4", (kernel_ulong_t)&adaq4380_4_chip_info },
2111 { "adaq4381-4", (kernel_ulong_t)&adaq4381_4_chip_info },
2112 { }
2113 };
2114 MODULE_DEVICE_TABLE(spi, ad7380_id_table);
2115
2116 static struct spi_driver ad7380_driver = {
2117 .driver = {
2118 .name = "ad7380",
2119 .of_match_table = ad7380_of_match_table,
2120 },
2121 .probe = ad7380_probe,
2122 .id_table = ad7380_id_table,
2123 };
2124 module_spi_driver(ad7380_driver);
2125
2126 MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>");
2127 MODULE_DESCRIPTION("Analog Devices AD738x ADC driver");
2128 MODULE_LICENSE("GPL");
2129 MODULE_IMPORT_NS("IIO_DMAENGINE_BUFFER");
2130