1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * AD7192 and similar SPI ADC driver
4 *
5 * Copyright 2011-2015 Analog Devices Inc.
6 */
7
8 #include <linux/interrupt.h>
9 #include <linux/bitfield.h>
10 #include <linux/clk.h>
11 #include <linux/clk-provider.h>
12 #include <linux/device.h>
13 #include <linux/kernel.h>
14 #include <linux/slab.h>
15 #include <linux/sysfs.h>
16 #include <linux/spi/spi.h>
17 #include <linux/regulator/consumer.h>
18 #include <linux/err.h>
19 #include <linux/sched.h>
20 #include <linux/delay.h>
21 #include <linux/module.h>
22 #include <linux/mod_devicetable.h>
23 #include <linux/property.h>
24 #include <linux/units.h>
25
26 #include <linux/iio/iio.h>
27 #include <linux/iio/sysfs.h>
28 #include <linux/iio/buffer.h>
29 #include <linux/iio/trigger.h>
30 #include <linux/iio/trigger_consumer.h>
31 #include <linux/iio/triggered_buffer.h>
32 #include <linux/iio/adc/ad_sigma_delta.h>
33
34 /* Registers */
35 #define AD7192_REG_COMM 0 /* Communications Register (WO, 8-bit) */
36 #define AD7192_REG_STAT 0 /* Status Register (RO, 8-bit) */
37 #define AD7192_REG_MODE 1 /* Mode Register (RW, 24-bit */
38 #define AD7192_REG_CONF 2 /* Configuration Register (RW, 24-bit) */
39 #define AD7192_REG_DATA 3 /* Data Register (RO, 24/32-bit) */
40 #define AD7192_REG_ID 4 /* ID Register (RO, 8-bit) */
41 #define AD7192_REG_GPOCON 5 /* GPOCON Register (RO, 8-bit) */
42 #define AD7192_REG_OFFSET 6 /* Offset Register (RW, 16-bit */
43 /* (AD7792)/24-bit (AD7192)) */
44 #define AD7192_REG_FULLSALE 7 /* Full-Scale Register */
45 /* (RW, 16-bit (AD7792)/24-bit (AD7192)) */
46
47 /* Communications Register Bit Designations (AD7192_REG_COMM) */
48 #define AD7192_COMM_WEN BIT(7) /* Write Enable */
49 #define AD7192_COMM_WRITE 0 /* Write Operation */
50 #define AD7192_COMM_READ BIT(6) /* Read Operation */
51 #define AD7192_COMM_ADDR_MASK GENMASK(5, 3) /* Register Address Mask */
52 #define AD7192_COMM_CREAD BIT(2) /* Continuous Read of Data Register */
53
54 /* Status Register Bit Designations (AD7192_REG_STAT) */
55 #define AD7192_STAT_RDY BIT(7) /* Ready */
56 #define AD7192_STAT_ERR BIT(6) /* Error (Overrange, Underrange) */
57 #define AD7192_STAT_NOREF BIT(5) /* Error no external reference */
58 #define AD7192_STAT_PARITY BIT(4) /* Parity */
59 #define AD7192_STAT_CH3 BIT(2) /* Channel 3 */
60 #define AD7192_STAT_CH2 BIT(1) /* Channel 2 */
61 #define AD7192_STAT_CH1 BIT(0) /* Channel 1 */
62
63 /* Mode Register Bit Designations (AD7192_REG_MODE) */
64 #define AD7192_MODE_SEL_MASK GENMASK(23, 21) /* Operation Mode Select Mask */
65 #define AD7192_MODE_STA_MASK BIT(20) /* Status Register transmission Mask */
66 #define AD7192_MODE_CLKSRC_MASK GENMASK(19, 18) /* Clock Source Select Mask */
67 #define AD7192_MODE_AVG_MASK GENMASK(17, 16)
68 /* Fast Settling Filter Average Select Mask (AD7193 only) */
69 #define AD7192_MODE_SINC3 BIT(15) /* SINC3 Filter Select */
70 #define AD7192_MODE_ENPAR BIT(13) /* Parity Enable */
71 #define AD7192_MODE_CLKDIV BIT(12) /* Clock divide by 2 (AD7190/2 only)*/
72 #define AD7192_MODE_SCYCLE BIT(11) /* Single cycle conversion */
73 #define AD7192_MODE_REJ60 BIT(10) /* 50/60Hz notch filter */
74 /* Filter Update Rate Select Mask */
75 #define AD7192_MODE_RATE_MASK GENMASK(9, 0)
76
77 /* Mode Register: AD7192_MODE_SEL options */
78 #define AD7192_MODE_CONT 0 /* Continuous Conversion Mode */
79 #define AD7192_MODE_SINGLE 1 /* Single Conversion Mode */
80 #define AD7192_MODE_IDLE 2 /* Idle Mode */
81 #define AD7192_MODE_PWRDN 3 /* Power-Down Mode */
82 #define AD7192_MODE_CAL_INT_ZERO 4 /* Internal Zero-Scale Calibration */
83 #define AD7192_MODE_CAL_INT_FULL 5 /* Internal Full-Scale Calibration */
84 #define AD7192_MODE_CAL_SYS_ZERO 6 /* System Zero-Scale Calibration */
85 #define AD7192_MODE_CAL_SYS_FULL 7 /* System Full-Scale Calibration */
86
87 /* Mode Register: AD7192_MODE_CLKSRC options */
88 #define AD7192_CLK_EXT_MCLK1_2 0 /* External 4.92 MHz Clock connected*/
89 /* from MCLK1 to MCLK2 */
90 #define AD7192_CLK_EXT_MCLK2 1 /* External Clock applied to MCLK2 */
91 #define AD7192_CLK_INT 2 /* Internal 4.92 MHz Clock not */
92 /* available at the MCLK2 pin */
93 #define AD7192_CLK_INT_CO 3 /* Internal 4.92 MHz Clock available*/
94 /* at the MCLK2 pin */
95
96 /* Configuration Register Bit Designations (AD7192_REG_CONF) */
97
98 #define AD7192_CONF_CHOP BIT(23) /* CHOP enable */
99 #define AD7192_CONF_ACX BIT(22) /* AC excitation enable(AD7195 only) */
100 #define AD7192_CONF_REFSEL BIT(20) /* REFIN1/REFIN2 Reference Select */
101 #define AD7192_CONF_CHAN_MASK GENMASK(18, 8) /* Channel select mask */
102 #define AD7192_CONF_BURN BIT(7) /* Burnout current enable */
103 #define AD7192_CONF_REFDET BIT(6) /* Reference detect enable */
104 #define AD7192_CONF_BUF BIT(4) /* Buffered Mode Enable */
105 #define AD7192_CONF_UNIPOLAR BIT(3) /* Unipolar/Bipolar Enable */
106 #define AD7192_CONF_GAIN_MASK GENMASK(2, 0) /* Gain Select */
107
108 #define AD7192_CH_AIN1P_AIN2M BIT(0) /* AIN1(+) - AIN2(-) */
109 #define AD7192_CH_AIN3P_AIN4M BIT(1) /* AIN3(+) - AIN4(-) */
110 #define AD7192_CH_TEMP BIT(2) /* Temp Sensor */
111 #define AD7192_CH_AIN2P_AIN2M BIT(3) /* AIN2(+) - AIN2(-) */
112 #define AD7192_CH_AIN1 BIT(4) /* AIN1 - AINCOM */
113 #define AD7192_CH_AIN2 BIT(5) /* AIN2 - AINCOM */
114 #define AD7192_CH_AIN3 BIT(6) /* AIN3 - AINCOM */
115 #define AD7192_CH_AIN4 BIT(7) /* AIN4 - AINCOM */
116
117 #define AD7193_CH_AIN1P_AIN2M 0x001 /* AIN1(+) - AIN2(-) */
118 #define AD7193_CH_AIN3P_AIN4M 0x002 /* AIN3(+) - AIN4(-) */
119 #define AD7193_CH_AIN5P_AIN6M 0x004 /* AIN5(+) - AIN6(-) */
120 #define AD7193_CH_AIN7P_AIN8M 0x008 /* AIN7(+) - AIN8(-) */
121 #define AD7193_CH_TEMP 0x100 /* Temp senseor */
122 #define AD7193_CH_AIN2P_AIN2M 0x200 /* AIN2(+) - AIN2(-) */
123 #define AD7193_CH_AIN1 0x401 /* AIN1 - AINCOM */
124 #define AD7193_CH_AIN2 0x402 /* AIN2 - AINCOM */
125 #define AD7193_CH_AIN3 0x404 /* AIN3 - AINCOM */
126 #define AD7193_CH_AIN4 0x408 /* AIN4 - AINCOM */
127 #define AD7193_CH_AIN5 0x410 /* AIN5 - AINCOM */
128 #define AD7193_CH_AIN6 0x420 /* AIN6 - AINCOM */
129 #define AD7193_CH_AIN7 0x440 /* AIN7 - AINCOM */
130 #define AD7193_CH_AIN8 0x480 /* AIN7 - AINCOM */
131 #define AD7193_CH_AINCOM 0x600 /* AINCOM - AINCOM */
132
133 #define AD7194_CH_POS(x) (((x) - 1) << 4)
134 #define AD7194_CH_NEG(x) ((x) - 1)
135
136 /* 10th bit corresponds to CON18(Pseudo) */
137 #define AD7194_CH(p) (BIT(10) | AD7194_CH_POS(p))
138
139 #define AD7194_DIFF_CH(p, n) (AD7194_CH_POS(p) | AD7194_CH_NEG(n))
140 #define AD7194_CH_TEMP 0x100
141 #define AD7194_CH_BASE_NR 2
142 #define AD7194_CH_AIN_START 1
143 #define AD7194_CH_AIN_NR 16
144 #define AD7194_CH_MAX_NR 272
145
146 /* ID Register Bit Designations (AD7192_REG_ID) */
147 #define CHIPID_AD7190 0x4
148 #define CHIPID_AD7192 0x0
149 #define CHIPID_AD7193 0x2
150 #define CHIPID_AD7194 0x3
151 #define CHIPID_AD7195 0x6
152 #define AD7192_ID_MASK GENMASK(3, 0)
153
154 /* GPOCON Register Bit Designations (AD7192_REG_GPOCON) */
155 #define AD7192_GPOCON_BPDSW BIT(6) /* Bridge power-down switch enable */
156 #define AD7192_GPOCON_GP32EN BIT(5) /* Digital Output P3 and P2 enable */
157 #define AD7192_GPOCON_GP10EN BIT(4) /* Digital Output P1 and P0 enable */
158 #define AD7192_GPOCON_P3DAT BIT(3) /* P3 state */
159 #define AD7192_GPOCON_P2DAT BIT(2) /* P2 state */
160 #define AD7192_GPOCON_P1DAT BIT(1) /* P1 state */
161 #define AD7192_GPOCON_P0DAT BIT(0) /* P0 state */
162
163 #define AD7192_EXT_FREQ_MHZ_MIN 2457600
164 #define AD7192_EXT_FREQ_MHZ_MAX 5120000
165 #define AD7192_INT_FREQ_MHZ 4915200
166
167 #define AD7192_NO_SYNC_FILTER 1
168 #define AD7192_SYNC3_FILTER 3
169 #define AD7192_SYNC4_FILTER 4
170
171 /* NOTE:
172 * The AD7190/2/5 features a dual use data out ready DOUT/RDY output.
173 * In order to avoid contentions on the SPI bus, it's therefore necessary
174 * to use spi bus locking.
175 *
176 * The DOUT/RDY output must also be wired to an interrupt capable GPIO.
177 */
178
179 enum {
180 AD7192_SYSCALIB_ZERO_SCALE,
181 AD7192_SYSCALIB_FULL_SCALE,
182 };
183
184 enum {
185 ID_AD7190,
186 ID_AD7192,
187 ID_AD7193,
188 ID_AD7194,
189 ID_AD7195,
190 };
191
192 struct ad7192_chip_info {
193 unsigned int chip_id;
194 const char *name;
195 const struct iio_chan_spec *channels;
196 u8 num_channels;
197 const struct ad_sigma_delta_info *sigma_delta_info;
198 const struct iio_info *info;
199 int (*parse_channels)(struct iio_dev *indio_dev);
200 };
201
202 struct ad7192_state {
203 const struct ad7192_chip_info *chip_info;
204 struct clk *mclk;
205 struct clk_hw int_clk_hw;
206 u16 int_vref_mv;
207 u32 aincom_mv;
208 u32 fclk;
209 u32 mode;
210 u32 conf;
211 u32 scale_avail[8][2];
212 u32 filter_freq_avail[4][2];
213 u32 oversampling_ratio_avail[4];
214 u8 gpocon;
215 u8 clock_sel;
216 struct mutex lock; /* protect sensor state */
217 u8 syscalib_mode[8];
218
219 struct ad_sigma_delta sd;
220 };
221
222 static const char * const ad7192_syscalib_modes[] = {
223 [AD7192_SYSCALIB_ZERO_SCALE] = "zero_scale",
224 [AD7192_SYSCALIB_FULL_SCALE] = "full_scale",
225 };
226
ad7192_set_syscalib_mode(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,unsigned int mode)227 static int ad7192_set_syscalib_mode(struct iio_dev *indio_dev,
228 const struct iio_chan_spec *chan,
229 unsigned int mode)
230 {
231 struct ad7192_state *st = iio_priv(indio_dev);
232
233 st->syscalib_mode[chan->channel] = mode;
234
235 return 0;
236 }
237
ad7192_get_syscalib_mode(struct iio_dev * indio_dev,const struct iio_chan_spec * chan)238 static int ad7192_get_syscalib_mode(struct iio_dev *indio_dev,
239 const struct iio_chan_spec *chan)
240 {
241 struct ad7192_state *st = iio_priv(indio_dev);
242
243 return st->syscalib_mode[chan->channel];
244 }
245
ad7192_write_syscalib(struct iio_dev * indio_dev,uintptr_t private,const struct iio_chan_spec * chan,const char * buf,size_t len)246 static ssize_t ad7192_write_syscalib(struct iio_dev *indio_dev,
247 uintptr_t private,
248 const struct iio_chan_spec *chan,
249 const char *buf, size_t len)
250 {
251 struct ad7192_state *st = iio_priv(indio_dev);
252 bool sys_calib;
253 int ret, temp;
254
255 ret = kstrtobool(buf, &sys_calib);
256 if (ret)
257 return ret;
258
259 temp = st->syscalib_mode[chan->channel];
260 if (sys_calib) {
261 if (temp == AD7192_SYSCALIB_ZERO_SCALE)
262 ret = ad_sd_calibrate(&st->sd, AD7192_MODE_CAL_SYS_ZERO,
263 chan->address);
264 else
265 ret = ad_sd_calibrate(&st->sd, AD7192_MODE_CAL_SYS_FULL,
266 chan->address);
267 }
268
269 return ret ? ret : len;
270 }
271
272 static const struct iio_enum ad7192_syscalib_mode_enum = {
273 .items = ad7192_syscalib_modes,
274 .num_items = ARRAY_SIZE(ad7192_syscalib_modes),
275 .set = ad7192_set_syscalib_mode,
276 .get = ad7192_get_syscalib_mode
277 };
278
279 static const struct iio_chan_spec_ext_info ad7192_calibsys_ext_info[] = {
280 {
281 .name = "sys_calibration",
282 .write = ad7192_write_syscalib,
283 .shared = IIO_SEPARATE,
284 },
285 IIO_ENUM("sys_calibration_mode", IIO_SEPARATE,
286 &ad7192_syscalib_mode_enum),
287 IIO_ENUM_AVAILABLE("sys_calibration_mode", IIO_SHARED_BY_TYPE,
288 &ad7192_syscalib_mode_enum),
289 { }
290 };
291
ad_sigma_delta_to_ad7192(struct ad_sigma_delta * sd)292 static struct ad7192_state *ad_sigma_delta_to_ad7192(struct ad_sigma_delta *sd)
293 {
294 return container_of(sd, struct ad7192_state, sd);
295 }
296
ad7192_set_channel(struct ad_sigma_delta * sd,unsigned int channel)297 static int ad7192_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
298 {
299 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);
300
301 st->conf &= ~AD7192_CONF_CHAN_MASK;
302 st->conf |= FIELD_PREP(AD7192_CONF_CHAN_MASK, channel);
303
304 return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);
305 }
306
ad7192_set_mode(struct ad_sigma_delta * sd,enum ad_sigma_delta_mode mode)307 static int ad7192_set_mode(struct ad_sigma_delta *sd,
308 enum ad_sigma_delta_mode mode)
309 {
310 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);
311
312 st->mode &= ~AD7192_MODE_SEL_MASK;
313 st->mode |= FIELD_PREP(AD7192_MODE_SEL_MASK, mode);
314
315 return ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
316 }
317
ad7192_append_status(struct ad_sigma_delta * sd,bool append)318 static int ad7192_append_status(struct ad_sigma_delta *sd, bool append)
319 {
320 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);
321 unsigned int mode = st->mode;
322 int ret;
323
324 mode &= ~AD7192_MODE_STA_MASK;
325 mode |= FIELD_PREP(AD7192_MODE_STA_MASK, append);
326
327 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, mode);
328 if (ret < 0)
329 return ret;
330
331 st->mode = mode;
332
333 return 0;
334 }
335
ad7192_disable_all(struct ad_sigma_delta * sd)336 static int ad7192_disable_all(struct ad_sigma_delta *sd)
337 {
338 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);
339 u32 conf = st->conf;
340 int ret;
341
342 conf &= ~AD7192_CONF_CHAN_MASK;
343
344 ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, conf);
345 if (ret < 0)
346 return ret;
347
348 st->conf = conf;
349
350 return 0;
351 }
352
353 static const struct ad_sigma_delta_info ad7192_sigma_delta_info = {
354 .set_channel = ad7192_set_channel,
355 .append_status = ad7192_append_status,
356 .disable_all = ad7192_disable_all,
357 .set_mode = ad7192_set_mode,
358 .has_registers = true,
359 .addr_shift = 3,
360 .read_mask = BIT(6),
361 .status_ch_mask = GENMASK(3, 0),
362 .num_slots = 4,
363 .irq_flags = IRQF_TRIGGER_FALLING,
364 .num_resetclks = 40,
365 };
366
367 static const struct ad_sigma_delta_info ad7194_sigma_delta_info = {
368 .set_channel = ad7192_set_channel,
369 .append_status = ad7192_append_status,
370 .disable_all = ad7192_disable_all,
371 .set_mode = ad7192_set_mode,
372 .has_registers = true,
373 .addr_shift = 3,
374 .read_mask = BIT(6),
375 .status_ch_mask = GENMASK(3, 0),
376 .irq_flags = IRQF_TRIGGER_FALLING,
377 .num_resetclks = 40,
378 };
379
380 static const struct ad_sd_calib_data ad7192_calib_arr[8] = {
381 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN1},
382 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN1},
383 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN2},
384 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN2},
385 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN3},
386 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN3},
387 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN4},
388 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN4}
389 };
390
ad7192_calibrate_all(struct ad7192_state * st)391 static int ad7192_calibrate_all(struct ad7192_state *st)
392 {
393 return ad_sd_calibrate_all(&st->sd, ad7192_calib_arr,
394 ARRAY_SIZE(ad7192_calib_arr));
395 }
396
ad7192_valid_external_frequency(u32 freq)397 static inline bool ad7192_valid_external_frequency(u32 freq)
398 {
399 return (freq >= AD7192_EXT_FREQ_MHZ_MIN &&
400 freq <= AD7192_EXT_FREQ_MHZ_MAX);
401 }
402
403 /*
404 * Position 0 of ad7192_clock_names, xtal, corresponds to clock source
405 * configuration AD7192_CLK_EXT_MCLK1_2 and position 1, mclk, corresponds to
406 * AD7192_CLK_EXT_MCLK2
407 */
408 static const char *const ad7192_clock_names[] = {
409 "xtal",
410 "mclk"
411 };
412
clk_hw_to_ad7192(struct clk_hw * hw)413 static struct ad7192_state *clk_hw_to_ad7192(struct clk_hw *hw)
414 {
415 return container_of(hw, struct ad7192_state, int_clk_hw);
416 }
417
ad7192_clk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)418 static unsigned long ad7192_clk_recalc_rate(struct clk_hw *hw,
419 unsigned long parent_rate)
420 {
421 return AD7192_INT_FREQ_MHZ;
422 }
423
ad7192_clk_output_is_enabled(struct clk_hw * hw)424 static int ad7192_clk_output_is_enabled(struct clk_hw *hw)
425 {
426 struct ad7192_state *st = clk_hw_to_ad7192(hw);
427
428 return st->clock_sel == AD7192_CLK_INT_CO;
429 }
430
ad7192_clk_prepare(struct clk_hw * hw)431 static int ad7192_clk_prepare(struct clk_hw *hw)
432 {
433 struct ad7192_state *st = clk_hw_to_ad7192(hw);
434 int ret;
435
436 st->mode &= ~AD7192_MODE_CLKSRC_MASK;
437 st->mode |= AD7192_CLK_INT_CO;
438
439 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
440 if (ret)
441 return ret;
442
443 st->clock_sel = AD7192_CLK_INT_CO;
444
445 return 0;
446 }
447
ad7192_clk_unprepare(struct clk_hw * hw)448 static void ad7192_clk_unprepare(struct clk_hw *hw)
449 {
450 struct ad7192_state *st = clk_hw_to_ad7192(hw);
451 int ret;
452
453 st->mode &= ~AD7192_MODE_CLKSRC_MASK;
454 st->mode |= AD7192_CLK_INT;
455
456 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
457 if (ret)
458 return;
459
460 st->clock_sel = AD7192_CLK_INT;
461 }
462
463 static const struct clk_ops ad7192_int_clk_ops = {
464 .recalc_rate = ad7192_clk_recalc_rate,
465 .is_enabled = ad7192_clk_output_is_enabled,
466 .prepare = ad7192_clk_prepare,
467 .unprepare = ad7192_clk_unprepare,
468 };
469
ad7192_register_clk_provider(struct ad7192_state * st)470 static int ad7192_register_clk_provider(struct ad7192_state *st)
471 {
472 struct device *dev = &st->sd.spi->dev;
473 struct clk_init_data init = {};
474 int ret;
475
476 if (!IS_ENABLED(CONFIG_COMMON_CLK))
477 return 0;
478
479 if (!device_property_present(dev, "#clock-cells"))
480 return 0;
481
482 init.name = devm_kasprintf(dev, GFP_KERNEL, "%s-clk",
483 fwnode_get_name(dev_fwnode(dev)));
484 if (!init.name)
485 return -ENOMEM;
486
487 init.ops = &ad7192_int_clk_ops;
488
489 st->int_clk_hw.init = &init;
490 ret = devm_clk_hw_register(dev, &st->int_clk_hw);
491 if (ret)
492 return ret;
493
494 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
495 &st->int_clk_hw);
496 }
497
ad7192_clock_setup(struct ad7192_state * st)498 static int ad7192_clock_setup(struct ad7192_state *st)
499 {
500 struct device *dev = &st->sd.spi->dev;
501 int ret;
502
503 /*
504 * The following two if branches are kept for backward compatibility but
505 * the use of the two devicetree properties is highly discouraged. Clock
506 * configuration should be done according to the bindings.
507 */
508
509 if (device_property_read_bool(dev, "adi,int-clock-output-enable")) {
510 st->clock_sel = AD7192_CLK_INT_CO;
511 st->fclk = AD7192_INT_FREQ_MHZ;
512 dev_warn(dev, "Property adi,int-clock-output-enable is deprecated! Check bindings!\n");
513 return 0;
514 }
515
516 if (device_property_read_bool(dev, "adi,clock-xtal")) {
517 st->clock_sel = AD7192_CLK_EXT_MCLK1_2;
518 st->mclk = devm_clk_get_enabled(dev, "mclk");
519 if (IS_ERR(st->mclk))
520 return dev_err_probe(dev, PTR_ERR(st->mclk),
521 "Failed to get mclk\n");
522
523 st->fclk = clk_get_rate(st->mclk);
524 if (!ad7192_valid_external_frequency(st->fclk))
525 return dev_err_probe(dev, -EINVAL,
526 "External clock frequency out of bounds\n");
527
528 dev_warn(dev, "Property adi,clock-xtal is deprecated! Check bindings!\n");
529 return 0;
530 }
531
532 ret = device_property_match_property_string(dev, "clock-names",
533 ad7192_clock_names,
534 ARRAY_SIZE(ad7192_clock_names));
535 if (ret < 0) {
536 st->clock_sel = AD7192_CLK_INT;
537 st->fclk = AD7192_INT_FREQ_MHZ;
538
539 ret = ad7192_register_clk_provider(st);
540 if (ret)
541 return dev_err_probe(dev, ret,
542 "Failed to register clock provider\n");
543 return 0;
544 }
545
546 st->clock_sel = AD7192_CLK_EXT_MCLK1_2 + ret;
547
548 st->mclk = devm_clk_get_enabled(dev, ad7192_clock_names[ret]);
549 if (IS_ERR(st->mclk))
550 return dev_err_probe(dev, PTR_ERR(st->mclk),
551 "Failed to get clock source\n");
552
553 st->fclk = clk_get_rate(st->mclk);
554 if (!ad7192_valid_external_frequency(st->fclk))
555 return dev_err_probe(dev, -EINVAL,
556 "External clock frequency out of bounds\n");
557
558 return 0;
559 }
560
ad7192_setup(struct iio_dev * indio_dev,struct device * dev)561 static int ad7192_setup(struct iio_dev *indio_dev, struct device *dev)
562 {
563 struct ad7192_state *st = iio_priv(indio_dev);
564 bool rej60_en, refin2_en;
565 bool buf_en, bipolar, burnout_curr_en;
566 unsigned long long scale_uv;
567 int i, ret, id;
568
569 /* reset the serial interface */
570 ret = ad_sd_reset(&st->sd);
571 if (ret < 0)
572 return ret;
573 usleep_range(500, 1000); /* Wait for at least 500us */
574
575 /* write/read test for device presence */
576 ret = ad_sd_read_reg(&st->sd, AD7192_REG_ID, 1, &id);
577 if (ret)
578 return ret;
579
580 id = FIELD_GET(AD7192_ID_MASK, id);
581
582 if (id != st->chip_info->chip_id)
583 dev_warn(dev, "device ID query failed (0x%X != 0x%X)\n",
584 id, st->chip_info->chip_id);
585
586 st->mode = FIELD_PREP(AD7192_MODE_SEL_MASK, AD7192_MODE_IDLE) |
587 FIELD_PREP(AD7192_MODE_CLKSRC_MASK, st->clock_sel) |
588 FIELD_PREP(AD7192_MODE_RATE_MASK, 480);
589
590 st->conf = FIELD_PREP(AD7192_CONF_GAIN_MASK, 0);
591
592 rej60_en = device_property_read_bool(dev, "adi,rejection-60-Hz-enable");
593 if (rej60_en)
594 st->mode |= AD7192_MODE_REJ60;
595
596 refin2_en = device_property_read_bool(dev, "adi,refin2-pins-enable");
597 if (refin2_en && st->chip_info->chip_id != CHIPID_AD7195)
598 st->conf |= AD7192_CONF_REFSEL;
599
600 st->conf &= ~AD7192_CONF_CHOP;
601
602 buf_en = device_property_read_bool(dev, "adi,buffer-enable");
603 if (buf_en)
604 st->conf |= AD7192_CONF_BUF;
605
606 bipolar = device_property_read_bool(dev, "bipolar");
607 if (!bipolar)
608 st->conf |= AD7192_CONF_UNIPOLAR;
609
610 burnout_curr_en = device_property_read_bool(dev,
611 "adi,burnout-currents-enable");
612 if (burnout_curr_en && buf_en) {
613 st->conf |= AD7192_CONF_BURN;
614 } else if (burnout_curr_en) {
615 dev_warn(dev,
616 "Can't enable burnout currents: see CHOP or buffer\n");
617 }
618
619 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
620 if (ret)
621 return ret;
622
623 ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);
624 if (ret)
625 return ret;
626
627 ret = ad7192_calibrate_all(st);
628 if (ret)
629 return ret;
630
631 /* Populate available ADC input ranges */
632 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) {
633 scale_uv = ((u64)st->int_vref_mv * 100000000)
634 >> (indio_dev->channels[0].scan_type.realbits -
635 !FIELD_GET(AD7192_CONF_UNIPOLAR, st->conf));
636 scale_uv >>= i;
637
638 st->scale_avail[i][1] = do_div(scale_uv, 100000000) * 10;
639 st->scale_avail[i][0] = scale_uv;
640 }
641
642 st->oversampling_ratio_avail[0] = 1;
643 st->oversampling_ratio_avail[1] = 2;
644 st->oversampling_ratio_avail[2] = 8;
645 st->oversampling_ratio_avail[3] = 16;
646
647 st->filter_freq_avail[0][0] = 600;
648 st->filter_freq_avail[1][0] = 800;
649 st->filter_freq_avail[2][0] = 2300;
650 st->filter_freq_avail[3][0] = 2720;
651
652 st->filter_freq_avail[0][1] = 1000;
653 st->filter_freq_avail[1][1] = 1000;
654 st->filter_freq_avail[2][1] = 1000;
655 st->filter_freq_avail[3][1] = 1000;
656
657 return 0;
658 }
659
ad7192_show_ac_excitation(struct device * dev,struct device_attribute * attr,char * buf)660 static ssize_t ad7192_show_ac_excitation(struct device *dev,
661 struct device_attribute *attr,
662 char *buf)
663 {
664 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
665 struct ad7192_state *st = iio_priv(indio_dev);
666
667 return sysfs_emit(buf, "%ld\n", FIELD_GET(AD7192_CONF_ACX, st->conf));
668 }
669
ad7192_show_bridge_switch(struct device * dev,struct device_attribute * attr,char * buf)670 static ssize_t ad7192_show_bridge_switch(struct device *dev,
671 struct device_attribute *attr,
672 char *buf)
673 {
674 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
675 struct ad7192_state *st = iio_priv(indio_dev);
676
677 return sysfs_emit(buf, "%ld\n",
678 FIELD_GET(AD7192_GPOCON_BPDSW, st->gpocon));
679 }
680
ad7192_set(struct device * dev,struct device_attribute * attr,const char * buf,size_t len)681 static ssize_t ad7192_set(struct device *dev,
682 struct device_attribute *attr,
683 const char *buf,
684 size_t len)
685 {
686 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
687 struct ad7192_state *st = iio_priv(indio_dev);
688 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
689 int ret;
690 bool val;
691
692 ret = kstrtobool(buf, &val);
693 if (ret < 0)
694 return ret;
695
696 ret = iio_device_claim_direct_mode(indio_dev);
697 if (ret)
698 return ret;
699
700 switch ((u32)this_attr->address) {
701 case AD7192_REG_GPOCON:
702 if (val)
703 st->gpocon |= AD7192_GPOCON_BPDSW;
704 else
705 st->gpocon &= ~AD7192_GPOCON_BPDSW;
706
707 ad_sd_write_reg(&st->sd, AD7192_REG_GPOCON, 1, st->gpocon);
708 break;
709 case AD7192_REG_CONF:
710 if (val)
711 st->conf |= AD7192_CONF_ACX;
712 else
713 st->conf &= ~AD7192_CONF_ACX;
714
715 ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);
716 break;
717 default:
718 ret = -EINVAL;
719 }
720
721 iio_device_release_direct_mode(indio_dev);
722
723 return ret ? ret : len;
724 }
725
ad7192_compute_f_order(struct ad7192_state * st,bool sinc3_en,bool chop_en)726 static int ad7192_compute_f_order(struct ad7192_state *st, bool sinc3_en, bool chop_en)
727 {
728 u8 avg_factor_selected, oversampling_ratio;
729
730 avg_factor_selected = FIELD_GET(AD7192_MODE_AVG_MASK, st->mode);
731
732 if (!avg_factor_selected && !chop_en)
733 return 1;
734
735 oversampling_ratio = st->oversampling_ratio_avail[avg_factor_selected];
736
737 if (sinc3_en)
738 return AD7192_SYNC3_FILTER + oversampling_ratio - 1;
739
740 return AD7192_SYNC4_FILTER + oversampling_ratio - 1;
741 }
742
ad7192_get_f_order(struct ad7192_state * st)743 static int ad7192_get_f_order(struct ad7192_state *st)
744 {
745 bool sinc3_en, chop_en;
746
747 sinc3_en = FIELD_GET(AD7192_MODE_SINC3, st->mode);
748 chop_en = FIELD_GET(AD7192_CONF_CHOP, st->conf);
749
750 return ad7192_compute_f_order(st, sinc3_en, chop_en);
751 }
752
ad7192_compute_f_adc(struct ad7192_state * st,bool sinc3_en,bool chop_en)753 static int ad7192_compute_f_adc(struct ad7192_state *st, bool sinc3_en,
754 bool chop_en)
755 {
756 unsigned int f_order = ad7192_compute_f_order(st, sinc3_en, chop_en);
757
758 return DIV_ROUND_CLOSEST(st->fclk,
759 f_order * FIELD_GET(AD7192_MODE_RATE_MASK, st->mode));
760 }
761
ad7192_get_f_adc(struct ad7192_state * st)762 static int ad7192_get_f_adc(struct ad7192_state *st)
763 {
764 unsigned int f_order = ad7192_get_f_order(st);
765
766 return DIV_ROUND_CLOSEST(st->fclk,
767 f_order * FIELD_GET(AD7192_MODE_RATE_MASK, st->mode));
768 }
769
ad7192_update_filter_freq_avail(struct ad7192_state * st)770 static void ad7192_update_filter_freq_avail(struct ad7192_state *st)
771 {
772 unsigned int fadc;
773
774 /* Formulas for filter at page 25 of the datasheet */
775 fadc = ad7192_compute_f_adc(st, false, true);
776 st->filter_freq_avail[0][0] = DIV_ROUND_CLOSEST(fadc * 240, 1024);
777
778 fadc = ad7192_compute_f_adc(st, true, true);
779 st->filter_freq_avail[1][0] = DIV_ROUND_CLOSEST(fadc * 240, 1024);
780
781 fadc = ad7192_compute_f_adc(st, false, false);
782 st->filter_freq_avail[2][0] = DIV_ROUND_CLOSEST(fadc * 230, 1024);
783
784 fadc = ad7192_compute_f_adc(st, true, false);
785 st->filter_freq_avail[3][0] = DIV_ROUND_CLOSEST(fadc * 272, 1024);
786 }
787
788 static IIO_DEVICE_ATTR(bridge_switch_en, 0644,
789 ad7192_show_bridge_switch, ad7192_set,
790 AD7192_REG_GPOCON);
791
792 static IIO_DEVICE_ATTR(ac_excitation_en, 0644,
793 ad7192_show_ac_excitation, ad7192_set,
794 AD7192_REG_CONF);
795
796 static struct attribute *ad7192_attributes[] = {
797 &iio_dev_attr_bridge_switch_en.dev_attr.attr,
798 NULL
799 };
800
801 static const struct attribute_group ad7192_attribute_group = {
802 .attrs = ad7192_attributes,
803 };
804
805 static struct attribute *ad7195_attributes[] = {
806 &iio_dev_attr_bridge_switch_en.dev_attr.attr,
807 &iio_dev_attr_ac_excitation_en.dev_attr.attr,
808 NULL
809 };
810
811 static const struct attribute_group ad7195_attribute_group = {
812 .attrs = ad7195_attributes,
813 };
814
ad7192_get_temp_scale(bool unipolar)815 static unsigned int ad7192_get_temp_scale(bool unipolar)
816 {
817 return unipolar ? 2815 * 2 : 2815;
818 }
819
ad7192_set_3db_filter_freq(struct ad7192_state * st,int val,int val2)820 static int ad7192_set_3db_filter_freq(struct ad7192_state *st,
821 int val, int val2)
822 {
823 int i, ret, freq;
824 unsigned int diff_new, diff_old;
825 int idx = 0;
826
827 diff_old = U32_MAX;
828 freq = val * 1000 + val2;
829
830 for (i = 0; i < ARRAY_SIZE(st->filter_freq_avail); i++) {
831 diff_new = abs(freq - st->filter_freq_avail[i][0]);
832 if (diff_new < diff_old) {
833 diff_old = diff_new;
834 idx = i;
835 }
836 }
837
838 switch (idx) {
839 case 0:
840 st->mode &= ~AD7192_MODE_SINC3;
841
842 st->conf |= AD7192_CONF_CHOP;
843 break;
844 case 1:
845 st->mode |= AD7192_MODE_SINC3;
846
847 st->conf |= AD7192_CONF_CHOP;
848 break;
849 case 2:
850 st->mode &= ~AD7192_MODE_SINC3;
851
852 st->conf &= ~AD7192_CONF_CHOP;
853 break;
854 case 3:
855 st->mode |= AD7192_MODE_SINC3;
856
857 st->conf &= ~AD7192_CONF_CHOP;
858 break;
859 }
860
861 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
862 if (ret < 0)
863 return ret;
864
865 return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);
866 }
867
ad7192_get_3db_filter_freq(struct ad7192_state * st)868 static int ad7192_get_3db_filter_freq(struct ad7192_state *st)
869 {
870 unsigned int fadc;
871
872 fadc = ad7192_get_f_adc(st);
873
874 if (FIELD_GET(AD7192_CONF_CHOP, st->conf))
875 return DIV_ROUND_CLOSEST(fadc * 240, 1024);
876 if (FIELD_GET(AD7192_MODE_SINC3, st->mode))
877 return DIV_ROUND_CLOSEST(fadc * 272, 1024);
878 else
879 return DIV_ROUND_CLOSEST(fadc * 230, 1024);
880 }
881
ad7192_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long m)882 static int ad7192_read_raw(struct iio_dev *indio_dev,
883 struct iio_chan_spec const *chan,
884 int *val,
885 int *val2,
886 long m)
887 {
888 struct ad7192_state *st = iio_priv(indio_dev);
889 bool unipolar = FIELD_GET(AD7192_CONF_UNIPOLAR, st->conf);
890 u8 gain = FIELD_GET(AD7192_CONF_GAIN_MASK, st->conf);
891
892 switch (m) {
893 case IIO_CHAN_INFO_RAW:
894 return ad_sigma_delta_single_conversion(indio_dev, chan, val);
895 case IIO_CHAN_INFO_SCALE:
896 switch (chan->type) {
897 case IIO_VOLTAGE:
898 mutex_lock(&st->lock);
899 *val = st->scale_avail[gain][0];
900 *val2 = st->scale_avail[gain][1];
901 mutex_unlock(&st->lock);
902 return IIO_VAL_INT_PLUS_NANO;
903 case IIO_TEMP:
904 *val = 0;
905 *val2 = 1000000000 / ad7192_get_temp_scale(unipolar);
906 return IIO_VAL_INT_PLUS_NANO;
907 default:
908 return -EINVAL;
909 }
910 case IIO_CHAN_INFO_OFFSET:
911 if (!unipolar)
912 *val = -(1 << (chan->scan_type.realbits - 1));
913 else
914 *val = 0;
915
916 switch (chan->type) {
917 case IIO_VOLTAGE:
918 /*
919 * Only applies to pseudo-differential inputs.
920 * AINCOM voltage has to be converted to "raw" units.
921 */
922 if (st->aincom_mv && !chan->differential)
923 *val += DIV_ROUND_CLOSEST_ULL((u64)st->aincom_mv * NANO,
924 st->scale_avail[gain][1]);
925 return IIO_VAL_INT;
926 /* Kelvin to Celsius */
927 case IIO_TEMP:
928 *val -= 273 * ad7192_get_temp_scale(unipolar);
929 return IIO_VAL_INT;
930 default:
931 return -EINVAL;
932 }
933 case IIO_CHAN_INFO_SAMP_FREQ:
934 *val = DIV_ROUND_CLOSEST(ad7192_get_f_adc(st), 1024);
935 return IIO_VAL_INT;
936 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
937 *val = ad7192_get_3db_filter_freq(st);
938 *val2 = 1000;
939 return IIO_VAL_FRACTIONAL;
940 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
941 *val = st->oversampling_ratio_avail[FIELD_GET(AD7192_MODE_AVG_MASK, st->mode)];
942 return IIO_VAL_INT;
943 }
944
945 return -EINVAL;
946 }
947
ad7192_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)948 static int ad7192_write_raw(struct iio_dev *indio_dev,
949 struct iio_chan_spec const *chan,
950 int val,
951 int val2,
952 long mask)
953 {
954 struct ad7192_state *st = iio_priv(indio_dev);
955 int ret, i, div;
956 unsigned int tmp;
957
958 ret = iio_device_claim_direct_mode(indio_dev);
959 if (ret)
960 return ret;
961
962 mutex_lock(&st->lock);
963
964 switch (mask) {
965 case IIO_CHAN_INFO_SCALE:
966 ret = -EINVAL;
967 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
968 if (val2 == st->scale_avail[i][1]) {
969 ret = 0;
970 tmp = st->conf;
971 st->conf &= ~AD7192_CONF_GAIN_MASK;
972 st->conf |= FIELD_PREP(AD7192_CONF_GAIN_MASK, i);
973 if (tmp == st->conf)
974 break;
975 ad_sd_write_reg(&st->sd, AD7192_REG_CONF,
976 3, st->conf);
977 ad7192_calibrate_all(st);
978 break;
979 }
980 break;
981 case IIO_CHAN_INFO_SAMP_FREQ:
982 if (!val) {
983 ret = -EINVAL;
984 break;
985 }
986
987 div = st->fclk / (val * ad7192_get_f_order(st) * 1024);
988 if (div < 1 || div > 1023) {
989 ret = -EINVAL;
990 break;
991 }
992
993 st->mode &= ~AD7192_MODE_RATE_MASK;
994 st->mode |= FIELD_PREP(AD7192_MODE_RATE_MASK, div);
995 ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
996 ad7192_update_filter_freq_avail(st);
997 break;
998 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
999 ret = ad7192_set_3db_filter_freq(st, val, val2 / 1000);
1000 break;
1001 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
1002 ret = -EINVAL;
1003 for (i = 0; i < ARRAY_SIZE(st->oversampling_ratio_avail); i++)
1004 if (val == st->oversampling_ratio_avail[i]) {
1005 ret = 0;
1006 tmp = st->mode;
1007 st->mode &= ~AD7192_MODE_AVG_MASK;
1008 st->mode |= FIELD_PREP(AD7192_MODE_AVG_MASK, i);
1009 if (tmp == st->mode)
1010 break;
1011 ad_sd_write_reg(&st->sd, AD7192_REG_MODE,
1012 3, st->mode);
1013 break;
1014 }
1015 ad7192_update_filter_freq_avail(st);
1016 break;
1017 default:
1018 ret = -EINVAL;
1019 }
1020
1021 mutex_unlock(&st->lock);
1022
1023 iio_device_release_direct_mode(indio_dev);
1024
1025 return ret;
1026 }
1027
ad7192_write_raw_get_fmt(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,long mask)1028 static int ad7192_write_raw_get_fmt(struct iio_dev *indio_dev,
1029 struct iio_chan_spec const *chan,
1030 long mask)
1031 {
1032 switch (mask) {
1033 case IIO_CHAN_INFO_SCALE:
1034 return IIO_VAL_INT_PLUS_NANO;
1035 case IIO_CHAN_INFO_SAMP_FREQ:
1036 return IIO_VAL_INT;
1037 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
1038 return IIO_VAL_INT_PLUS_MICRO;
1039 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
1040 return IIO_VAL_INT;
1041 default:
1042 return -EINVAL;
1043 }
1044 }
1045
ad7192_read_avail(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,const int ** vals,int * type,int * length,long mask)1046 static int ad7192_read_avail(struct iio_dev *indio_dev,
1047 struct iio_chan_spec const *chan,
1048 const int **vals, int *type, int *length,
1049 long mask)
1050 {
1051 struct ad7192_state *st = iio_priv(indio_dev);
1052
1053 switch (mask) {
1054 case IIO_CHAN_INFO_SCALE:
1055 *vals = (int *)st->scale_avail;
1056 *type = IIO_VAL_INT_PLUS_NANO;
1057 /* Values are stored in a 2D matrix */
1058 *length = ARRAY_SIZE(st->scale_avail) * 2;
1059
1060 return IIO_AVAIL_LIST;
1061 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
1062 *vals = (int *)st->filter_freq_avail;
1063 *type = IIO_VAL_FRACTIONAL;
1064 *length = ARRAY_SIZE(st->filter_freq_avail) * 2;
1065
1066 return IIO_AVAIL_LIST;
1067 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
1068 *vals = (int *)st->oversampling_ratio_avail;
1069 *type = IIO_VAL_INT;
1070 *length = ARRAY_SIZE(st->oversampling_ratio_avail);
1071
1072 return IIO_AVAIL_LIST;
1073 }
1074
1075 return -EINVAL;
1076 }
1077
ad7192_update_scan_mode(struct iio_dev * indio_dev,const unsigned long * scan_mask)1078 static int ad7192_update_scan_mode(struct iio_dev *indio_dev, const unsigned long *scan_mask)
1079 {
1080 struct ad7192_state *st = iio_priv(indio_dev);
1081 u32 conf = st->conf;
1082 int ret;
1083 int i;
1084
1085 conf &= ~AD7192_CONF_CHAN_MASK;
1086 for_each_set_bit(i, scan_mask, 8)
1087 conf |= FIELD_PREP(AD7192_CONF_CHAN_MASK, BIT(i));
1088
1089 ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, conf);
1090 if (ret < 0)
1091 return ret;
1092
1093 st->conf = conf;
1094
1095 return 0;
1096 }
1097
1098 static const struct iio_info ad7192_info = {
1099 .read_raw = ad7192_read_raw,
1100 .write_raw = ad7192_write_raw,
1101 .write_raw_get_fmt = ad7192_write_raw_get_fmt,
1102 .read_avail = ad7192_read_avail,
1103 .attrs = &ad7192_attribute_group,
1104 .validate_trigger = ad_sd_validate_trigger,
1105 .update_scan_mode = ad7192_update_scan_mode,
1106 };
1107
1108 static const struct iio_info ad7194_info = {
1109 .read_raw = ad7192_read_raw,
1110 .write_raw = ad7192_write_raw,
1111 .write_raw_get_fmt = ad7192_write_raw_get_fmt,
1112 .read_avail = ad7192_read_avail,
1113 .validate_trigger = ad_sd_validate_trigger,
1114 };
1115
1116 static const struct iio_info ad7195_info = {
1117 .read_raw = ad7192_read_raw,
1118 .write_raw = ad7192_write_raw,
1119 .write_raw_get_fmt = ad7192_write_raw_get_fmt,
1120 .read_avail = ad7192_read_avail,
1121 .attrs = &ad7195_attribute_group,
1122 .validate_trigger = ad_sd_validate_trigger,
1123 .update_scan_mode = ad7192_update_scan_mode,
1124 };
1125
1126 #define __AD719x_CHANNEL(_si, _channel1, _channel2, _address, _type, \
1127 _mask_all, _mask_type_av, _mask_all_av, _ext_info) \
1128 { \
1129 .type = (_type), \
1130 .differential = ((_channel2) == -1 ? 0 : 1), \
1131 .indexed = 1, \
1132 .channel = (_channel1), \
1133 .channel2 = (_channel2), \
1134 .address = (_address), \
1135 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1136 BIT(IIO_CHAN_INFO_OFFSET), \
1137 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
1138 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
1139 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \
1140 (_mask_all), \
1141 .info_mask_shared_by_type_available = (_mask_type_av), \
1142 .info_mask_shared_by_all_available = \
1143 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \
1144 (_mask_all_av), \
1145 .ext_info = (_ext_info), \
1146 .scan_index = (_si), \
1147 .scan_type = { \
1148 .sign = 'u', \
1149 .realbits = 24, \
1150 .storagebits = 32, \
1151 .endianness = IIO_BE, \
1152 }, \
1153 }
1154
1155 #define AD719x_DIFF_CHANNEL(_si, _channel1, _channel2, _address) \
1156 __AD719x_CHANNEL(_si, _channel1, _channel2, _address, IIO_VOLTAGE, 0, \
1157 BIT(IIO_CHAN_INFO_SCALE), 0, ad7192_calibsys_ext_info)
1158
1159 #define AD719x_CHANNEL(_si, _channel1, _address) \
1160 __AD719x_CHANNEL(_si, _channel1, -1, _address, IIO_VOLTAGE, 0, \
1161 BIT(IIO_CHAN_INFO_SCALE), 0, ad7192_calibsys_ext_info)
1162
1163 #define AD719x_TEMP_CHANNEL(_si, _address) \
1164 __AD719x_CHANNEL(_si, 0, -1, _address, IIO_TEMP, 0, 0, 0, NULL)
1165
1166 #define AD7193_DIFF_CHANNEL(_si, _channel1, _channel2, _address) \
1167 __AD719x_CHANNEL(_si, _channel1, _channel2, _address, \
1168 IIO_VOLTAGE, \
1169 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
1170 BIT(IIO_CHAN_INFO_SCALE), \
1171 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
1172 ad7192_calibsys_ext_info)
1173
1174 #define AD7193_CHANNEL(_si, _channel1, _address) \
1175 AD7193_DIFF_CHANNEL(_si, _channel1, -1, _address)
1176
1177 static const struct iio_chan_spec ad7192_channels[] = {
1178 AD719x_DIFF_CHANNEL(0, 1, 2, AD7192_CH_AIN1P_AIN2M),
1179 AD719x_DIFF_CHANNEL(1, 3, 4, AD7192_CH_AIN3P_AIN4M),
1180 AD719x_TEMP_CHANNEL(2, AD7192_CH_TEMP),
1181 AD719x_DIFF_CHANNEL(3, 2, 2, AD7192_CH_AIN2P_AIN2M),
1182 AD719x_CHANNEL(4, 1, AD7192_CH_AIN1),
1183 AD719x_CHANNEL(5, 2, AD7192_CH_AIN2),
1184 AD719x_CHANNEL(6, 3, AD7192_CH_AIN3),
1185 AD719x_CHANNEL(7, 4, AD7192_CH_AIN4),
1186 IIO_CHAN_SOFT_TIMESTAMP(8),
1187 };
1188
1189 static const struct iio_chan_spec ad7193_channels[] = {
1190 AD7193_DIFF_CHANNEL(0, 1, 2, AD7193_CH_AIN1P_AIN2M),
1191 AD7193_DIFF_CHANNEL(1, 3, 4, AD7193_CH_AIN3P_AIN4M),
1192 AD7193_DIFF_CHANNEL(2, 5, 6, AD7193_CH_AIN5P_AIN6M),
1193 AD7193_DIFF_CHANNEL(3, 7, 8, AD7193_CH_AIN7P_AIN8M),
1194 AD719x_TEMP_CHANNEL(4, AD7193_CH_TEMP),
1195 AD7193_DIFF_CHANNEL(5, 2, 2, AD7193_CH_AIN2P_AIN2M),
1196 AD7193_CHANNEL(6, 1, AD7193_CH_AIN1),
1197 AD7193_CHANNEL(7, 2, AD7193_CH_AIN2),
1198 AD7193_CHANNEL(8, 3, AD7193_CH_AIN3),
1199 AD7193_CHANNEL(9, 4, AD7193_CH_AIN4),
1200 AD7193_CHANNEL(10, 5, AD7193_CH_AIN5),
1201 AD7193_CHANNEL(11, 6, AD7193_CH_AIN6),
1202 AD7193_CHANNEL(12, 7, AD7193_CH_AIN7),
1203 AD7193_CHANNEL(13, 8, AD7193_CH_AIN8),
1204 IIO_CHAN_SOFT_TIMESTAMP(14),
1205 };
1206
ad7194_validate_ain_channel(struct device * dev,u32 ain)1207 static bool ad7194_validate_ain_channel(struct device *dev, u32 ain)
1208 {
1209 return in_range(ain, AD7194_CH_AIN_START, AD7194_CH_AIN_NR);
1210 }
1211
ad7194_parse_channels(struct iio_dev * indio_dev)1212 static int ad7194_parse_channels(struct iio_dev *indio_dev)
1213 {
1214 struct device *dev = indio_dev->dev.parent;
1215 struct iio_chan_spec *ad7194_channels;
1216 const struct iio_chan_spec ad7194_chan = AD7193_CHANNEL(0, 0, 0);
1217 const struct iio_chan_spec ad7194_chan_diff = AD7193_DIFF_CHANNEL(0, 0, 0, 0);
1218 const struct iio_chan_spec ad7194_chan_temp = AD719x_TEMP_CHANNEL(0, 0);
1219 const struct iio_chan_spec ad7194_chan_timestamp = IIO_CHAN_SOFT_TIMESTAMP(0);
1220 unsigned int num_channels, index = 0;
1221 u32 ain[2];
1222 int ret;
1223
1224 num_channels = device_get_child_node_count(dev);
1225 if (num_channels > AD7194_CH_MAX_NR)
1226 return dev_err_probe(dev, -EINVAL, "Too many channels: %u\n",
1227 num_channels);
1228
1229 num_channels += AD7194_CH_BASE_NR;
1230
1231 ad7194_channels = devm_kcalloc(dev, num_channels,
1232 sizeof(*ad7194_channels), GFP_KERNEL);
1233 if (!ad7194_channels)
1234 return -ENOMEM;
1235
1236 indio_dev->channels = ad7194_channels;
1237 indio_dev->num_channels = num_channels;
1238
1239 device_for_each_child_node_scoped(dev, child) {
1240 ret = fwnode_property_read_u32_array(child, "diff-channels",
1241 ain, ARRAY_SIZE(ain));
1242 if (ret == 0) {
1243 if (!ad7194_validate_ain_channel(dev, ain[0]))
1244 return dev_err_probe(dev, -EINVAL,
1245 "Invalid AIN channel: %u\n",
1246 ain[0]);
1247
1248 if (!ad7194_validate_ain_channel(dev, ain[1]))
1249 return dev_err_probe(dev, -EINVAL,
1250 "Invalid AIN channel: %u\n",
1251 ain[1]);
1252
1253 *ad7194_channels = ad7194_chan_diff;
1254 ad7194_channels->scan_index = index++;
1255 ad7194_channels->channel = ain[0];
1256 ad7194_channels->channel2 = ain[1];
1257 ad7194_channels->address = AD7194_DIFF_CH(ain[0], ain[1]);
1258 } else {
1259 ret = fwnode_property_read_u32(child, "single-channel",
1260 &ain[0]);
1261 if (ret)
1262 return dev_err_probe(dev, ret,
1263 "Missing channel property\n");
1264
1265 if (!ad7194_validate_ain_channel(dev, ain[0]))
1266 return dev_err_probe(dev, -EINVAL,
1267 "Invalid AIN channel: %u\n",
1268 ain[0]);
1269
1270 *ad7194_channels = ad7194_chan;
1271 ad7194_channels->scan_index = index++;
1272 ad7194_channels->channel = ain[0];
1273 ad7194_channels->address = AD7194_CH(ain[0]);
1274 }
1275 ad7194_channels++;
1276 }
1277
1278 *ad7194_channels = ad7194_chan_temp;
1279 ad7194_channels->scan_index = index++;
1280 ad7194_channels->address = AD7194_CH_TEMP;
1281 ad7194_channels++;
1282
1283 *ad7194_channels = ad7194_chan_timestamp;
1284 ad7194_channels->scan_index = index;
1285
1286 return 0;
1287 }
1288
1289 static const struct ad7192_chip_info ad7192_chip_info_tbl[] = {
1290 [ID_AD7190] = {
1291 .chip_id = CHIPID_AD7190,
1292 .name = "ad7190",
1293 .channels = ad7192_channels,
1294 .num_channels = ARRAY_SIZE(ad7192_channels),
1295 .sigma_delta_info = &ad7192_sigma_delta_info,
1296 .info = &ad7192_info,
1297 },
1298 [ID_AD7192] = {
1299 .chip_id = CHIPID_AD7192,
1300 .name = "ad7192",
1301 .channels = ad7192_channels,
1302 .num_channels = ARRAY_SIZE(ad7192_channels),
1303 .sigma_delta_info = &ad7192_sigma_delta_info,
1304 .info = &ad7192_info,
1305 },
1306 [ID_AD7193] = {
1307 .chip_id = CHIPID_AD7193,
1308 .name = "ad7193",
1309 .channels = ad7193_channels,
1310 .num_channels = ARRAY_SIZE(ad7193_channels),
1311 .sigma_delta_info = &ad7192_sigma_delta_info,
1312 .info = &ad7192_info,
1313 },
1314 [ID_AD7194] = {
1315 .chip_id = CHIPID_AD7194,
1316 .name = "ad7194",
1317 .info = &ad7194_info,
1318 .sigma_delta_info = &ad7194_sigma_delta_info,
1319 .parse_channels = ad7194_parse_channels,
1320 },
1321 [ID_AD7195] = {
1322 .chip_id = CHIPID_AD7195,
1323 .name = "ad7195",
1324 .channels = ad7192_channels,
1325 .num_channels = ARRAY_SIZE(ad7192_channels),
1326 .sigma_delta_info = &ad7192_sigma_delta_info,
1327 .info = &ad7195_info,
1328 },
1329 };
1330
ad7192_probe(struct spi_device * spi)1331 static int ad7192_probe(struct spi_device *spi)
1332 {
1333 struct device *dev = &spi->dev;
1334 struct ad7192_state *st;
1335 struct iio_dev *indio_dev;
1336 int ret, avdd_mv;
1337
1338 if (!spi->irq)
1339 return dev_err_probe(dev, -ENODEV, "Failed to get IRQ\n");
1340
1341 indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
1342 if (!indio_dev)
1343 return -ENOMEM;
1344
1345 st = iio_priv(indio_dev);
1346
1347 mutex_init(&st->lock);
1348
1349 /*
1350 * Regulator aincom is optional to maintain compatibility with older DT.
1351 * Newer firmware should provide a zero volt fixed supply if wired to
1352 * ground.
1353 */
1354 ret = devm_regulator_get_enable_read_voltage(dev, "aincom");
1355 if (ret < 0 && ret != -ENODEV)
1356 return dev_err_probe(dev, ret, "Failed to get AINCOM voltage\n");
1357
1358 st->aincom_mv = ret == -ENODEV ? 0 : ret / MILLI;
1359
1360 /* AVDD can optionally be used as reference voltage */
1361 ret = devm_regulator_get_enable_read_voltage(dev, "avdd");
1362 if (ret == -ENODEV || ret == -EINVAL) {
1363 int ret2;
1364
1365 /*
1366 * We get -EINVAL if avdd is a supply with unknown voltage. We
1367 * still need to enable it since it is also a power supply.
1368 */
1369 ret2 = devm_regulator_get_enable(dev, "avdd");
1370 if (ret2)
1371 return dev_err_probe(dev, ret2,
1372 "Failed to enable AVDD supply\n");
1373 } else if (ret < 0) {
1374 return dev_err_probe(dev, ret, "Failed to get AVDD voltage\n");
1375 }
1376
1377 avdd_mv = ret == -ENODEV || ret == -EINVAL ? 0 : ret / MILLI;
1378
1379 ret = devm_regulator_get_enable(dev, "dvdd");
1380 if (ret)
1381 return dev_err_probe(dev, ret, "Failed to enable specified DVdd supply\n");
1382
1383 /*
1384 * This is either REFIN1 or REFIN2 depending on adi,refin2-pins-enable.
1385 * If this supply is not present, fall back to AVDD as reference.
1386 */
1387 ret = devm_regulator_get_enable_read_voltage(dev, "vref");
1388 if (ret == -ENODEV) {
1389 if (avdd_mv == 0)
1390 return dev_err_probe(dev, -ENODEV,
1391 "No reference voltage available\n");
1392 } else if (ret < 0) {
1393 return ret;
1394 }
1395
1396 st->int_vref_mv = ret == -ENODEV ? avdd_mv : ret / MILLI;
1397
1398 st->chip_info = spi_get_device_match_data(spi);
1399 if (!st->chip_info)
1400 return -ENODEV;
1401
1402 indio_dev->name = st->chip_info->name;
1403 indio_dev->modes = INDIO_DIRECT_MODE;
1404 indio_dev->info = st->chip_info->info;
1405 if (st->chip_info->parse_channels) {
1406 ret = st->chip_info->parse_channels(indio_dev);
1407 if (ret)
1408 return ret;
1409 } else {
1410 indio_dev->channels = st->chip_info->channels;
1411 indio_dev->num_channels = st->chip_info->num_channels;
1412 }
1413
1414 ret = ad_sd_init(&st->sd, indio_dev, spi, st->chip_info->sigma_delta_info);
1415 if (ret)
1416 return ret;
1417
1418 ret = devm_ad_sd_setup_buffer_and_trigger(dev, indio_dev);
1419 if (ret)
1420 return ret;
1421
1422 ret = ad7192_clock_setup(st);
1423 if (ret)
1424 return ret;
1425
1426 ret = ad7192_setup(indio_dev, dev);
1427 if (ret)
1428 return ret;
1429
1430 return devm_iio_device_register(dev, indio_dev);
1431 }
1432
1433 static const struct of_device_id ad7192_of_match[] = {
1434 { .compatible = "adi,ad7190", .data = &ad7192_chip_info_tbl[ID_AD7190] },
1435 { .compatible = "adi,ad7192", .data = &ad7192_chip_info_tbl[ID_AD7192] },
1436 { .compatible = "adi,ad7193", .data = &ad7192_chip_info_tbl[ID_AD7193] },
1437 { .compatible = "adi,ad7194", .data = &ad7192_chip_info_tbl[ID_AD7194] },
1438 { .compatible = "adi,ad7195", .data = &ad7192_chip_info_tbl[ID_AD7195] },
1439 { }
1440 };
1441 MODULE_DEVICE_TABLE(of, ad7192_of_match);
1442
1443 static const struct spi_device_id ad7192_ids[] = {
1444 { "ad7190", (kernel_ulong_t)&ad7192_chip_info_tbl[ID_AD7190] },
1445 { "ad7192", (kernel_ulong_t)&ad7192_chip_info_tbl[ID_AD7192] },
1446 { "ad7193", (kernel_ulong_t)&ad7192_chip_info_tbl[ID_AD7193] },
1447 { "ad7194", (kernel_ulong_t)&ad7192_chip_info_tbl[ID_AD7194] },
1448 { "ad7195", (kernel_ulong_t)&ad7192_chip_info_tbl[ID_AD7195] },
1449 { }
1450 };
1451 MODULE_DEVICE_TABLE(spi, ad7192_ids);
1452
1453 static struct spi_driver ad7192_driver = {
1454 .driver = {
1455 .name = "ad7192",
1456 .of_match_table = ad7192_of_match,
1457 },
1458 .probe = ad7192_probe,
1459 .id_table = ad7192_ids,
1460 };
1461 module_spi_driver(ad7192_driver);
1462
1463 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
1464 MODULE_DESCRIPTION("Analog Devices AD7192 and similar ADC");
1465 MODULE_LICENSE("GPL v2");
1466 MODULE_IMPORT_NS("IIO_AD_SIGMA_DELTA");
1467