1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * AD5686R, AD5685R, AD5684R Digital to analog converters driver 4 * 5 * Copyright 2011 Analog Devices Inc. 6 */ 7 8 #include <linux/array_size.h> 9 #include <linux/bitfield.h> 10 #include <linux/bitops.h> 11 #include <linux/errno.h> 12 #include <linux/export.h> 13 #include <linux/kstrtox.h> 14 #include <linux/module.h> 15 #include <linux/regulator/consumer.h> 16 #include <linux/sysfs.h> 17 #include <linux/wordpart.h> 18 19 #include <linux/iio/iio.h> 20 21 #include "ad5686.h" 22 23 static const char * const ad5686_powerdown_modes[] = { 24 "1kohm_to_gnd", 25 "100kohm_to_gnd", 26 "three_state" 27 }; 28 29 static int ad5310_control_sync(struct ad5686_state *st) 30 { 31 unsigned int pd_val = st->pwr_down_mask & st->pwr_down_mode; 32 33 return ad5686_write(st, AD5686_CMD_CONTROL_REG, 0, 34 FIELD_PREP(AD5310_PD_MSK, pd_val & AD5686_PD_MSK) | 35 FIELD_PREP(AD5310_REF_BIT_MSK, st->use_internal_vref ? 0 : 1)); 36 } 37 38 static int ad5683_control_sync(struct ad5686_state *st) 39 { 40 unsigned int pd_val = st->pwr_down_mask & st->pwr_down_mode; 41 42 return ad5686_write(st, AD5686_CMD_CONTROL_REG, 0, 43 FIELD_PREP(AD5683_PD_MSK, pd_val & AD5686_PD_MSK) | 44 FIELD_PREP(AD5683_REF_BIT_MSK, st->use_internal_vref ? 0 : 1)); 45 } 46 47 static inline unsigned int ad5686_pd_mask_shift(const struct iio_chan_spec *chan) 48 { 49 if (chan->channel == chan->address) 50 return chan->channel * 2; 51 52 /* one-hot encoding is used in dual/quad channel devices */ 53 return __ffs(chan->address) * 2; 54 } 55 56 static inline void ad5686_pd_field_set(const struct iio_chan_spec *chan, 57 unsigned int *pd, unsigned int val) 58 { 59 unsigned int shift = ad5686_pd_mask_shift(chan); 60 61 *pd = (*pd & ~(AD5686_PD_MSK << shift)) | ((val & AD5686_PD_MSK) << shift); 62 } 63 64 static inline unsigned int ad5686_pd_field_get(const struct iio_chan_spec *chan, 65 unsigned int pd) 66 { 67 unsigned int shift = ad5686_pd_mask_shift(chan); 68 69 return (pd >> shift) & AD5686_PD_MSK; 70 } 71 72 static int ad5686_get_powerdown_mode(struct iio_dev *indio_dev, 73 const struct iio_chan_spec *chan) 74 { 75 struct ad5686_state *st = iio_priv(indio_dev); 76 77 guard(mutex)(&st->lock); 78 79 return ad5686_pd_field_get(chan, st->pwr_down_mode) - 1; 80 } 81 82 static int ad5686_set_powerdown_mode(struct iio_dev *indio_dev, 83 const struct iio_chan_spec *chan, 84 unsigned int mode) 85 { 86 struct ad5686_state *st = iio_priv(indio_dev); 87 88 guard(mutex)(&st->lock); 89 ad5686_pd_field_set(chan, &st->pwr_down_mode, mode + 1); 90 91 return 0; 92 } 93 94 static const struct iio_enum ad5686_powerdown_mode_enum = { 95 .items = ad5686_powerdown_modes, 96 .num_items = ARRAY_SIZE(ad5686_powerdown_modes), 97 .get = ad5686_get_powerdown_mode, 98 .set = ad5686_set_powerdown_mode, 99 }; 100 101 static ssize_t ad5686_read_dac_powerdown(struct iio_dev *indio_dev, 102 uintptr_t private, const struct iio_chan_spec *chan, char *buf) 103 { 104 struct ad5686_state *st = iio_priv(indio_dev); 105 106 guard(mutex)(&st->lock); 107 108 return sysfs_emit(buf, "%d\n", 109 !!ad5686_pd_field_get(chan, st->pwr_down_mask)); 110 } 111 112 static ssize_t ad5686_write_dac_powerdown(struct iio_dev *indio_dev, 113 uintptr_t private, 114 const struct iio_chan_spec *chan, 115 const char *buf, 116 size_t len) 117 { 118 bool readin; 119 int ret; 120 struct ad5686_state *st = iio_priv(indio_dev); 121 unsigned int val; 122 u8 address; 123 124 ret = kstrtobool(buf, &readin); 125 if (ret) 126 return ret; 127 128 guard(mutex)(&st->lock); 129 130 if (readin) 131 ad5686_pd_field_set(chan, &st->pwr_down_mask, AD5686_PD_MSK_PWR_DOWN); 132 else 133 ad5686_pd_field_set(chan, &st->pwr_down_mask, AD5686_PD_MSK_PWR_UP); 134 135 switch (st->chip_info->regmap_type) { 136 case AD5310_REGMAP: 137 ret = ad5310_control_sync(st); 138 if (ret) 139 return ret; 140 break; 141 case AD5683_REGMAP: 142 ret = ad5683_control_sync(st); 143 if (ret) 144 return ret; 145 break; 146 case AD5686_REGMAP: 147 /* AD5674R/AD5679R have 16 channels and 2 powerdown registers */ 148 val = st->pwr_down_mask & st->pwr_down_mode; 149 if (chan->channel > 0x7) { 150 address = 0x8; 151 val = upper_16_bits(val); 152 } else { 153 address = 0x0; 154 val = lower_16_bits(val); 155 } 156 ret = ad5686_write(st, AD5686_CMD_POWERDOWN_DAC, address, val); 157 if (ret) 158 return ret; 159 break; 160 default: 161 return -EINVAL; 162 } 163 164 return len; 165 } 166 167 static int ad5686_read_raw(struct iio_dev *indio_dev, 168 struct iio_chan_spec const *chan, 169 int *val, 170 int *val2, 171 long m) 172 { 173 struct ad5686_state *st = iio_priv(indio_dev); 174 int ret; 175 176 switch (m) { 177 case IIO_CHAN_INFO_RAW: 178 mutex_lock(&st->lock); 179 ret = ad5686_read(st, chan->address); 180 mutex_unlock(&st->lock); 181 if (ret < 0) 182 return ret; 183 *val = (ret >> chan->scan_type.shift) & 184 GENMASK(chan->scan_type.realbits - 1, 0); 185 return IIO_VAL_INT; 186 case IIO_CHAN_INFO_SCALE: 187 *val = st->vref_mv; 188 *val2 = chan->scan_type.realbits; 189 return IIO_VAL_FRACTIONAL_LOG2; 190 } 191 return -EINVAL; 192 } 193 194 static int ad5686_write_raw(struct iio_dev *indio_dev, 195 struct iio_chan_spec const *chan, 196 int val, 197 int val2, 198 long mask) 199 { 200 struct ad5686_state *st = iio_priv(indio_dev); 201 int ret; 202 203 switch (mask) { 204 case IIO_CHAN_INFO_RAW: 205 if (val >= (1 << chan->scan_type.realbits) || val < 0) 206 return -EINVAL; 207 208 mutex_lock(&st->lock); 209 ret = ad5686_write(st, AD5686_CMD_WRITE_INPUT_N_UPDATE_N, 210 chan->address, val << chan->scan_type.shift); 211 mutex_unlock(&st->lock); 212 break; 213 default: 214 ret = -EINVAL; 215 } 216 217 return ret; 218 } 219 220 static const struct iio_info ad5686_info = { 221 .read_raw = ad5686_read_raw, 222 .write_raw = ad5686_write_raw, 223 }; 224 225 static const struct iio_chan_spec_ext_info ad5686_ext_info[] = { 226 { 227 .name = "powerdown", 228 .read = ad5686_read_dac_powerdown, 229 .write = ad5686_write_dac_powerdown, 230 .shared = IIO_SEPARATE, 231 }, 232 IIO_ENUM("powerdown_mode", IIO_SEPARATE, &ad5686_powerdown_mode_enum), 233 IIO_ENUM_AVAILABLE("powerdown_mode", IIO_SHARED_BY_TYPE, &ad5686_powerdown_mode_enum), 234 { } 235 }; 236 237 #define AD5868_CHANNEL(chan, addr, bits, _shift) { \ 238 .type = IIO_VOLTAGE, \ 239 .indexed = 1, \ 240 .output = 1, \ 241 .channel = chan, \ 242 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 243 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),\ 244 .address = addr, \ 245 .scan_type = { \ 246 .sign = 'u', \ 247 .realbits = (bits), \ 248 .storagebits = 16, \ 249 .shift = (_shift), \ 250 }, \ 251 .ext_info = ad5686_ext_info, \ 252 } 253 254 #define DECLARE_AD5683_CHANNELS(name, bits, _shift) \ 255 static const struct iio_chan_spec name[] = { \ 256 AD5868_CHANNEL(0, 0, bits, _shift), \ 257 } 258 259 #define DECLARE_AD5338_CHANNELS(name, bits, _shift) \ 260 static const struct iio_chan_spec name[] = { \ 261 AD5868_CHANNEL(0, 1, bits, _shift), \ 262 AD5868_CHANNEL(1, 8, bits, _shift), \ 263 } 264 265 #define DECLARE_AD5686_CHANNELS(name, bits, _shift) \ 266 static const struct iio_chan_spec name[] = { \ 267 AD5868_CHANNEL(0, 1, bits, _shift), \ 268 AD5868_CHANNEL(1, 2, bits, _shift), \ 269 AD5868_CHANNEL(2, 4, bits, _shift), \ 270 AD5868_CHANNEL(3, 8, bits, _shift), \ 271 } 272 273 #define DECLARE_AD5676_CHANNELS(name, bits, _shift) \ 274 static const struct iio_chan_spec name[] = { \ 275 AD5868_CHANNEL(0, 0, bits, _shift), \ 276 AD5868_CHANNEL(1, 1, bits, _shift), \ 277 AD5868_CHANNEL(2, 2, bits, _shift), \ 278 AD5868_CHANNEL(3, 3, bits, _shift), \ 279 AD5868_CHANNEL(4, 4, bits, _shift), \ 280 AD5868_CHANNEL(5, 5, bits, _shift), \ 281 AD5868_CHANNEL(6, 6, bits, _shift), \ 282 AD5868_CHANNEL(7, 7, bits, _shift), \ 283 } 284 285 #define DECLARE_AD5679_CHANNELS(name, bits, _shift) \ 286 static const struct iio_chan_spec name[] = { \ 287 AD5868_CHANNEL(0, 0, bits, _shift), \ 288 AD5868_CHANNEL(1, 1, bits, _shift), \ 289 AD5868_CHANNEL(2, 2, bits, _shift), \ 290 AD5868_CHANNEL(3, 3, bits, _shift), \ 291 AD5868_CHANNEL(4, 4, bits, _shift), \ 292 AD5868_CHANNEL(5, 5, bits, _shift), \ 293 AD5868_CHANNEL(6, 6, bits, _shift), \ 294 AD5868_CHANNEL(7, 7, bits, _shift), \ 295 AD5868_CHANNEL(8, 8, bits, _shift), \ 296 AD5868_CHANNEL(9, 9, bits, _shift), \ 297 AD5868_CHANNEL(10, 10, bits, _shift), \ 298 AD5868_CHANNEL(11, 11, bits, _shift), \ 299 AD5868_CHANNEL(12, 12, bits, _shift), \ 300 AD5868_CHANNEL(13, 13, bits, _shift), \ 301 AD5868_CHANNEL(14, 14, bits, _shift), \ 302 AD5868_CHANNEL(15, 15, bits, _shift), \ 303 } 304 305 /* single-channel */ 306 DECLARE_AD5683_CHANNELS(ad5310r_channels, 10, 2); 307 DECLARE_AD5683_CHANNELS(ad5311r_channels, 10, 6); 308 DECLARE_AD5683_CHANNELS(ad5681r_channels, 12, 4); 309 DECLARE_AD5683_CHANNELS(ad5682r_channels, 14, 2); 310 DECLARE_AD5683_CHANNELS(ad5683r_channels, 16, 0); 311 312 /* dual-channel */ 313 DECLARE_AD5338_CHANNELS(ad5337r_channels, 8, 8); 314 DECLARE_AD5338_CHANNELS(ad5338r_channels, 10, 6); 315 316 /* quad-channel */ 317 DECLARE_AD5686_CHANNELS(ad5684r_channels, 12, 4); 318 DECLARE_AD5686_CHANNELS(ad5685r_channels, 14, 2); 319 DECLARE_AD5686_CHANNELS(ad5686r_channels, 16, 0); 320 321 /* 8-channel */ 322 DECLARE_AD5676_CHANNELS(ad5672r_channels, 12, 4); 323 DECLARE_AD5676_CHANNELS(ad5676r_channels, 16, 0); 324 325 /* 16-channel */ 326 DECLARE_AD5679_CHANNELS(ad5674r_channels, 12, 4); 327 DECLARE_AD5679_CHANNELS(ad5679r_channels, 16, 0); 328 329 const struct ad5686_chip_info ad5310r_chip_info = { 330 .channels = ad5310r_channels, 331 .int_vref_mv = 2500, 332 .num_channels = 1, 333 .regmap_type = AD5310_REGMAP, 334 }; 335 EXPORT_SYMBOL_NS_GPL(ad5310r_chip_info, "IIO_AD5686"); 336 337 const struct ad5686_chip_info ad5311r_chip_info = { 338 .channels = ad5311r_channels, 339 .int_vref_mv = 2500, 340 .num_channels = 1, 341 .regmap_type = AD5683_REGMAP, 342 }; 343 EXPORT_SYMBOL_NS_GPL(ad5311r_chip_info, "IIO_AD5686"); 344 345 const struct ad5686_chip_info ad5681r_chip_info = { 346 .channels = ad5681r_channels, 347 .int_vref_mv = 2500, 348 .num_channels = 1, 349 .regmap_type = AD5683_REGMAP, 350 }; 351 EXPORT_SYMBOL_NS_GPL(ad5681r_chip_info, "IIO_AD5686"); 352 353 const struct ad5686_chip_info ad5682r_chip_info = { 354 .channels = ad5682r_channels, 355 .int_vref_mv = 2500, 356 .num_channels = 1, 357 .regmap_type = AD5683_REGMAP, 358 }; 359 EXPORT_SYMBOL_NS_GPL(ad5682r_chip_info, "IIO_AD5686"); 360 361 const struct ad5686_chip_info ad5683_chip_info = { 362 .channels = ad5683r_channels, 363 .num_channels = 1, 364 .regmap_type = AD5683_REGMAP, 365 }; 366 EXPORT_SYMBOL_NS_GPL(ad5683_chip_info, "IIO_AD5686"); 367 368 const struct ad5686_chip_info ad5683r_chip_info = { 369 .channels = ad5683r_channels, 370 .int_vref_mv = 2500, 371 .num_channels = 1, 372 .regmap_type = AD5683_REGMAP, 373 }; 374 EXPORT_SYMBOL_NS_GPL(ad5683r_chip_info, "IIO_AD5686"); 375 376 const struct ad5686_chip_info ad5337r_chip_info = { 377 .channels = ad5337r_channels, 378 .int_vref_mv = 2500, 379 .num_channels = 2, 380 .regmap_type = AD5686_REGMAP, 381 }; 382 EXPORT_SYMBOL_NS_GPL(ad5337r_chip_info, "IIO_AD5686"); 383 384 const struct ad5686_chip_info ad5338r_chip_info = { 385 .channels = ad5338r_channels, 386 .int_vref_mv = 2500, 387 .num_channels = 2, 388 .regmap_type = AD5686_REGMAP, 389 }; 390 EXPORT_SYMBOL_NS_GPL(ad5338r_chip_info, "IIO_AD5686"); 391 392 const struct ad5686_chip_info ad5684_chip_info = { 393 .channels = ad5684r_channels, 394 .num_channels = 4, 395 .regmap_type = AD5686_REGMAP, 396 }; 397 EXPORT_SYMBOL_NS_GPL(ad5684_chip_info, "IIO_AD5686"); 398 399 const struct ad5686_chip_info ad5684r_chip_info = { 400 .channels = ad5684r_channels, 401 .int_vref_mv = 2500, 402 .num_channels = 4, 403 .regmap_type = AD5686_REGMAP, 404 }; 405 EXPORT_SYMBOL_NS_GPL(ad5684r_chip_info, "IIO_AD5686"); 406 407 const struct ad5686_chip_info ad5685r_chip_info = { 408 .channels = ad5685r_channels, 409 .int_vref_mv = 2500, 410 .num_channels = 4, 411 .regmap_type = AD5686_REGMAP, 412 }; 413 EXPORT_SYMBOL_NS_GPL(ad5685r_chip_info, "IIO_AD5686"); 414 415 const struct ad5686_chip_info ad5686_chip_info = { 416 .channels = ad5686r_channels, 417 .num_channels = 4, 418 .regmap_type = AD5686_REGMAP, 419 }; 420 EXPORT_SYMBOL_NS_GPL(ad5686_chip_info, "IIO_AD5686"); 421 422 const struct ad5686_chip_info ad5686r_chip_info = { 423 .channels = ad5686r_channels, 424 .int_vref_mv = 2500, 425 .num_channels = 4, 426 .regmap_type = AD5686_REGMAP, 427 }; 428 EXPORT_SYMBOL_NS_GPL(ad5686r_chip_info, "IIO_AD5686"); 429 430 const struct ad5686_chip_info ad5672r_chip_info = { 431 .channels = ad5672r_channels, 432 .int_vref_mv = 2500, 433 .num_channels = 8, 434 .regmap_type = AD5686_REGMAP, 435 }; 436 EXPORT_SYMBOL_NS_GPL(ad5672r_chip_info, "IIO_AD5686"); 437 438 const struct ad5686_chip_info ad5676_chip_info = { 439 .channels = ad5676r_channels, 440 .num_channels = 8, 441 .regmap_type = AD5686_REGMAP, 442 }; 443 EXPORT_SYMBOL_NS_GPL(ad5676_chip_info, "IIO_AD5686"); 444 445 const struct ad5686_chip_info ad5676r_chip_info = { 446 .channels = ad5676r_channels, 447 .int_vref_mv = 2500, 448 .num_channels = 8, 449 .regmap_type = AD5686_REGMAP, 450 }; 451 EXPORT_SYMBOL_NS_GPL(ad5676r_chip_info, "IIO_AD5686"); 452 453 const struct ad5686_chip_info ad5674r_chip_info = { 454 .channels = ad5674r_channels, 455 .int_vref_mv = 2500, 456 .num_channels = 16, 457 .regmap_type = AD5686_REGMAP, 458 }; 459 EXPORT_SYMBOL_NS_GPL(ad5674r_chip_info, "IIO_AD5686"); 460 461 const struct ad5686_chip_info ad5679r_chip_info = { 462 .channels = ad5679r_channels, 463 .int_vref_mv = 2500, 464 .num_channels = 16, 465 .regmap_type = AD5686_REGMAP, 466 }; 467 EXPORT_SYMBOL_NS_GPL(ad5679r_chip_info, "IIO_AD5686"); 468 469 int ad5686_probe(struct device *dev, 470 const struct ad5686_chip_info *chip_info, 471 const char *name, const struct ad5686_bus_ops *ops) 472 { 473 struct ad5686_state *st; 474 struct iio_dev *indio_dev; 475 int ret, i; 476 477 indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 478 if (indio_dev == NULL) 479 return -ENOMEM; 480 481 st = iio_priv(indio_dev); 482 483 st->dev = dev; 484 st->ops = ops; 485 st->chip_info = chip_info; 486 487 ret = devm_regulator_get_enable_read_voltage(dev, "vcc"); 488 if (ret < 0 && ret != -ENODEV) 489 return ret; 490 491 st->use_internal_vref = ret == -ENODEV; 492 st->vref_mv = st->use_internal_vref ? st->chip_info->int_vref_mv : ret / 1000; 493 494 /* Initialize masks to all ones */ 495 st->pwr_down_mask = ~0; 496 st->pwr_down_mode = ~0; 497 498 /* Set all the power down mode for all channels to 1K pulldown */ 499 for (i = 0; i < st->chip_info->num_channels; i++) { 500 ad5686_pd_field_set(&st->chip_info->channels[i], 501 &st->pwr_down_mask, AD5686_PD_MSK_PWR_UP); 502 ad5686_pd_field_set(&st->chip_info->channels[i], 503 &st->pwr_down_mode, AD5686_PD_MODE_1K_TO_GND); 504 } 505 506 indio_dev->name = name; 507 indio_dev->info = &ad5686_info; 508 indio_dev->modes = INDIO_DIRECT_MODE; 509 indio_dev->channels = st->chip_info->channels; 510 indio_dev->num_channels = st->chip_info->num_channels; 511 512 ret = devm_mutex_init(dev, &st->lock); 513 if (ret) 514 return ret; 515 516 switch (st->chip_info->regmap_type) { 517 case AD5310_REGMAP: 518 ret = ad5310_control_sync(st); 519 if (ret) 520 return ret; 521 break; 522 case AD5683_REGMAP: 523 ret = ad5683_control_sync(st); 524 if (ret) 525 return ret; 526 break; 527 case AD5686_REGMAP: 528 ret = ad5686_write(st, AD5686_CMD_INTERNAL_REFER_SETUP, 0, 529 st->use_internal_vref ? 0 : AD5686_REF_BIT_MSK); 530 if (ret) 531 return ret; 532 break; 533 default: 534 return -EINVAL; 535 } 536 537 return devm_iio_device_register(dev, indio_dev); 538 } 539 EXPORT_SYMBOL_NS_GPL(ad5686_probe, "IIO_AD5686"); 540 541 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>"); 542 MODULE_DESCRIPTION("Analog Devices AD5686/85/84 DAC"); 543 MODULE_LICENSE("GPL v2"); 544