1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * AD5592R Digital <-> Analog converters driver
4 *
5 * Copyright 2014-2016 Analog Devices Inc.
6 * Author: Paul Cercueil <paul.cercueil@analog.com>
7 */
8
9 #include <linux/bitops.h>
10 #include <linux/cleanup.h>
11 #include <linux/delay.h>
12 #include <linux/iio/iio.h>
13 #include <linux/module.h>
14 #include <linux/mutex.h>
15 #include <linux/regulator/consumer.h>
16 #include <linux/gpio/consumer.h>
17 #include <linux/gpio/driver.h>
18 #include <linux/property.h>
19
20 #include <dt-bindings/iio/adi,ad5592r.h>
21
22 #include "ad5592r-base.h"
23
ad5592r_gpio_get(struct gpio_chip * chip,unsigned offset)24 static int ad5592r_gpio_get(struct gpio_chip *chip, unsigned offset)
25 {
26 struct ad5592r_state *st = gpiochip_get_data(chip);
27 int ret = 0;
28 u8 val = 0;
29
30 scoped_guard(mutex, &st->gpio_lock) {
31 if (st->gpio_out & BIT(offset))
32 val = st->gpio_val;
33 else
34 ret = st->ops->gpio_read(st, &val);
35 }
36
37 if (ret < 0)
38 return ret;
39
40 return !!(val & BIT(offset));
41 }
42
ad5592r_gpio_set(struct gpio_chip * chip,unsigned int offset,int value)43 static int ad5592r_gpio_set(struct gpio_chip *chip, unsigned int offset,
44 int value)
45 {
46 struct ad5592r_state *st = gpiochip_get_data(chip);
47
48 guard(mutex)(&st->gpio_lock);
49
50 if (value)
51 st->gpio_val |= BIT(offset);
52 else
53 st->gpio_val &= ~BIT(offset);
54
55 return st->ops->reg_write(st, AD5592R_REG_GPIO_SET, st->gpio_val);
56 }
57
ad5592r_gpio_direction_input(struct gpio_chip * chip,unsigned offset)58 static int ad5592r_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
59 {
60 struct ad5592r_state *st = gpiochip_get_data(chip);
61 int ret;
62
63 guard(mutex)(&st->gpio_lock);
64
65 st->gpio_out &= ~BIT(offset);
66 st->gpio_in |= BIT(offset);
67
68 ret = st->ops->reg_write(st, AD5592R_REG_GPIO_OUT_EN, st->gpio_out);
69 if (ret < 0)
70 return ret;
71
72 return st->ops->reg_write(st, AD5592R_REG_GPIO_IN_EN, st->gpio_in);
73 }
74
ad5592r_gpio_direction_output(struct gpio_chip * chip,unsigned offset,int value)75 static int ad5592r_gpio_direction_output(struct gpio_chip *chip,
76 unsigned offset, int value)
77 {
78 struct ad5592r_state *st = gpiochip_get_data(chip);
79 int ret;
80
81 guard(mutex)(&st->gpio_lock);
82
83 if (value)
84 st->gpio_val |= BIT(offset);
85 else
86 st->gpio_val &= ~BIT(offset);
87
88 st->gpio_in &= ~BIT(offset);
89 st->gpio_out |= BIT(offset);
90
91 ret = st->ops->reg_write(st, AD5592R_REG_GPIO_SET, st->gpio_val);
92 if (ret < 0)
93 return ret;
94
95 ret = st->ops->reg_write(st, AD5592R_REG_GPIO_OUT_EN, st->gpio_out);
96 if (ret < 0)
97 return ret;
98
99 return st->ops->reg_write(st, AD5592R_REG_GPIO_IN_EN, st->gpio_in);
100 }
101
ad5592r_gpio_request(struct gpio_chip * chip,unsigned offset)102 static int ad5592r_gpio_request(struct gpio_chip *chip, unsigned offset)
103 {
104 struct ad5592r_state *st = gpiochip_get_data(chip);
105
106 if (!(st->gpio_map & BIT(offset))) {
107 dev_err(st->dev, "GPIO %d is reserved by alternate function\n",
108 offset);
109 return -ENODEV;
110 }
111
112 return 0;
113 }
114
115 static const char * const ad5592r_gpio_names[] = {
116 "GPIO0", "GPIO1", "GPIO2", "GPIO3", "GPIO4", "GPIO5", "GPIO6", "GPIO7",
117 };
118
ad5592r_gpio_init(struct ad5592r_state * st)119 static int ad5592r_gpio_init(struct ad5592r_state *st)
120 {
121 if (!st->gpio_map)
122 return 0;
123
124 st->gpiochip.label = dev_name(st->dev);
125 st->gpiochip.base = -1;
126 st->gpiochip.ngpio = 8;
127 st->gpiochip.parent = st->dev;
128 st->gpiochip.can_sleep = true;
129 st->gpiochip.direction_input = ad5592r_gpio_direction_input;
130 st->gpiochip.direction_output = ad5592r_gpio_direction_output;
131 st->gpiochip.get = ad5592r_gpio_get;
132 st->gpiochip.set_rv = ad5592r_gpio_set;
133 st->gpiochip.request = ad5592r_gpio_request;
134 st->gpiochip.owner = THIS_MODULE;
135 st->gpiochip.names = ad5592r_gpio_names;
136
137 mutex_init(&st->gpio_lock);
138
139 return gpiochip_add_data(&st->gpiochip, st);
140 }
141
ad5592r_gpio_cleanup(struct ad5592r_state * st)142 static void ad5592r_gpio_cleanup(struct ad5592r_state *st)
143 {
144 if (st->gpio_map)
145 gpiochip_remove(&st->gpiochip);
146
147 mutex_destroy(&st->gpio_lock);
148 }
149
ad5592r_reset(struct ad5592r_state * st)150 static int ad5592r_reset(struct ad5592r_state *st)
151 {
152 struct gpio_desc *gpio;
153
154 gpio = devm_gpiod_get_optional(st->dev, "reset", GPIOD_OUT_LOW);
155 if (IS_ERR(gpio))
156 return PTR_ERR(gpio);
157
158 if (gpio) {
159 udelay(1);
160 gpiod_set_value(gpio, 1);
161 } else {
162 scoped_guard(mutex, &st->lock)
163 /* Writing this magic value resets the device */
164 st->ops->reg_write(st, AD5592R_REG_RESET, 0xdac);
165 }
166
167 udelay(250);
168
169 return 0;
170 }
171
ad5592r_get_vref(struct ad5592r_state * st)172 static int ad5592r_get_vref(struct ad5592r_state *st)
173 {
174 int ret;
175
176 if (st->reg) {
177 ret = regulator_get_voltage(st->reg);
178 if (ret < 0)
179 return ret;
180
181 return ret / 1000;
182 } else {
183 return 2500;
184 }
185 }
186
ad5592r_set_channel_modes(struct ad5592r_state * st)187 static int ad5592r_set_channel_modes(struct ad5592r_state *st)
188 {
189 const struct ad5592r_rw_ops *ops = st->ops;
190 int ret;
191 unsigned i;
192 u8 pulldown = 0, tristate = 0, dac = 0, adc = 0;
193 u16 read_back;
194
195 for (i = 0; i < st->num_channels; i++) {
196 switch (st->channel_modes[i]) {
197 case CH_MODE_DAC:
198 dac |= BIT(i);
199 break;
200
201 case CH_MODE_ADC:
202 adc |= BIT(i);
203 break;
204
205 case CH_MODE_DAC_AND_ADC:
206 dac |= BIT(i);
207 adc |= BIT(i);
208 break;
209
210 case CH_MODE_GPIO:
211 st->gpio_map |= BIT(i);
212 st->gpio_in |= BIT(i); /* Default to input */
213 break;
214
215 case CH_MODE_UNUSED:
216 default:
217 switch (st->channel_offstate[i]) {
218 case CH_OFFSTATE_OUT_TRISTATE:
219 tristate |= BIT(i);
220 break;
221
222 case CH_OFFSTATE_OUT_LOW:
223 st->gpio_out |= BIT(i);
224 break;
225
226 case CH_OFFSTATE_OUT_HIGH:
227 st->gpio_out |= BIT(i);
228 st->gpio_val |= BIT(i);
229 break;
230
231 case CH_OFFSTATE_PULLDOWN:
232 default:
233 pulldown |= BIT(i);
234 break;
235 }
236 }
237 }
238
239 guard(mutex)(&st->lock);
240
241 /* Pull down unused pins to GND */
242 ret = ops->reg_write(st, AD5592R_REG_PULLDOWN, pulldown);
243 if (ret)
244 return ret;
245
246 ret = ops->reg_write(st, AD5592R_REG_TRISTATE, tristate);
247 if (ret)
248 return ret;
249
250 /* Configure pins that we use */
251 ret = ops->reg_write(st, AD5592R_REG_DAC_EN, dac);
252 if (ret)
253 return ret;
254
255 ret = ops->reg_write(st, AD5592R_REG_ADC_EN, adc);
256 if (ret)
257 return ret;
258
259 ret = ops->reg_write(st, AD5592R_REG_GPIO_SET, st->gpio_val);
260 if (ret)
261 return ret;
262
263 ret = ops->reg_write(st, AD5592R_REG_GPIO_OUT_EN, st->gpio_out);
264 if (ret)
265 return ret;
266
267 ret = ops->reg_write(st, AD5592R_REG_GPIO_IN_EN, st->gpio_in);
268 if (ret)
269 return ret;
270
271 /* Verify that we can read back at least one register */
272 ret = ops->reg_read(st, AD5592R_REG_ADC_EN, &read_back);
273 if (!ret && (read_back & 0xff) != adc)
274 return -EIO;
275
276 return 0;
277 }
278
ad5592r_reset_channel_modes(struct ad5592r_state * st)279 static int ad5592r_reset_channel_modes(struct ad5592r_state *st)
280 {
281 int i;
282
283 for (i = 0; i < ARRAY_SIZE(st->channel_modes); i++)
284 st->channel_modes[i] = CH_MODE_UNUSED;
285
286 return ad5592r_set_channel_modes(st);
287 }
288
ad5592r_write_raw(struct iio_dev * iio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)289 static int ad5592r_write_raw(struct iio_dev *iio_dev,
290 struct iio_chan_spec const *chan, int val, int val2, long mask)
291 {
292 struct ad5592r_state *st = iio_priv(iio_dev);
293 int ret = 0;
294
295 switch (mask) {
296 case IIO_CHAN_INFO_RAW:
297
298 if (val >= (1 << chan->scan_type.realbits) || val < 0)
299 return -EINVAL;
300
301 if (!chan->output)
302 return -EINVAL;
303
304 scoped_guard(mutex, &st->lock) {
305 ret = st->ops->write_dac(st, chan->channel, val);
306 if (!ret)
307 st->cached_dac[chan->channel] = val;
308 }
309 return ret;
310 case IIO_CHAN_INFO_SCALE:
311 if (chan->type == IIO_VOLTAGE) {
312 bool gain;
313
314 if (val == st->scale_avail[0][0] &&
315 val2 == st->scale_avail[0][1])
316 gain = false;
317 else if (val == st->scale_avail[1][0] &&
318 val2 == st->scale_avail[1][1])
319 gain = true;
320 else
321 return -EINVAL;
322
323 guard(mutex)(&st->lock);
324
325 ret = st->ops->reg_read(st, AD5592R_REG_CTRL,
326 &st->cached_gp_ctrl);
327 if (ret < 0)
328 return ret;
329
330 if (chan->output) {
331 if (gain)
332 st->cached_gp_ctrl |=
333 AD5592R_REG_CTRL_DAC_RANGE;
334 else
335 st->cached_gp_ctrl &=
336 ~AD5592R_REG_CTRL_DAC_RANGE;
337 } else {
338 if (gain)
339 st->cached_gp_ctrl |=
340 AD5592R_REG_CTRL_ADC_RANGE;
341 else
342 st->cached_gp_ctrl &=
343 ~AD5592R_REG_CTRL_ADC_RANGE;
344 }
345
346 return st->ops->reg_write(st, AD5592R_REG_CTRL,
347 st->cached_gp_ctrl);
348 }
349 break;
350 default:
351 return -EINVAL;
352 }
353
354 return 0;
355 }
356
ad5592r_read_raw(struct iio_dev * iio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long m)357 static int ad5592r_read_raw(struct iio_dev *iio_dev,
358 struct iio_chan_spec const *chan,
359 int *val, int *val2, long m)
360 {
361 struct ad5592r_state *st = iio_priv(iio_dev);
362 u16 read_val = 0;
363 int ret = 0, mult = 0;
364
365 switch (m) {
366 case IIO_CHAN_INFO_RAW:
367 if (!chan->output) {
368 scoped_guard(mutex, &st->lock)
369 ret = st->ops->read_adc(st, chan->channel,
370 &read_val);
371 if (ret)
372 return ret;
373
374 if ((read_val >> 12 & 0x7) != (chan->channel & 0x7)) {
375 dev_err(st->dev, "Error while reading channel %u\n",
376 chan->channel);
377 return -EIO;
378 }
379
380 read_val &= GENMASK(11, 0);
381
382 } else {
383 scoped_guard(mutex, &st->lock)
384 read_val = st->cached_dac[chan->channel];
385 }
386
387 dev_dbg(st->dev, "Channel %u read: 0x%04hX\n",
388 chan->channel, read_val);
389
390 *val = (int) read_val;
391 return IIO_VAL_INT;
392 case IIO_CHAN_INFO_SCALE:
393 *val = ad5592r_get_vref(st);
394
395 if (chan->type == IIO_TEMP) {
396 s64 tmp = *val * (3767897513LL / 25LL);
397 *val = div_s64_rem(tmp, 1000000000LL, val2);
398
399 return IIO_VAL_INT_PLUS_NANO;
400 }
401
402 scoped_guard(mutex, &st->lock) {
403 if (chan->output)
404 mult = !!(st->cached_gp_ctrl &
405 AD5592R_REG_CTRL_DAC_RANGE);
406 else
407 mult = !!(st->cached_gp_ctrl &
408 AD5592R_REG_CTRL_ADC_RANGE);
409 }
410
411 *val *= ++mult;
412
413 *val2 = chan->scan_type.realbits;
414
415 return IIO_VAL_FRACTIONAL_LOG2;
416 case IIO_CHAN_INFO_OFFSET: {
417 ret = ad5592r_get_vref(st);
418
419 guard(mutex)(&st->lock);
420
421 if (st->cached_gp_ctrl & AD5592R_REG_CTRL_ADC_RANGE)
422 *val = (-34365 * 25) / ret;
423 else
424 *val = (-75365 * 25) / ret;
425
426 return IIO_VAL_INT;
427 }
428 default:
429 return -EINVAL;
430 }
431 }
432
ad5592r_write_raw_get_fmt(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,long mask)433 static int ad5592r_write_raw_get_fmt(struct iio_dev *indio_dev,
434 struct iio_chan_spec const *chan, long mask)
435 {
436 switch (mask) {
437 case IIO_CHAN_INFO_SCALE:
438 return IIO_VAL_INT_PLUS_NANO;
439
440 default:
441 return IIO_VAL_INT_PLUS_MICRO;
442 }
443
444 return -EINVAL;
445 }
446
447 static const struct iio_info ad5592r_info = {
448 .read_raw = ad5592r_read_raw,
449 .write_raw = ad5592r_write_raw,
450 .write_raw_get_fmt = ad5592r_write_raw_get_fmt,
451 };
452
ad5592r_show_scale_available(struct iio_dev * iio_dev,uintptr_t private,const struct iio_chan_spec * chan,char * buf)453 static ssize_t ad5592r_show_scale_available(struct iio_dev *iio_dev,
454 uintptr_t private,
455 const struct iio_chan_spec *chan,
456 char *buf)
457 {
458 struct ad5592r_state *st = iio_priv(iio_dev);
459
460 return sprintf(buf, "%d.%09u %d.%09u\n",
461 st->scale_avail[0][0], st->scale_avail[0][1],
462 st->scale_avail[1][0], st->scale_avail[1][1]);
463 }
464
465 static const struct iio_chan_spec_ext_info ad5592r_ext_info[] = {
466 {
467 .name = "scale_available",
468 .read = ad5592r_show_scale_available,
469 .shared = IIO_SHARED_BY_TYPE,
470 },
471 { }
472 };
473
ad5592r_setup_channel(struct iio_dev * iio_dev,struct iio_chan_spec * chan,bool output,unsigned id)474 static void ad5592r_setup_channel(struct iio_dev *iio_dev,
475 struct iio_chan_spec *chan, bool output, unsigned id)
476 {
477 chan->type = IIO_VOLTAGE;
478 chan->indexed = 1;
479 chan->output = output;
480 chan->channel = id;
481 chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
482 chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE);
483 chan->scan_type.sign = 'u';
484 chan->scan_type.realbits = 12;
485 chan->scan_type.storagebits = 16;
486 chan->ext_info = ad5592r_ext_info;
487 }
488
ad5592r_alloc_channels(struct iio_dev * iio_dev)489 static int ad5592r_alloc_channels(struct iio_dev *iio_dev)
490 {
491 struct ad5592r_state *st = iio_priv(iio_dev);
492 unsigned i, curr_channel = 0,
493 num_channels = st->num_channels;
494 struct iio_chan_spec *channels;
495 struct fwnode_handle *child;
496 u32 reg, tmp;
497 int ret;
498
499 device_for_each_child_node(st->dev, child) {
500 ret = fwnode_property_read_u32(child, "reg", ®);
501 if (ret || reg >= ARRAY_SIZE(st->channel_modes))
502 continue;
503
504 ret = fwnode_property_read_u32(child, "adi,mode", &tmp);
505 if (!ret)
506 st->channel_modes[reg] = tmp;
507
508 ret = fwnode_property_read_u32(child, "adi,off-state", &tmp);
509 if (!ret)
510 st->channel_offstate[reg] = tmp;
511 }
512
513 channels = devm_kcalloc(st->dev,
514 1 + 2 * num_channels, sizeof(*channels),
515 GFP_KERNEL);
516 if (!channels)
517 return -ENOMEM;
518
519 for (i = 0; i < num_channels; i++) {
520 switch (st->channel_modes[i]) {
521 case CH_MODE_DAC:
522 ad5592r_setup_channel(iio_dev, &channels[curr_channel],
523 true, i);
524 curr_channel++;
525 break;
526
527 case CH_MODE_ADC:
528 ad5592r_setup_channel(iio_dev, &channels[curr_channel],
529 false, i);
530 curr_channel++;
531 break;
532
533 case CH_MODE_DAC_AND_ADC:
534 ad5592r_setup_channel(iio_dev, &channels[curr_channel],
535 true, i);
536 curr_channel++;
537 ad5592r_setup_channel(iio_dev, &channels[curr_channel],
538 false, i);
539 curr_channel++;
540 break;
541
542 default:
543 continue;
544 }
545 }
546
547 channels[curr_channel].type = IIO_TEMP;
548 channels[curr_channel].channel = 8;
549 channels[curr_channel].info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
550 BIT(IIO_CHAN_INFO_SCALE) |
551 BIT(IIO_CHAN_INFO_OFFSET);
552 curr_channel++;
553
554 iio_dev->num_channels = curr_channel;
555 iio_dev->channels = channels;
556
557 return 0;
558 }
559
ad5592r_init_scales(struct ad5592r_state * st,int vref_mV)560 static void ad5592r_init_scales(struct ad5592r_state *st, int vref_mV)
561 {
562 s64 tmp = (s64)vref_mV * 1000000000LL >> 12;
563
564 st->scale_avail[0][0] =
565 div_s64_rem(tmp, 1000000000LL, &st->scale_avail[0][1]);
566 st->scale_avail[1][0] =
567 div_s64_rem(tmp * 2, 1000000000LL, &st->scale_avail[1][1]);
568 }
569
ad5592r_probe(struct device * dev,const char * name,const struct ad5592r_rw_ops * ops)570 int ad5592r_probe(struct device *dev, const char *name,
571 const struct ad5592r_rw_ops *ops)
572 {
573 struct iio_dev *iio_dev;
574 struct ad5592r_state *st;
575 int ret;
576
577 iio_dev = devm_iio_device_alloc(dev, sizeof(*st));
578 if (!iio_dev)
579 return -ENOMEM;
580
581 st = iio_priv(iio_dev);
582 st->dev = dev;
583 st->ops = ops;
584 st->num_channels = 8;
585 dev_set_drvdata(dev, iio_dev);
586
587 ret = devm_mutex_init(dev, &st->lock);
588 if (ret)
589 return ret;
590
591 st->reg = devm_regulator_get_optional(dev, "vref");
592 if (IS_ERR(st->reg)) {
593 if ((PTR_ERR(st->reg) != -ENODEV) && dev_fwnode(dev))
594 return PTR_ERR(st->reg);
595
596 st->reg = NULL;
597 } else {
598 ret = regulator_enable(st->reg);
599 if (ret)
600 return ret;
601 }
602
603 iio_dev->name = name;
604 iio_dev->info = &ad5592r_info;
605 iio_dev->modes = INDIO_DIRECT_MODE;
606
607 ad5592r_init_scales(st, ad5592r_get_vref(st));
608
609 ret = ad5592r_reset(st);
610 if (ret)
611 goto error_disable_reg;
612
613 ret = ops->reg_write(st, AD5592R_REG_PD,
614 (st->reg == NULL) ? AD5592R_REG_PD_EN_REF : 0);
615 if (ret)
616 goto error_disable_reg;
617
618 ret = ad5592r_alloc_channels(iio_dev);
619 if (ret)
620 goto error_disable_reg;
621
622 ret = ad5592r_set_channel_modes(st);
623 if (ret)
624 goto error_reset_ch_modes;
625
626 ret = iio_device_register(iio_dev);
627 if (ret)
628 goto error_reset_ch_modes;
629
630 ret = ad5592r_gpio_init(st);
631 if (ret)
632 goto error_dev_unregister;
633
634 return 0;
635
636 error_dev_unregister:
637 iio_device_unregister(iio_dev);
638
639 error_reset_ch_modes:
640 ad5592r_reset_channel_modes(st);
641
642 error_disable_reg:
643 if (st->reg)
644 regulator_disable(st->reg);
645
646 return ret;
647 }
648 EXPORT_SYMBOL_NS_GPL(ad5592r_probe, "IIO_AD5592R");
649
ad5592r_remove(struct device * dev)650 void ad5592r_remove(struct device *dev)
651 {
652 struct iio_dev *iio_dev = dev_get_drvdata(dev);
653 struct ad5592r_state *st = iio_priv(iio_dev);
654
655 iio_device_unregister(iio_dev);
656 ad5592r_reset_channel_modes(st);
657 ad5592r_gpio_cleanup(st);
658
659 if (st->reg)
660 regulator_disable(st->reg);
661 }
662 EXPORT_SYMBOL_NS_GPL(ad5592r_remove, "IIO_AD5592R");
663
664 MODULE_AUTHOR("Paul Cercueil <paul.cercueil@analog.com>");
665 MODULE_DESCRIPTION("Analog Devices AD5592R multi-channel converters");
666 MODULE_LICENSE("GPL v2");
667