1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Analog Devices AD3552R 4 * Digital to Analog converter driver 5 * 6 * Copyright 2021 Analog Devices Inc. 7 */ 8 #include <linux/unaligned.h> 9 #include <linux/bitfield.h> 10 #include <linux/device.h> 11 #include <linux/iio/triggered_buffer.h> 12 #include <linux/iio/trigger_consumer.h> 13 #include <linux/iopoll.h> 14 #include <linux/kernel.h> 15 #include <linux/spi/spi.h> 16 17 #include "ad3552r.h" 18 19 struct ad3552r_desc { 20 const struct ad3552r_model_data *model_data; 21 /* Used to look the spi bus for atomic operations where needed */ 22 struct mutex lock; 23 struct gpio_desc *gpio_reset; 24 struct gpio_desc *gpio_ldac; 25 struct spi_device *spi; 26 struct ad3552r_ch_data ch_data[AD3552R_MAX_CH]; 27 struct iio_chan_spec channels[AD3552R_MAX_CH + 1]; 28 unsigned long enabled_ch; 29 unsigned int num_ch; 30 }; 31 32 static u8 _ad3552r_reg_len(u8 addr) 33 { 34 switch (addr) { 35 case AD3552R_REG_ADDR_HW_LDAC_16B: 36 case AD3552R_REG_ADDR_CH_SELECT_16B: 37 case AD3552R_REG_ADDR_SW_LDAC_16B: 38 case AD3552R_REG_ADDR_HW_LDAC_24B: 39 case AD3552R_REG_ADDR_CH_SELECT_24B: 40 case AD3552R_REG_ADDR_SW_LDAC_24B: 41 return 1; 42 default: 43 break; 44 } 45 46 if (addr > AD3552R_REG_ADDR_HW_LDAC_24B) 47 return 3; 48 if (addr > AD3552R_REG_ADDR_HW_LDAC_16B) 49 return 2; 50 51 return 1; 52 } 53 54 /* SPI transfer to device */ 55 static int ad3552r_transfer(struct ad3552r_desc *dac, u8 addr, u32 len, 56 u8 *data, bool is_read) 57 { 58 /* Maximum transfer: Addr (1B) + 2 * (Data Reg (3B)) + SW LDAC(1B) */ 59 u8 buf[8]; 60 61 buf[0] = addr & AD3552R_ADDR_MASK; 62 buf[0] |= is_read ? AD3552R_READ_BIT : 0; 63 if (is_read) 64 return spi_write_then_read(dac->spi, buf, 1, data, len); 65 66 memcpy(buf + 1, data, len); 67 return spi_write_then_read(dac->spi, buf, len + 1, NULL, 0); 68 } 69 70 static int ad3552r_write_reg(struct ad3552r_desc *dac, u8 addr, u16 val) 71 { 72 u8 reg_len; 73 u8 buf[AD3552R_MAX_REG_SIZE] = { 0 }; 74 75 reg_len = _ad3552r_reg_len(addr); 76 if (reg_len == 2) 77 /* Only DAC register are 2 bytes wide */ 78 val &= AD3552R_MASK_DAC_12B; 79 if (reg_len == 1) 80 buf[0] = val & 0xFF; 81 else 82 /* reg_len can be 2 or 3, but 3rd bytes needs to be set to 0 */ 83 put_unaligned_be16(val, buf); 84 85 return ad3552r_transfer(dac, addr, reg_len, buf, false); 86 } 87 88 static int ad3552r_read_reg(struct ad3552r_desc *dac, u8 addr, u16 *val) 89 { 90 int err; 91 u8 reg_len, buf[AD3552R_MAX_REG_SIZE] = { 0 }; 92 93 reg_len = _ad3552r_reg_len(addr); 94 err = ad3552r_transfer(dac, addr, reg_len, buf, true); 95 if (err) 96 return err; 97 98 if (reg_len == 1) 99 *val = buf[0]; 100 else 101 /* reg_len can be 2 or 3, but only first 2 bytes are relevant */ 102 *val = get_unaligned_be16(buf); 103 104 return 0; 105 } 106 107 /* Update field of a register, shift val if needed */ 108 static int ad3552r_update_reg_field(struct ad3552r_desc *dac, u8 addr, u16 mask, 109 u16 val) 110 { 111 int ret; 112 u16 reg; 113 114 ret = ad3552r_read_reg(dac, addr, ®); 115 if (ret < 0) 116 return ret; 117 118 reg &= ~mask; 119 reg |= val; 120 121 return ad3552r_write_reg(dac, addr, reg); 122 } 123 124 #define AD3552R_CH_DAC(_idx) ((struct iio_chan_spec) { \ 125 .type = IIO_VOLTAGE, \ 126 .output = true, \ 127 .indexed = true, \ 128 .channel = _idx, \ 129 .scan_index = _idx, \ 130 .scan_type = { \ 131 .sign = 'u', \ 132 .realbits = 16, \ 133 .storagebits = 16, \ 134 .endianness = IIO_BE, \ 135 }, \ 136 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 137 BIT(IIO_CHAN_INFO_SCALE) | \ 138 BIT(IIO_CHAN_INFO_ENABLE) | \ 139 BIT(IIO_CHAN_INFO_OFFSET), \ 140 }) 141 142 static int ad3552r_read_raw(struct iio_dev *indio_dev, 143 struct iio_chan_spec const *chan, 144 int *val, 145 int *val2, 146 long mask) 147 { 148 struct ad3552r_desc *dac = iio_priv(indio_dev); 149 u16 tmp_val; 150 int err; 151 u8 ch = chan->channel; 152 153 switch (mask) { 154 case IIO_CHAN_INFO_RAW: 155 mutex_lock(&dac->lock); 156 err = ad3552r_read_reg(dac, AD3552R_REG_ADDR_CH_DAC_24B(ch), 157 &tmp_val); 158 mutex_unlock(&dac->lock); 159 if (err < 0) 160 return err; 161 *val = tmp_val; 162 return IIO_VAL_INT; 163 case IIO_CHAN_INFO_ENABLE: 164 mutex_lock(&dac->lock); 165 err = ad3552r_read_reg(dac, AD3552R_REG_ADDR_POWERDOWN_CONFIG, 166 &tmp_val); 167 mutex_unlock(&dac->lock); 168 if (err < 0) 169 return err; 170 *val = !field_get(AD3552R_MASK_CH_DAC_POWERDOWN(ch), tmp_val); 171 return IIO_VAL_INT; 172 case IIO_CHAN_INFO_SCALE: 173 *val = dac->ch_data[ch].scale_int; 174 *val2 = dac->ch_data[ch].scale_dec; 175 return IIO_VAL_INT_PLUS_MICRO; 176 case IIO_CHAN_INFO_OFFSET: 177 *val = dac->ch_data[ch].offset_int; 178 *val2 = dac->ch_data[ch].offset_dec; 179 return IIO_VAL_INT_PLUS_MICRO; 180 default: 181 return -EINVAL; 182 } 183 } 184 185 static int ad3552r_write_raw(struct iio_dev *indio_dev, 186 struct iio_chan_spec const *chan, 187 int val, 188 int val2, 189 long mask) 190 { 191 struct ad3552r_desc *dac = iio_priv(indio_dev); 192 int err; 193 194 mutex_lock(&dac->lock); 195 switch (mask) { 196 case IIO_CHAN_INFO_RAW: 197 err = ad3552r_write_reg(dac, 198 AD3552R_REG_ADDR_CH_DAC_24B(chan->channel), 199 val); 200 break; 201 case IIO_CHAN_INFO_ENABLE: 202 if (chan->channel == 0) 203 val = FIELD_PREP(AD3552R_MASK_CH_DAC_POWERDOWN(0), !val); 204 else 205 val = FIELD_PREP(AD3552R_MASK_CH_DAC_POWERDOWN(1), !val); 206 207 err = ad3552r_update_reg_field(dac, AD3552R_REG_ADDR_POWERDOWN_CONFIG, 208 AD3552R_MASK_CH_DAC_POWERDOWN(chan->channel), 209 val); 210 break; 211 default: 212 err = -EINVAL; 213 break; 214 } 215 mutex_unlock(&dac->lock); 216 217 return err; 218 } 219 220 static const struct iio_info ad3552r_iio_info = { 221 .read_raw = ad3552r_read_raw, 222 .write_raw = ad3552r_write_raw 223 }; 224 225 static int32_t ad3552r_trigger_hw_ldac(struct gpio_desc *ldac) 226 { 227 gpiod_set_value_cansleep(ldac, 0); 228 usleep_range(AD3552R_LDAC_PULSE_US, AD3552R_LDAC_PULSE_US + 10); 229 gpiod_set_value_cansleep(ldac, 1); 230 231 return 0; 232 } 233 234 static int ad3552r_write_all_channels(struct ad3552r_desc *dac, u8 *data) 235 { 236 int err, len; 237 u8 addr, buff[AD3552R_MAX_CH * AD3552R_MAX_REG_SIZE + 1]; 238 239 addr = AD3552R_REG_ADDR_CH_INPUT_24B(1); 240 /* CH1 */ 241 memcpy(buff, data + 2, 2); 242 buff[2] = 0; 243 /* CH0 */ 244 memcpy(buff + 3, data, 2); 245 buff[5] = 0; 246 len = 6; 247 if (!dac->gpio_ldac) { 248 /* Software LDAC */ 249 buff[6] = AD3552R_MASK_ALL_CH; 250 ++len; 251 } 252 err = ad3552r_transfer(dac, addr, len, buff, false); 253 if (err) 254 return err; 255 256 if (dac->gpio_ldac) 257 return ad3552r_trigger_hw_ldac(dac->gpio_ldac); 258 259 return 0; 260 } 261 262 static int ad3552r_write_codes(struct ad3552r_desc *dac, u32 mask, u8 *data) 263 { 264 int err; 265 u8 addr, buff[AD3552R_MAX_REG_SIZE]; 266 267 if (mask == AD3552R_MASK_ALL_CH) { 268 if (memcmp(data, data + 2, 2) != 0) 269 return ad3552r_write_all_channels(dac, data); 270 271 addr = AD3552R_REG_ADDR_INPUT_PAGE_MASK_24B; 272 } else { 273 addr = AD3552R_REG_ADDR_CH_INPUT_24B(__ffs(mask)); 274 } 275 276 memcpy(buff, data, 2); 277 buff[2] = 0; 278 err = ad3552r_transfer(dac, addr, 3, data, false); 279 if (err) 280 return err; 281 282 if (dac->gpio_ldac) 283 return ad3552r_trigger_hw_ldac(dac->gpio_ldac); 284 285 return ad3552r_write_reg(dac, AD3552R_REG_ADDR_SW_LDAC_24B, mask); 286 } 287 288 static irqreturn_t ad3552r_trigger_handler(int irq, void *p) 289 { 290 struct iio_poll_func *pf = p; 291 struct iio_dev *indio_dev = pf->indio_dev; 292 struct iio_buffer *buf = indio_dev->buffer; 293 struct ad3552r_desc *dac = iio_priv(indio_dev); 294 /* Maximum size of a scan */ 295 u8 buff[AD3552R_MAX_CH * AD3552R_MAX_REG_SIZE] = { }; 296 int err; 297 298 err = iio_pop_from_buffer(buf, buff); 299 if (err) 300 goto end; 301 302 mutex_lock(&dac->lock); 303 ad3552r_write_codes(dac, *indio_dev->active_scan_mask, buff); 304 mutex_unlock(&dac->lock); 305 end: 306 iio_trigger_notify_done(indio_dev->trig); 307 308 return IRQ_HANDLED; 309 } 310 311 static int ad3552r_check_scratch_pad(struct ad3552r_desc *dac) 312 { 313 const u16 val1 = AD3552R_SCRATCH_PAD_TEST_VAL1; 314 const u16 val2 = AD3552R_SCRATCH_PAD_TEST_VAL2; 315 u16 val; 316 int err; 317 318 err = ad3552r_write_reg(dac, AD3552R_REG_ADDR_SCRATCH_PAD, val1); 319 if (err < 0) 320 return err; 321 322 err = ad3552r_read_reg(dac, AD3552R_REG_ADDR_SCRATCH_PAD, &val); 323 if (err < 0) 324 return err; 325 326 if (val1 != val) 327 return -ENODEV; 328 329 err = ad3552r_write_reg(dac, AD3552R_REG_ADDR_SCRATCH_PAD, val2); 330 if (err < 0) 331 return err; 332 333 err = ad3552r_read_reg(dac, AD3552R_REG_ADDR_SCRATCH_PAD, &val); 334 if (err < 0) 335 return err; 336 337 if (val2 != val) 338 return -ENODEV; 339 340 return 0; 341 } 342 343 struct reg_addr_pool { 344 struct ad3552r_desc *dac; 345 u8 addr; 346 }; 347 348 static int ad3552r_read_reg_wrapper(struct reg_addr_pool *addr) 349 { 350 int err; 351 u16 val; 352 353 err = ad3552r_read_reg(addr->dac, addr->addr, &val); 354 if (err) 355 return err; 356 357 return val; 358 } 359 360 static int ad3552r_reset(struct ad3552r_desc *dac) 361 { 362 struct reg_addr_pool addr; 363 int ret; 364 int val; 365 366 dac->gpio_reset = devm_gpiod_get_optional(&dac->spi->dev, "reset", 367 GPIOD_OUT_LOW); 368 if (IS_ERR(dac->gpio_reset)) 369 return dev_err_probe(&dac->spi->dev, PTR_ERR(dac->gpio_reset), 370 "Error while getting gpio reset"); 371 372 if (dac->gpio_reset) { 373 /* Perform hardware reset */ 374 usleep_range(10, 20); 375 gpiod_set_value_cansleep(dac->gpio_reset, 1); 376 } else { 377 /* Perform software reset if no GPIO provided */ 378 ret = ad3552r_update_reg_field(dac, 379 AD3552R_REG_ADDR_INTERFACE_CONFIG_A, 380 AD3552R_MASK_SOFTWARE_RESET, 381 AD3552R_MASK_SOFTWARE_RESET); 382 if (ret < 0) 383 return ret; 384 385 } 386 387 addr.dac = dac; 388 addr.addr = AD3552R_REG_ADDR_INTERFACE_CONFIG_B; 389 ret = readx_poll_timeout(ad3552r_read_reg_wrapper, &addr, val, 390 val == AD3552R_DEFAULT_CONFIG_B_VALUE || 391 val < 0, 392 5000, 50000); 393 if (val < 0) 394 ret = val; 395 if (ret) { 396 dev_err(&dac->spi->dev, "Error while resetting"); 397 return ret; 398 } 399 400 ret = readx_poll_timeout(ad3552r_read_reg_wrapper, &addr, val, 401 !(val & AD3552R_MASK_INTERFACE_NOT_READY) || 402 val < 0, 403 5000, 50000); 404 if (val < 0) 405 ret = val; 406 if (ret) { 407 dev_err(&dac->spi->dev, "Error while resetting"); 408 return ret; 409 } 410 411 /* Clear reset error flag, see ad3552r manual, rev B table 38. */ 412 ret = ad3552r_write_reg(dac, AD3552R_REG_ADDR_ERR_STATUS, 413 AD3552R_MASK_RESET_STATUS); 414 if (ret) 415 return ret; 416 417 return ad3552r_update_reg_field(dac, 418 AD3552R_REG_ADDR_INTERFACE_CONFIG_A, 419 AD3552R_MASK_ADDR_ASCENSION, 420 FIELD_PREP(AD3552R_MASK_ADDR_ASCENSION, val)); 421 } 422 423 static int ad3552r_configure_custom_gain(struct ad3552r_desc *dac, 424 struct fwnode_handle *child, 425 u32 ch) 426 { 427 struct device *dev = &dac->spi->dev; 428 int err; 429 u8 addr; 430 u16 reg; 431 432 err = ad3552r_get_custom_gain(dev, child, 433 &dac->ch_data[ch].p, 434 &dac->ch_data[ch].n, 435 &dac->ch_data[ch].rfb, 436 &dac->ch_data[ch].gain_offset); 437 if (err) 438 return err; 439 440 dac->ch_data[ch].range_override = 1; 441 442 addr = AD3552R_REG_ADDR_CH_GAIN(ch); 443 err = ad3552r_write_reg(dac, addr, 444 abs((s32)dac->ch_data[ch].gain_offset) & 445 AD3552R_MASK_CH_OFFSET_BITS_0_7); 446 if (err) 447 return dev_err_probe(dev, err, "Error writing register\n"); 448 449 reg = ad3552r_calc_custom_gain(dac->ch_data[ch].p, dac->ch_data[ch].n, 450 dac->ch_data[ch].gain_offset); 451 452 err = ad3552r_write_reg(dac, addr, reg); 453 if (err) 454 return dev_err_probe(dev, err, "Error writing register\n"); 455 456 return 0; 457 } 458 459 static int ad3552r_configure_device(struct ad3552r_desc *dac) 460 { 461 struct device *dev = &dac->spi->dev; 462 int err, cnt = 0; 463 u32 val, ch; 464 465 dac->gpio_ldac = devm_gpiod_get_optional(dev, "ldac", GPIOD_OUT_HIGH); 466 if (IS_ERR(dac->gpio_ldac)) 467 return dev_err_probe(dev, PTR_ERR(dac->gpio_ldac), 468 "Error getting gpio ldac"); 469 470 err = ad3552r_get_ref_voltage(dev, &val); 471 if (err < 0) 472 return err; 473 474 err = ad3552r_update_reg_field(dac, 475 AD3552R_REG_ADDR_SH_REFERENCE_CONFIG, 476 AD3552R_MASK_REFERENCE_VOLTAGE_SEL, 477 FIELD_PREP(AD3552R_MASK_REFERENCE_VOLTAGE_SEL, val)); 478 if (err) 479 return err; 480 481 err = ad3552r_get_drive_strength(dev, &val); 482 if (!err) { 483 err = ad3552r_update_reg_field(dac, 484 AD3552R_REG_ADDR_INTERFACE_CONFIG_D, 485 AD3552R_MASK_SDO_DRIVE_STRENGTH, 486 FIELD_PREP(AD3552R_MASK_SDO_DRIVE_STRENGTH, val)); 487 if (err) 488 return err; 489 } 490 491 dac->num_ch = device_get_child_node_count(dev); 492 if (!dac->num_ch) { 493 dev_err(dev, "No channels defined\n"); 494 return -ENODEV; 495 } 496 497 device_for_each_child_node_scoped(dev, child) { 498 err = fwnode_property_read_u32(child, "reg", &ch); 499 if (err) 500 return dev_err_probe(dev, err, 501 "mandatory reg property missing\n"); 502 if (ch >= dac->model_data->num_hw_channels) 503 return dev_err_probe(dev, -EINVAL, 504 "reg must be less than %d\n", 505 dac->model_data->num_hw_channels); 506 507 err = ad3552r_get_output_range(dev, dac->model_data, 508 child, &val); 509 if (err && err != -ENOENT) 510 return err; 511 512 if (!err) { 513 if (ch == 0) 514 val = FIELD_PREP(AD3552R_MASK_CH_OUTPUT_RANGE_SEL(0), val); 515 else 516 val = FIELD_PREP(AD3552R_MASK_CH_OUTPUT_RANGE_SEL(1), val); 517 518 err = ad3552r_update_reg_field(dac, 519 AD3552R_REG_ADDR_CH0_CH1_OUTPUT_RANGE, 520 AD3552R_MASK_CH_OUTPUT_RANGE_SEL(ch), 521 val); 522 if (err) 523 return err; 524 525 dac->ch_data[ch].range = val; 526 } else if (dac->model_data->requires_output_range) { 527 return dev_err_probe(dev, -EINVAL, 528 "adi,output-range-microvolt is required for %s\n", 529 dac->model_data->model_name); 530 } else { 531 err = ad3552r_configure_custom_gain(dac, child, ch); 532 if (err) 533 return err; 534 } 535 536 ad3552r_calc_gain_and_offset(&dac->ch_data[ch], dac->model_data); 537 dac->enabled_ch |= BIT(ch); 538 539 if (ch == 0) 540 val = FIELD_PREP(AD3552R_MASK_CH(0), 1); 541 else 542 val = FIELD_PREP(AD3552R_MASK_CH(1), 1); 543 544 err = ad3552r_update_reg_field(dac, 545 AD3552R_REG_ADDR_CH_SELECT_16B, 546 AD3552R_MASK_CH(ch), val); 547 if (err < 0) 548 return err; 549 550 dac->channels[cnt] = AD3552R_CH_DAC(ch); 551 ++cnt; 552 553 } 554 555 /* Disable unused channels */ 556 for_each_clear_bit(ch, &dac->enabled_ch, 557 dac->model_data->num_hw_channels) { 558 if (ch == 0) 559 val = FIELD_PREP(AD3552R_MASK_CH_AMPLIFIER_POWERDOWN(0), 1); 560 else 561 val = FIELD_PREP(AD3552R_MASK_CH_AMPLIFIER_POWERDOWN(1), 1); 562 563 err = ad3552r_update_reg_field(dac, 564 AD3552R_REG_ADDR_POWERDOWN_CONFIG, 565 AD3552R_MASK_CH_AMPLIFIER_POWERDOWN(ch), 566 val); 567 if (err) 568 return err; 569 } 570 571 dac->num_ch = cnt; 572 573 return 0; 574 } 575 576 static int ad3552r_init(struct ad3552r_desc *dac) 577 { 578 int err; 579 u16 val, id; 580 581 err = ad3552r_reset(dac); 582 if (err) { 583 dev_err(&dac->spi->dev, "Reset failed\n"); 584 return err; 585 } 586 587 err = ad3552r_check_scratch_pad(dac); 588 if (err) { 589 dev_err(&dac->spi->dev, "Scratch pad test failed\n"); 590 return err; 591 } 592 593 err = ad3552r_read_reg(dac, AD3552R_REG_ADDR_PRODUCT_ID_L, &val); 594 if (err) { 595 dev_err(&dac->spi->dev, "Fail read PRODUCT_ID_L\n"); 596 return err; 597 } 598 599 id = val; 600 err = ad3552r_read_reg(dac, AD3552R_REG_ADDR_PRODUCT_ID_H, &val); 601 if (err) { 602 dev_err(&dac->spi->dev, "Fail read PRODUCT_ID_H\n"); 603 return err; 604 } 605 606 id |= val << 8; 607 if (id != dac->model_data->chip_id) { 608 dev_err(&dac->spi->dev, "Product id not matching\n"); 609 return -ENODEV; 610 } 611 612 return ad3552r_configure_device(dac); 613 } 614 615 static int ad3552r_probe(struct spi_device *spi) 616 { 617 struct ad3552r_desc *dac; 618 struct iio_dev *indio_dev; 619 int err; 620 621 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*dac)); 622 if (!indio_dev) 623 return -ENOMEM; 624 625 dac = iio_priv(indio_dev); 626 dac->spi = spi; 627 dac->model_data = spi_get_device_match_data(spi); 628 if (!dac->model_data) 629 return -EINVAL; 630 631 err = devm_mutex_init(&spi->dev, &dac->lock); 632 if (err) 633 return err; 634 635 err = ad3552r_init(dac); 636 if (err) 637 return err; 638 639 /* Config triggered buffer device */ 640 indio_dev->name = dac->model_data->model_name; 641 indio_dev->dev.parent = &spi->dev; 642 indio_dev->info = &ad3552r_iio_info; 643 indio_dev->num_channels = dac->num_ch; 644 indio_dev->channels = dac->channels; 645 indio_dev->modes = INDIO_DIRECT_MODE; 646 647 err = devm_iio_triggered_buffer_setup_ext(&indio_dev->dev, indio_dev, NULL, 648 &ad3552r_trigger_handler, 649 IIO_BUFFER_DIRECTION_OUT, 650 NULL, 651 NULL); 652 if (err) 653 return err; 654 655 return devm_iio_device_register(&spi->dev, indio_dev); 656 } 657 658 static const struct spi_device_id ad3552r_id[] = { 659 { 660 .name = "ad3541r", 661 .driver_data = (kernel_ulong_t)&ad3541r_model_data 662 }, 663 { 664 .name = "ad3542r", 665 .driver_data = (kernel_ulong_t)&ad3542r_model_data 666 }, 667 { 668 .name = "ad3551r", 669 .driver_data = (kernel_ulong_t)&ad3551r_model_data 670 }, 671 { 672 .name = "ad3552r", 673 .driver_data = (kernel_ulong_t)&ad3552r_model_data 674 }, 675 { } 676 }; 677 MODULE_DEVICE_TABLE(spi, ad3552r_id); 678 679 static const struct of_device_id ad3552r_of_match[] = { 680 { .compatible = "adi,ad3541r", .data = &ad3541r_model_data }, 681 { .compatible = "adi,ad3542r", .data = &ad3542r_model_data }, 682 { .compatible = "adi,ad3551r", .data = &ad3551r_model_data }, 683 { .compatible = "adi,ad3552r", .data = &ad3552r_model_data }, 684 { } 685 }; 686 MODULE_DEVICE_TABLE(of, ad3552r_of_match); 687 688 static struct spi_driver ad3552r_driver = { 689 .driver = { 690 .name = "ad3552r", 691 .of_match_table = ad3552r_of_match, 692 }, 693 .probe = ad3552r_probe, 694 .id_table = ad3552r_id 695 }; 696 module_spi_driver(ad3552r_driver); 697 698 MODULE_AUTHOR("Mihail Chindris <mihail.chindris@analog.com>"); 699 MODULE_DESCRIPTION("Analog Device AD3552R DAC"); 700 MODULE_LICENSE("GPL v2"); 701 MODULE_IMPORT_NS("IIO_AD3552R"); 702