1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * AD3530R/AD3530 8-channel, 16-bit Voltage Output DAC Driver
4 * AD3531R/AD3531 4-channel, 16-bit Voltage Output DAC Driver
5 *
6 * Copyright 2025 Analog Devices Inc.
7 */
8
9 #include <linux/array_size.h>
10 #include <linux/bitfield.h>
11 #include <linux/bits.h>
12 #include <linux/cleanup.h>
13 #include <linux/delay.h>
14 #include <linux/dev_printk.h>
15 #include <linux/err.h>
16 #include <linux/gpio/consumer.h>
17 #include <linux/iio/iio.h>
18 #include <linux/kstrtox.h>
19 #include <linux/mod_devicetable.h>
20 #include <linux/module.h>
21 #include <linux/mutex.h>
22 #include <linux/property.h>
23 #include <linux/regmap.h>
24 #include <linux/regulator/consumer.h>
25 #include <linux/spi/spi.h>
26 #include <linux/sysfs.h>
27 #include <linux/types.h>
28 #include <linux/units.h>
29
30 #define AD3530R_INTERFACE_CONFIG_A 0x00
31 #define AD3530R_OUTPUT_OPERATING_MODE_0 0x20
32 #define AD3530R_OUTPUT_OPERATING_MODE_1 0x21
33 #define AD3530R_OUTPUT_CONTROL_0 0x2A
34 #define AD3530R_REFERENCE_CONTROL_0 0x3C
35 #define AD3530R_SW_LDAC_TRIG_A 0xE5
36 #define AD3530R_INPUT_CH 0xEB
37 #define AD3530R_MAX_REG_ADDR 0xF9
38
39 #define AD3531R_SW_LDAC_TRIG_A 0xDD
40 #define AD3531R_INPUT_CH 0xE3
41
42 #define AD3530R_SLD_TRIG_A BIT(7)
43 #define AD3530R_OUTPUT_CONTROL_RANGE BIT(2)
44 #define AD3530R_REFERENCE_CONTROL_SEL BIT(0)
45 #define AD3530R_REG_VAL_MASK GENMASK(15, 0)
46 #define AD3530R_OP_MODE_CHAN_MSK(chan) (GENMASK(1, 0) << 2 * (chan))
47
48 #define AD3530R_SW_RESET (BIT(7) | BIT(0))
49 #define AD3530R_INTERNAL_VREF_mV 2500
50 #define AD3530R_LDAC_PULSE_US 100
51
52 #define AD3530R_DAC_MAX_VAL GENMASK(15, 0)
53 #define AD3530R_MAX_CHANNELS 8
54 #define AD3531R_MAX_CHANNELS 4
55
56 enum ad3530r_mode {
57 AD3530R_NORMAL_OP,
58 AD3530R_POWERDOWN_1K,
59 AD3530R_POWERDOWN_7K7,
60 AD3530R_POWERDOWN_32K,
61 };
62
63 struct ad3530r_chan {
64 enum ad3530r_mode powerdown_mode;
65 bool powerdown;
66 };
67
68 struct ad3530r_chip_info {
69 const char *name;
70 const struct iio_chan_spec *channels;
71 int (*input_ch_reg)(unsigned int channel);
72 unsigned int num_channels;
73 unsigned int sw_ldac_trig_reg;
74 bool internal_ref_support;
75 };
76
77 struct ad3530r_state {
78 struct regmap *regmap;
79 /* lock to protect against multiple access to the device and shared data */
80 struct mutex lock;
81 struct ad3530r_chan chan[AD3530R_MAX_CHANNELS];
82 const struct ad3530r_chip_info *chip_info;
83 struct gpio_desc *ldac_gpio;
84 int vref_mV;
85 /*
86 * DMA (thus cache coherency maintenance) may require the transfer
87 * buffers to live in their own cache lines.
88 */
89 __be16 buf __aligned(IIO_DMA_MINALIGN);
90 };
91
ad3530r_input_ch_reg(unsigned int channel)92 static int ad3530r_input_ch_reg(unsigned int channel)
93 {
94 return 2 * channel + AD3530R_INPUT_CH;
95 }
96
ad3531r_input_ch_reg(unsigned int channel)97 static int ad3531r_input_ch_reg(unsigned int channel)
98 {
99 return 2 * channel + AD3531R_INPUT_CH;
100 }
101
102 static const char * const ad3530r_powerdown_modes[] = {
103 "1kohm_to_gnd",
104 "7.7kohm_to_gnd",
105 "32kohm_to_gnd",
106 };
107
ad3530r_get_powerdown_mode(struct iio_dev * indio_dev,const struct iio_chan_spec * chan)108 static int ad3530r_get_powerdown_mode(struct iio_dev *indio_dev,
109 const struct iio_chan_spec *chan)
110 {
111 struct ad3530r_state *st = iio_priv(indio_dev);
112
113 guard(mutex)(&st->lock);
114 return st->chan[chan->channel].powerdown_mode - 1;
115 }
116
ad3530r_set_powerdown_mode(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,unsigned int mode)117 static int ad3530r_set_powerdown_mode(struct iio_dev *indio_dev,
118 const struct iio_chan_spec *chan,
119 unsigned int mode)
120 {
121 struct ad3530r_state *st = iio_priv(indio_dev);
122
123 guard(mutex)(&st->lock);
124 st->chan[chan->channel].powerdown_mode = mode + 1;
125
126 return 0;
127 }
128
129 static const struct iio_enum ad3530r_powerdown_mode_enum = {
130 .items = ad3530r_powerdown_modes,
131 .num_items = ARRAY_SIZE(ad3530r_powerdown_modes),
132 .get = ad3530r_get_powerdown_mode,
133 .set = ad3530r_set_powerdown_mode,
134 };
135
ad3530r_get_dac_powerdown(struct iio_dev * indio_dev,uintptr_t private,const struct iio_chan_spec * chan,char * buf)136 static ssize_t ad3530r_get_dac_powerdown(struct iio_dev *indio_dev,
137 uintptr_t private,
138 const struct iio_chan_spec *chan,
139 char *buf)
140 {
141 struct ad3530r_state *st = iio_priv(indio_dev);
142
143 guard(mutex)(&st->lock);
144 return sysfs_emit(buf, "%d\n", st->chan[chan->channel].powerdown);
145 }
146
ad3530r_set_dac_powerdown(struct iio_dev * indio_dev,uintptr_t private,const struct iio_chan_spec * chan,const char * buf,size_t len)147 static ssize_t ad3530r_set_dac_powerdown(struct iio_dev *indio_dev,
148 uintptr_t private,
149 const struct iio_chan_spec *chan,
150 const char *buf, size_t len)
151 {
152 struct ad3530r_state *st = iio_priv(indio_dev);
153 int ret;
154 unsigned int reg, pdmode, mask, val;
155 bool powerdown;
156
157 ret = kstrtobool(buf, &powerdown);
158 if (ret)
159 return ret;
160
161 guard(mutex)(&st->lock);
162 reg = chan->channel < AD3531R_MAX_CHANNELS ?
163 AD3530R_OUTPUT_OPERATING_MODE_0 :
164 AD3530R_OUTPUT_OPERATING_MODE_1;
165 pdmode = powerdown ? st->chan[chan->channel].powerdown_mode : 0;
166 mask = chan->channel < AD3531R_MAX_CHANNELS ?
167 AD3530R_OP_MODE_CHAN_MSK(chan->channel) :
168 AD3530R_OP_MODE_CHAN_MSK(chan->channel - 4);
169 val = field_prep(mask, pdmode);
170
171 ret = regmap_update_bits(st->regmap, reg, mask, val);
172 if (ret)
173 return ret;
174
175 st->chan[chan->channel].powerdown = powerdown;
176
177 return len;
178 }
179
ad3530r_trigger_hw_ldac(struct gpio_desc * ldac_gpio)180 static int ad3530r_trigger_hw_ldac(struct gpio_desc *ldac_gpio)
181 {
182 gpiod_set_value_cansleep(ldac_gpio, 1);
183 fsleep(AD3530R_LDAC_PULSE_US);
184 gpiod_set_value_cansleep(ldac_gpio, 0);
185
186 return 0;
187 }
188
ad3530r_dac_write(struct ad3530r_state * st,unsigned int chan,unsigned int val)189 static int ad3530r_dac_write(struct ad3530r_state *st, unsigned int chan,
190 unsigned int val)
191 {
192 int ret;
193
194 guard(mutex)(&st->lock);
195 st->buf = cpu_to_be16(val);
196
197 ret = regmap_bulk_write(st->regmap, st->chip_info->input_ch_reg(chan),
198 &st->buf, sizeof(st->buf));
199 if (ret)
200 return ret;
201
202 if (st->ldac_gpio)
203 return ad3530r_trigger_hw_ldac(st->ldac_gpio);
204
205 return regmap_set_bits(st->regmap, st->chip_info->sw_ldac_trig_reg,
206 AD3530R_SLD_TRIG_A);
207 }
208
ad3530r_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long info)209 static int ad3530r_read_raw(struct iio_dev *indio_dev,
210 struct iio_chan_spec const *chan,
211 int *val, int *val2, long info)
212 {
213 struct ad3530r_state *st = iio_priv(indio_dev);
214 int ret;
215
216 guard(mutex)(&st->lock);
217 switch (info) {
218 case IIO_CHAN_INFO_RAW:
219 ret = regmap_bulk_read(st->regmap,
220 st->chip_info->input_ch_reg(chan->channel),
221 &st->buf, sizeof(st->buf));
222 if (ret)
223 return ret;
224
225 *val = FIELD_GET(AD3530R_REG_VAL_MASK, be16_to_cpu(st->buf));
226
227 return IIO_VAL_INT;
228 case IIO_CHAN_INFO_SCALE:
229 *val = st->vref_mV;
230 *val2 = 16;
231
232 return IIO_VAL_FRACTIONAL_LOG2;
233 default:
234 return -EINVAL;
235 }
236 }
237
ad3530r_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long info)238 static int ad3530r_write_raw(struct iio_dev *indio_dev,
239 struct iio_chan_spec const *chan,
240 int val, int val2, long info)
241 {
242 struct ad3530r_state *st = iio_priv(indio_dev);
243
244 switch (info) {
245 case IIO_CHAN_INFO_RAW:
246 if (val < 0 || val > AD3530R_DAC_MAX_VAL)
247 return -EINVAL;
248
249 return ad3530r_dac_write(st, chan->channel, val);
250 default:
251 return -EINVAL;
252 }
253 }
254
ad3530r_reg_access(struct iio_dev * indio_dev,unsigned int reg,unsigned int writeval,unsigned int * readval)255 static int ad3530r_reg_access(struct iio_dev *indio_dev, unsigned int reg,
256 unsigned int writeval, unsigned int *readval)
257 {
258 struct ad3530r_state *st = iio_priv(indio_dev);
259
260 if (readval)
261 return regmap_read(st->regmap, reg, readval);
262
263 return regmap_write(st->regmap, reg, writeval);
264 }
265
266 static const struct iio_chan_spec_ext_info ad3530r_ext_info[] = {
267 {
268 .name = "powerdown",
269 .shared = IIO_SEPARATE,
270 .read = ad3530r_get_dac_powerdown,
271 .write = ad3530r_set_dac_powerdown,
272 },
273 IIO_ENUM("powerdown_mode", IIO_SEPARATE, &ad3530r_powerdown_mode_enum),
274 IIO_ENUM_AVAILABLE("powerdown_mode", IIO_SHARED_BY_TYPE,
275 &ad3530r_powerdown_mode_enum),
276 { }
277 };
278
279 #define AD3530R_CHAN(_chan) \
280 { \
281 .type = IIO_VOLTAGE, \
282 .indexed = 1, \
283 .channel = _chan, \
284 .output = 1, \
285 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
286 BIT(IIO_CHAN_INFO_SCALE), \
287 .ext_info = ad3530r_ext_info, \
288 }
289
290 static const struct iio_chan_spec ad3530r_channels[] = {
291 AD3530R_CHAN(0),
292 AD3530R_CHAN(1),
293 AD3530R_CHAN(2),
294 AD3530R_CHAN(3),
295 AD3530R_CHAN(4),
296 AD3530R_CHAN(5),
297 AD3530R_CHAN(6),
298 AD3530R_CHAN(7),
299 };
300
301 static const struct iio_chan_spec ad3531r_channels[] = {
302 AD3530R_CHAN(0),
303 AD3530R_CHAN(1),
304 AD3530R_CHAN(2),
305 AD3530R_CHAN(3),
306 };
307
308 static const struct ad3530r_chip_info ad3530_chip = {
309 .name = "ad3530",
310 .channels = ad3530r_channels,
311 .num_channels = ARRAY_SIZE(ad3530r_channels),
312 .sw_ldac_trig_reg = AD3530R_SW_LDAC_TRIG_A,
313 .input_ch_reg = ad3530r_input_ch_reg,
314 .internal_ref_support = false,
315 };
316
317 static const struct ad3530r_chip_info ad3530r_chip = {
318 .name = "ad3530r",
319 .channels = ad3530r_channels,
320 .num_channels = ARRAY_SIZE(ad3530r_channels),
321 .sw_ldac_trig_reg = AD3530R_SW_LDAC_TRIG_A,
322 .input_ch_reg = ad3530r_input_ch_reg,
323 .internal_ref_support = true,
324 };
325
326 static const struct ad3530r_chip_info ad3531_chip = {
327 .name = "ad3531",
328 .channels = ad3531r_channels,
329 .num_channels = ARRAY_SIZE(ad3531r_channels),
330 .sw_ldac_trig_reg = AD3531R_SW_LDAC_TRIG_A,
331 .input_ch_reg = ad3531r_input_ch_reg,
332 .internal_ref_support = false,
333 };
334
335 static const struct ad3530r_chip_info ad3531r_chip = {
336 .name = "ad3531r",
337 .channels = ad3531r_channels,
338 .num_channels = ARRAY_SIZE(ad3531r_channels),
339 .sw_ldac_trig_reg = AD3531R_SW_LDAC_TRIG_A,
340 .input_ch_reg = ad3531r_input_ch_reg,
341 .internal_ref_support = true,
342 };
343
ad3530r_setup(struct ad3530r_state * st,int external_vref_uV)344 static int ad3530r_setup(struct ad3530r_state *st, int external_vref_uV)
345 {
346 struct device *dev = regmap_get_device(st->regmap);
347 struct gpio_desc *reset_gpio;
348 int i, ret;
349 u8 range_multiplier, val;
350
351 reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
352 if (IS_ERR(reset_gpio))
353 return dev_err_probe(dev, PTR_ERR(reset_gpio),
354 "Failed to get reset GPIO\n");
355
356 if (reset_gpio) {
357 /* Perform hardware reset */
358 fsleep(1 * USEC_PER_MSEC);
359 gpiod_set_value_cansleep(reset_gpio, 0);
360 } else {
361 /* Perform software reset */
362 ret = regmap_update_bits(st->regmap, AD3530R_INTERFACE_CONFIG_A,
363 AD3530R_SW_RESET, AD3530R_SW_RESET);
364 if (ret)
365 return ret;
366 }
367
368 fsleep(10 * USEC_PER_MSEC);
369
370 range_multiplier = 1;
371 if (device_property_read_bool(dev, "adi,range-double")) {
372 ret = regmap_set_bits(st->regmap, AD3530R_OUTPUT_CONTROL_0,
373 AD3530R_OUTPUT_CONTROL_RANGE);
374 if (ret)
375 return ret;
376
377 range_multiplier = 2;
378 }
379
380 if (external_vref_uV) {
381 st->vref_mV = range_multiplier * external_vref_uV / MILLI;
382 } else {
383 ret = regmap_set_bits(st->regmap, AD3530R_REFERENCE_CONTROL_0,
384 AD3530R_REFERENCE_CONTROL_SEL);
385 if (ret)
386 return ret;
387
388 st->vref_mV = range_multiplier * AD3530R_INTERNAL_VREF_mV;
389 }
390
391 /* Set normal operating mode for all channels */
392 val = FIELD_PREP(AD3530R_OP_MODE_CHAN_MSK(0), AD3530R_NORMAL_OP) |
393 FIELD_PREP(AD3530R_OP_MODE_CHAN_MSK(1), AD3530R_NORMAL_OP) |
394 FIELD_PREP(AD3530R_OP_MODE_CHAN_MSK(2), AD3530R_NORMAL_OP) |
395 FIELD_PREP(AD3530R_OP_MODE_CHAN_MSK(3), AD3530R_NORMAL_OP);
396
397 ret = regmap_write(st->regmap, AD3530R_OUTPUT_OPERATING_MODE_0, val);
398 if (ret)
399 return ret;
400
401 if (st->chip_info->num_channels > 4) {
402 ret = regmap_write(st->regmap, AD3530R_OUTPUT_OPERATING_MODE_1,
403 val);
404 if (ret)
405 return ret;
406 }
407
408 for (i = 0; i < st->chip_info->num_channels; i++)
409 st->chan[i].powerdown_mode = AD3530R_POWERDOWN_32K;
410
411 st->ldac_gpio = devm_gpiod_get_optional(dev, "ldac", GPIOD_OUT_LOW);
412 if (IS_ERR(st->ldac_gpio))
413 return dev_err_probe(dev, PTR_ERR(st->ldac_gpio),
414 "Failed to get ldac GPIO\n");
415
416 return 0;
417 }
418
419 static const struct regmap_config ad3530r_regmap_config = {
420 .reg_bits = 16,
421 .val_bits = 8,
422 .max_register = AD3530R_MAX_REG_ADDR,
423 };
424
425 static const struct iio_info ad3530r_info = {
426 .read_raw = ad3530r_read_raw,
427 .write_raw = ad3530r_write_raw,
428 .debugfs_reg_access = ad3530r_reg_access,
429 };
430
ad3530r_probe(struct spi_device * spi)431 static int ad3530r_probe(struct spi_device *spi)
432 {
433 static const char * const regulators[] = { "vdd", "iovdd" };
434 struct device *dev = &spi->dev;
435 struct iio_dev *indio_dev;
436 struct ad3530r_state *st;
437 int ret, external_vref_uV;
438
439 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
440 if (!indio_dev)
441 return -ENOMEM;
442
443 st = iio_priv(indio_dev);
444
445 st->regmap = devm_regmap_init_spi(spi, &ad3530r_regmap_config);
446 if (IS_ERR(st->regmap))
447 return dev_err_probe(dev, PTR_ERR(st->regmap),
448 "Failed to init regmap");
449
450 ret = devm_mutex_init(dev, &st->lock);
451 if (ret)
452 return ret;
453
454 st->chip_info = spi_get_device_match_data(spi);
455 if (!st->chip_info)
456 return -ENODEV;
457
458 ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(regulators),
459 regulators);
460 if (ret)
461 return dev_err_probe(dev, ret, "Failed to enable regulators\n");
462
463 external_vref_uV = devm_regulator_get_enable_read_voltage(dev, "ref");
464 if (external_vref_uV < 0 && external_vref_uV != -ENODEV)
465 return external_vref_uV;
466
467 if (external_vref_uV == -ENODEV)
468 external_vref_uV = 0;
469
470 if (!st->chip_info->internal_ref_support && external_vref_uV == 0)
471 return -ENODEV;
472
473 ret = ad3530r_setup(st, external_vref_uV);
474 if (ret)
475 return ret;
476
477 indio_dev->name = st->chip_info->name;
478 indio_dev->info = &ad3530r_info;
479 indio_dev->modes = INDIO_DIRECT_MODE;
480 indio_dev->channels = st->chip_info->channels;
481 indio_dev->num_channels = st->chip_info->num_channels;
482
483 return devm_iio_device_register(&spi->dev, indio_dev);
484 }
485
486 static const struct spi_device_id ad3530r_id[] = {
487 { "ad3530", (kernel_ulong_t)&ad3530_chip },
488 { "ad3530r", (kernel_ulong_t)&ad3530r_chip },
489 { "ad3531", (kernel_ulong_t)&ad3531_chip },
490 { "ad3531r", (kernel_ulong_t)&ad3531r_chip },
491 { }
492 };
493 MODULE_DEVICE_TABLE(spi, ad3530r_id);
494
495 static const struct of_device_id ad3530r_of_match[] = {
496 { .compatible = "adi,ad3530", .data = &ad3530_chip },
497 { .compatible = "adi,ad3530r", .data = &ad3530r_chip },
498 { .compatible = "adi,ad3531", .data = &ad3531_chip },
499 { .compatible = "adi,ad3531r", .data = &ad3531r_chip },
500 { }
501 };
502 MODULE_DEVICE_TABLE(of, ad3530r_of_match);
503
504 static struct spi_driver ad3530r_driver = {
505 .driver = {
506 .name = "ad3530r",
507 .of_match_table = ad3530r_of_match,
508 },
509 .probe = ad3530r_probe,
510 .id_table = ad3530r_id,
511 };
512 module_spi_driver(ad3530r_driver);
513
514 MODULE_AUTHOR("Kim Seer Paller <kimseer.paller@analog.com>");
515 MODULE_DESCRIPTION("Analog Devices AD3530R and Similar DACs Driver");
516 MODULE_LICENSE("GPL");
517