1 /* 2 * Broadcom NetXtreme-E RoCE driver. 3 * 4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term 5 * Broadcom refers to Broadcom Limited and/or its subsidiaries. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in 21 * the documentation and/or other materials provided with the 22 * distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 * 36 * Description: IB Verbs interpreter 37 */ 38 39 #include <linux/interrupt.h> 40 #include <linux/types.h> 41 #include <linux/pci.h> 42 #include <linux/netdevice.h> 43 #include <linux/if_ether.h> 44 #include <net/addrconf.h> 45 46 #include <rdma/ib_verbs.h> 47 #include <rdma/ib_user_verbs.h> 48 #include <rdma/ib_umem.h> 49 #include <rdma/ib_addr.h> 50 #include <rdma/ib_mad.h> 51 #include <rdma/ib_cache.h> 52 #include <rdma/ib_pma.h> 53 #include <rdma/uverbs_ioctl.h> 54 #include <linux/hashtable.h> 55 56 #include "roce_hsi.h" 57 #include "qplib_res.h" 58 #include "qplib_sp.h" 59 #include "qplib_fp.h" 60 #include "qplib_rcfw.h" 61 62 #include "bnxt_re.h" 63 #include "ib_verbs.h" 64 #include "debugfs.h" 65 66 #include <rdma/uverbs_types.h> 67 #include <rdma/uverbs_std_types.h> 68 69 #include <rdma/ib_user_ioctl_cmds.h> 70 71 #define UVERBS_MODULE_NAME bnxt_re 72 #include <rdma/uverbs_named_ioctl.h> 73 74 #include <rdma/bnxt_re-abi.h> 75 76 static int __from_ib_access_flags(int iflags) 77 { 78 int qflags = 0; 79 80 if (iflags & IB_ACCESS_LOCAL_WRITE) 81 qflags |= BNXT_QPLIB_ACCESS_LOCAL_WRITE; 82 if (iflags & IB_ACCESS_REMOTE_READ) 83 qflags |= BNXT_QPLIB_ACCESS_REMOTE_READ; 84 if (iflags & IB_ACCESS_REMOTE_WRITE) 85 qflags |= BNXT_QPLIB_ACCESS_REMOTE_WRITE; 86 if (iflags & IB_ACCESS_REMOTE_ATOMIC) 87 qflags |= BNXT_QPLIB_ACCESS_REMOTE_ATOMIC; 88 if (iflags & IB_ACCESS_MW_BIND) 89 qflags |= BNXT_QPLIB_ACCESS_MW_BIND; 90 if (iflags & IB_ZERO_BASED) 91 qflags |= BNXT_QPLIB_ACCESS_ZERO_BASED; 92 if (iflags & IB_ACCESS_ON_DEMAND) 93 qflags |= BNXT_QPLIB_ACCESS_ON_DEMAND; 94 return qflags; 95 }; 96 97 static int __to_ib_access_flags(int qflags) 98 { 99 int iflags = 0; 100 101 if (qflags & BNXT_QPLIB_ACCESS_LOCAL_WRITE) 102 iflags |= IB_ACCESS_LOCAL_WRITE; 103 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_WRITE) 104 iflags |= IB_ACCESS_REMOTE_WRITE; 105 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_READ) 106 iflags |= IB_ACCESS_REMOTE_READ; 107 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_ATOMIC) 108 iflags |= IB_ACCESS_REMOTE_ATOMIC; 109 if (qflags & BNXT_QPLIB_ACCESS_MW_BIND) 110 iflags |= IB_ACCESS_MW_BIND; 111 if (qflags & BNXT_QPLIB_ACCESS_ZERO_BASED) 112 iflags |= IB_ZERO_BASED; 113 if (qflags & BNXT_QPLIB_ACCESS_ON_DEMAND) 114 iflags |= IB_ACCESS_ON_DEMAND; 115 return iflags; 116 } 117 118 static u8 __qp_access_flags_from_ib(struct bnxt_qplib_chip_ctx *cctx, int iflags) 119 { 120 u8 qflags = 0; 121 122 if (!bnxt_qplib_is_chip_gen_p5_p7(cctx)) 123 /* For Wh+ */ 124 return (u8)__from_ib_access_flags(iflags); 125 126 /* For P5, P7 and later chips */ 127 if (iflags & IB_ACCESS_LOCAL_WRITE) 128 qflags |= CMDQ_MODIFY_QP_ACCESS_LOCAL_WRITE; 129 if (iflags & IB_ACCESS_REMOTE_WRITE) 130 qflags |= CMDQ_MODIFY_QP_ACCESS_REMOTE_WRITE; 131 if (iflags & IB_ACCESS_REMOTE_READ) 132 qflags |= CMDQ_MODIFY_QP_ACCESS_REMOTE_READ; 133 if (iflags & IB_ACCESS_REMOTE_ATOMIC) 134 qflags |= CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC; 135 136 return qflags; 137 } 138 139 static int __qp_access_flags_to_ib(struct bnxt_qplib_chip_ctx *cctx, u8 qflags) 140 { 141 int iflags = 0; 142 143 if (!bnxt_qplib_is_chip_gen_p5_p7(cctx)) 144 /* For Wh+ */ 145 return __to_ib_access_flags(qflags); 146 147 /* For P5, P7 and later chips */ 148 if (qflags & CMDQ_MODIFY_QP_ACCESS_LOCAL_WRITE) 149 iflags |= IB_ACCESS_LOCAL_WRITE; 150 if (qflags & CMDQ_MODIFY_QP_ACCESS_REMOTE_WRITE) 151 iflags |= IB_ACCESS_REMOTE_WRITE; 152 if (qflags & CMDQ_MODIFY_QP_ACCESS_REMOTE_READ) 153 iflags |= IB_ACCESS_REMOTE_READ; 154 if (qflags & CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC) 155 iflags |= IB_ACCESS_REMOTE_ATOMIC; 156 157 return iflags; 158 } 159 160 static void bnxt_re_check_and_set_relaxed_ordering(struct bnxt_re_dev *rdev, 161 struct bnxt_qplib_mrw *qplib_mr) 162 { 163 if (_is_relaxed_ordering_supported(rdev->dev_attr->dev_cap_flags2) && 164 pcie_relaxed_ordering_enabled(rdev->en_dev->pdev)) 165 qplib_mr->flags |= CMDQ_REGISTER_MR_FLAGS_ENABLE_RO; 166 } 167 168 static int bnxt_re_build_sgl(struct ib_sge *ib_sg_list, 169 struct bnxt_qplib_sge *sg_list, int num) 170 { 171 int i, total = 0; 172 173 for (i = 0; i < num; i++) { 174 sg_list[i].addr = ib_sg_list[i].addr; 175 sg_list[i].lkey = ib_sg_list[i].lkey; 176 sg_list[i].size = ib_sg_list[i].length; 177 total += sg_list[i].size; 178 } 179 return total; 180 } 181 182 /* Device */ 183 int bnxt_re_query_device(struct ib_device *ibdev, 184 struct ib_device_attr *ib_attr, 185 struct ib_udata *udata) 186 { 187 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 188 struct bnxt_qplib_dev_attr *dev_attr = rdev->dev_attr; 189 struct bnxt_re_query_device_ex_resp resp = {}; 190 int rc = 0; 191 192 rc = ib_is_udata_in_empty(udata); 193 if (rc) 194 return rc; 195 196 memset(ib_attr, 0, sizeof(*ib_attr)); 197 memcpy(&ib_attr->fw_ver, dev_attr->fw_ver, 198 min(sizeof(dev_attr->fw_ver), 199 sizeof(ib_attr->fw_ver))); 200 addrconf_addr_eui48((u8 *)&ib_attr->sys_image_guid, 201 rdev->netdev->dev_addr); 202 ib_attr->max_mr_size = BNXT_RE_MAX_MR_SIZE; 203 ib_attr->page_size_cap = BNXT_RE_PAGE_SIZE_SUPPORTED; 204 205 ib_attr->vendor_id = rdev->en_dev->pdev->vendor; 206 ib_attr->vendor_part_id = rdev->en_dev->pdev->device; 207 ib_attr->hw_ver = rdev->en_dev->pdev->revision; 208 ib_attr->max_qp = dev_attr->max_qp; 209 ib_attr->max_qp_wr = dev_attr->max_qp_wqes; 210 ib_attr->device_cap_flags = 211 IB_DEVICE_CURR_QP_STATE_MOD 212 | IB_DEVICE_RC_RNR_NAK_GEN 213 | IB_DEVICE_SHUTDOWN_PORT 214 | IB_DEVICE_SYS_IMAGE_GUID 215 | IB_DEVICE_RESIZE_MAX_WR 216 | IB_DEVICE_PORT_ACTIVE_EVENT 217 | IB_DEVICE_N_NOTIFY_CQ 218 | IB_DEVICE_MEM_WINDOW 219 | IB_DEVICE_MEM_WINDOW_TYPE_2B 220 | IB_DEVICE_MEM_MGT_EXTENSIONS; 221 ib_attr->kernel_cap_flags = IBK_LOCAL_DMA_LKEY; 222 ib_attr->max_send_sge = dev_attr->max_qp_sges; 223 ib_attr->max_recv_sge = dev_attr->max_qp_sges; 224 ib_attr->max_sge_rd = dev_attr->max_qp_sges; 225 ib_attr->max_cq = dev_attr->max_cq; 226 ib_attr->max_cqe = dev_attr->max_cq_wqes; 227 ib_attr->max_mr = dev_attr->max_mr; 228 ib_attr->max_pd = dev_attr->max_pd; 229 ib_attr->max_qp_rd_atom = dev_attr->max_qp_rd_atom; 230 ib_attr->max_qp_init_rd_atom = dev_attr->max_qp_init_rd_atom; 231 ib_attr->atomic_cap = IB_ATOMIC_NONE; 232 ib_attr->masked_atomic_cap = IB_ATOMIC_NONE; 233 if (dev_attr->is_atomic) { 234 ib_attr->atomic_cap = IB_ATOMIC_GLOB; 235 ib_attr->masked_atomic_cap = IB_ATOMIC_GLOB; 236 } 237 238 ib_attr->max_ee_rd_atom = 0; 239 ib_attr->max_res_rd_atom = 0; 240 ib_attr->max_ee_init_rd_atom = 0; 241 ib_attr->max_ee = 0; 242 ib_attr->max_rdd = 0; 243 ib_attr->max_mw = dev_attr->max_mw; 244 ib_attr->max_raw_ipv6_qp = 0; 245 ib_attr->max_raw_ethy_qp = dev_attr->max_raw_ethy_qp; 246 ib_attr->max_mcast_grp = 0; 247 ib_attr->max_mcast_qp_attach = 0; 248 ib_attr->max_total_mcast_qp_attach = 0; 249 ib_attr->max_ah = dev_attr->max_ah; 250 251 ib_attr->max_srq = dev_attr->max_srq; 252 ib_attr->max_srq_wr = dev_attr->max_srq_wqes; 253 ib_attr->max_srq_sge = dev_attr->max_srq_sges; 254 255 ib_attr->max_fast_reg_page_list_len = MAX_PBL_LVL_1_PGS; 256 257 ib_attr->max_pkeys = 1; 258 ib_attr->local_ca_ack_delay = BNXT_RE_DEFAULT_ACK_DELAY; 259 260 if (_is_modify_qp_rate_limit_supported(dev_attr->dev_cap_flags2)) { 261 resp.packet_pacing_caps.qp_rate_limit_min = 262 dev_attr->rate_limit_min; 263 resp.packet_pacing_caps.qp_rate_limit_max = 264 dev_attr->rate_limit_max; 265 resp.packet_pacing_caps.supported_qpts = 266 1 << IB_QPT_RC; 267 } 268 269 if (udata) 270 return ib_respond_udata(udata, resp); 271 return 0; 272 } 273 274 int bnxt_re_modify_device(struct ib_device *ibdev, 275 int device_modify_mask, 276 struct ib_device_modify *device_modify) 277 { 278 ibdev_dbg(ibdev, "Modify device with mask 0x%x", device_modify_mask); 279 280 if (device_modify_mask & ~IB_DEVICE_MODIFY_NODE_DESC) 281 return -EOPNOTSUPP; 282 283 if (!(device_modify_mask & IB_DEVICE_MODIFY_NODE_DESC)) 284 return 0; 285 286 memcpy(ibdev->node_desc, device_modify->node_desc, IB_DEVICE_NODE_DESC_MAX); 287 return 0; 288 } 289 290 /* Port */ 291 int bnxt_re_query_port(struct ib_device *ibdev, u32 port_num, 292 struct ib_port_attr *port_attr) 293 { 294 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 295 struct bnxt_qplib_dev_attr *dev_attr = rdev->dev_attr; 296 int rc; 297 298 memset(port_attr, 0, sizeof(*port_attr)); 299 300 if (netif_running(rdev->netdev) && netif_carrier_ok(rdev->netdev)) { 301 port_attr->state = IB_PORT_ACTIVE; 302 port_attr->phys_state = IB_PORT_PHYS_STATE_LINK_UP; 303 } else { 304 port_attr->state = IB_PORT_DOWN; 305 port_attr->phys_state = IB_PORT_PHYS_STATE_DISABLED; 306 } 307 port_attr->max_mtu = IB_MTU_4096; 308 port_attr->active_mtu = iboe_get_mtu(rdev->netdev->mtu); 309 /* One GID is reserved for RawEth QP. Report one less */ 310 port_attr->gid_tbl_len = (rdev->rcfw.roce_mirror ? (dev_attr->max_sgid - 1) : 311 dev_attr->max_sgid); 312 port_attr->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP | 313 IB_PORT_DEVICE_MGMT_SUP | 314 IB_PORT_VENDOR_CLASS_SUP; 315 port_attr->ip_gids = true; 316 317 port_attr->max_msg_sz = (u32)BNXT_RE_MAX_MR_SIZE_LOW; 318 port_attr->bad_pkey_cntr = 0; 319 port_attr->qkey_viol_cntr = 0; 320 port_attr->pkey_tbl_len = dev_attr->max_pkey; 321 port_attr->lid = 0; 322 port_attr->sm_lid = 0; 323 port_attr->lmc = 0; 324 port_attr->max_vl_num = 4; 325 port_attr->sm_sl = 0; 326 port_attr->subnet_timeout = 0; 327 port_attr->init_type_reply = 0; 328 rc = ib_get_eth_speed(&rdev->ibdev, port_num, &port_attr->active_speed, 329 &port_attr->active_width); 330 331 return rc; 332 } 333 334 int bnxt_re_get_port_immutable(struct ib_device *ibdev, u32 port_num, 335 struct ib_port_immutable *immutable) 336 { 337 struct ib_port_attr port_attr; 338 339 if (bnxt_re_query_port(ibdev, port_num, &port_attr)) 340 return -EINVAL; 341 342 immutable->pkey_tbl_len = port_attr.pkey_tbl_len; 343 immutable->gid_tbl_len = port_attr.gid_tbl_len; 344 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE; 345 immutable->core_cap_flags |= RDMA_CORE_CAP_PROT_ROCE_UDP_ENCAP; 346 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 347 return 0; 348 } 349 350 void bnxt_re_query_fw_str(struct ib_device *ibdev, char *str) 351 { 352 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 353 354 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%d.%d", 355 rdev->dev_attr->fw_ver[0], rdev->dev_attr->fw_ver[1], 356 rdev->dev_attr->fw_ver[2], rdev->dev_attr->fw_ver[3]); 357 } 358 359 int bnxt_re_query_pkey(struct ib_device *ibdev, u32 port_num, 360 u16 index, u16 *pkey) 361 { 362 if (index > 0) 363 return -EINVAL; 364 365 *pkey = IB_DEFAULT_PKEY_FULL; 366 367 return 0; 368 } 369 370 int bnxt_re_query_gid(struct ib_device *ibdev, u32 port_num, 371 int index, union ib_gid *gid) 372 { 373 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 374 int rc; 375 376 /* Ignore port_num */ 377 memset(gid, 0, sizeof(*gid)); 378 rc = bnxt_qplib_get_sgid(&rdev->qplib_res, 379 &rdev->qplib_res.sgid_tbl, index, 380 (struct bnxt_qplib_gid *)gid); 381 return rc; 382 } 383 384 int bnxt_re_del_gid(const struct ib_gid_attr *attr, void **context) 385 { 386 int rc = 0; 387 struct bnxt_re_gid_ctx *ctx, **ctx_tbl; 388 struct bnxt_re_dev *rdev = to_bnxt_re_dev(attr->device, ibdev); 389 struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl; 390 struct bnxt_qplib_gid *gid_to_del; 391 u16 vlan_id = 0xFFFF; 392 393 /* Delete the entry from the hardware */ 394 ctx = *context; 395 if (!ctx) 396 return -EINVAL; 397 398 if (sgid_tbl->active) { 399 if (ctx->idx >= sgid_tbl->max) 400 return -EINVAL; 401 gid_to_del = &sgid_tbl->tbl[ctx->idx].gid; 402 vlan_id = sgid_tbl->tbl[ctx->idx].vlan_id; 403 /* DEL_GID is called in WQ context(netdevice_event_work_handler) 404 * or via the ib_unregister_device path. In the former case QP1 405 * may not be destroyed yet, in which case just return as FW 406 * needs that entry to be present and will fail it's deletion. 407 * We could get invoked again after QP1 is destroyed OR get an 408 * ADD_GID call with a different GID value for the same index 409 * where we issue MODIFY_GID cmd to update the GID entry -- TBD 410 */ 411 if (ctx->idx == 0 && 412 rdma_link_local_addr((struct in6_addr *)gid_to_del) && 413 ctx->refcnt == 1 && rdev->gsi_ctx.gsi_sqp) { 414 ibdev_dbg(&rdev->ibdev, 415 "Trying to delete GID0 while QP1 is alive\n"); 416 return -EFAULT; 417 } 418 ctx->refcnt--; 419 if (!ctx->refcnt) { 420 rc = bnxt_qplib_del_sgid(sgid_tbl, gid_to_del, 421 vlan_id, true); 422 if (rc) { 423 ibdev_err(&rdev->ibdev, 424 "Failed to remove GID: %#x", rc); 425 } else { 426 ctx_tbl = sgid_tbl->ctx; 427 ctx_tbl[ctx->idx] = NULL; 428 kfree(ctx); 429 } 430 } 431 } else { 432 return -EINVAL; 433 } 434 return rc; 435 } 436 437 int bnxt_re_add_gid(const struct ib_gid_attr *attr, void **context) 438 { 439 int rc; 440 u32 tbl_idx = 0; 441 u16 vlan_id = 0xFFFF; 442 struct bnxt_re_gid_ctx *ctx, **ctx_tbl; 443 struct bnxt_re_dev *rdev = to_bnxt_re_dev(attr->device, ibdev); 444 struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl; 445 446 rc = rdma_read_gid_l2_fields(attr, &vlan_id, NULL); 447 if (rc) 448 return rc; 449 450 rc = bnxt_qplib_add_sgid(sgid_tbl, (struct bnxt_qplib_gid *)&attr->gid, 451 rdev->qplib_res.netdev->dev_addr, 452 vlan_id, true, &tbl_idx, false, 0); 453 if (rc == -EALREADY) { 454 ctx_tbl = sgid_tbl->ctx; 455 ctx_tbl[tbl_idx]->refcnt++; 456 *context = ctx_tbl[tbl_idx]; 457 return 0; 458 } 459 460 if (rc < 0) { 461 ibdev_err(&rdev->ibdev, "Failed to add GID: %#x", rc); 462 return rc; 463 } 464 465 ctx = kmalloc_obj(*ctx); 466 if (!ctx) 467 return -ENOMEM; 468 ctx_tbl = sgid_tbl->ctx; 469 ctx->idx = tbl_idx; 470 ctx->refcnt = 1; 471 ctx_tbl[tbl_idx] = ctx; 472 *context = ctx; 473 474 return rc; 475 } 476 477 enum rdma_link_layer bnxt_re_get_link_layer(struct ib_device *ibdev, 478 u32 port_num) 479 { 480 return IB_LINK_LAYER_ETHERNET; 481 } 482 483 #define BNXT_RE_FENCE_PBL_SIZE DIV_ROUND_UP(BNXT_RE_FENCE_BYTES, PAGE_SIZE) 484 485 static void bnxt_re_create_fence_wqe(struct bnxt_re_pd *pd) 486 { 487 struct bnxt_re_fence_data *fence = &pd->fence; 488 struct ib_mr *ib_mr = &fence->mr->ib_mr; 489 struct bnxt_qplib_swqe *wqe = &fence->bind_wqe; 490 struct bnxt_re_dev *rdev = pd->rdev; 491 492 if (bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) 493 return; 494 495 memset(wqe, 0, sizeof(*wqe)); 496 wqe->type = BNXT_QPLIB_SWQE_TYPE_BIND_MW; 497 wqe->wr_id = BNXT_QPLIB_FENCE_WRID; 498 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 499 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 500 wqe->bind.zero_based = false; 501 wqe->bind.parent_l_key = ib_mr->lkey; 502 wqe->bind.va = (u64)(unsigned long)fence->va; 503 wqe->bind.length = fence->size; 504 wqe->bind.access_cntl = __from_ib_access_flags(IB_ACCESS_REMOTE_READ); 505 wqe->bind.mw_type = SQ_BIND_MW_TYPE_TYPE1; 506 507 /* Save the initial rkey in fence structure for now; 508 * wqe->bind.r_key will be set at (re)bind time. 509 */ 510 fence->bind_rkey = ib_inc_rkey(fence->mw->rkey); 511 } 512 513 static int bnxt_re_bind_fence_mw(struct bnxt_qplib_qp *qplib_qp) 514 { 515 struct bnxt_re_qp *qp = container_of(qplib_qp, struct bnxt_re_qp, 516 qplib_qp); 517 struct ib_pd *ib_pd = qp->ib_qp.pd; 518 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 519 struct bnxt_re_fence_data *fence = &pd->fence; 520 struct bnxt_qplib_swqe *fence_wqe = &fence->bind_wqe; 521 struct bnxt_qplib_swqe wqe; 522 int rc; 523 524 memcpy(&wqe, fence_wqe, sizeof(wqe)); 525 wqe.bind.r_key = fence->bind_rkey; 526 fence->bind_rkey = ib_inc_rkey(fence->bind_rkey); 527 528 ibdev_dbg(&qp->rdev->ibdev, 529 "Posting bind fence-WQE: rkey: %#x QP: %d PD: %p\n", 530 wqe.bind.r_key, qp->qplib_qp.id, pd); 531 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe); 532 if (rc) { 533 ibdev_err(&qp->rdev->ibdev, "Failed to bind fence-WQE\n"); 534 return rc; 535 } 536 bnxt_qplib_post_send_db(&qp->qplib_qp); 537 538 return rc; 539 } 540 541 static void bnxt_re_destroy_fence_mr(struct bnxt_re_pd *pd) 542 { 543 struct bnxt_re_fence_data *fence = &pd->fence; 544 struct bnxt_re_dev *rdev = pd->rdev; 545 struct device *dev = &rdev->en_dev->pdev->dev; 546 struct bnxt_re_mr *mr = fence->mr; 547 548 if (bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) 549 return; 550 551 if (fence->mw) { 552 bnxt_re_dealloc_mw(fence->mw); 553 fence->mw = NULL; 554 } 555 if (mr) { 556 if (mr->ib_mr.rkey) 557 bnxt_qplib_dereg_mrw(&rdev->qplib_res, &mr->qplib_mr, 558 true); 559 if (mr->ib_mr.lkey) 560 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 561 kfree(mr); 562 fence->mr = NULL; 563 } 564 if (fence->dma_addr) { 565 dma_unmap_single(dev, fence->dma_addr, BNXT_RE_FENCE_BYTES, 566 DMA_BIDIRECTIONAL); 567 fence->dma_addr = 0; 568 } 569 } 570 571 static int bnxt_re_create_fence_mr(struct bnxt_re_pd *pd) 572 { 573 int mr_access_flags = IB_ACCESS_LOCAL_WRITE | IB_ACCESS_MW_BIND; 574 struct bnxt_re_fence_data *fence = &pd->fence; 575 struct bnxt_re_dev *rdev = pd->rdev; 576 struct device *dev = &rdev->en_dev->pdev->dev; 577 struct bnxt_re_mr *mr = NULL; 578 dma_addr_t dma_addr = 0; 579 struct ib_mw *mw; 580 int rc; 581 582 if (bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) 583 return 0; 584 585 dma_addr = dma_map_single(dev, fence->va, BNXT_RE_FENCE_BYTES, 586 DMA_BIDIRECTIONAL); 587 rc = dma_mapping_error(dev, dma_addr); 588 if (rc) { 589 ibdev_err(&rdev->ibdev, "Failed to dma-map fence-MR-mem\n"); 590 rc = -EIO; 591 fence->dma_addr = 0; 592 goto fail; 593 } 594 fence->dma_addr = dma_addr; 595 596 /* Allocate a MR */ 597 mr = kzalloc_obj(*mr); 598 if (!mr) { 599 rc = -ENOMEM; 600 goto fail; 601 } 602 fence->mr = mr; 603 mr->rdev = rdev; 604 mr->qplib_mr.pd = &pd->qplib_pd; 605 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR; 606 mr->qplib_mr.access_flags = __from_ib_access_flags(mr_access_flags); 607 if (!_is_alloc_mr_unified(rdev->dev_attr->dev_cap_flags)) { 608 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr); 609 if (rc) { 610 ibdev_err(&rdev->ibdev, "Failed to alloc fence-HW-MR\n"); 611 goto fail; 612 } 613 614 /* Register MR */ 615 mr->ib_mr.lkey = mr->qplib_mr.lkey; 616 } else { 617 mr->qplib_mr.flags = CMDQ_REGISTER_MR_FLAGS_ALLOC_MR; 618 } 619 mr->qplib_mr.va = (u64)(unsigned long)fence->va; 620 mr->qplib_mr.total_size = BNXT_RE_FENCE_BYTES; 621 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, NULL, 622 BNXT_RE_FENCE_PBL_SIZE, PAGE_SIZE, 623 _is_alloc_mr_unified(rdev->dev_attr->dev_cap_flags)); 624 if (rc) { 625 ibdev_err(&rdev->ibdev, "Failed to register fence-MR\n"); 626 goto fail; 627 } 628 mr->ib_mr.rkey = mr->qplib_mr.rkey; 629 630 /* Create a fence MW only for kernel consumers */ 631 mw = bnxt_re_alloc_mw(&pd->ib_pd, IB_MW_TYPE_1, NULL); 632 if (IS_ERR(mw)) { 633 ibdev_err(&rdev->ibdev, 634 "Failed to create fence-MW for PD: %p\n", pd); 635 rc = PTR_ERR(mw); 636 goto fail; 637 } 638 fence->mw = mw; 639 640 bnxt_re_create_fence_wqe(pd); 641 return 0; 642 643 fail: 644 bnxt_re_destroy_fence_mr(pd); 645 return rc; 646 } 647 648 struct bnxt_re_user_mmap_entry* 649 bnxt_re_mmap_entry_insert(struct bnxt_re_ucontext *uctx, u64 mem_offset, 650 enum bnxt_re_mmap_flag mmap_flag, u64 *offset) 651 { 652 struct bnxt_re_user_mmap_entry *entry; 653 int ret; 654 655 entry = kzalloc_obj(*entry); 656 if (!entry) 657 return NULL; 658 659 entry->mem_offset = mem_offset; 660 entry->mmap_flag = mmap_flag; 661 entry->uctx = uctx; 662 663 switch (mmap_flag) { 664 case BNXT_RE_MMAP_SH_PAGE: 665 ret = rdma_user_mmap_entry_insert_exact(&uctx->ib_uctx, 666 &entry->rdma_entry, PAGE_SIZE, 0); 667 break; 668 case BNXT_RE_MMAP_UC_DB: 669 case BNXT_RE_MMAP_WC_DB: 670 case BNXT_RE_MMAP_DBR_BAR: 671 case BNXT_RE_MMAP_DBR_PAGE: 672 case BNXT_RE_MMAP_TOGGLE_PAGE: 673 ret = rdma_user_mmap_entry_insert(&uctx->ib_uctx, 674 &entry->rdma_entry, PAGE_SIZE); 675 break; 676 default: 677 ret = -EINVAL; 678 break; 679 } 680 681 if (ret) { 682 kfree(entry); 683 return NULL; 684 } 685 if (offset) 686 *offset = rdma_user_mmap_get_offset(&entry->rdma_entry); 687 688 return entry; 689 } 690 691 /* Protection Domains */ 692 int bnxt_re_dealloc_pd(struct ib_pd *ib_pd, struct ib_udata *udata) 693 { 694 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 695 struct bnxt_re_dev *rdev = pd->rdev; 696 int ret; 697 698 ret = ib_is_udata_in_empty(udata); 699 if (ret) 700 return ret; 701 702 if (udata) { 703 rdma_user_mmap_entry_remove(pd->pd_db_mmap); 704 pd->pd_db_mmap = NULL; 705 } 706 707 bnxt_re_destroy_fence_mr(pd); 708 709 if (pd->qplib_pd.id) { 710 if (!bnxt_qplib_dealloc_pd(&rdev->qplib_res, 711 &rdev->qplib_res.pd_tbl, 712 &pd->qplib_pd)) 713 atomic_dec(&rdev->stats.res.pd_count); 714 } 715 return ib_respond_empty_udata(udata); 716 } 717 718 int bnxt_re_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata) 719 { 720 struct ib_device *ibdev = ibpd->device; 721 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 722 struct bnxt_re_ucontext *ucntx = rdma_udata_to_drv_context( 723 udata, struct bnxt_re_ucontext, ib_uctx); 724 struct bnxt_re_pd *pd = container_of(ibpd, struct bnxt_re_pd, ib_pd); 725 struct bnxt_re_user_mmap_entry *entry = NULL; 726 u32 active_pds; 727 int rc = 0; 728 729 rc = ib_is_udata_in_empty(udata); 730 if (rc) 731 return rc; 732 733 pd->rdev = rdev; 734 if (bnxt_qplib_alloc_pd(&rdev->qplib_res, &pd->qplib_pd)) { 735 ibdev_err(&rdev->ibdev, "Failed to allocate HW PD"); 736 rc = -ENOMEM; 737 goto fail; 738 } 739 740 if (udata) { 741 struct bnxt_re_pd_resp resp = {}; 742 743 if (!ucntx->dpi.dbr) { 744 /* Allocate DPI in alloc_pd to avoid failing of 745 * ibv_devinfo and family of application when DPIs 746 * are depleted. 747 */ 748 if (bnxt_qplib_alloc_dpi(&rdev->qplib_res, 749 &ucntx->dpi, ucntx, BNXT_QPLIB_DPI_TYPE_UC)) { 750 rc = -ENOMEM; 751 goto dbfail; 752 } 753 } 754 755 resp.pdid = pd->qplib_pd.id; 756 /* Still allow mapping this DBR to the new user PD. */ 757 resp.dpi = ucntx->dpi.dpi; 758 759 entry = bnxt_re_mmap_entry_insert(ucntx, (u64)ucntx->dpi.umdbr, 760 BNXT_RE_MMAP_UC_DB, &resp.dbr); 761 762 if (!entry) { 763 rc = -ENOMEM; 764 goto dbfail; 765 } 766 767 pd->pd_db_mmap = &entry->rdma_entry; 768 769 rc = ib_respond_udata(udata, resp); 770 if (rc) { 771 rdma_user_mmap_entry_remove(pd->pd_db_mmap); 772 rc = -EFAULT; 773 goto dbfail; 774 } 775 } 776 777 if (!udata) 778 if (bnxt_re_create_fence_mr(pd)) 779 ibdev_warn(&rdev->ibdev, 780 "Failed to create Fence-MR\n"); 781 active_pds = atomic_inc_return(&rdev->stats.res.pd_count); 782 if (active_pds > rdev->stats.res.pd_watermark) 783 rdev->stats.res.pd_watermark = active_pds; 784 785 return 0; 786 dbfail: 787 bnxt_qplib_dealloc_pd(&rdev->qplib_res, &rdev->qplib_res.pd_tbl, 788 &pd->qplib_pd); 789 fail: 790 return rc; 791 } 792 793 /* Address Handles */ 794 int bnxt_re_destroy_ah(struct ib_ah *ib_ah, u32 flags) 795 { 796 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah); 797 struct bnxt_re_dev *rdev = ah->rdev; 798 bool block = true; 799 int rc; 800 801 block = !(flags & RDMA_DESTROY_AH_SLEEPABLE); 802 rc = bnxt_qplib_destroy_ah(&rdev->qplib_res, &ah->qplib_ah, block); 803 if (BNXT_RE_CHECK_RC(rc)) { 804 if (rc == -ETIMEDOUT) 805 rc = 0; 806 else 807 goto fail; 808 } 809 atomic_dec(&rdev->stats.res.ah_count); 810 fail: 811 return rc; 812 } 813 814 static u8 bnxt_re_stack_to_dev_nw_type(enum rdma_network_type ntype) 815 { 816 u8 nw_type; 817 818 switch (ntype) { 819 case RDMA_NETWORK_IPV4: 820 nw_type = CMDQ_CREATE_AH_TYPE_V2IPV4; 821 break; 822 case RDMA_NETWORK_IPV6: 823 nw_type = CMDQ_CREATE_AH_TYPE_V2IPV6; 824 break; 825 default: 826 nw_type = CMDQ_CREATE_AH_TYPE_V1; 827 break; 828 } 829 return nw_type; 830 } 831 832 int bnxt_re_create_ah(struct ib_ah *ib_ah, struct rdma_ah_init_attr *init_attr, 833 struct ib_udata *udata) 834 { 835 struct ib_pd *ib_pd = ib_ah->pd; 836 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 837 struct rdma_ah_attr *ah_attr = init_attr->ah_attr; 838 const struct ib_global_route *grh = rdma_ah_read_grh(ah_attr); 839 struct bnxt_re_dev *rdev = pd->rdev; 840 const struct ib_gid_attr *sgid_attr; 841 struct bnxt_re_gid_ctx *ctx; 842 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah); 843 u32 active_ahs; 844 u8 nw_type; 845 int rc; 846 847 rc = ib_is_udata_in_empty(udata); 848 if (rc) 849 return rc; 850 851 if (!(rdma_ah_get_ah_flags(ah_attr) & IB_AH_GRH)) { 852 ibdev_err(&rdev->ibdev, "Failed to alloc AH: GRH not set"); 853 return -EINVAL; 854 } 855 856 ah->rdev = rdev; 857 ah->qplib_ah.pd = &pd->qplib_pd; 858 859 /* Supply the configuration for the HW */ 860 memcpy(ah->qplib_ah.dgid.data, grh->dgid.raw, 861 sizeof(union ib_gid)); 862 sgid_attr = grh->sgid_attr; 863 /* Get the HW context of the GID. The reference 864 * of GID table entry is already taken by the caller. 865 */ 866 ctx = rdma_read_gid_hw_context(sgid_attr); 867 ah->qplib_ah.sgid_index = ctx->idx; 868 ah->qplib_ah.host_sgid_index = grh->sgid_index; 869 ah->qplib_ah.traffic_class = grh->traffic_class; 870 ah->qplib_ah.flow_label = grh->flow_label; 871 ah->qplib_ah.hop_limit = grh->hop_limit; 872 ah->qplib_ah.sl = rdma_ah_get_sl(ah_attr); 873 874 /* Get network header type for this GID */ 875 nw_type = rdma_gid_attr_network_type(sgid_attr); 876 ah->qplib_ah.nw_type = bnxt_re_stack_to_dev_nw_type(nw_type); 877 878 memcpy(ah->qplib_ah.dmac, ah_attr->roce.dmac, ETH_ALEN); 879 rc = bnxt_qplib_create_ah(&rdev->qplib_res, &ah->qplib_ah, 880 !(init_attr->flags & 881 RDMA_CREATE_AH_SLEEPABLE)); 882 if (rc) { 883 ibdev_err(&rdev->ibdev, "Failed to allocate HW AH"); 884 return rc; 885 } 886 887 /* Write AVID to shared page. */ 888 if (udata) { 889 struct bnxt_re_ucontext *uctx = rdma_udata_to_drv_context( 890 udata, struct bnxt_re_ucontext, ib_uctx); 891 unsigned long flag; 892 u32 *wrptr; 893 894 spin_lock_irqsave(&uctx->sh_lock, flag); 895 wrptr = (u32 *)(uctx->shpg + BNXT_RE_AVID_OFFT); 896 *wrptr = ah->qplib_ah.id; 897 wmb(); /* make sure cache is updated. */ 898 spin_unlock_irqrestore(&uctx->sh_lock, flag); 899 } 900 active_ahs = atomic_inc_return(&rdev->stats.res.ah_count); 901 if (active_ahs > rdev->stats.res.ah_watermark) 902 rdev->stats.res.ah_watermark = active_ahs; 903 904 return ib_respond_empty_udata(udata); 905 } 906 907 int bnxt_re_query_ah(struct ib_ah *ib_ah, struct rdma_ah_attr *ah_attr) 908 { 909 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah); 910 911 ah_attr->type = ib_ah->type; 912 rdma_ah_set_sl(ah_attr, ah->qplib_ah.sl); 913 memcpy(ah_attr->roce.dmac, ah->qplib_ah.dmac, ETH_ALEN); 914 rdma_ah_set_grh(ah_attr, NULL, 0, 915 ah->qplib_ah.host_sgid_index, 916 0, ah->qplib_ah.traffic_class); 917 rdma_ah_set_dgid_raw(ah_attr, ah->qplib_ah.dgid.data); 918 rdma_ah_set_port_num(ah_attr, 1); 919 rdma_ah_set_static_rate(ah_attr, 0); 920 return 0; 921 } 922 923 unsigned long bnxt_re_lock_cqs(struct bnxt_re_qp *qp) 924 __acquires(&qp->scq->cq_lock) __acquires(&qp->rcq->cq_lock) 925 { 926 unsigned long flags; 927 928 spin_lock_irqsave(&qp->scq->cq_lock, flags); 929 if (qp->rcq != qp->scq) 930 spin_lock(&qp->rcq->cq_lock); 931 else 932 __acquire(&qp->rcq->cq_lock); 933 934 return flags; 935 } 936 937 void bnxt_re_unlock_cqs(struct bnxt_re_qp *qp, 938 unsigned long flags) 939 __releases(&qp->scq->cq_lock) __releases(&qp->rcq->cq_lock) 940 { 941 if (qp->rcq != qp->scq) 942 spin_unlock(&qp->rcq->cq_lock); 943 else 944 __release(&qp->rcq->cq_lock); 945 spin_unlock_irqrestore(&qp->scq->cq_lock, flags); 946 } 947 948 static void bnxt_re_destroy_gsi_sqp(struct bnxt_re_qp *qp) 949 { 950 struct bnxt_re_qp *gsi_sqp; 951 struct bnxt_re_ah *gsi_sah; 952 struct bnxt_re_dev *rdev; 953 int rc; 954 955 rdev = qp->rdev; 956 gsi_sqp = rdev->gsi_ctx.gsi_sqp; 957 gsi_sah = rdev->gsi_ctx.gsi_sah; 958 959 ibdev_dbg(&rdev->ibdev, "Destroy the shadow AH\n"); 960 bnxt_qplib_destroy_ah(&rdev->qplib_res, 961 &gsi_sah->qplib_ah, 962 true); 963 atomic_dec(&rdev->stats.res.ah_count); 964 bnxt_qplib_clean_qp(&qp->qplib_qp); 965 966 ibdev_dbg(&rdev->ibdev, "Destroy the shadow QP\n"); 967 rc = bnxt_qplib_destroy_qp(&rdev->qplib_res, &gsi_sqp->qplib_qp); 968 if (rc) 969 ibdev_err(&rdev->ibdev, "Destroy Shadow QP failed"); 970 971 bnxt_qplib_free_qp_res(&rdev->qplib_res, &gsi_sqp->qplib_qp); 972 973 /* remove from active qp list */ 974 mutex_lock(&rdev->qp_lock); 975 list_del(&gsi_sqp->list); 976 mutex_unlock(&rdev->qp_lock); 977 atomic_dec(&rdev->stats.res.qp_count); 978 979 kfree(rdev->gsi_ctx.sqp_tbl); 980 kfree(gsi_sah); 981 kfree(gsi_sqp); 982 rdev->gsi_ctx.gsi_sqp = NULL; 983 rdev->gsi_ctx.gsi_sah = NULL; 984 rdev->gsi_ctx.sqp_tbl = NULL; 985 } 986 987 static void bnxt_re_del_unique_gid(struct bnxt_re_dev *rdev) 988 { 989 int rc; 990 991 if (!rdev->rcfw.roce_mirror) 992 return; 993 994 rc = bnxt_qplib_del_sgid(&rdev->qplib_res.sgid_tbl, 995 (struct bnxt_qplib_gid *)&rdev->ugid, 996 0xFFFF, true); 997 if (rc) 998 dev_err(rdev_to_dev(rdev), "Failed to delete unique GID, rc: %d\n", rc); 999 } 1000 1001 static void bnxt_re_qp_free_umem(struct bnxt_re_qp *qp) 1002 { 1003 ib_umem_release(qp->rumem); 1004 ib_umem_release(qp->sumem); 1005 } 1006 1007 /* Queue Pairs */ 1008 int bnxt_re_destroy_qp(struct ib_qp *ib_qp, struct ib_udata *udata) 1009 { 1010 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 1011 struct bnxt_qplib_qp *qplib_qp = &qp->qplib_qp; 1012 struct bnxt_re_dev *rdev = qp->rdev; 1013 struct bnxt_qplib_nq *scq_nq = NULL; 1014 struct bnxt_qplib_nq *rcq_nq = NULL; 1015 unsigned int flags; 1016 int rc; 1017 1018 rc = ib_is_udata_in_empty(udata); 1019 if (rc) 1020 return rc; 1021 1022 bnxt_re_debug_rem_qpinfo(rdev, qp); 1023 1024 bnxt_qplib_flush_cqn_wq(&qp->qplib_qp); 1025 1026 rc = bnxt_qplib_destroy_qp(&rdev->qplib_res, &qp->qplib_qp); 1027 if (rc) 1028 ibdev_err(&rdev->ibdev, "Failed to destroy HW QP"); 1029 1030 if (qp->dbr_obj) 1031 kref_put(&qp->dbr_obj->usecnt, bnxt_re_dbr_kref_release); 1032 1033 if (rdma_is_kernel_res(&qp->ib_qp.res)) { 1034 flags = bnxt_re_lock_cqs(qp); 1035 bnxt_qplib_clean_qp(&qp->qplib_qp); 1036 bnxt_re_unlock_cqs(qp, flags); 1037 } 1038 1039 bnxt_qplib_free_qp_res(&rdev->qplib_res, &qp->qplib_qp); 1040 1041 if (ib_qp->qp_type == IB_QPT_GSI && rdev->gsi_ctx.gsi_sqp) 1042 bnxt_re_destroy_gsi_sqp(qp); 1043 1044 mutex_lock(&rdev->qp_lock); 1045 list_del(&qp->list); 1046 mutex_unlock(&rdev->qp_lock); 1047 atomic_dec(&rdev->stats.res.qp_count); 1048 if (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_RC) 1049 atomic_dec(&rdev->stats.res.rc_qp_count); 1050 else if (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_UD) 1051 atomic_dec(&rdev->stats.res.ud_qp_count); 1052 1053 if (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_RAW_ETHERTYPE) 1054 bnxt_re_del_unique_gid(rdev); 1055 1056 bnxt_re_qp_free_umem(qp); 1057 1058 /* Flush all the entries of notification queue associated with 1059 * given qp. 1060 */ 1061 scq_nq = qplib_qp->scq->nq; 1062 rcq_nq = qplib_qp->rcq->nq; 1063 bnxt_re_synchronize_nq(scq_nq); 1064 if (scq_nq != rcq_nq) 1065 bnxt_re_synchronize_nq(rcq_nq); 1066 1067 return ib_respond_empty_udata(udata); 1068 } 1069 1070 static u8 __from_ib_qp_type(enum ib_qp_type type) 1071 { 1072 switch (type) { 1073 case IB_QPT_GSI: 1074 return CMDQ_CREATE_QP1_TYPE_GSI; 1075 case IB_QPT_RC: 1076 return CMDQ_CREATE_QP_TYPE_RC; 1077 case IB_QPT_UD: 1078 return CMDQ_CREATE_QP_TYPE_UD; 1079 case IB_QPT_RAW_PACKET: 1080 return CMDQ_CREATE_QP_TYPE_RAW_ETHERTYPE; 1081 default: 1082 return IB_QPT_MAX; 1083 } 1084 } 1085 1086 static u16 bnxt_re_setup_rwqe_size(struct bnxt_qplib_qp *qplqp, 1087 int rsge, int max) 1088 { 1089 if (qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC) 1090 rsge = max; 1091 return bnxt_re_get_rwqe_size(rsge); 1092 } 1093 1094 static u16 bnxt_re_get_wqe_size(int ilsize, int nsge) 1095 { 1096 u16 wqe_size, calc_ils; 1097 1098 wqe_size = bnxt_re_get_swqe_size(nsge); 1099 if (ilsize) { 1100 calc_ils = sizeof(struct sq_send_hdr) + ilsize; 1101 wqe_size = max_t(u16, calc_ils, wqe_size); 1102 wqe_size = ALIGN(wqe_size, sizeof(struct sq_send_hdr)); 1103 } 1104 return wqe_size; 1105 } 1106 1107 static int bnxt_re_setup_swqe_size(struct bnxt_re_qp *qp, 1108 struct ib_qp_init_attr *init_attr) 1109 { 1110 struct bnxt_qplib_dev_attr *dev_attr; 1111 struct bnxt_qplib_qp *qplqp; 1112 struct bnxt_re_dev *rdev; 1113 struct bnxt_qplib_q *sq; 1114 int align, ilsize; 1115 1116 rdev = qp->rdev; 1117 qplqp = &qp->qplib_qp; 1118 sq = &qplqp->sq; 1119 dev_attr = rdev->dev_attr; 1120 1121 align = sizeof(struct sq_send_hdr); 1122 ilsize = ALIGN(init_attr->cap.max_inline_data, align); 1123 1124 /* For gen p4 and gen p5 fixed wqe compatibility mode 1125 * wqe size is fixed to 128 bytes - ie 6 SGEs 1126 */ 1127 if (qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC) { 1128 sq->wqe_size = bnxt_re_get_swqe_size(BNXT_STATIC_MAX_SGE); 1129 sq->max_sge = BNXT_STATIC_MAX_SGE; 1130 } else { 1131 sq->wqe_size = bnxt_re_get_wqe_size(ilsize, sq->max_sge); 1132 if (sq->wqe_size > bnxt_re_get_swqe_size(dev_attr->max_qp_sges)) 1133 return -EINVAL; 1134 } 1135 1136 if (init_attr->cap.max_inline_data) { 1137 qplqp->max_inline_data = sq->wqe_size - 1138 sizeof(struct sq_send_hdr); 1139 init_attr->cap.max_inline_data = qplqp->max_inline_data; 1140 } 1141 1142 return 0; 1143 } 1144 1145 static int bnxt_re_setup_sginfo(struct bnxt_re_dev *rdev, 1146 struct ib_umem *umem, 1147 struct bnxt_qplib_sg_info *sginfo) 1148 { 1149 unsigned long page_size; 1150 1151 if (!umem) 1152 return -EINVAL; 1153 1154 page_size = ib_umem_find_best_pgsz(umem, SZ_4K, 0); 1155 if (!page_size || page_size != SZ_4K) 1156 return -EINVAL; 1157 1158 sginfo->umem = umem; 1159 sginfo->npages = ib_umem_num_dma_blocks(umem, page_size); 1160 sginfo->pgsize = page_size; 1161 sginfo->pgshft = __builtin_ctz(page_size); 1162 return 0; 1163 } 1164 1165 static int bnxt_re_get_psn_bytes(struct bnxt_re_dev *rdev, 1166 struct bnxt_re_ucontext *cntx, 1167 struct bnxt_qplib_qp *qplib_qp, 1168 struct bnxt_re_qp_req *ureq, 1169 bool fixed_que_attr) 1170 { 1171 int psn_sz, psn_nume; 1172 1173 if (rdev->dev_attr && 1174 _is_host_msn_table(rdev->dev_attr->dev_cap_flags2)) 1175 psn_sz = sizeof(struct sq_msn_search); 1176 else 1177 psn_sz = bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx) ? 1178 sizeof(struct sq_psn_search_ext) : 1179 sizeof(struct sq_psn_search); 1180 if (!fixed_que_attr) { 1181 if (cntx && bnxt_re_is_var_size_supported(rdev, cntx)) { 1182 psn_nume = ureq->sq_slots; 1183 } else { 1184 psn_nume = (qplib_qp->wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC) ? 1185 qplib_qp->sq.max_wqe : ((qplib_qp->sq.max_wqe * qplib_qp->sq.wqe_size) / 1186 sizeof(struct bnxt_qplib_sge)); 1187 } 1188 if (_is_host_msn_table(rdev->qplib_res.dattr->dev_cap_flags2)) 1189 psn_nume = roundup_pow_of_two(psn_nume); 1190 } else { 1191 psn_nume = ureq->sq_npsn; 1192 } 1193 1194 return psn_nume * psn_sz; 1195 } 1196 1197 static int bnxt_re_init_user_qp(struct bnxt_re_dev *rdev, struct bnxt_re_pd *pd, 1198 struct bnxt_re_qp *qp, struct bnxt_re_ucontext *cntx, 1199 struct bnxt_re_qp_req *ureq, 1200 bool fixed_que_attr, 1201 struct bnxt_re_dbr_obj *dbr_obj, 1202 struct uverbs_attr_bundle *attrs) 1203 { 1204 struct bnxt_qplib_qp *qplib_qp; 1205 struct ib_umem *umem; 1206 int bytes; 1207 int rc; 1208 1209 qplib_qp = &qp->qplib_qp; 1210 1211 bytes = (qplib_qp->sq.max_wqe * qplib_qp->sq.wqe_size); 1212 /* Consider mapping PSN search memory only for RC QPs. */ 1213 if (qplib_qp->type == CMDQ_CREATE_QP_TYPE_RC) 1214 bytes += bnxt_re_get_psn_bytes(rdev, cntx, qplib_qp, ureq, fixed_que_attr); 1215 1216 bytes = PAGE_ALIGN(bytes); 1217 umem = ib_umem_get_attr_or_va(&rdev->ibdev, attrs, 1218 UVERBS_ATTR_CREATE_QP_SQ_BUF_UMEM, 1219 ureq->qpsva, bytes, IB_ACCESS_LOCAL_WRITE); 1220 if (IS_ERR(umem)) 1221 return PTR_ERR(umem); 1222 1223 qp->sumem = umem; 1224 rc = bnxt_re_setup_sginfo(rdev, qp->sumem, &qplib_qp->sq.sg_info); 1225 if (rc) 1226 goto fail; 1227 1228 if (qp->qplib_qp.srq) 1229 goto done; 1230 1231 bytes = (qplib_qp->rq.max_wqe * qplib_qp->rq.wqe_size); 1232 bytes = PAGE_ALIGN(bytes); 1233 umem = ib_umem_get_attr_or_va(&rdev->ibdev, attrs, 1234 UVERBS_ATTR_CREATE_QP_RQ_BUF_UMEM, 1235 ureq->qprva, bytes, IB_ACCESS_LOCAL_WRITE); 1236 if (IS_ERR(umem)) { 1237 rc = PTR_ERR(umem); 1238 goto fail; 1239 } 1240 1241 qp->rumem = umem; 1242 rc = bnxt_re_setup_sginfo(rdev, qp->rumem, &qplib_qp->rq.sg_info); 1243 if (rc) 1244 goto rqfail; 1245 1246 done: 1247 if (dbr_obj) 1248 qplib_qp->dpi = &dbr_obj->dpi; 1249 else 1250 qplib_qp->dpi = &cntx->dpi; 1251 qplib_qp->qp_handle = ureq->qp_handle; 1252 qplib_qp->is_user = true; 1253 return 0; 1254 1255 rqfail: 1256 ib_umem_release(qp->rumem); 1257 qp->rumem = NULL; 1258 memset(&qplib_qp->rq.sg_info, 0, sizeof(qplib_qp->rq.sg_info)); 1259 fail: 1260 ib_umem_release(qp->sumem); 1261 qp->sumem = NULL; 1262 memset(&qplib_qp->sq.sg_info, 0, sizeof(qplib_qp->sq.sg_info)); 1263 return rc; 1264 } 1265 1266 static struct bnxt_re_ah *bnxt_re_create_shadow_qp_ah 1267 (struct bnxt_re_pd *pd, 1268 struct bnxt_qplib_res *qp1_res, 1269 struct bnxt_qplib_qp *qp1_qp) 1270 { 1271 struct bnxt_re_dev *rdev = pd->rdev; 1272 struct bnxt_re_ah *ah; 1273 union ib_gid sgid; 1274 int rc; 1275 1276 ah = kzalloc_obj(*ah); 1277 if (!ah) 1278 return NULL; 1279 1280 ah->rdev = rdev; 1281 ah->qplib_ah.pd = &pd->qplib_pd; 1282 1283 rc = bnxt_re_query_gid(&rdev->ibdev, 1, 0, &sgid); 1284 if (rc) 1285 goto fail; 1286 1287 /* supply the dgid data same as sgid */ 1288 memcpy(ah->qplib_ah.dgid.data, &sgid.raw, 1289 sizeof(union ib_gid)); 1290 ah->qplib_ah.sgid_index = 0; 1291 1292 ah->qplib_ah.traffic_class = 0; 1293 ah->qplib_ah.flow_label = 0; 1294 ah->qplib_ah.hop_limit = 1; 1295 ah->qplib_ah.sl = 0; 1296 /* Have DMAC same as SMAC */ 1297 ether_addr_copy(ah->qplib_ah.dmac, rdev->netdev->dev_addr); 1298 1299 rc = bnxt_qplib_create_ah(&rdev->qplib_res, &ah->qplib_ah, false); 1300 if (rc) { 1301 ibdev_err(&rdev->ibdev, 1302 "Failed to allocate HW AH for Shadow QP"); 1303 goto fail; 1304 } 1305 atomic_inc(&rdev->stats.res.ah_count); 1306 1307 return ah; 1308 1309 fail: 1310 kfree(ah); 1311 return NULL; 1312 } 1313 1314 static int bnxt_re_qp_alloc_init_xrrq(struct bnxt_re_qp *qp) 1315 { 1316 struct bnxt_qplib_res *res = &qp->rdev->qplib_res; 1317 struct bnxt_qplib_qp *qplib_qp = &qp->qplib_qp; 1318 struct bnxt_qplib_hwq_attr hwq_attr = {}; 1319 struct bnxt_qplib_sg_info sginfo = {}; 1320 struct bnxt_qplib_hwq *irrq, *orrq; 1321 int rc, req_size; 1322 1323 orrq = &qplib_qp->orrq; 1324 orrq->max_elements = 1325 ORD_LIMIT_TO_ORRQ_SLOTS(qplib_qp->max_rd_atomic); 1326 req_size = orrq->max_elements * 1327 BNXT_QPLIB_MAX_ORRQE_ENTRY_SIZE + PAGE_SIZE - 1; 1328 req_size &= ~(PAGE_SIZE - 1); 1329 sginfo.pgsize = req_size; 1330 sginfo.pgshft = PAGE_SHIFT; 1331 1332 hwq_attr.res = res; 1333 hwq_attr.sginfo = &sginfo; 1334 hwq_attr.depth = orrq->max_elements; 1335 hwq_attr.stride = BNXT_QPLIB_MAX_ORRQE_ENTRY_SIZE; 1336 hwq_attr.aux_stride = 0; 1337 hwq_attr.aux_depth = 0; 1338 hwq_attr.type = HWQ_TYPE_CTX; 1339 rc = bnxt_qplib_alloc_init_hwq(orrq, &hwq_attr); 1340 if (rc) 1341 return rc; 1342 1343 irrq = &qplib_qp->irrq; 1344 irrq->max_elements = 1345 IRD_LIMIT_TO_IRRQ_SLOTS(qplib_qp->max_dest_rd_atomic); 1346 req_size = irrq->max_elements * 1347 BNXT_QPLIB_MAX_IRRQE_ENTRY_SIZE + PAGE_SIZE - 1; 1348 req_size &= ~(PAGE_SIZE - 1); 1349 sginfo.pgsize = req_size; 1350 hwq_attr.sginfo = &sginfo; 1351 hwq_attr.depth = irrq->max_elements; 1352 hwq_attr.stride = BNXT_QPLIB_MAX_IRRQE_ENTRY_SIZE; 1353 rc = bnxt_qplib_alloc_init_hwq(irrq, &hwq_attr); 1354 if (rc) 1355 goto free_orrq_hwq; 1356 return 0; 1357 free_orrq_hwq: 1358 bnxt_qplib_free_hwq(res, orrq); 1359 return rc; 1360 } 1361 1362 static int bnxt_re_setup_qp_hwqs(struct bnxt_re_qp *qp, bool fixed_que_attr) 1363 { 1364 struct bnxt_qplib_res *res = &qp->rdev->qplib_res; 1365 struct bnxt_qplib_qp *qplib_qp = &qp->qplib_qp; 1366 struct bnxt_qplib_hwq_attr hwq_attr = {}; 1367 struct bnxt_qplib_q *sq = &qplib_qp->sq; 1368 struct bnxt_qplib_q *rq = &qplib_qp->rq; 1369 u8 wqe_mode = qplib_qp->wqe_mode; 1370 u8 pg_sz_lvl; 1371 int rc; 1372 1373 hwq_attr.res = res; 1374 hwq_attr.sginfo = &sq->sg_info; 1375 hwq_attr.stride = bnxt_qplib_get_stride(); 1376 hwq_attr.aux_stride = qplib_qp->psn_sz; 1377 if (!fixed_que_attr) { 1378 hwq_attr.depth = bnxt_qplib_get_depth(sq, wqe_mode, true); 1379 hwq_attr.aux_depth = (qplib_qp->psn_sz) ? 1380 bnxt_qplib_set_sq_size(sq, wqe_mode) : 0; 1381 if (qplib_qp->is_host_msn_tbl && qplib_qp->psn_sz) 1382 hwq_attr.aux_depth = qplib_qp->msn_tbl_sz; 1383 } else { 1384 hwq_attr.depth = sq->max_wqe; 1385 hwq_attr.aux_depth = qplib_qp->msn_tbl_sz; 1386 } 1387 hwq_attr.type = HWQ_TYPE_QUEUE; 1388 rc = bnxt_qplib_alloc_init_hwq(&sq->hwq, &hwq_attr); 1389 if (rc) 1390 return rc; 1391 1392 pg_sz_lvl = bnxt_qplib_base_pg_size(&sq->hwq) << CMDQ_CREATE_QP_SQ_PG_SIZE_SFT; 1393 pg_sz_lvl |= ((sq->hwq.level & CMDQ_CREATE_QP_SQ_LVL_MASK) << 1394 CMDQ_CREATE_QP_SQ_LVL_SFT); 1395 sq->hwq.pg_sz_lvl = pg_sz_lvl; 1396 1397 if (qplib_qp->srq) 1398 goto done; 1399 1400 hwq_attr.res = res; 1401 hwq_attr.sginfo = &rq->sg_info; 1402 hwq_attr.stride = bnxt_qplib_get_stride(); 1403 hwq_attr.depth = bnxt_qplib_get_depth(rq, qplib_qp->wqe_mode, false); 1404 hwq_attr.aux_stride = 0; 1405 hwq_attr.aux_depth = 0; 1406 hwq_attr.type = HWQ_TYPE_QUEUE; 1407 rc = bnxt_qplib_alloc_init_hwq(&rq->hwq, &hwq_attr); 1408 if (rc) 1409 goto free_sq_hwq; 1410 pg_sz_lvl = bnxt_qplib_base_pg_size(&rq->hwq) << 1411 CMDQ_CREATE_QP_RQ_PG_SIZE_SFT; 1412 pg_sz_lvl |= ((rq->hwq.level & CMDQ_CREATE_QP_RQ_LVL_MASK) << 1413 CMDQ_CREATE_QP_RQ_LVL_SFT); 1414 rq->hwq.pg_sz_lvl = pg_sz_lvl; 1415 1416 done: 1417 if (qplib_qp->psn_sz) { 1418 rc = bnxt_re_qp_alloc_init_xrrq(qp); 1419 if (rc) 1420 goto free_rq_hwq; 1421 } 1422 1423 return 0; 1424 free_rq_hwq: 1425 bnxt_qplib_free_hwq(res, &rq->hwq); 1426 free_sq_hwq: 1427 bnxt_qplib_free_hwq(res, &sq->hwq); 1428 return rc; 1429 } 1430 1431 static struct bnxt_re_qp *bnxt_re_create_shadow_qp 1432 (struct bnxt_re_pd *pd, 1433 struct bnxt_qplib_res *qp1_res, 1434 struct bnxt_qplib_qp *qp1_qp) 1435 { 1436 struct bnxt_re_dev *rdev = pd->rdev; 1437 struct bnxt_re_qp *qp; 1438 int rc; 1439 1440 qp = kzalloc_obj(*qp); 1441 if (!qp) 1442 return NULL; 1443 1444 qp->rdev = rdev; 1445 1446 /* Initialize the shadow QP structure from the QP1 values */ 1447 ether_addr_copy(qp->qplib_qp.smac, rdev->netdev->dev_addr); 1448 1449 qp->qplib_qp.pd = &pd->qplib_pd; 1450 qp->qplib_qp.qp_handle = (u64)(unsigned long)(&qp->qplib_qp); 1451 qp->qplib_qp.type = IB_QPT_UD; 1452 qp->qplib_qp.cctx = rdev->chip_ctx; 1453 1454 qp->qplib_qp.max_inline_data = 0; 1455 qp->qplib_qp.sig_type = true; 1456 1457 /* Shadow QP SQ depth should be same as QP1 RQ depth */ 1458 qp->qplib_qp.sq.wqe_size = bnxt_re_get_wqe_size(0, 6); 1459 qp->qplib_qp.sq.max_wqe = qp1_qp->rq.max_wqe; 1460 qp->qplib_qp.sq.max_sw_wqe = qp1_qp->rq.max_wqe; 1461 qp->qplib_qp.sq.max_sge = 2; 1462 /* Q full delta can be 1 since it is internal QP */ 1463 qp->qplib_qp.sq.q_full_delta = 1; 1464 qp->qplib_qp.sq.sg_info.pgsize = PAGE_SIZE; 1465 qp->qplib_qp.sq.sg_info.pgshft = PAGE_SHIFT; 1466 1467 qp->qplib_qp.scq = qp1_qp->scq; 1468 qp->qplib_qp.rcq = qp1_qp->rcq; 1469 1470 qp->qplib_qp.rq.wqe_size = bnxt_re_get_rwqe_size(6); 1471 qp->qplib_qp.rq.max_wqe = qp1_qp->rq.max_wqe; 1472 qp->qplib_qp.rq.max_sw_wqe = qp1_qp->rq.max_wqe; 1473 qp->qplib_qp.rq.max_sge = qp1_qp->rq.max_sge; 1474 /* Q full delta can be 1 since it is internal QP */ 1475 qp->qplib_qp.rq.q_full_delta = 1; 1476 qp->qplib_qp.rq.sg_info.pgsize = PAGE_SIZE; 1477 qp->qplib_qp.rq.sg_info.pgshft = PAGE_SHIFT; 1478 1479 qp->qplib_qp.mtu = qp1_qp->mtu; 1480 1481 qp->qplib_qp.sq_hdr_buf_size = 0; 1482 qp->qplib_qp.rq_hdr_buf_size = BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6; 1483 qp->qplib_qp.dpi = &rdev->dpi_privileged; 1484 1485 rc = bnxt_re_setup_qp_hwqs(qp, false); 1486 if (rc) 1487 goto fail; 1488 1489 rc = bnxt_qplib_create_qp(qp1_res, &qp->qplib_qp); 1490 if (rc) 1491 goto free_hwq; 1492 1493 spin_lock_init(&qp->sq_lock); 1494 INIT_LIST_HEAD(&qp->list); 1495 mutex_lock(&rdev->qp_lock); 1496 list_add_tail(&qp->list, &rdev->qp_list); 1497 atomic_inc(&rdev->stats.res.qp_count); 1498 mutex_unlock(&rdev->qp_lock); 1499 return qp; 1500 1501 free_hwq: 1502 bnxt_qplib_free_qp_res(&rdev->qplib_res, &qp->qplib_qp); 1503 fail: 1504 kfree(qp); 1505 return NULL; 1506 } 1507 1508 static int bnxt_re_init_rq_attr(struct bnxt_re_qp *qp, 1509 struct ib_qp_init_attr *init_attr, 1510 struct bnxt_re_ucontext *uctx, 1511 bool fixed_que_attr) 1512 { 1513 struct bnxt_qplib_dev_attr *dev_attr; 1514 struct bnxt_qplib_qp *qplqp; 1515 struct bnxt_re_dev *rdev; 1516 struct bnxt_qplib_q *rq; 1517 1518 rdev = qp->rdev; 1519 qplqp = &qp->qplib_qp; 1520 rq = &qplqp->rq; 1521 dev_attr = rdev->dev_attr; 1522 1523 if (init_attr->srq) { 1524 struct bnxt_re_srq *srq; 1525 1526 srq = container_of(init_attr->srq, struct bnxt_re_srq, ib_srq); 1527 qplqp->srq = &srq->qplib_srq; 1528 rq->max_wqe = 0; 1529 } else { 1530 rq->max_sge = init_attr->cap.max_recv_sge; 1531 if (rq->max_sge > dev_attr->max_qp_sges) 1532 rq->max_sge = dev_attr->max_qp_sges; 1533 init_attr->cap.max_recv_sge = rq->max_sge; 1534 rq->wqe_size = bnxt_re_setup_rwqe_size(qplqp, rq->max_sge, 1535 dev_attr->max_qp_sges); 1536 if (!fixed_que_attr) { 1537 /* Allocate 1 more than what's provided so posting max doesn't 1538 * mean empty. 1539 */ 1540 rq->max_wqe = bnxt_re_init_depth(init_attr->cap.max_recv_wr + 1, 1541 dev_attr->max_qp_wqes + 1, 1542 uctx); 1543 } else { 1544 rq->max_wqe = init_attr->cap.max_recv_wr; 1545 } 1546 rq->max_sw_wqe = rq->max_wqe; 1547 rq->q_full_delta = 0; 1548 rq->sg_info.pgsize = PAGE_SIZE; 1549 rq->sg_info.pgshft = PAGE_SHIFT; 1550 } 1551 1552 return 0; 1553 } 1554 1555 static void bnxt_re_adjust_gsi_rq_attr(struct bnxt_re_qp *qp) 1556 { 1557 struct bnxt_qplib_dev_attr *dev_attr; 1558 struct bnxt_qplib_qp *qplqp; 1559 struct bnxt_re_dev *rdev; 1560 1561 rdev = qp->rdev; 1562 qplqp = &qp->qplib_qp; 1563 dev_attr = rdev->dev_attr; 1564 1565 if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) { 1566 qplqp->rq.max_sge = dev_attr->max_qp_sges; 1567 if (qplqp->rq.max_sge > dev_attr->max_qp_sges) 1568 qplqp->rq.max_sge = dev_attr->max_qp_sges; 1569 qplqp->rq.max_sge = 6; 1570 } 1571 } 1572 1573 static int bnxt_re_init_sq_attr(struct bnxt_re_qp *qp, 1574 struct ib_qp_init_attr *init_attr, 1575 struct bnxt_re_ucontext *uctx, 1576 struct bnxt_re_qp_req *ureq, 1577 bool fixed_que_attr) 1578 { 1579 struct bnxt_qplib_dev_attr *dev_attr; 1580 struct bnxt_qplib_qp *qplqp; 1581 struct bnxt_re_dev *rdev; 1582 struct bnxt_qplib_q *sq; 1583 int diff = 0; 1584 int rc; 1585 1586 rdev = qp->rdev; 1587 qplqp = &qp->qplib_qp; 1588 sq = &qplqp->sq; 1589 dev_attr = rdev->dev_attr; 1590 1591 sq->max_sge = init_attr->cap.max_send_sge; 1592 if (uctx && qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_VARIABLE) { 1593 sq->max_wqe = ureq->sq_slots; 1594 sq->max_sw_wqe = ureq->sq_slots; 1595 sq->wqe_size = sizeof(struct sq_sge); 1596 } else { 1597 if (sq->max_sge > dev_attr->max_qp_sges) { 1598 sq->max_sge = dev_attr->max_qp_sges; 1599 init_attr->cap.max_send_sge = sq->max_sge; 1600 } 1601 1602 rc = bnxt_re_setup_swqe_size(qp, init_attr); 1603 if (rc) 1604 return rc; 1605 1606 /* Allocate 128 + 1 more than what's provided */ 1607 if (qplqp->wqe_mode != BNXT_QPLIB_WQE_MODE_VARIABLE) 1608 diff = BNXT_QPLIB_RESERVED_QP_WRS; 1609 sq->max_wqe = bnxt_re_init_depth( 1610 init_attr->cap.max_send_wr + diff + 1, 1611 dev_attr->max_qp_wqes + diff + 1, uctx); 1612 if (qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_VARIABLE) 1613 sq->max_sw_wqe = bnxt_qplib_get_depth(sq, qplqp->wqe_mode, true); 1614 else 1615 sq->max_sw_wqe = sq->max_wqe; 1616 1617 } 1618 if (!fixed_que_attr) { 1619 sq->q_full_delta = diff + 1; 1620 /* 1621 * Reserving one slot for Phantom WQE. Application can 1622 * post one extra entry in this case. But allowing this to avoid 1623 * unexpected Queue full condition 1624 */ 1625 qplqp->sq.q_full_delta -= 1; 1626 } else { 1627 sq->q_full_delta = 0; 1628 } 1629 1630 qplqp->sq.sg_info.pgsize = PAGE_SIZE; 1631 qplqp->sq.sg_info.pgshft = PAGE_SHIFT; 1632 1633 return 0; 1634 } 1635 1636 static void bnxt_re_adjust_gsi_sq_attr(struct bnxt_re_qp *qp, 1637 struct ib_qp_init_attr *init_attr, 1638 struct bnxt_re_ucontext *uctx) 1639 { 1640 struct bnxt_qplib_dev_attr *dev_attr; 1641 struct bnxt_qplib_qp *qplqp; 1642 struct bnxt_re_dev *rdev; 1643 1644 rdev = qp->rdev; 1645 qplqp = &qp->qplib_qp; 1646 dev_attr = rdev->dev_attr; 1647 1648 if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) { 1649 qplqp->sq.max_wqe = 1650 bnxt_re_init_depth(init_attr->cap.max_send_wr + 1, 1651 dev_attr->max_qp_wqes + 1, uctx); 1652 qplqp->sq.q_full_delta = qplqp->sq.max_wqe - 1653 init_attr->cap.max_send_wr; 1654 qplqp->sq.max_sge++; /* Need one extra sge to put UD header */ 1655 if (qplqp->sq.max_sge > dev_attr->max_qp_sges) 1656 qplqp->sq.max_sge = dev_attr->max_qp_sges; 1657 } 1658 } 1659 1660 static int bnxt_re_init_qp_type(struct bnxt_re_dev *rdev, 1661 struct ib_qp_init_attr *init_attr) 1662 { 1663 struct bnxt_qplib_chip_ctx *chip_ctx; 1664 int qptype; 1665 1666 chip_ctx = rdev->chip_ctx; 1667 1668 qptype = __from_ib_qp_type(init_attr->qp_type); 1669 if (qptype == IB_QPT_MAX) { 1670 ibdev_err(&rdev->ibdev, "QP type 0x%x not supported", qptype); 1671 qptype = -EOPNOTSUPP; 1672 goto out; 1673 } 1674 1675 if (bnxt_qplib_is_chip_gen_p5_p7(chip_ctx) && 1676 init_attr->qp_type == IB_QPT_GSI) 1677 qptype = CMDQ_CREATE_QP_TYPE_GSI; 1678 out: 1679 return qptype; 1680 } 1681 1682 static void bnxt_re_qp_calculate_msn_psn_size(struct bnxt_re_qp *qp, 1683 bool fixed_que_attr, 1684 struct bnxt_re_qp_req *req) 1685 { 1686 struct bnxt_qplib_qp *qplib_qp = &qp->qplib_qp; 1687 struct bnxt_qplib_q *sq = &qplib_qp->sq; 1688 struct bnxt_re_dev *rdev = qp->rdev; 1689 u8 wqe_mode = qplib_qp->wqe_mode; 1690 1691 if (rdev->dev_attr) 1692 qplib_qp->is_host_msn_tbl = 1693 _is_host_msn_table(rdev->dev_attr->dev_cap_flags2); 1694 1695 if (qplib_qp->type == CMDQ_CREATE_QP_TYPE_RC) { 1696 qplib_qp->psn_sz = bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx) ? 1697 sizeof(struct sq_psn_search_ext) : 1698 sizeof(struct sq_psn_search); 1699 if (qplib_qp->is_host_msn_tbl) { 1700 qplib_qp->psn_sz = sizeof(struct sq_msn_search); 1701 qplib_qp->msn = 0; 1702 } 1703 } 1704 1705 /* Update msn tbl size */ 1706 if (qplib_qp->is_host_msn_tbl && qplib_qp->psn_sz) { 1707 if (!fixed_que_attr) { 1708 if (wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC) 1709 qplib_qp->msn_tbl_sz = 1710 roundup_pow_of_two(bnxt_qplib_set_sq_size(sq, wqe_mode)); 1711 else 1712 qplib_qp->msn_tbl_sz = 1713 roundup_pow_of_two(bnxt_qplib_set_sq_size(sq, wqe_mode)) 1714 / 2; 1715 } else { 1716 qplib_qp->msn_tbl_sz = req->sq_npsn; 1717 } 1718 qplib_qp->msn = 0; 1719 } 1720 } 1721 1722 static int bnxt_re_init_qp_attr(struct bnxt_re_qp *qp, struct bnxt_re_pd *pd, 1723 struct ib_qp_init_attr *init_attr, 1724 struct bnxt_re_ucontext *uctx, 1725 struct bnxt_re_qp_req *ureq, 1726 struct bnxt_re_dbr_obj *dbr_obj, 1727 bool fixed_que_attr, 1728 struct uverbs_attr_bundle *attrs) 1729 { 1730 struct bnxt_qplib_dev_attr *dev_attr; 1731 struct bnxt_qplib_qp *qplqp; 1732 struct bnxt_re_dev *rdev; 1733 struct bnxt_re_cq *cq; 1734 int rc = 0, qptype; 1735 1736 rdev = qp->rdev; 1737 qplqp = &qp->qplib_qp; 1738 dev_attr = rdev->dev_attr; 1739 1740 /* Setup misc params */ 1741 ether_addr_copy(qplqp->smac, rdev->netdev->dev_addr); 1742 qplqp->pd = &pd->qplib_pd; 1743 qplqp->qp_handle = (u64)qplqp; 1744 qplqp->max_inline_data = init_attr->cap.max_inline_data; 1745 qplqp->sig_type = init_attr->sq_sig_type == IB_SIGNAL_ALL_WR; 1746 qptype = bnxt_re_init_qp_type(rdev, init_attr); 1747 if (qptype < 0) 1748 return qptype; 1749 qplqp->type = (u8)qptype; 1750 qplqp->wqe_mode = bnxt_re_is_var_size_supported(rdev, uctx); 1751 if (uctx && qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_VARIABLE && 1752 (!ureq->sq_slots || ureq->sq_slots > BNXT_RE_MAX_SQ_SLOTS)) 1753 return -EINVAL; 1754 if (fixed_que_attr) { 1755 if (qplqp->wqe_mode != BNXT_QPLIB_WQE_MODE_VARIABLE) 1756 return -EOPNOTSUPP; 1757 if (!ureq->sq_npsn || 1758 ureq->sq_npsn > roundup_pow_of_two(ureq->sq_slots / 2)) 1759 return -EINVAL; 1760 } 1761 qplqp->dev_cap_flags = dev_attr->dev_cap_flags; 1762 qplqp->cctx = rdev->chip_ctx; 1763 if (init_attr->qp_type == IB_QPT_RC) { 1764 qplqp->max_rd_atomic = dev_attr->max_qp_rd_atom; 1765 qplqp->max_dest_rd_atomic = dev_attr->max_qp_init_rd_atom; 1766 } 1767 qplqp->mtu = ib_mtu_enum_to_int(iboe_get_mtu(rdev->netdev->mtu)); 1768 qplqp->dpi = &rdev->dpi_privileged; /* Doorbell page */ 1769 if (init_attr->create_flags) { 1770 ibdev_dbg(&rdev->ibdev, 1771 "QP create flags 0x%x not supported", 1772 init_attr->create_flags); 1773 return -EOPNOTSUPP; 1774 } 1775 1776 /* Setup CQs */ 1777 if (init_attr->send_cq) { 1778 cq = container_of(init_attr->send_cq, struct bnxt_re_cq, ib_cq); 1779 qplqp->scq = &cq->qplib_cq; 1780 qp->scq = cq; 1781 } 1782 1783 if (init_attr->recv_cq) { 1784 cq = container_of(init_attr->recv_cq, struct bnxt_re_cq, ib_cq); 1785 qplqp->rcq = &cq->qplib_cq; 1786 qp->rcq = cq; 1787 } 1788 1789 /* Setup RQ/SRQ */ 1790 rc = bnxt_re_init_rq_attr(qp, init_attr, uctx, fixed_que_attr); 1791 if (rc) 1792 return rc; 1793 if (init_attr->qp_type == IB_QPT_GSI) 1794 bnxt_re_adjust_gsi_rq_attr(qp); 1795 1796 /* Setup SQ */ 1797 rc = bnxt_re_init_sq_attr(qp, init_attr, uctx, ureq, fixed_que_attr); 1798 if (rc) 1799 return rc; 1800 if (init_attr->qp_type == IB_QPT_GSI) 1801 bnxt_re_adjust_gsi_sq_attr(qp, init_attr, uctx); 1802 1803 if (uctx) { /* This will update DPI and qp_handle */ 1804 rc = bnxt_re_init_user_qp(rdev, pd, qp, uctx, ureq, fixed_que_attr, 1805 dbr_obj, attrs); 1806 if (rc) 1807 return rc; 1808 } 1809 1810 bnxt_re_qp_calculate_msn_psn_size(qp, fixed_que_attr, ureq); 1811 1812 rc = bnxt_re_setup_qp_hwqs(qp, fixed_que_attr); 1813 if (rc) 1814 goto free_umem; 1815 1816 return 0; 1817 free_umem: 1818 bnxt_re_qp_free_umem(qp); 1819 return rc; 1820 } 1821 1822 static int bnxt_re_create_shadow_gsi(struct bnxt_re_qp *qp, 1823 struct bnxt_re_pd *pd) 1824 { 1825 struct bnxt_re_sqp_entries *sqp_tbl; 1826 struct bnxt_re_dev *rdev; 1827 struct bnxt_re_qp *sqp; 1828 struct bnxt_re_ah *sah; 1829 int rc = 0; 1830 1831 rdev = qp->rdev; 1832 /* Create a shadow QP to handle the QP1 traffic */ 1833 sqp_tbl = kzalloc_objs(*sqp_tbl, BNXT_RE_MAX_GSI_SQP_ENTRIES); 1834 if (!sqp_tbl) 1835 return -ENOMEM; 1836 rdev->gsi_ctx.sqp_tbl = sqp_tbl; 1837 1838 sqp = bnxt_re_create_shadow_qp(pd, &rdev->qplib_res, &qp->qplib_qp); 1839 if (!sqp) { 1840 rc = -ENODEV; 1841 ibdev_err(&rdev->ibdev, "Failed to create Shadow QP for QP1"); 1842 goto out; 1843 } 1844 rdev->gsi_ctx.gsi_sqp = sqp; 1845 1846 sqp->rcq = qp->rcq; 1847 sqp->scq = qp->scq; 1848 sah = bnxt_re_create_shadow_qp_ah(pd, &rdev->qplib_res, 1849 &qp->qplib_qp); 1850 if (!sah) { 1851 bnxt_qplib_destroy_qp(&rdev->qplib_res, 1852 &sqp->qplib_qp); 1853 rc = -ENODEV; 1854 ibdev_err(&rdev->ibdev, 1855 "Failed to create AH entry for ShadowQP"); 1856 goto out; 1857 } 1858 rdev->gsi_ctx.gsi_sah = sah; 1859 1860 return 0; 1861 out: 1862 kfree(sqp_tbl); 1863 return rc; 1864 } 1865 1866 static int bnxt_re_create_gsi_qp(struct bnxt_re_qp *qp, struct bnxt_re_pd *pd, 1867 struct ib_qp_init_attr *init_attr) 1868 { 1869 struct bnxt_re_dev *rdev; 1870 struct bnxt_qplib_qp *qplqp; 1871 int rc; 1872 1873 rdev = qp->rdev; 1874 qplqp = &qp->qplib_qp; 1875 qplqp->cctx = rdev->chip_ctx; 1876 1877 qplqp->rq_hdr_buf_size = BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2; 1878 qplqp->sq_hdr_buf_size = BNXT_QPLIB_MAX_QP1_SQ_HDR_SIZE_V2; 1879 1880 rc = bnxt_qplib_create_qp1(&rdev->qplib_res, qplqp); 1881 if (rc) { 1882 ibdev_err(&rdev->ibdev, "create HW QP1 failed!"); 1883 goto out; 1884 } 1885 1886 rc = bnxt_re_create_shadow_gsi(qp, pd); 1887 out: 1888 return rc; 1889 } 1890 1891 static bool bnxt_re_test_qp_limits(struct bnxt_re_dev *rdev, 1892 struct ib_qp_init_attr *init_attr, 1893 struct bnxt_qplib_dev_attr *dev_attr) 1894 { 1895 bool rc = true; 1896 1897 if (init_attr->cap.max_send_wr > dev_attr->max_qp_wqes || 1898 init_attr->cap.max_recv_wr > dev_attr->max_qp_wqes || 1899 init_attr->cap.max_send_sge > dev_attr->max_qp_sges || 1900 init_attr->cap.max_recv_sge > dev_attr->max_qp_sges || 1901 init_attr->cap.max_inline_data > dev_attr->max_inline_data) { 1902 ibdev_err(&rdev->ibdev, 1903 "Create QP failed - max exceeded! 0x%x/0x%x 0x%x/0x%x 0x%x/0x%x 0x%x/0x%x 0x%x/0x%x", 1904 init_attr->cap.max_send_wr, dev_attr->max_qp_wqes, 1905 init_attr->cap.max_recv_wr, dev_attr->max_qp_wqes, 1906 init_attr->cap.max_send_sge, dev_attr->max_qp_sges, 1907 init_attr->cap.max_recv_sge, dev_attr->max_qp_sges, 1908 init_attr->cap.max_inline_data, 1909 dev_attr->max_inline_data); 1910 rc = false; 1911 } 1912 return rc; 1913 } 1914 1915 static int bnxt_re_add_unique_gid(struct bnxt_re_dev *rdev) 1916 { 1917 struct bnxt_qplib_ctx *hctx = &rdev->qplib_ctx; 1918 struct bnxt_qplib_res *res = &rdev->qplib_res; 1919 int rc; 1920 1921 if (!rdev->rcfw.roce_mirror) 1922 return 0; 1923 1924 rdev->ugid.global.subnet_prefix = cpu_to_be64(0xfe8000000000abcdLL); 1925 addrconf_ifid_eui48(&rdev->ugid.raw[8], rdev->netdev); 1926 1927 rc = bnxt_qplib_add_sgid(&res->sgid_tbl, 1928 (struct bnxt_qplib_gid *)&rdev->ugid, 1929 rdev->qplib_res.netdev->dev_addr, 1930 0xFFFF, true, &rdev->ugid_index, true, 1931 hctx->stats3.fw_id); 1932 if (rc) 1933 dev_err(rdev_to_dev(rdev), "Failed to add unique GID. rc = %d\n", rc); 1934 1935 return rc; 1936 } 1937 1938 int bnxt_re_create_qp(struct ib_qp *ib_qp, struct ib_qp_init_attr *qp_init_attr, 1939 struct ib_udata *udata) 1940 { 1941 struct uverbs_attr_bundle *attrs = NULL; 1942 struct bnxt_re_dbr_obj *dbr_obj = NULL; 1943 struct bnxt_qplib_dev_attr *dev_attr; 1944 struct bnxt_re_ucontext *uctx; 1945 bool fixed_que_attr = false; 1946 struct bnxt_re_qp_req ureq; 1947 struct bnxt_re_dev *rdev; 1948 struct bnxt_re_pd *pd; 1949 struct bnxt_re_qp *qp; 1950 struct ib_pd *ib_pd; 1951 u32 active_qps; 1952 int rc; 1953 1954 ib_pd = ib_qp->pd; 1955 pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 1956 rdev = pd->rdev; 1957 dev_attr = rdev->dev_attr; 1958 qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 1959 1960 uctx = rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx); 1961 if (udata) { 1962 rc = ib_copy_validate_udata_in_cm(udata, ureq, qp_handle, 1963 BNXT_RE_QP_REQ_MASK_FIXED_QUE_ATTR); 1964 if (rc) 1965 return rc; 1966 1967 attrs = rdma_udata_to_uverbs_attr_bundle(udata); 1968 if (uverbs_attr_is_valid(attrs, 1969 BNXT_RE_CREATE_QP_ATTR_DBR_HANDLE)) { 1970 dbr_obj = uverbs_attr_get_obj(attrs, 1971 BNXT_RE_CREATE_QP_ATTR_DBR_HANDLE); 1972 if (IS_ERR(dbr_obj)) 1973 return PTR_ERR(dbr_obj); 1974 kref_get(&dbr_obj->usecnt); 1975 qp->dbr_obj = dbr_obj; 1976 } 1977 if (ureq.comp_mask & BNXT_RE_QP_REQ_MASK_FIXED_QUE_ATTR) 1978 fixed_que_attr = true; 1979 } 1980 1981 rc = bnxt_re_test_qp_limits(rdev, qp_init_attr, dev_attr); 1982 if (!rc) { 1983 rc = -EINVAL; 1984 goto fail; 1985 } 1986 1987 qp->rdev = rdev; 1988 rc = bnxt_re_init_qp_attr(qp, pd, qp_init_attr, uctx, &ureq, 1989 dbr_obj, fixed_que_attr, attrs); 1990 if (rc) 1991 goto fail; 1992 1993 if (qp_init_attr->qp_type == IB_QPT_GSI && 1994 !(bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx))) { 1995 rc = bnxt_re_create_gsi_qp(qp, pd, qp_init_attr); 1996 if (rc == -ENODEV) 1997 goto qp_destroy; 1998 if (rc) 1999 goto free_hwq; 2000 } else { 2001 rc = bnxt_qplib_create_qp(&rdev->qplib_res, &qp->qplib_qp); 2002 if (rc) { 2003 ibdev_err(&rdev->ibdev, "Failed to create HW QP"); 2004 goto free_hwq; 2005 } 2006 2007 if (udata) { 2008 struct bnxt_re_qp_resp resp = {}; 2009 2010 resp.qpid = qp->qplib_qp.id; 2011 resp.rsvd = 0; 2012 rc = ib_respond_udata(udata, resp); 2013 if (rc) 2014 goto qp_destroy; 2015 } 2016 } 2017 2018 /* Support for RawEth QP is added to capture TCP pkt dump. 2019 * So unique SGID is used to avoid incorrect statistics on per 2020 * function stats_ctx 2021 */ 2022 if (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_RAW_ETHERTYPE) { 2023 rc = bnxt_re_add_unique_gid(rdev); 2024 if (rc) 2025 goto qp_destroy; 2026 qp->qplib_qp.ugid_index = rdev->ugid_index; 2027 } 2028 2029 qp->ib_qp.qp_num = qp->qplib_qp.id; 2030 if (qp_init_attr->qp_type == IB_QPT_GSI) 2031 rdev->gsi_ctx.gsi_qp = qp; 2032 spin_lock_init(&qp->sq_lock); 2033 spin_lock_init(&qp->rq_lock); 2034 INIT_LIST_HEAD(&qp->list); 2035 mutex_lock(&rdev->qp_lock); 2036 list_add_tail(&qp->list, &rdev->qp_list); 2037 mutex_unlock(&rdev->qp_lock); 2038 active_qps = atomic_inc_return(&rdev->stats.res.qp_count); 2039 if (active_qps > rdev->stats.res.qp_watermark) 2040 rdev->stats.res.qp_watermark = active_qps; 2041 if (qp_init_attr->qp_type == IB_QPT_RC) { 2042 active_qps = atomic_inc_return(&rdev->stats.res.rc_qp_count); 2043 if (active_qps > rdev->stats.res.rc_qp_watermark) 2044 rdev->stats.res.rc_qp_watermark = active_qps; 2045 } else if (qp_init_attr->qp_type == IB_QPT_UD) { 2046 active_qps = atomic_inc_return(&rdev->stats.res.ud_qp_count); 2047 if (active_qps > rdev->stats.res.ud_qp_watermark) 2048 rdev->stats.res.ud_qp_watermark = active_qps; 2049 } 2050 bnxt_re_debug_add_qpinfo(rdev, qp); 2051 2052 return 0; 2053 qp_destroy: 2054 bnxt_qplib_destroy_qp(&rdev->qplib_res, &qp->qplib_qp); 2055 free_hwq: 2056 bnxt_qplib_free_qp_res(&rdev->qplib_res, &qp->qplib_qp); 2057 bnxt_re_qp_free_umem(qp); 2058 fail: 2059 if (dbr_obj) 2060 kref_put(&dbr_obj->usecnt, bnxt_re_dbr_kref_release); 2061 return rc; 2062 } 2063 2064 static u8 __from_ib_qp_state(enum ib_qp_state state) 2065 { 2066 switch (state) { 2067 case IB_QPS_RESET: 2068 return CMDQ_MODIFY_QP_NEW_STATE_RESET; 2069 case IB_QPS_INIT: 2070 return CMDQ_MODIFY_QP_NEW_STATE_INIT; 2071 case IB_QPS_RTR: 2072 return CMDQ_MODIFY_QP_NEW_STATE_RTR; 2073 case IB_QPS_RTS: 2074 return CMDQ_MODIFY_QP_NEW_STATE_RTS; 2075 case IB_QPS_SQD: 2076 return CMDQ_MODIFY_QP_NEW_STATE_SQD; 2077 case IB_QPS_SQE: 2078 return CMDQ_MODIFY_QP_NEW_STATE_SQE; 2079 case IB_QPS_ERR: 2080 default: 2081 return CMDQ_MODIFY_QP_NEW_STATE_ERR; 2082 } 2083 } 2084 2085 static enum ib_qp_state __to_ib_qp_state(u8 state) 2086 { 2087 switch (state) { 2088 case CMDQ_MODIFY_QP_NEW_STATE_RESET: 2089 return IB_QPS_RESET; 2090 case CMDQ_MODIFY_QP_NEW_STATE_INIT: 2091 return IB_QPS_INIT; 2092 case CMDQ_MODIFY_QP_NEW_STATE_RTR: 2093 return IB_QPS_RTR; 2094 case CMDQ_MODIFY_QP_NEW_STATE_RTS: 2095 return IB_QPS_RTS; 2096 case CMDQ_MODIFY_QP_NEW_STATE_SQD: 2097 return IB_QPS_SQD; 2098 case CMDQ_MODIFY_QP_NEW_STATE_SQE: 2099 return IB_QPS_SQE; 2100 case CMDQ_MODIFY_QP_NEW_STATE_ERR: 2101 default: 2102 return IB_QPS_ERR; 2103 } 2104 } 2105 2106 static u32 __from_ib_mtu(enum ib_mtu mtu) 2107 { 2108 switch (mtu) { 2109 case IB_MTU_256: 2110 return CMDQ_MODIFY_QP_PATH_MTU_MTU_256; 2111 case IB_MTU_512: 2112 return CMDQ_MODIFY_QP_PATH_MTU_MTU_512; 2113 case IB_MTU_1024: 2114 return CMDQ_MODIFY_QP_PATH_MTU_MTU_1024; 2115 case IB_MTU_2048: 2116 return CMDQ_MODIFY_QP_PATH_MTU_MTU_2048; 2117 case IB_MTU_4096: 2118 return CMDQ_MODIFY_QP_PATH_MTU_MTU_4096; 2119 default: 2120 return CMDQ_MODIFY_QP_PATH_MTU_MTU_2048; 2121 } 2122 } 2123 2124 static enum ib_mtu __to_ib_mtu(u32 mtu) 2125 { 2126 switch (mtu & CREQ_QUERY_QP_RESP_SB_PATH_MTU_MASK) { 2127 case CMDQ_MODIFY_QP_PATH_MTU_MTU_256: 2128 return IB_MTU_256; 2129 case CMDQ_MODIFY_QP_PATH_MTU_MTU_512: 2130 return IB_MTU_512; 2131 case CMDQ_MODIFY_QP_PATH_MTU_MTU_1024: 2132 return IB_MTU_1024; 2133 case CMDQ_MODIFY_QP_PATH_MTU_MTU_2048: 2134 return IB_MTU_2048; 2135 case CMDQ_MODIFY_QP_PATH_MTU_MTU_4096: 2136 return IB_MTU_4096; 2137 default: 2138 return IB_MTU_2048; 2139 } 2140 } 2141 2142 /* Shared Receive Queues */ 2143 int bnxt_re_destroy_srq(struct ib_srq *ib_srq, struct ib_udata *udata) 2144 { 2145 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq, 2146 ib_srq); 2147 struct bnxt_re_dev *rdev = srq->rdev; 2148 struct bnxt_qplib_srq *qplib_srq = &srq->qplib_srq; 2149 int ret; 2150 2151 ret = ib_is_udata_in_empty(udata); 2152 if (ret) 2153 return ret; 2154 2155 if (rdev->chip_ctx->modes.toggle_bits & BNXT_QPLIB_SRQ_TOGGLE_BIT) 2156 hash_del(&srq->hash_entry); 2157 bnxt_qplib_destroy_srq(&rdev->qplib_res, qplib_srq); 2158 if (rdev->chip_ctx->modes.toggle_bits & BNXT_QPLIB_SRQ_TOGGLE_BIT) 2159 free_page((unsigned long)srq->uctx_srq_page); 2160 ib_umem_release(srq->umem); 2161 atomic_dec(&rdev->stats.res.srq_count); 2162 return ib_respond_empty_udata(udata); 2163 } 2164 2165 static int bnxt_re_init_user_srq(struct bnxt_re_dev *rdev, 2166 struct bnxt_re_pd *pd, 2167 struct bnxt_re_srq *srq, 2168 struct ib_udata *udata) 2169 { 2170 struct bnxt_re_srq_req ureq; 2171 struct bnxt_qplib_srq *qplib_srq = &srq->qplib_srq; 2172 struct ib_umem *umem; 2173 int bytes = 0; 2174 struct bnxt_re_ucontext *cntx = rdma_udata_to_drv_context( 2175 udata, struct bnxt_re_ucontext, ib_uctx); 2176 int rc; 2177 2178 rc = ib_copy_validate_udata_in(udata, ureq, srq_handle); 2179 if (rc) 2180 return rc; 2181 2182 bytes = (qplib_srq->max_wqe * qplib_srq->wqe_size); 2183 bytes = PAGE_ALIGN(bytes); 2184 umem = ib_umem_get_va(&rdev->ibdev, ureq.srqva, bytes, 2185 IB_ACCESS_LOCAL_WRITE); 2186 if (IS_ERR(umem)) 2187 return PTR_ERR(umem); 2188 2189 srq->umem = umem; 2190 qplib_srq->sg_info.umem = umem; 2191 qplib_srq->sg_info.pgsize = PAGE_SIZE; 2192 qplib_srq->sg_info.pgshft = PAGE_SHIFT; 2193 qplib_srq->srq_handle = ureq.srq_handle; 2194 qplib_srq->dpi = &cntx->dpi; 2195 2196 return 0; 2197 } 2198 2199 int bnxt_re_create_srq(struct ib_srq *ib_srq, 2200 struct ib_srq_init_attr *srq_init_attr, 2201 struct ib_udata *udata) 2202 { 2203 struct bnxt_qplib_dev_attr *dev_attr; 2204 struct bnxt_re_ucontext *uctx; 2205 struct bnxt_re_dev *rdev; 2206 struct bnxt_re_srq *srq; 2207 struct bnxt_re_pd *pd; 2208 struct ib_pd *ib_pd; 2209 u32 active_srqs; 2210 int rc; 2211 2212 ib_pd = ib_srq->pd; 2213 pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 2214 rdev = pd->rdev; 2215 dev_attr = rdev->dev_attr; 2216 srq = container_of(ib_srq, struct bnxt_re_srq, ib_srq); 2217 2218 if (srq_init_attr->attr.max_wr >= dev_attr->max_srq_wqes) { 2219 ibdev_err(&rdev->ibdev, "Create CQ failed - max exceeded"); 2220 rc = -EINVAL; 2221 goto exit; 2222 } 2223 2224 if (srq_init_attr->srq_type != IB_SRQT_BASIC) { 2225 rc = -EOPNOTSUPP; 2226 goto exit; 2227 } 2228 2229 uctx = rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx); 2230 srq->rdev = rdev; 2231 srq->qplib_srq.pd = &pd->qplib_pd; 2232 srq->qplib_srq.dpi = &rdev->dpi_privileged; 2233 /* Allocate 1 more than what's provided so posting max doesn't 2234 * mean empty 2235 */ 2236 srq->qplib_srq.max_wqe = 2237 bnxt_re_init_depth(srq_init_attr->attr.max_wr + 1, 2238 dev_attr->max_srq_wqes + 1, uctx); 2239 2240 srq->qplib_srq.max_sge = srq_init_attr->attr.max_sge; 2241 /* 128 byte wqe size for SRQ . So use max sges */ 2242 srq->qplib_srq.wqe_size = bnxt_re_get_rwqe_size(dev_attr->max_srq_sges); 2243 srq->qplib_srq.threshold = srq_init_attr->attr.srq_limit; 2244 srq->srq_limit = srq_init_attr->attr.srq_limit; 2245 srq->qplib_srq.eventq_hw_ring_id = rdev->nqr->nq[0].ring_id; 2246 srq->qplib_srq.sg_info.pgsize = PAGE_SIZE; 2247 srq->qplib_srq.sg_info.pgshft = PAGE_SHIFT; 2248 2249 if (udata) { 2250 rc = bnxt_re_init_user_srq(rdev, pd, srq, udata); 2251 if (rc) 2252 goto fail; 2253 } 2254 2255 rc = bnxt_qplib_create_srq(&rdev->qplib_res, &srq->qplib_srq); 2256 if (rc) { 2257 ibdev_err(&rdev->ibdev, "Create HW SRQ failed!"); 2258 goto fail; 2259 } 2260 2261 if (udata) { 2262 struct bnxt_re_srq_resp resp = {}; 2263 2264 resp.srqid = srq->qplib_srq.id; 2265 if (rdev->chip_ctx->modes.toggle_bits & BNXT_QPLIB_SRQ_TOGGLE_BIT) { 2266 hash_add(rdev->srq_hash, &srq->hash_entry, srq->qplib_srq.id); 2267 srq->uctx_srq_page = (void *)get_zeroed_page(GFP_KERNEL); 2268 if (!srq->uctx_srq_page) { 2269 rc = -ENOMEM; 2270 goto fail; 2271 } 2272 resp.comp_mask |= BNXT_RE_SRQ_TOGGLE_PAGE_SUPPORT; 2273 } 2274 rc = ib_respond_udata(udata, resp); 2275 if (rc) { 2276 bnxt_qplib_destroy_srq(&rdev->qplib_res, 2277 &srq->qplib_srq); 2278 goto fail; 2279 } 2280 } 2281 active_srqs = atomic_inc_return(&rdev->stats.res.srq_count); 2282 if (active_srqs > rdev->stats.res.srq_watermark) 2283 rdev->stats.res.srq_watermark = active_srqs; 2284 spin_lock_init(&srq->lock); 2285 2286 return 0; 2287 2288 fail: 2289 ib_umem_release(srq->umem); 2290 exit: 2291 return rc; 2292 } 2293 2294 int bnxt_re_modify_srq(struct ib_srq *ib_srq, struct ib_srq_attr *srq_attr, 2295 enum ib_srq_attr_mask srq_attr_mask, 2296 struct ib_udata *udata) 2297 { 2298 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq, 2299 ib_srq); 2300 struct bnxt_re_dev *rdev = srq->rdev; 2301 int ret; 2302 2303 ret = ib_is_udata_in_empty(udata); 2304 if (ret) 2305 return ret; 2306 2307 switch (srq_attr_mask) { 2308 case IB_SRQ_MAX_WR: 2309 /* SRQ resize is not supported */ 2310 return -EINVAL; 2311 case IB_SRQ_LIMIT: 2312 /* Change the SRQ threshold */ 2313 if (srq_attr->srq_limit > srq->qplib_srq.max_wqe) 2314 return -EINVAL; 2315 2316 srq->qplib_srq.threshold = srq_attr->srq_limit; 2317 bnxt_qplib_srq_arm_db(&srq->qplib_srq.dbinfo, srq->qplib_srq.threshold); 2318 2319 /* On success, update the shadow */ 2320 srq->srq_limit = srq_attr->srq_limit; 2321 /* No need to Build and send response back to udata */ 2322 return ib_respond_empty_udata(udata); 2323 default: 2324 ibdev_err(&rdev->ibdev, 2325 "Unsupported srq_attr_mask 0x%x", srq_attr_mask); 2326 return -EINVAL; 2327 } 2328 } 2329 2330 int bnxt_re_query_srq(struct ib_srq *ib_srq, struct ib_srq_attr *srq_attr) 2331 { 2332 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq, 2333 ib_srq); 2334 struct bnxt_re_srq tsrq; 2335 struct bnxt_re_dev *rdev = srq->rdev; 2336 int rc; 2337 2338 /* Get live SRQ attr */ 2339 tsrq.qplib_srq.id = srq->qplib_srq.id; 2340 rc = bnxt_qplib_query_srq(&rdev->qplib_res, &tsrq.qplib_srq); 2341 if (rc) { 2342 ibdev_err(&rdev->ibdev, "Query HW SRQ failed!"); 2343 return rc; 2344 } 2345 srq_attr->max_wr = srq->qplib_srq.max_wqe; 2346 srq_attr->max_sge = srq->qplib_srq.max_sge; 2347 srq_attr->srq_limit = tsrq.qplib_srq.threshold; 2348 2349 return 0; 2350 } 2351 2352 int bnxt_re_post_srq_recv(struct ib_srq *ib_srq, const struct ib_recv_wr *wr, 2353 const struct ib_recv_wr **bad_wr) 2354 { 2355 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq, 2356 ib_srq); 2357 struct bnxt_qplib_swqe wqe; 2358 unsigned long flags; 2359 int rc = 0; 2360 2361 spin_lock_irqsave(&srq->lock, flags); 2362 while (wr) { 2363 /* Transcribe each ib_recv_wr to qplib_swqe */ 2364 wqe.num_sge = wr->num_sge; 2365 bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, wr->num_sge); 2366 wqe.wr_id = wr->wr_id; 2367 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV; 2368 2369 rc = bnxt_qplib_post_srq_recv(&srq->qplib_srq, &wqe); 2370 if (rc) { 2371 *bad_wr = wr; 2372 break; 2373 } 2374 wr = wr->next; 2375 } 2376 spin_unlock_irqrestore(&srq->lock, flags); 2377 2378 return rc; 2379 } 2380 static int bnxt_re_modify_shadow_qp(struct bnxt_re_dev *rdev, 2381 struct bnxt_re_qp *qp1_qp, 2382 int qp_attr_mask) 2383 { 2384 struct bnxt_re_qp *qp = rdev->gsi_ctx.gsi_sqp; 2385 int rc; 2386 2387 if (qp_attr_mask & IB_QP_STATE) { 2388 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_STATE; 2389 qp->qplib_qp.state = qp1_qp->qplib_qp.state; 2390 } 2391 if (qp_attr_mask & IB_QP_PKEY_INDEX) { 2392 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PKEY; 2393 qp->qplib_qp.pkey_index = qp1_qp->qplib_qp.pkey_index; 2394 } 2395 2396 if (qp_attr_mask & IB_QP_QKEY) { 2397 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_QKEY; 2398 /* Using a Random QKEY */ 2399 qp->qplib_qp.qkey = 0x81818181; 2400 } 2401 if (qp_attr_mask & IB_QP_SQ_PSN) { 2402 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN; 2403 qp->qplib_qp.sq.psn = qp1_qp->qplib_qp.sq.psn; 2404 } 2405 2406 rc = bnxt_qplib_modify_qp(&rdev->qplib_res, &qp->qplib_qp); 2407 if (rc) 2408 ibdev_err(&rdev->ibdev, "Failed to modify Shadow QP for QP1"); 2409 return rc; 2410 } 2411 2412 static bool bnxt_re_is_modify_ok(enum ib_qp_attr_mask ext_mask, 2413 enum ib_qp_type type, enum ib_qp_state cur, 2414 enum ib_qp_state next) 2415 { 2416 if (!ext_mask) 2417 return true; 2418 2419 if (ext_mask & ~IB_QP_RATE_LIMIT) 2420 return false; 2421 2422 /* Rate limit is only supported for RC QPs during specific transitions */ 2423 return type == IB_QPT_RC && 2424 ((cur == IB_QPS_INIT && next == IB_QPS_RTR) || 2425 (cur == IB_QPS_RTR && next == IB_QPS_RTS) || 2426 (cur == IB_QPS_RTS && next == IB_QPS_RTS)); 2427 } 2428 2429 int bnxt_re_modify_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr, 2430 int qp_attr_mask, struct ib_udata *udata) 2431 { 2432 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 2433 struct bnxt_re_dev *rdev = qp->rdev; 2434 struct bnxt_qplib_dev_attr *dev_attr = rdev->dev_attr; 2435 enum ib_qp_state curr_qp_state, new_qp_state; 2436 int rc; 2437 unsigned int flags; 2438 u8 nw_type; 2439 2440 rc = ib_is_udata_in_empty(udata); 2441 if (rc) 2442 return rc; 2443 2444 if (qp_attr_mask & ~(IB_QP_ATTR_STANDARD_BITS | IB_QP_RATE_LIMIT)) 2445 return -EOPNOTSUPP; 2446 2447 qp->qplib_qp.modify_flags = 0; 2448 qp->qplib_qp.ext_modify_flags = 0; 2449 if (qp_attr_mask & IB_QP_STATE) { 2450 curr_qp_state = __to_ib_qp_state(qp->qplib_qp.cur_qp_state); 2451 new_qp_state = qp_attr->qp_state; 2452 if (!ib_modify_qp_is_ok(curr_qp_state, new_qp_state, 2453 ib_qp->qp_type, qp_attr_mask) || 2454 !bnxt_re_is_modify_ok(qp_attr_mask & ~IB_QP_ATTR_STANDARD_BITS, 2455 ib_qp->qp_type, curr_qp_state, 2456 new_qp_state)) { 2457 ibdev_err(&rdev->ibdev, 2458 "Invalid attribute mask: %#x specified ", 2459 qp_attr_mask); 2460 ibdev_err(&rdev->ibdev, 2461 "for qpn: %#x type: %#x", 2462 ib_qp->qp_num, ib_qp->qp_type); 2463 ibdev_err(&rdev->ibdev, 2464 "curr_qp_state=0x%x, new_qp_state=0x%x\n", 2465 curr_qp_state, new_qp_state); 2466 return -EINVAL; 2467 } 2468 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_STATE; 2469 qp->qplib_qp.state = __from_ib_qp_state(qp_attr->qp_state); 2470 2471 if (!qp->sumem && 2472 qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_ERR) { 2473 ibdev_dbg(&rdev->ibdev, 2474 "Move QP = %p to flush list\n", qp); 2475 flags = bnxt_re_lock_cqs(qp); 2476 bnxt_qplib_add_flush_qp(&qp->qplib_qp); 2477 bnxt_re_unlock_cqs(qp, flags); 2478 } 2479 if (!qp->sumem && 2480 qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_RESET) { 2481 ibdev_dbg(&rdev->ibdev, 2482 "Move QP = %p out of flush list\n", qp); 2483 flags = bnxt_re_lock_cqs(qp); 2484 bnxt_qplib_clean_qp(&qp->qplib_qp); 2485 bnxt_re_unlock_cqs(qp, flags); 2486 } 2487 } 2488 2489 if (qp_attr_mask & IB_QP_RATE_LIMIT) { 2490 if (qp->qplib_qp.type != IB_QPT_RC || 2491 !_is_modify_qp_rate_limit_supported(dev_attr->dev_cap_flags2)) 2492 return -EOPNOTSUPP; 2493 qp->qplib_qp.ext_modify_flags |= 2494 CMDQ_MODIFY_QP_EXT_MODIFY_MASK_RATE_LIMIT_VALID; 2495 qp->qplib_qp.rate_limit = qp_attr->rate_limit; 2496 } 2497 if (qp_attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY) { 2498 qp->qplib_qp.modify_flags |= 2499 CMDQ_MODIFY_QP_MODIFY_MASK_EN_SQD_ASYNC_NOTIFY; 2500 qp->qplib_qp.en_sqd_async_notify = true; 2501 } 2502 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) { 2503 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_ACCESS; 2504 qp->qplib_qp.access = 2505 __qp_access_flags_from_ib(qp->qplib_qp.cctx, 2506 qp_attr->qp_access_flags); 2507 /* LOCAL_WRITE access must be set to allow RC receive */ 2508 qp->qplib_qp.access |= CMDQ_MODIFY_QP_ACCESS_LOCAL_WRITE; 2509 } 2510 if (qp_attr_mask & IB_QP_PKEY_INDEX) { 2511 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PKEY; 2512 qp->qplib_qp.pkey_index = qp_attr->pkey_index; 2513 } 2514 if (qp_attr_mask & IB_QP_QKEY) { 2515 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_QKEY; 2516 qp->qplib_qp.qkey = qp_attr->qkey; 2517 } 2518 if (qp_attr_mask & IB_QP_AV) { 2519 const struct ib_global_route *grh = 2520 rdma_ah_read_grh(&qp_attr->ah_attr); 2521 const struct ib_gid_attr *sgid_attr; 2522 struct bnxt_re_gid_ctx *ctx; 2523 2524 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_DGID | 2525 CMDQ_MODIFY_QP_MODIFY_MASK_FLOW_LABEL | 2526 CMDQ_MODIFY_QP_MODIFY_MASK_SGID_INDEX | 2527 CMDQ_MODIFY_QP_MODIFY_MASK_HOP_LIMIT | 2528 CMDQ_MODIFY_QP_MODIFY_MASK_TRAFFIC_CLASS | 2529 CMDQ_MODIFY_QP_MODIFY_MASK_DEST_MAC | 2530 CMDQ_MODIFY_QP_MODIFY_MASK_VLAN_ID; 2531 memcpy(qp->qplib_qp.ah.dgid.data, grh->dgid.raw, 2532 sizeof(qp->qplib_qp.ah.dgid.data)); 2533 qp->qplib_qp.ah.flow_label = grh->flow_label; 2534 sgid_attr = grh->sgid_attr; 2535 /* Get the HW context of the GID. The reference 2536 * of GID table entry is already taken by the caller. 2537 */ 2538 ctx = rdma_read_gid_hw_context(sgid_attr); 2539 qp->qplib_qp.ah.sgid_index = ctx->idx; 2540 qp->qplib_qp.ah.host_sgid_index = grh->sgid_index; 2541 qp->qplib_qp.ah.hop_limit = grh->hop_limit; 2542 qp->qplib_qp.ah.traffic_class = grh->traffic_class >> 2; 2543 qp->qplib_qp.ah.sl = rdma_ah_get_sl(&qp_attr->ah_attr); 2544 ether_addr_copy(qp->qplib_qp.ah.dmac, 2545 qp_attr->ah_attr.roce.dmac); 2546 2547 rc = rdma_read_gid_l2_fields(sgid_attr, NULL, 2548 &qp->qplib_qp.smac[0]); 2549 if (rc) 2550 return rc; 2551 2552 nw_type = rdma_gid_attr_network_type(sgid_attr); 2553 switch (nw_type) { 2554 case RDMA_NETWORK_IPV4: 2555 qp->qplib_qp.nw_type = 2556 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV4; 2557 break; 2558 case RDMA_NETWORK_IPV6: 2559 qp->qplib_qp.nw_type = 2560 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV6; 2561 break; 2562 default: 2563 qp->qplib_qp.nw_type = 2564 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV1; 2565 break; 2566 } 2567 } 2568 2569 if (qp_attr->qp_state == IB_QPS_RTR) { 2570 enum ib_mtu qpmtu; 2571 2572 qpmtu = iboe_get_mtu(rdev->netdev->mtu); 2573 if (qp_attr_mask & IB_QP_PATH_MTU) { 2574 if (ib_mtu_enum_to_int(qp_attr->path_mtu) > 2575 ib_mtu_enum_to_int(qpmtu)) 2576 return -EINVAL; 2577 qpmtu = qp_attr->path_mtu; 2578 } 2579 2580 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU; 2581 qp->qplib_qp.path_mtu = __from_ib_mtu(qpmtu); 2582 qp->qplib_qp.mtu = ib_mtu_enum_to_int(qpmtu); 2583 } 2584 2585 if (qp_attr_mask & IB_QP_TIMEOUT) { 2586 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_TIMEOUT; 2587 qp->qplib_qp.timeout = qp_attr->timeout; 2588 } 2589 if (qp_attr_mask & IB_QP_RETRY_CNT) { 2590 qp->qplib_qp.modify_flags |= 2591 CMDQ_MODIFY_QP_MODIFY_MASK_RETRY_CNT; 2592 qp->qplib_qp.retry_cnt = qp_attr->retry_cnt; 2593 } 2594 if (qp_attr_mask & IB_QP_RNR_RETRY) { 2595 qp->qplib_qp.modify_flags |= 2596 CMDQ_MODIFY_QP_MODIFY_MASK_RNR_RETRY; 2597 qp->qplib_qp.rnr_retry = qp_attr->rnr_retry; 2598 } 2599 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER) { 2600 qp->qplib_qp.modify_flags |= 2601 CMDQ_MODIFY_QP_MODIFY_MASK_MIN_RNR_TIMER; 2602 qp->qplib_qp.min_rnr_timer = qp_attr->min_rnr_timer; 2603 } 2604 if (qp_attr_mask & IB_QP_RQ_PSN) { 2605 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_RQ_PSN; 2606 qp->qplib_qp.rq.psn = qp_attr->rq_psn; 2607 } 2608 if (qp_attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { 2609 qp->qplib_qp.modify_flags |= 2610 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_RD_ATOMIC; 2611 /* Cap the max_rd_atomic to device max */ 2612 qp->qplib_qp.max_rd_atomic = min_t(u32, qp_attr->max_rd_atomic, 2613 dev_attr->max_qp_rd_atom); 2614 } 2615 if (qp_attr_mask & IB_QP_SQ_PSN) { 2616 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN; 2617 qp->qplib_qp.sq.psn = qp_attr->sq_psn; 2618 } 2619 if (qp_attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { 2620 if (qp_attr->max_dest_rd_atomic > 2621 dev_attr->max_qp_init_rd_atom) { 2622 ibdev_err(&rdev->ibdev, 2623 "max_dest_rd_atomic requested%d is > dev_max%d", 2624 qp_attr->max_dest_rd_atomic, 2625 dev_attr->max_qp_init_rd_atom); 2626 return -EINVAL; 2627 } 2628 2629 qp->qplib_qp.modify_flags |= 2630 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_DEST_RD_ATOMIC; 2631 qp->qplib_qp.max_dest_rd_atomic = qp_attr->max_dest_rd_atomic; 2632 } 2633 if (qp_attr_mask & IB_QP_CAP) { 2634 struct bnxt_re_ucontext *uctx = 2635 rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx); 2636 2637 qp->qplib_qp.modify_flags |= 2638 CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SIZE | 2639 CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SIZE | 2640 CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SGE | 2641 CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SGE | 2642 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_INLINE_DATA; 2643 if ((qp_attr->cap.max_send_wr >= dev_attr->max_qp_wqes) || 2644 (qp_attr->cap.max_recv_wr >= dev_attr->max_qp_wqes) || 2645 (qp_attr->cap.max_send_sge >= dev_attr->max_qp_sges) || 2646 (qp_attr->cap.max_recv_sge >= dev_attr->max_qp_sges) || 2647 (qp_attr->cap.max_inline_data >= 2648 dev_attr->max_inline_data)) { 2649 ibdev_err(&rdev->ibdev, 2650 "Create QP failed - max exceeded"); 2651 return -EINVAL; 2652 } 2653 qp->qplib_qp.sq.max_wqe = 2654 bnxt_re_init_depth(qp_attr->cap.max_send_wr, 2655 dev_attr->max_qp_wqes + 1, uctx); 2656 qp->qplib_qp.sq.q_full_delta = qp->qplib_qp.sq.max_wqe - 2657 qp_attr->cap.max_send_wr; 2658 /* 2659 * Reserving one slot for Phantom WQE. Some application can 2660 * post one extra entry in this case. Allowing this to avoid 2661 * unexpected Queue full condition 2662 */ 2663 qp->qplib_qp.sq.q_full_delta -= 1; 2664 qp->qplib_qp.sq.max_sge = qp_attr->cap.max_send_sge; 2665 if (qp->qplib_qp.rq.max_wqe) { 2666 qp->qplib_qp.rq.max_wqe = bnxt_re_init_depth( 2667 qp_attr->cap.max_recv_wr, 2668 dev_attr->max_qp_wqes + 1, uctx); 2669 qp->qplib_qp.rq.max_sw_wqe = qp->qplib_qp.rq.max_wqe; 2670 qp->qplib_qp.rq.q_full_delta = qp->qplib_qp.rq.max_wqe - 2671 qp_attr->cap.max_recv_wr; 2672 qp->qplib_qp.rq.max_sge = qp_attr->cap.max_recv_sge; 2673 } else { 2674 /* SRQ was used prior, just ignore the RQ caps */ 2675 } 2676 } 2677 if (qp_attr_mask & IB_QP_DEST_QPN) { 2678 qp->qplib_qp.modify_flags |= 2679 CMDQ_MODIFY_QP_MODIFY_MASK_DEST_QP_ID; 2680 qp->qplib_qp.dest_qpn = qp_attr->dest_qp_num; 2681 } 2682 rc = bnxt_qplib_modify_qp(&rdev->qplib_res, &qp->qplib_qp); 2683 if (rc) { 2684 ibdev_err(&rdev->ibdev, "Failed to modify HW QP"); 2685 return rc; 2686 } 2687 if (ib_qp->qp_type == IB_QPT_GSI && rdev->gsi_ctx.gsi_sqp) { 2688 rc = bnxt_re_modify_shadow_qp(rdev, qp, qp_attr_mask); 2689 if (rc) 2690 return rc; 2691 } 2692 return ib_respond_empty_udata(udata); 2693 } 2694 2695 int bnxt_re_query_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr, 2696 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr) 2697 { 2698 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 2699 struct bnxt_re_dev *rdev = qp->rdev; 2700 struct bnxt_qplib_qp *qplib_qp; 2701 int rc; 2702 2703 qplib_qp = kzalloc_obj(*qplib_qp); 2704 if (!qplib_qp) 2705 return -ENOMEM; 2706 2707 qplib_qp->id = qp->qplib_qp.id; 2708 qplib_qp->ah.host_sgid_index = qp->qplib_qp.ah.host_sgid_index; 2709 2710 rc = bnxt_qplib_query_qp(&rdev->qplib_res, qplib_qp); 2711 if (rc) { 2712 ibdev_err(&rdev->ibdev, "Failed to query HW QP"); 2713 goto out; 2714 } 2715 qp_attr->qp_state = __to_ib_qp_state(qplib_qp->state); 2716 qp_attr->cur_qp_state = __to_ib_qp_state(qplib_qp->cur_qp_state); 2717 qp_attr->en_sqd_async_notify = qplib_qp->en_sqd_async_notify ? 1 : 0; 2718 qp_attr->qp_access_flags = __qp_access_flags_to_ib(qp->qplib_qp.cctx, 2719 qplib_qp->access); 2720 qp_attr->pkey_index = qplib_qp->pkey_index; 2721 qp_attr->qkey = qplib_qp->qkey; 2722 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE; 2723 rdma_ah_set_grh(&qp_attr->ah_attr, NULL, qplib_qp->udp_sport, 2724 qplib_qp->ah.host_sgid_index, 2725 qplib_qp->ah.hop_limit, 2726 qplib_qp->ah.traffic_class); 2727 rdma_ah_set_dgid_raw(&qp_attr->ah_attr, qplib_qp->ah.dgid.data); 2728 rdma_ah_set_sl(&qp_attr->ah_attr, qplib_qp->ah.sl); 2729 ether_addr_copy(qp_attr->ah_attr.roce.dmac, qplib_qp->ah.dmac); 2730 qp_attr->path_mtu = __to_ib_mtu(qplib_qp->path_mtu); 2731 qp_attr->timeout = qplib_qp->timeout; 2732 qp_attr->retry_cnt = qplib_qp->retry_cnt; 2733 qp_attr->rnr_retry = qplib_qp->rnr_retry; 2734 qp_attr->min_rnr_timer = qplib_qp->min_rnr_timer; 2735 qp_attr->port_num = __to_ib_port_num(qplib_qp->port_id); 2736 qp_attr->rq_psn = qplib_qp->rq.psn; 2737 qp_attr->max_rd_atomic = qplib_qp->max_rd_atomic; 2738 qp_attr->sq_psn = qplib_qp->sq.psn; 2739 qp_attr->max_dest_rd_atomic = qplib_qp->max_dest_rd_atomic; 2740 qp_init_attr->sq_sig_type = qplib_qp->sig_type ? IB_SIGNAL_ALL_WR : 2741 IB_SIGNAL_REQ_WR; 2742 qp_attr->dest_qp_num = qplib_qp->dest_qpn; 2743 2744 qp_attr->cap.max_send_wr = qp->qplib_qp.sq.max_wqe; 2745 qp_attr->cap.max_send_sge = qp->qplib_qp.sq.max_sge; 2746 qp_attr->cap.max_recv_wr = qp->qplib_qp.rq.max_wqe; 2747 qp_attr->cap.max_recv_sge = qp->qplib_qp.rq.max_sge; 2748 qp_attr->cap.max_inline_data = qp->qplib_qp.max_inline_data; 2749 qp_init_attr->cap = qp_attr->cap; 2750 2751 out: 2752 kfree(qplib_qp); 2753 return rc; 2754 } 2755 2756 /* Routine for sending QP1 packets for RoCE V1 an V2 2757 */ 2758 static int bnxt_re_build_qp1_send_v2(struct bnxt_re_qp *qp, 2759 const struct ib_send_wr *wr, 2760 struct bnxt_qplib_swqe *wqe, 2761 int payload_size) 2762 { 2763 struct bnxt_re_ah *ah = container_of(ud_wr(wr)->ah, struct bnxt_re_ah, 2764 ib_ah); 2765 struct bnxt_qplib_ah *qplib_ah = &ah->qplib_ah; 2766 const struct ib_gid_attr *sgid_attr = ah->ib_ah.sgid_attr; 2767 struct bnxt_qplib_sge sge; 2768 u8 nw_type; 2769 u16 ether_type; 2770 union ib_gid dgid; 2771 bool is_eth = false; 2772 bool is_vlan = false; 2773 bool is_grh = false; 2774 bool is_udp = false; 2775 u8 ip_version = 0; 2776 u16 vlan_id = 0xFFFF; 2777 void *buf; 2778 int i, rc; 2779 2780 memset(&qp->qp1_hdr, 0, sizeof(qp->qp1_hdr)); 2781 2782 rc = rdma_read_gid_l2_fields(sgid_attr, &vlan_id, NULL); 2783 if (rc) 2784 return rc; 2785 2786 /* Get network header type for this GID */ 2787 nw_type = rdma_gid_attr_network_type(sgid_attr); 2788 switch (nw_type) { 2789 case RDMA_NETWORK_IPV4: 2790 nw_type = BNXT_RE_ROCEV2_IPV4_PACKET; 2791 break; 2792 case RDMA_NETWORK_IPV6: 2793 nw_type = BNXT_RE_ROCEV2_IPV6_PACKET; 2794 break; 2795 default: 2796 nw_type = BNXT_RE_ROCE_V1_PACKET; 2797 break; 2798 } 2799 memcpy(&dgid.raw, &qplib_ah->dgid, 16); 2800 is_udp = sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP; 2801 if (is_udp) { 2802 if (ipv6_addr_v4mapped((struct in6_addr *)&sgid_attr->gid)) { 2803 ip_version = 4; 2804 ether_type = ETH_P_IP; 2805 } else { 2806 ip_version = 6; 2807 ether_type = ETH_P_IPV6; 2808 } 2809 is_grh = false; 2810 } else { 2811 ether_type = ETH_P_IBOE; 2812 is_grh = true; 2813 } 2814 2815 is_eth = true; 2816 is_vlan = vlan_id && (vlan_id < 0x1000); 2817 2818 ib_ud_header_init(payload_size, !is_eth, is_eth, is_vlan, is_grh, 2819 ip_version, is_udp, 0, &qp->qp1_hdr); 2820 2821 /* ETH */ 2822 ether_addr_copy(qp->qp1_hdr.eth.dmac_h, ah->qplib_ah.dmac); 2823 ether_addr_copy(qp->qp1_hdr.eth.smac_h, qp->qplib_qp.smac); 2824 2825 /* For vlan, check the sgid for vlan existence */ 2826 2827 if (!is_vlan) { 2828 qp->qp1_hdr.eth.type = cpu_to_be16(ether_type); 2829 } else { 2830 qp->qp1_hdr.vlan.type = cpu_to_be16(ether_type); 2831 qp->qp1_hdr.vlan.tag = cpu_to_be16(vlan_id); 2832 } 2833 2834 if (is_grh || (ip_version == 6)) { 2835 memcpy(qp->qp1_hdr.grh.source_gid.raw, sgid_attr->gid.raw, 2836 sizeof(sgid_attr->gid)); 2837 memcpy(qp->qp1_hdr.grh.destination_gid.raw, qplib_ah->dgid.data, 2838 sizeof(sgid_attr->gid)); 2839 qp->qp1_hdr.grh.hop_limit = qplib_ah->hop_limit; 2840 } 2841 2842 if (ip_version == 4) { 2843 qp->qp1_hdr.ip4.tos = 0; 2844 qp->qp1_hdr.ip4.id = 0; 2845 qp->qp1_hdr.ip4.frag_off = htons(IP_DF); 2846 qp->qp1_hdr.ip4.ttl = qplib_ah->hop_limit; 2847 2848 memcpy(&qp->qp1_hdr.ip4.saddr, sgid_attr->gid.raw + 12, 4); 2849 memcpy(&qp->qp1_hdr.ip4.daddr, qplib_ah->dgid.data + 12, 4); 2850 qp->qp1_hdr.ip4.check = ib_ud_ip4_csum(&qp->qp1_hdr); 2851 } 2852 2853 if (is_udp) { 2854 qp->qp1_hdr.udp.dport = htons(ROCE_V2_UDP_DPORT); 2855 qp->qp1_hdr.udp.sport = htons(0x8CD1); 2856 qp->qp1_hdr.udp.csum = 0; 2857 } 2858 2859 /* BTH */ 2860 if (wr->opcode == IB_WR_SEND_WITH_IMM) { 2861 qp->qp1_hdr.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE; 2862 qp->qp1_hdr.immediate_present = 1; 2863 } else { 2864 qp->qp1_hdr.bth.opcode = IB_OPCODE_UD_SEND_ONLY; 2865 } 2866 if (wr->send_flags & IB_SEND_SOLICITED) 2867 qp->qp1_hdr.bth.solicited_event = 1; 2868 /* pad_count */ 2869 qp->qp1_hdr.bth.pad_count = (4 - payload_size) & 3; 2870 2871 /* P_key for QP1 is for all members */ 2872 qp->qp1_hdr.bth.pkey = cpu_to_be16(0xFFFF); 2873 qp->qp1_hdr.bth.destination_qpn = IB_QP1; 2874 qp->qp1_hdr.bth.ack_req = 0; 2875 qp->send_psn++; 2876 qp->send_psn &= BTH_PSN_MASK; 2877 qp->qp1_hdr.bth.psn = cpu_to_be32(qp->send_psn); 2878 /* DETH */ 2879 /* Use the priviledged Q_Key for QP1 */ 2880 qp->qp1_hdr.deth.qkey = cpu_to_be32(IB_QP1_QKEY); 2881 qp->qp1_hdr.deth.source_qpn = IB_QP1; 2882 2883 /* Pack the QP1 to the transmit buffer */ 2884 buf = bnxt_qplib_get_qp1_sq_buf(&qp->qplib_qp, &sge); 2885 if (buf) { 2886 ib_ud_header_pack(&qp->qp1_hdr, buf); 2887 for (i = wqe->num_sge; i; i--) { 2888 wqe->sg_list[i].addr = wqe->sg_list[i - 1].addr; 2889 wqe->sg_list[i].lkey = wqe->sg_list[i - 1].lkey; 2890 wqe->sg_list[i].size = wqe->sg_list[i - 1].size; 2891 } 2892 2893 /* 2894 * Max Header buf size for IPV6 RoCE V2 is 86, 2895 * which is same as the QP1 SQ header buffer. 2896 * Header buf size for IPV4 RoCE V2 can be 66. 2897 * ETH(14) + VLAN(4)+ IP(20) + UDP (8) + BTH(20). 2898 * Subtract 20 bytes from QP1 SQ header buf size 2899 */ 2900 if (is_udp && ip_version == 4) 2901 sge.size -= 20; 2902 /* 2903 * Max Header buf size for RoCE V1 is 78. 2904 * ETH(14) + VLAN(4) + GRH(40) + BTH(20). 2905 * Subtract 8 bytes from QP1 SQ header buf size 2906 */ 2907 if (!is_udp) 2908 sge.size -= 8; 2909 2910 /* Subtract 4 bytes for non vlan packets */ 2911 if (!is_vlan) 2912 sge.size -= 4; 2913 2914 wqe->sg_list[0].addr = sge.addr; 2915 wqe->sg_list[0].lkey = sge.lkey; 2916 wqe->sg_list[0].size = sge.size; 2917 wqe->num_sge++; 2918 2919 } else { 2920 ibdev_err(&qp->rdev->ibdev, "QP1 buffer is empty!"); 2921 rc = -ENOMEM; 2922 } 2923 return rc; 2924 } 2925 2926 /* For the MAD layer, it only provides the recv SGE the size of 2927 * ib_grh + MAD datagram. No Ethernet headers, Ethertype, BTH, DETH, 2928 * nor RoCE iCRC. The Cu+ solution must provide buffer for the entire 2929 * receive packet (334 bytes) with no VLAN and then copy the GRH 2930 * and the MAD datagram out to the provided SGE. 2931 */ 2932 static int bnxt_re_build_qp1_shadow_qp_recv(struct bnxt_re_qp *qp, 2933 const struct ib_recv_wr *wr, 2934 struct bnxt_qplib_swqe *wqe, 2935 int payload_size) 2936 { 2937 struct bnxt_re_sqp_entries *sqp_entry; 2938 struct bnxt_qplib_sge ref, sge; 2939 struct bnxt_re_dev *rdev; 2940 u32 rq_prod_index; 2941 2942 rdev = qp->rdev; 2943 2944 rq_prod_index = bnxt_qplib_get_rq_prod_index(&qp->qplib_qp); 2945 2946 if (!bnxt_qplib_get_qp1_rq_buf(&qp->qplib_qp, &sge)) 2947 return -ENOMEM; 2948 2949 /* Create 1 SGE to receive the entire 2950 * ethernet packet 2951 */ 2952 /* Save the reference from ULP */ 2953 ref.addr = wqe->sg_list[0].addr; 2954 ref.lkey = wqe->sg_list[0].lkey; 2955 ref.size = wqe->sg_list[0].size; 2956 2957 sqp_entry = &rdev->gsi_ctx.sqp_tbl[rq_prod_index]; 2958 2959 /* SGE 1 */ 2960 wqe->sg_list[0].addr = sge.addr; 2961 wqe->sg_list[0].lkey = sge.lkey; 2962 wqe->sg_list[0].size = BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2; 2963 sge.size -= wqe->sg_list[0].size; 2964 2965 sqp_entry->sge.addr = ref.addr; 2966 sqp_entry->sge.lkey = ref.lkey; 2967 sqp_entry->sge.size = ref.size; 2968 /* Store the wrid for reporting completion */ 2969 sqp_entry->wrid = wqe->wr_id; 2970 /* change the wqe->wrid to table index */ 2971 wqe->wr_id = rq_prod_index; 2972 return 0; 2973 } 2974 2975 static int is_ud_qp(struct bnxt_re_qp *qp) 2976 { 2977 return (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_UD || 2978 qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_GSI); 2979 } 2980 2981 static int bnxt_re_build_send_wqe(struct bnxt_re_qp *qp, 2982 const struct ib_send_wr *wr, 2983 struct bnxt_qplib_swqe *wqe) 2984 { 2985 struct bnxt_re_ah *ah = NULL; 2986 2987 if (is_ud_qp(qp)) { 2988 ah = container_of(ud_wr(wr)->ah, struct bnxt_re_ah, ib_ah); 2989 wqe->send.q_key = ud_wr(wr)->remote_qkey; 2990 wqe->send.dst_qp = ud_wr(wr)->remote_qpn; 2991 wqe->send.avid = ah->qplib_ah.id; 2992 } 2993 switch (wr->opcode) { 2994 case IB_WR_SEND: 2995 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND; 2996 break; 2997 case IB_WR_SEND_WITH_IMM: 2998 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM; 2999 wqe->send.imm_data = be32_to_cpu(wr->ex.imm_data); 3000 break; 3001 case IB_WR_SEND_WITH_INV: 3002 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV; 3003 wqe->send.inv_key = wr->ex.invalidate_rkey; 3004 break; 3005 default: 3006 return -EINVAL; 3007 } 3008 if (wr->send_flags & IB_SEND_SIGNALED) 3009 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 3010 if (wr->send_flags & IB_SEND_FENCE) 3011 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 3012 if (wr->send_flags & IB_SEND_SOLICITED) 3013 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT; 3014 if (wr->send_flags & IB_SEND_INLINE) 3015 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_INLINE; 3016 3017 return 0; 3018 } 3019 3020 static int bnxt_re_build_rdma_wqe(const struct ib_send_wr *wr, 3021 struct bnxt_qplib_swqe *wqe) 3022 { 3023 switch (wr->opcode) { 3024 case IB_WR_RDMA_WRITE: 3025 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE; 3026 break; 3027 case IB_WR_RDMA_WRITE_WITH_IMM: 3028 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM; 3029 wqe->rdma.imm_data = be32_to_cpu(wr->ex.imm_data); 3030 break; 3031 case IB_WR_RDMA_READ: 3032 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_READ; 3033 wqe->rdma.inv_key = wr->ex.invalidate_rkey; 3034 break; 3035 default: 3036 return -EINVAL; 3037 } 3038 wqe->rdma.remote_va = rdma_wr(wr)->remote_addr; 3039 wqe->rdma.r_key = rdma_wr(wr)->rkey; 3040 if (wr->send_flags & IB_SEND_SIGNALED) 3041 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 3042 if (wr->send_flags & IB_SEND_FENCE) 3043 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 3044 if (wr->send_flags & IB_SEND_SOLICITED) 3045 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT; 3046 if (wr->send_flags & IB_SEND_INLINE) 3047 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_INLINE; 3048 3049 return 0; 3050 } 3051 3052 static int bnxt_re_build_atomic_wqe(const struct ib_send_wr *wr, 3053 struct bnxt_qplib_swqe *wqe) 3054 { 3055 switch (wr->opcode) { 3056 case IB_WR_ATOMIC_CMP_AND_SWP: 3057 wqe->type = BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP; 3058 wqe->atomic.cmp_data = atomic_wr(wr)->compare_add; 3059 wqe->atomic.swap_data = atomic_wr(wr)->swap; 3060 break; 3061 case IB_WR_ATOMIC_FETCH_AND_ADD: 3062 wqe->type = BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD; 3063 wqe->atomic.cmp_data = atomic_wr(wr)->compare_add; 3064 break; 3065 default: 3066 return -EINVAL; 3067 } 3068 wqe->atomic.remote_va = atomic_wr(wr)->remote_addr; 3069 wqe->atomic.r_key = atomic_wr(wr)->rkey; 3070 if (wr->send_flags & IB_SEND_SIGNALED) 3071 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 3072 if (wr->send_flags & IB_SEND_FENCE) 3073 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 3074 if (wr->send_flags & IB_SEND_SOLICITED) 3075 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT; 3076 return 0; 3077 } 3078 3079 static int bnxt_re_build_inv_wqe(const struct ib_send_wr *wr, 3080 struct bnxt_qplib_swqe *wqe) 3081 { 3082 wqe->type = BNXT_QPLIB_SWQE_TYPE_LOCAL_INV; 3083 wqe->local_inv.inv_l_key = wr->ex.invalidate_rkey; 3084 3085 if (wr->send_flags & IB_SEND_SIGNALED) 3086 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 3087 if (wr->send_flags & IB_SEND_SOLICITED) 3088 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT; 3089 3090 return 0; 3091 } 3092 3093 static int bnxt_re_build_reg_wqe(const struct ib_reg_wr *wr, 3094 struct bnxt_qplib_swqe *wqe) 3095 { 3096 struct bnxt_re_mr *mr = container_of(wr->mr, struct bnxt_re_mr, ib_mr); 3097 struct bnxt_qplib_frpl *qplib_frpl = &mr->qplib_frpl; 3098 int access = wr->access; 3099 3100 wqe->frmr.pbl_ptr = (__le64 *)qplib_frpl->hwq.pbl_ptr[0]; 3101 wqe->frmr.pbl_dma_ptr = qplib_frpl->hwq.pbl_dma_ptr[0]; 3102 wqe->frmr.page_list = mr->pages; 3103 wqe->frmr.page_list_len = mr->npages; 3104 wqe->frmr.levels = qplib_frpl->hwq.level; 3105 wqe->type = BNXT_QPLIB_SWQE_TYPE_REG_MR; 3106 3107 if (wr->wr.send_flags & IB_SEND_SIGNALED) 3108 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 3109 3110 if (access & IB_ACCESS_LOCAL_WRITE) 3111 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_LOCAL_WRITE; 3112 if (access & IB_ACCESS_REMOTE_READ) 3113 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_READ; 3114 if (access & IB_ACCESS_REMOTE_WRITE) 3115 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_WRITE; 3116 if (access & IB_ACCESS_REMOTE_ATOMIC) 3117 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_ATOMIC; 3118 if (access & IB_ACCESS_MW_BIND) 3119 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_WINDOW_BIND; 3120 3121 wqe->frmr.l_key = wr->key; 3122 wqe->frmr.length = wr->mr->length; 3123 wqe->frmr.pbl_pg_sz_log = ilog2(PAGE_SIZE >> PAGE_SHIFT_4K); 3124 wqe->frmr.pg_sz_log = ilog2(wr->mr->page_size >> PAGE_SHIFT_4K); 3125 wqe->frmr.va = wr->mr->iova; 3126 return 0; 3127 } 3128 3129 static int bnxt_re_copy_inline_data(struct bnxt_re_dev *rdev, 3130 const struct ib_send_wr *wr, 3131 struct bnxt_qplib_swqe *wqe) 3132 { 3133 /* Copy the inline data to the data field */ 3134 u8 *in_data; 3135 u32 i, sge_len; 3136 void *sge_addr; 3137 3138 in_data = wqe->inline_data; 3139 for (i = 0; i < wr->num_sge; i++) { 3140 sge_addr = (void *)(unsigned long) 3141 wr->sg_list[i].addr; 3142 sge_len = wr->sg_list[i].length; 3143 3144 if ((sge_len + wqe->inline_len) > 3145 BNXT_QPLIB_SWQE_MAX_INLINE_LENGTH) { 3146 ibdev_err(&rdev->ibdev, 3147 "Inline data size requested > supported value"); 3148 return -EINVAL; 3149 } 3150 sge_len = wr->sg_list[i].length; 3151 3152 memcpy(in_data, sge_addr, sge_len); 3153 in_data += wr->sg_list[i].length; 3154 wqe->inline_len += wr->sg_list[i].length; 3155 } 3156 return wqe->inline_len; 3157 } 3158 3159 static int bnxt_re_copy_wr_payload(struct bnxt_re_dev *rdev, 3160 const struct ib_send_wr *wr, 3161 struct bnxt_qplib_swqe *wqe) 3162 { 3163 int payload_sz = 0; 3164 3165 if (wr->send_flags & IB_SEND_INLINE) 3166 payload_sz = bnxt_re_copy_inline_data(rdev, wr, wqe); 3167 else 3168 payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe->sg_list, 3169 wqe->num_sge); 3170 3171 return payload_sz; 3172 } 3173 3174 static void bnxt_ud_qp_hw_stall_workaround(struct bnxt_re_qp *qp) 3175 { 3176 if ((qp->ib_qp.qp_type == IB_QPT_UD || 3177 qp->ib_qp.qp_type == IB_QPT_GSI || 3178 qp->ib_qp.qp_type == IB_QPT_RAW_ETHERTYPE) && 3179 qp->qplib_qp.wqe_cnt == BNXT_RE_UD_QP_HW_STALL) { 3180 int qp_attr_mask; 3181 struct ib_qp_attr qp_attr; 3182 3183 qp_attr_mask = IB_QP_STATE; 3184 qp_attr.qp_state = IB_QPS_RTS; 3185 bnxt_re_modify_qp(&qp->ib_qp, &qp_attr, qp_attr_mask, NULL); 3186 qp->qplib_qp.wqe_cnt = 0; 3187 } 3188 } 3189 3190 static int bnxt_re_post_send_shadow_qp(struct bnxt_re_dev *rdev, 3191 struct bnxt_re_qp *qp, 3192 const struct ib_send_wr *wr) 3193 { 3194 int rc = 0, payload_sz = 0; 3195 unsigned long flags; 3196 3197 spin_lock_irqsave(&qp->sq_lock, flags); 3198 while (wr) { 3199 struct bnxt_qplib_swqe wqe = {}; 3200 3201 /* Common */ 3202 wqe.num_sge = wr->num_sge; 3203 if (wr->num_sge > qp->qplib_qp.sq.max_sge) { 3204 ibdev_err(&rdev->ibdev, 3205 "Limit exceeded for Send SGEs"); 3206 rc = -EINVAL; 3207 goto bad; 3208 } 3209 3210 payload_sz = bnxt_re_copy_wr_payload(qp->rdev, wr, &wqe); 3211 if (payload_sz < 0) { 3212 rc = -EINVAL; 3213 goto bad; 3214 } 3215 wqe.wr_id = wr->wr_id; 3216 3217 wqe.type = BNXT_QPLIB_SWQE_TYPE_SEND; 3218 3219 rc = bnxt_re_build_send_wqe(qp, wr, &wqe); 3220 if (!rc) 3221 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe); 3222 bad: 3223 if (rc) { 3224 ibdev_err(&rdev->ibdev, 3225 "Post send failed opcode = %#x rc = %d", 3226 wr->opcode, rc); 3227 break; 3228 } 3229 wr = wr->next; 3230 } 3231 bnxt_qplib_post_send_db(&qp->qplib_qp); 3232 if (!bnxt_qplib_is_chip_gen_p5_p7(qp->rdev->chip_ctx)) 3233 bnxt_ud_qp_hw_stall_workaround(qp); 3234 spin_unlock_irqrestore(&qp->sq_lock, flags); 3235 return rc; 3236 } 3237 3238 static void bnxt_re_legacy_set_uc_fence(struct bnxt_qplib_swqe *wqe) 3239 { 3240 /* Need unconditional fence for non-wire memory opcode 3241 * to work as expected. 3242 */ 3243 if (wqe->type == BNXT_QPLIB_SWQE_TYPE_LOCAL_INV || 3244 wqe->type == BNXT_QPLIB_SWQE_TYPE_FAST_REG_MR || 3245 wqe->type == BNXT_QPLIB_SWQE_TYPE_REG_MR || 3246 wqe->type == BNXT_QPLIB_SWQE_TYPE_BIND_MW) 3247 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 3248 } 3249 3250 int bnxt_re_post_send(struct ib_qp *ib_qp, const struct ib_send_wr *wr, 3251 const struct ib_send_wr **bad_wr) 3252 { 3253 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 3254 struct bnxt_qplib_swqe wqe; 3255 int rc = 0, payload_sz = 0; 3256 unsigned long flags; 3257 3258 spin_lock_irqsave(&qp->sq_lock, flags); 3259 while (wr) { 3260 /* House keeping */ 3261 memset(&wqe, 0, sizeof(wqe)); 3262 3263 /* Common */ 3264 wqe.num_sge = wr->num_sge; 3265 if (wr->num_sge > qp->qplib_qp.sq.max_sge) { 3266 ibdev_err(&qp->rdev->ibdev, 3267 "Limit exceeded for Send SGEs"); 3268 rc = -EINVAL; 3269 goto bad; 3270 } 3271 3272 payload_sz = bnxt_re_copy_wr_payload(qp->rdev, wr, &wqe); 3273 if (payload_sz < 0) { 3274 rc = -EINVAL; 3275 goto bad; 3276 } 3277 wqe.wr_id = wr->wr_id; 3278 3279 switch (wr->opcode) { 3280 case IB_WR_SEND: 3281 case IB_WR_SEND_WITH_IMM: 3282 if (qp->qplib_qp.type == CMDQ_CREATE_QP1_TYPE_GSI) { 3283 rc = bnxt_re_build_qp1_send_v2(qp, wr, &wqe, 3284 payload_sz); 3285 if (rc) 3286 goto bad; 3287 wqe.rawqp1.lflags |= 3288 SQ_SEND_RAWETH_QP1_LFLAGS_ROCE_CRC; 3289 } 3290 if (wr->send_flags & IB_SEND_IP_CSUM) 3291 wqe.rawqp1.lflags |= 3292 SQ_SEND_RAWETH_QP1_LFLAGS_IP_CHKSUM; 3293 fallthrough; 3294 case IB_WR_SEND_WITH_INV: 3295 rc = bnxt_re_build_send_wqe(qp, wr, &wqe); 3296 break; 3297 case IB_WR_RDMA_WRITE: 3298 case IB_WR_RDMA_WRITE_WITH_IMM: 3299 case IB_WR_RDMA_READ: 3300 rc = bnxt_re_build_rdma_wqe(wr, &wqe); 3301 break; 3302 case IB_WR_ATOMIC_CMP_AND_SWP: 3303 case IB_WR_ATOMIC_FETCH_AND_ADD: 3304 rc = bnxt_re_build_atomic_wqe(wr, &wqe); 3305 break; 3306 case IB_WR_RDMA_READ_WITH_INV: 3307 ibdev_err(&qp->rdev->ibdev, 3308 "RDMA Read with Invalidate is not supported"); 3309 rc = -EINVAL; 3310 goto bad; 3311 case IB_WR_LOCAL_INV: 3312 rc = bnxt_re_build_inv_wqe(wr, &wqe); 3313 break; 3314 case IB_WR_REG_MR: 3315 rc = bnxt_re_build_reg_wqe(reg_wr(wr), &wqe); 3316 break; 3317 default: 3318 /* Unsupported WRs */ 3319 ibdev_err(&qp->rdev->ibdev, 3320 "WR (%#x) is not supported", wr->opcode); 3321 rc = -EINVAL; 3322 goto bad; 3323 } 3324 if (!rc) { 3325 if (!bnxt_qplib_is_chip_gen_p5_p7(qp->rdev->chip_ctx)) 3326 bnxt_re_legacy_set_uc_fence(&wqe); 3327 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe); 3328 } 3329 bad: 3330 if (rc) { 3331 ibdev_err(&qp->rdev->ibdev, 3332 "post_send failed op:%#x qps = %#x rc = %d\n", 3333 wr->opcode, qp->qplib_qp.state, rc); 3334 *bad_wr = wr; 3335 break; 3336 } 3337 wr = wr->next; 3338 } 3339 bnxt_qplib_post_send_db(&qp->qplib_qp); 3340 if (!bnxt_qplib_is_chip_gen_p5_p7(qp->rdev->chip_ctx)) 3341 bnxt_ud_qp_hw_stall_workaround(qp); 3342 spin_unlock_irqrestore(&qp->sq_lock, flags); 3343 3344 return rc; 3345 } 3346 3347 static int bnxt_re_post_recv_shadow_qp(struct bnxt_re_dev *rdev, 3348 struct bnxt_re_qp *qp, 3349 const struct ib_recv_wr *wr) 3350 { 3351 struct bnxt_qplib_swqe wqe; 3352 int rc = 0; 3353 3354 while (wr) { 3355 /* House keeping */ 3356 memset(&wqe, 0, sizeof(wqe)); 3357 3358 /* Common */ 3359 wqe.num_sge = wr->num_sge; 3360 if (wr->num_sge > qp->qplib_qp.rq.max_sge) { 3361 ibdev_err(&rdev->ibdev, 3362 "Limit exceeded for Receive SGEs"); 3363 rc = -EINVAL; 3364 break; 3365 } 3366 bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, wr->num_sge); 3367 wqe.wr_id = wr->wr_id; 3368 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV; 3369 3370 rc = bnxt_qplib_post_recv(&qp->qplib_qp, &wqe); 3371 if (rc) 3372 break; 3373 3374 wr = wr->next; 3375 } 3376 if (!rc) 3377 bnxt_qplib_post_recv_db(&qp->qplib_qp); 3378 return rc; 3379 } 3380 3381 int bnxt_re_post_recv(struct ib_qp *ib_qp, const struct ib_recv_wr *wr, 3382 const struct ib_recv_wr **bad_wr) 3383 { 3384 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 3385 struct bnxt_qplib_swqe wqe; 3386 int rc = 0, payload_sz = 0; 3387 unsigned long flags; 3388 u32 count = 0; 3389 3390 spin_lock_irqsave(&qp->rq_lock, flags); 3391 while (wr) { 3392 /* House keeping */ 3393 memset(&wqe, 0, sizeof(wqe)); 3394 3395 /* Common */ 3396 wqe.num_sge = wr->num_sge; 3397 if (wr->num_sge > qp->qplib_qp.rq.max_sge) { 3398 ibdev_err(&qp->rdev->ibdev, 3399 "Limit exceeded for Receive SGEs"); 3400 rc = -EINVAL; 3401 *bad_wr = wr; 3402 break; 3403 } 3404 3405 payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, 3406 wr->num_sge); 3407 wqe.wr_id = wr->wr_id; 3408 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV; 3409 3410 if (ib_qp->qp_type == IB_QPT_GSI && 3411 qp->qplib_qp.type != CMDQ_CREATE_QP_TYPE_GSI) 3412 rc = bnxt_re_build_qp1_shadow_qp_recv(qp, wr, &wqe, 3413 payload_sz); 3414 if (!rc) 3415 rc = bnxt_qplib_post_recv(&qp->qplib_qp, &wqe); 3416 if (rc) { 3417 *bad_wr = wr; 3418 break; 3419 } 3420 3421 /* Ring DB if the RQEs posted reaches a threshold value */ 3422 if (++count >= BNXT_RE_RQ_WQE_THRESHOLD) { 3423 bnxt_qplib_post_recv_db(&qp->qplib_qp); 3424 count = 0; 3425 } 3426 3427 wr = wr->next; 3428 } 3429 3430 if (count) 3431 bnxt_qplib_post_recv_db(&qp->qplib_qp); 3432 3433 spin_unlock_irqrestore(&qp->rq_lock, flags); 3434 3435 return rc; 3436 } 3437 3438 static struct bnxt_qplib_nq *bnxt_re_get_nq(struct bnxt_re_dev *rdev) 3439 { 3440 int min, indx; 3441 3442 mutex_lock(&rdev->nqr->load_lock); 3443 for (indx = 0, min = 0; indx < (rdev->nqr->num_msix - 1); indx++) { 3444 if (rdev->nqr->nq[min].load > rdev->nqr->nq[indx].load) 3445 min = indx; 3446 } 3447 rdev->nqr->nq[min].load++; 3448 mutex_unlock(&rdev->nqr->load_lock); 3449 3450 return &rdev->nqr->nq[min]; 3451 } 3452 3453 static void bnxt_re_put_nq(struct bnxt_re_dev *rdev, struct bnxt_qplib_nq *nq) 3454 { 3455 mutex_lock(&rdev->nqr->load_lock); 3456 nq->load--; 3457 mutex_unlock(&rdev->nqr->load_lock); 3458 } 3459 3460 /* Completion Queues */ 3461 int bnxt_re_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata) 3462 { 3463 struct bnxt_qplib_chip_ctx *cctx; 3464 struct bnxt_qplib_nq *nq; 3465 struct bnxt_re_dev *rdev; 3466 struct bnxt_re_cq *cq; 3467 int ret; 3468 3469 cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq); 3470 rdev = cq->rdev; 3471 nq = cq->qplib_cq.nq; 3472 cctx = rdev->chip_ctx; 3473 3474 ret = ib_is_udata_in_empty(udata); 3475 if (ret) 3476 return ret; 3477 3478 if (cctx->modes.toggle_bits & BNXT_QPLIB_CQ_TOGGLE_BIT) 3479 hash_del(&cq->hash_entry); 3480 bnxt_qplib_destroy_cq(&rdev->qplib_res, &cq->qplib_cq); 3481 if (cctx->modes.toggle_bits & BNXT_QPLIB_CQ_TOGGLE_BIT) 3482 free_page((unsigned long)cq->uctx_cq_page); 3483 3484 bnxt_re_put_nq(rdev, nq); 3485 3486 atomic_dec(&rdev->stats.res.cq_count); 3487 kfree(cq->cql); 3488 ib_umem_release(cq->umem); 3489 return ib_respond_empty_udata(udata); 3490 } 3491 3492 int bnxt_re_create_user_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr, 3493 struct uverbs_attr_bundle *attrs) 3494 { 3495 struct bnxt_re_cq *cq = container_of(ibcq, struct bnxt_re_cq, ib_cq); 3496 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibcq->device, ibdev); 3497 struct ib_udata *udata = &attrs->driver_udata; 3498 struct bnxt_re_ucontext *uctx = 3499 rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx); 3500 struct bnxt_qplib_dev_attr *dev_attr = rdev->dev_attr; 3501 struct bnxt_qplib_chip_ctx *cctx; 3502 struct bnxt_re_cq_resp resp = {}; 3503 struct bnxt_re_cq_req req; 3504 int rc; 3505 u32 active_cqs, entries; 3506 3507 if (attr->flags) 3508 return -EOPNOTSUPP; 3509 3510 /* Validate CQ fields */ 3511 if (attr->cqe > dev_attr->max_cq_wqes) 3512 return -EINVAL; 3513 3514 cq->rdev = rdev; 3515 cctx = rdev->chip_ctx; 3516 cq->qplib_cq.cq_handle = (u64)(unsigned long)(&cq->qplib_cq); 3517 3518 rc = ib_copy_validate_udata_in_cm(udata, req, cq_handle, 3519 BNXT_RE_CQ_FIXED_NUM_CQE_ENABLE); 3520 if (rc) 3521 return rc; 3522 3523 if (req.comp_mask & BNXT_RE_CQ_FIXED_NUM_CQE_ENABLE) 3524 entries = attr->cqe; 3525 else 3526 entries = bnxt_re_init_depth(attr->cqe + 1, 3527 dev_attr->max_cq_wqes + 1, uctx); 3528 3529 cq->umem = ib_umem_get_cq_buf_or_va(&rdev->ibdev, attrs, req.cq_va, 3530 entries * sizeof(struct cq_base), 3531 IB_ACCESS_LOCAL_WRITE); 3532 if (IS_ERR(cq->umem)) 3533 return PTR_ERR(cq->umem); 3534 3535 rc = bnxt_re_setup_sginfo(rdev, cq->umem, &cq->qplib_cq.sg_info); 3536 if (rc) 3537 goto free_umem; 3538 3539 cq->qplib_cq.dpi = &uctx->dpi; 3540 cq->qplib_cq.max_wqe = entries; 3541 cq->qplib_cq.coalescing = &rdev->cq_coalescing; 3542 cq->qplib_cq.nq = bnxt_re_get_nq(rdev); 3543 cq->qplib_cq.cnq_hw_ring_id = cq->qplib_cq.nq->ring_id; 3544 3545 rc = bnxt_qplib_create_cq(&rdev->qplib_res, &cq->qplib_cq); 3546 if (rc) 3547 goto free_umem; 3548 3549 cq->ib_cq.cqe = entries; 3550 cq->cq_period = cq->qplib_cq.period; 3551 active_cqs = atomic_inc_return(&rdev->stats.res.cq_count); 3552 if (active_cqs > rdev->stats.res.cq_watermark) 3553 rdev->stats.res.cq_watermark = active_cqs; 3554 spin_lock_init(&cq->cq_lock); 3555 3556 if (cctx->modes.toggle_bits & BNXT_QPLIB_CQ_TOGGLE_BIT) { 3557 hash_add(rdev->cq_hash, &cq->hash_entry, cq->qplib_cq.id); 3558 /* Allocate a page */ 3559 cq->uctx_cq_page = (void *)get_zeroed_page(GFP_KERNEL); 3560 if (!cq->uctx_cq_page) { 3561 rc = -ENOMEM; 3562 goto destroy_cq; 3563 } 3564 3565 resp.comp_mask |= BNXT_RE_CQ_TOGGLE_PAGE_SUPPORT; 3566 } 3567 resp.cqid = cq->qplib_cq.id; 3568 resp.tail = cq->qplib_cq.hwq.cons; 3569 resp.phase = cq->qplib_cq.period; 3570 rc = ib_respond_udata(udata, resp); 3571 if (rc) 3572 goto free_mem; 3573 3574 return 0; 3575 3576 free_mem: 3577 free_page((unsigned long)cq->uctx_cq_page); 3578 destroy_cq: 3579 bnxt_qplib_destroy_cq(&rdev->qplib_res, &cq->qplib_cq); 3580 free_umem: 3581 ib_umem_release(cq->umem); 3582 return rc; 3583 } 3584 3585 int bnxt_re_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr, 3586 struct uverbs_attr_bundle *attrs) 3587 { 3588 struct bnxt_re_cq *cq = container_of(ibcq, struct bnxt_re_cq, ib_cq); 3589 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibcq->device, ibdev); 3590 struct bnxt_qplib_dev_attr *dev_attr = rdev->dev_attr; 3591 int rc; 3592 u32 active_cqs; 3593 3594 if (attr->flags) 3595 return -EOPNOTSUPP; 3596 3597 /* Validate CQ fields */ 3598 if (attr->cqe > dev_attr->max_cq_wqes) 3599 return -EINVAL; 3600 3601 cq->rdev = rdev; 3602 cq->qplib_cq.cq_handle = (u64)(unsigned long)(&cq->qplib_cq); 3603 3604 cq->max_cql = attr->cqe + 1; 3605 cq->cql = kzalloc_objs(struct bnxt_qplib_cqe, cq->max_cql); 3606 if (!cq->cql) 3607 return -ENOMEM; 3608 3609 cq->qplib_cq.sg_info.pgsize = SZ_4K; 3610 cq->qplib_cq.sg_info.pgshft = __builtin_ctz(SZ_4K); 3611 cq->qplib_cq.dpi = &rdev->dpi_privileged; 3612 cq->qplib_cq.max_wqe = cq->max_cql; 3613 cq->qplib_cq.coalescing = &rdev->cq_coalescing; 3614 cq->qplib_cq.nq = bnxt_re_get_nq(rdev); 3615 cq->qplib_cq.cnq_hw_ring_id = cq->qplib_cq.nq->ring_id; 3616 3617 rc = bnxt_qplib_create_cq(&rdev->qplib_res, &cq->qplib_cq); 3618 if (rc) { 3619 ibdev_err(&rdev->ibdev, "Failed to create HW CQ"); 3620 goto fail; 3621 } 3622 3623 cq->ib_cq.cqe = cq->max_cql; 3624 cq->cq_period = cq->qplib_cq.period; 3625 active_cqs = atomic_inc_return(&rdev->stats.res.cq_count); 3626 if (active_cqs > rdev->stats.res.cq_watermark) 3627 rdev->stats.res.cq_watermark = active_cqs; 3628 spin_lock_init(&cq->cq_lock); 3629 3630 return 0; 3631 3632 fail: 3633 kfree(cq->cql); 3634 return rc; 3635 } 3636 3637 static void bnxt_re_resize_cq_complete(struct bnxt_re_cq *cq) 3638 { 3639 struct bnxt_re_dev *rdev = cq->rdev; 3640 3641 bnxt_qplib_resize_cq_complete(&rdev->qplib_res, &cq->qplib_cq); 3642 3643 cq->qplib_cq.max_wqe = cq->resize_cqe; 3644 if (cq->resize_umem) { 3645 ib_umem_release(cq->umem); 3646 cq->umem = cq->resize_umem; 3647 cq->resize_umem = NULL; 3648 cq->resize_cqe = 0; 3649 } 3650 } 3651 3652 int bnxt_re_resize_cq(struct ib_cq *ibcq, unsigned int cqe, 3653 struct ib_udata *udata) 3654 { 3655 struct bnxt_qplib_sg_info sg_info = {}; 3656 struct bnxt_qplib_dpi *orig_dpi = NULL; 3657 struct bnxt_qplib_dev_attr *dev_attr; 3658 struct bnxt_re_ucontext *uctx = NULL; 3659 struct bnxt_re_resize_cq_req req; 3660 struct bnxt_re_dev *rdev; 3661 struct bnxt_re_cq *cq; 3662 int rc; 3663 u32 entries; 3664 3665 cq = container_of(ibcq, struct bnxt_re_cq, ib_cq); 3666 rdev = cq->rdev; 3667 dev_attr = rdev->dev_attr; 3668 if (!ibcq->uobject) { 3669 ibdev_err(&rdev->ibdev, "Kernel CQ Resize not supported"); 3670 return -EOPNOTSUPP; 3671 } 3672 3673 if (cq->resize_umem) { 3674 ibdev_err(&rdev->ibdev, "Resize CQ %#x failed - Busy", 3675 cq->qplib_cq.id); 3676 return -EBUSY; 3677 } 3678 3679 /* Check the requested cq depth out of supported depth */ 3680 if (cqe > dev_attr->max_cq_wqes) 3681 return -EINVAL; 3682 3683 uctx = rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx); 3684 entries = bnxt_re_init_depth(cqe + 1, dev_attr->max_cq_wqes + 1, uctx); 3685 3686 /* uverbs consumer */ 3687 rc = ib_copy_validate_udata_in(udata, req, cq_va); 3688 if (rc) 3689 goto fail; 3690 3691 cq->resize_umem = ib_umem_get_va(&rdev->ibdev, req.cq_va, 3692 entries * sizeof(struct cq_base), 3693 IB_ACCESS_LOCAL_WRITE); 3694 if (IS_ERR(cq->resize_umem)) { 3695 rc = PTR_ERR(cq->resize_umem); 3696 ibdev_err(&rdev->ibdev, "%s: ib_umem_get_va failed! rc = %pe\n", 3697 __func__, cq->resize_umem); 3698 cq->resize_umem = NULL; 3699 goto fail; 3700 } 3701 cq->resize_cqe = entries; 3702 memcpy(&sg_info, &cq->qplib_cq.sg_info, sizeof(sg_info)); 3703 orig_dpi = cq->qplib_cq.dpi; 3704 3705 cq->qplib_cq.sg_info.umem = cq->resize_umem; 3706 cq->qplib_cq.sg_info.pgsize = PAGE_SIZE; 3707 cq->qplib_cq.sg_info.pgshft = PAGE_SHIFT; 3708 cq->qplib_cq.dpi = &uctx->dpi; 3709 3710 rc = bnxt_qplib_resize_cq(&rdev->qplib_res, &cq->qplib_cq, entries); 3711 if (rc) { 3712 ibdev_err(&rdev->ibdev, "Resize HW CQ %#x failed!", 3713 cq->qplib_cq.id); 3714 goto fail; 3715 } 3716 3717 cq->ib_cq.cqe = cq->resize_cqe; 3718 atomic_inc(&rdev->stats.res.resize_count); 3719 3720 return ib_respond_empty_udata(udata); 3721 3722 fail: 3723 if (cq->resize_umem) { 3724 ib_umem_release(cq->resize_umem); 3725 cq->resize_umem = NULL; 3726 cq->resize_cqe = 0; 3727 memcpy(&cq->qplib_cq.sg_info, &sg_info, sizeof(sg_info)); 3728 cq->qplib_cq.dpi = orig_dpi; 3729 } 3730 return rc; 3731 } 3732 3733 static u8 __req_to_ib_wc_status(u8 qstatus) 3734 { 3735 switch (qstatus) { 3736 case CQ_REQ_STATUS_OK: 3737 return IB_WC_SUCCESS; 3738 case CQ_REQ_STATUS_BAD_RESPONSE_ERR: 3739 return IB_WC_BAD_RESP_ERR; 3740 case CQ_REQ_STATUS_LOCAL_LENGTH_ERR: 3741 return IB_WC_LOC_LEN_ERR; 3742 case CQ_REQ_STATUS_LOCAL_QP_OPERATION_ERR: 3743 return IB_WC_LOC_QP_OP_ERR; 3744 case CQ_REQ_STATUS_LOCAL_PROTECTION_ERR: 3745 return IB_WC_LOC_PROT_ERR; 3746 case CQ_REQ_STATUS_MEMORY_MGT_OPERATION_ERR: 3747 return IB_WC_GENERAL_ERR; 3748 case CQ_REQ_STATUS_REMOTE_INVALID_REQUEST_ERR: 3749 return IB_WC_REM_INV_REQ_ERR; 3750 case CQ_REQ_STATUS_REMOTE_ACCESS_ERR: 3751 return IB_WC_REM_ACCESS_ERR; 3752 case CQ_REQ_STATUS_REMOTE_OPERATION_ERR: 3753 return IB_WC_REM_OP_ERR; 3754 case CQ_REQ_STATUS_RNR_NAK_RETRY_CNT_ERR: 3755 return IB_WC_RNR_RETRY_EXC_ERR; 3756 case CQ_REQ_STATUS_TRANSPORT_RETRY_CNT_ERR: 3757 return IB_WC_RETRY_EXC_ERR; 3758 case CQ_REQ_STATUS_WORK_REQUEST_FLUSHED_ERR: 3759 return IB_WC_WR_FLUSH_ERR; 3760 default: 3761 return IB_WC_GENERAL_ERR; 3762 } 3763 return 0; 3764 } 3765 3766 static u8 __rawqp1_to_ib_wc_status(u8 qstatus) 3767 { 3768 switch (qstatus) { 3769 case CQ_RES_RAWETH_QP1_STATUS_OK: 3770 return IB_WC_SUCCESS; 3771 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_ACCESS_ERROR: 3772 return IB_WC_LOC_ACCESS_ERR; 3773 case CQ_RES_RAWETH_QP1_STATUS_HW_LOCAL_LENGTH_ERR: 3774 return IB_WC_LOC_LEN_ERR; 3775 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_PROTECTION_ERR: 3776 return IB_WC_LOC_PROT_ERR; 3777 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_QP_OPERATION_ERR: 3778 return IB_WC_LOC_QP_OP_ERR; 3779 case CQ_RES_RAWETH_QP1_STATUS_MEMORY_MGT_OPERATION_ERR: 3780 return IB_WC_GENERAL_ERR; 3781 case CQ_RES_RAWETH_QP1_STATUS_WORK_REQUEST_FLUSHED_ERR: 3782 return IB_WC_WR_FLUSH_ERR; 3783 case CQ_RES_RAWETH_QP1_STATUS_HW_FLUSH_ERR: 3784 return IB_WC_WR_FLUSH_ERR; 3785 default: 3786 return IB_WC_GENERAL_ERR; 3787 } 3788 } 3789 3790 static u8 __rc_to_ib_wc_status(u8 qstatus) 3791 { 3792 switch (qstatus) { 3793 case CQ_RES_RC_STATUS_OK: 3794 return IB_WC_SUCCESS; 3795 case CQ_RES_RC_STATUS_LOCAL_ACCESS_ERROR: 3796 return IB_WC_LOC_ACCESS_ERR; 3797 case CQ_RES_RC_STATUS_LOCAL_LENGTH_ERR: 3798 return IB_WC_LOC_LEN_ERR; 3799 case CQ_RES_RC_STATUS_LOCAL_PROTECTION_ERR: 3800 return IB_WC_LOC_PROT_ERR; 3801 case CQ_RES_RC_STATUS_LOCAL_QP_OPERATION_ERR: 3802 return IB_WC_LOC_QP_OP_ERR; 3803 case CQ_RES_RC_STATUS_MEMORY_MGT_OPERATION_ERR: 3804 return IB_WC_GENERAL_ERR; 3805 case CQ_RES_RC_STATUS_REMOTE_INVALID_REQUEST_ERR: 3806 return IB_WC_REM_INV_REQ_ERR; 3807 case CQ_RES_RC_STATUS_WORK_REQUEST_FLUSHED_ERR: 3808 return IB_WC_WR_FLUSH_ERR; 3809 case CQ_RES_RC_STATUS_HW_FLUSH_ERR: 3810 return IB_WC_WR_FLUSH_ERR; 3811 default: 3812 return IB_WC_GENERAL_ERR; 3813 } 3814 } 3815 3816 static void bnxt_re_process_req_wc(struct ib_wc *wc, struct bnxt_qplib_cqe *cqe) 3817 { 3818 switch (cqe->type) { 3819 case BNXT_QPLIB_SWQE_TYPE_SEND: 3820 wc->opcode = IB_WC_SEND; 3821 break; 3822 case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM: 3823 wc->opcode = IB_WC_SEND; 3824 wc->wc_flags |= IB_WC_WITH_IMM; 3825 break; 3826 case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV: 3827 wc->opcode = IB_WC_SEND; 3828 wc->wc_flags |= IB_WC_WITH_INVALIDATE; 3829 break; 3830 case BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE: 3831 wc->opcode = IB_WC_RDMA_WRITE; 3832 break; 3833 case BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM: 3834 wc->opcode = IB_WC_RDMA_WRITE; 3835 wc->wc_flags |= IB_WC_WITH_IMM; 3836 break; 3837 case BNXT_QPLIB_SWQE_TYPE_RDMA_READ: 3838 wc->opcode = IB_WC_RDMA_READ; 3839 break; 3840 case BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP: 3841 wc->opcode = IB_WC_COMP_SWAP; 3842 break; 3843 case BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD: 3844 wc->opcode = IB_WC_FETCH_ADD; 3845 break; 3846 case BNXT_QPLIB_SWQE_TYPE_LOCAL_INV: 3847 wc->opcode = IB_WC_LOCAL_INV; 3848 break; 3849 case BNXT_QPLIB_SWQE_TYPE_REG_MR: 3850 wc->opcode = IB_WC_REG_MR; 3851 break; 3852 default: 3853 wc->opcode = IB_WC_SEND; 3854 break; 3855 } 3856 3857 wc->status = __req_to_ib_wc_status(cqe->status); 3858 } 3859 3860 static int bnxt_re_check_packet_type(u16 raweth_qp1_flags, 3861 u16 raweth_qp1_flags2) 3862 { 3863 bool is_ipv6 = false, is_ipv4 = false; 3864 3865 /* raweth_qp1_flags Bit 9-6 indicates itype */ 3866 if ((raweth_qp1_flags & CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE) 3867 != CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE) 3868 return -1; 3869 3870 if (raweth_qp1_flags2 & 3871 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_CS_CALC && 3872 raweth_qp1_flags2 & 3873 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_L4_CS_CALC) { 3874 /* raweth_qp1_flags2 Bit 8 indicates ip_type. 0-v4 1 - v6 */ 3875 (raweth_qp1_flags2 & 3876 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_TYPE) ? 3877 (is_ipv6 = true) : (is_ipv4 = true); 3878 return ((is_ipv6) ? 3879 BNXT_RE_ROCEV2_IPV6_PACKET : 3880 BNXT_RE_ROCEV2_IPV4_PACKET); 3881 } else { 3882 return BNXT_RE_ROCE_V1_PACKET; 3883 } 3884 } 3885 3886 static int bnxt_re_to_ib_nw_type(int nw_type) 3887 { 3888 u8 nw_hdr_type = 0xFF; 3889 3890 switch (nw_type) { 3891 case BNXT_RE_ROCE_V1_PACKET: 3892 nw_hdr_type = RDMA_NETWORK_ROCE_V1; 3893 break; 3894 case BNXT_RE_ROCEV2_IPV4_PACKET: 3895 nw_hdr_type = RDMA_NETWORK_IPV4; 3896 break; 3897 case BNXT_RE_ROCEV2_IPV6_PACKET: 3898 nw_hdr_type = RDMA_NETWORK_IPV6; 3899 break; 3900 } 3901 return nw_hdr_type; 3902 } 3903 3904 static bool bnxt_re_is_loopback_packet(struct bnxt_re_dev *rdev, 3905 void *rq_hdr_buf) 3906 { 3907 u8 *tmp_buf = NULL; 3908 struct ethhdr *eth_hdr; 3909 u16 eth_type; 3910 bool rc = false; 3911 3912 tmp_buf = (u8 *)rq_hdr_buf; 3913 /* 3914 * If dest mac is not same as I/F mac, this could be a 3915 * loopback address or multicast address, check whether 3916 * it is a loopback packet 3917 */ 3918 if (!ether_addr_equal(tmp_buf, rdev->netdev->dev_addr)) { 3919 tmp_buf += 4; 3920 /* Check the ether type */ 3921 eth_hdr = (struct ethhdr *)tmp_buf; 3922 eth_type = ntohs(eth_hdr->h_proto); 3923 switch (eth_type) { 3924 case ETH_P_IBOE: 3925 rc = true; 3926 break; 3927 case ETH_P_IP: 3928 case ETH_P_IPV6: { 3929 u32 len; 3930 struct udphdr *udp_hdr; 3931 3932 len = (eth_type == ETH_P_IP ? sizeof(struct iphdr) : 3933 sizeof(struct ipv6hdr)); 3934 tmp_buf += sizeof(struct ethhdr) + len; 3935 udp_hdr = (struct udphdr *)tmp_buf; 3936 if (ntohs(udp_hdr->dest) == 3937 ROCE_V2_UDP_DPORT) 3938 rc = true; 3939 break; 3940 } 3941 default: 3942 break; 3943 } 3944 } 3945 3946 return rc; 3947 } 3948 3949 static int bnxt_re_process_raw_qp_pkt_rx(struct bnxt_re_qp *gsi_qp, 3950 struct bnxt_qplib_cqe *cqe) 3951 { 3952 struct bnxt_re_dev *rdev = gsi_qp->rdev; 3953 struct bnxt_re_sqp_entries *sqp_entry = NULL; 3954 struct bnxt_re_qp *gsi_sqp = rdev->gsi_ctx.gsi_sqp; 3955 dma_addr_t shrq_hdr_buf_map; 3956 struct ib_sge s_sge[2] = {}; 3957 struct ib_sge r_sge[2] = {}; 3958 struct bnxt_re_ah *gsi_sah; 3959 struct ib_recv_wr rwr = {}; 3960 dma_addr_t rq_hdr_buf_map; 3961 struct ib_ud_wr udwr = {}; 3962 struct ib_send_wr *swr; 3963 u32 skip_bytes = 0; 3964 int pkt_type = 0; 3965 void *rq_hdr_buf; 3966 u32 offset = 0; 3967 u32 tbl_idx; 3968 int rc; 3969 3970 swr = &udwr.wr; 3971 tbl_idx = cqe->wr_id; 3972 3973 rq_hdr_buf = gsi_qp->qplib_qp.rq_hdr_buf + 3974 (tbl_idx * gsi_qp->qplib_qp.rq_hdr_buf_size); 3975 rq_hdr_buf_map = bnxt_qplib_get_qp_buf_from_index(&gsi_qp->qplib_qp, 3976 tbl_idx); 3977 3978 /* Shadow QP header buffer */ 3979 shrq_hdr_buf_map = bnxt_qplib_get_qp_buf_from_index(&gsi_qp->qplib_qp, 3980 tbl_idx); 3981 sqp_entry = &rdev->gsi_ctx.sqp_tbl[tbl_idx]; 3982 3983 /* Store this cqe */ 3984 memcpy(&sqp_entry->cqe, cqe, sizeof(struct bnxt_qplib_cqe)); 3985 sqp_entry->qp1_qp = gsi_qp; 3986 3987 /* Find packet type from the cqe */ 3988 3989 pkt_type = bnxt_re_check_packet_type(cqe->raweth_qp1_flags, 3990 cqe->raweth_qp1_flags2); 3991 if (pkt_type < 0) { 3992 ibdev_err(&rdev->ibdev, "Invalid packet\n"); 3993 return -EINVAL; 3994 } 3995 3996 /* Adjust the offset for the user buffer and post in the rq */ 3997 3998 if (pkt_type == BNXT_RE_ROCEV2_IPV4_PACKET) 3999 offset = 20; 4000 4001 /* 4002 * QP1 loopback packet has 4 bytes of internal header before 4003 * ether header. Skip these four bytes. 4004 */ 4005 if (bnxt_re_is_loopback_packet(rdev, rq_hdr_buf)) 4006 skip_bytes = 4; 4007 4008 /* First send SGE . Skip the ether header*/ 4009 s_sge[0].addr = rq_hdr_buf_map + BNXT_QPLIB_MAX_QP1_RQ_ETH_HDR_SIZE 4010 + skip_bytes; 4011 s_sge[0].lkey = 0xFFFFFFFF; 4012 s_sge[0].length = offset ? BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV4 : 4013 BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6; 4014 4015 /* Second Send SGE */ 4016 s_sge[1].addr = s_sge[0].addr + s_sge[0].length + 4017 BNXT_QPLIB_MAX_QP1_RQ_BDETH_HDR_SIZE; 4018 if (pkt_type != BNXT_RE_ROCE_V1_PACKET) 4019 s_sge[1].addr += 8; 4020 s_sge[1].lkey = 0xFFFFFFFF; 4021 s_sge[1].length = 256; 4022 4023 /* First recv SGE */ 4024 4025 r_sge[0].addr = shrq_hdr_buf_map; 4026 r_sge[0].lkey = 0xFFFFFFFF; 4027 r_sge[0].length = 40; 4028 4029 r_sge[1].addr = sqp_entry->sge.addr + offset; 4030 r_sge[1].lkey = sqp_entry->sge.lkey; 4031 r_sge[1].length = BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6 + 256 - offset; 4032 4033 /* Create receive work request */ 4034 rwr.num_sge = 2; 4035 rwr.sg_list = r_sge; 4036 rwr.wr_id = tbl_idx; 4037 rwr.next = NULL; 4038 4039 rc = bnxt_re_post_recv_shadow_qp(rdev, gsi_sqp, &rwr); 4040 if (rc) { 4041 ibdev_err(&rdev->ibdev, 4042 "Failed to post Rx buffers to shadow QP"); 4043 return -ENOMEM; 4044 } 4045 4046 swr->num_sge = 2; 4047 swr->sg_list = s_sge; 4048 swr->wr_id = tbl_idx; 4049 swr->opcode = IB_WR_SEND; 4050 swr->next = NULL; 4051 gsi_sah = rdev->gsi_ctx.gsi_sah; 4052 udwr.ah = &gsi_sah->ib_ah; 4053 udwr.remote_qpn = gsi_sqp->qplib_qp.id; 4054 udwr.remote_qkey = gsi_sqp->qplib_qp.qkey; 4055 4056 /* post data received in the send queue */ 4057 return bnxt_re_post_send_shadow_qp(rdev, gsi_sqp, swr); 4058 } 4059 4060 static void bnxt_re_process_res_rawqp1_wc(struct ib_wc *wc, 4061 struct bnxt_qplib_cqe *cqe) 4062 { 4063 wc->opcode = IB_WC_RECV; 4064 wc->status = __rawqp1_to_ib_wc_status(cqe->status); 4065 wc->wc_flags |= IB_WC_GRH; 4066 } 4067 4068 static bool bnxt_re_check_if_vlan_valid(struct bnxt_re_dev *rdev, 4069 u16 vlan_id) 4070 { 4071 /* 4072 * Check if the vlan is configured in the host. If not configured, it 4073 * can be a transparent VLAN. So dont report the vlan id. 4074 */ 4075 if (!__vlan_find_dev_deep_rcu(rdev->netdev, 4076 htons(ETH_P_8021Q), vlan_id)) 4077 return false; 4078 return true; 4079 } 4080 4081 static bool bnxt_re_is_vlan_pkt(struct bnxt_qplib_cqe *orig_cqe, 4082 u16 *vid, u8 *sl) 4083 { 4084 bool ret = false; 4085 u32 metadata; 4086 u16 tpid; 4087 4088 metadata = orig_cqe->raweth_qp1_metadata; 4089 if (orig_cqe->raweth_qp1_flags2 & 4090 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_VLAN) { 4091 tpid = ((metadata & 4092 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_MASK) >> 4093 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_SFT); 4094 if (tpid == ETH_P_8021Q) { 4095 *vid = metadata & 4096 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_VID_MASK; 4097 *sl = (metadata & 4098 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_MASK) >> 4099 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_SFT; 4100 ret = true; 4101 } 4102 } 4103 4104 return ret; 4105 } 4106 4107 static void bnxt_re_process_res_rc_wc(struct ib_wc *wc, 4108 struct bnxt_qplib_cqe *cqe) 4109 { 4110 wc->opcode = IB_WC_RECV; 4111 wc->status = __rc_to_ib_wc_status(cqe->status); 4112 4113 if (cqe->flags & CQ_RES_RC_FLAGS_IMM) 4114 wc->wc_flags |= IB_WC_WITH_IMM; 4115 if (cqe->flags & CQ_RES_RC_FLAGS_INV) 4116 wc->wc_flags |= IB_WC_WITH_INVALIDATE; 4117 if ((cqe->flags & (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM)) == 4118 (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM)) 4119 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM; 4120 } 4121 4122 static void bnxt_re_process_res_shadow_qp_wc(struct bnxt_re_qp *gsi_sqp, 4123 struct ib_wc *wc, 4124 struct bnxt_qplib_cqe *cqe) 4125 { 4126 struct bnxt_re_dev *rdev = gsi_sqp->rdev; 4127 struct bnxt_re_qp *gsi_qp = NULL; 4128 struct bnxt_qplib_cqe *orig_cqe = NULL; 4129 struct bnxt_re_sqp_entries *sqp_entry = NULL; 4130 int nw_type; 4131 u32 tbl_idx; 4132 u16 vlan_id; 4133 u8 sl; 4134 4135 tbl_idx = cqe->wr_id; 4136 4137 sqp_entry = &rdev->gsi_ctx.sqp_tbl[tbl_idx]; 4138 gsi_qp = sqp_entry->qp1_qp; 4139 orig_cqe = &sqp_entry->cqe; 4140 4141 wc->wr_id = sqp_entry->wrid; 4142 wc->byte_len = orig_cqe->length; 4143 wc->qp = &gsi_qp->ib_qp; 4144 4145 wc->ex.imm_data = cpu_to_be32(orig_cqe->immdata); 4146 wc->src_qp = orig_cqe->src_qp; 4147 memcpy(wc->smac, orig_cqe->smac, ETH_ALEN); 4148 if (bnxt_re_is_vlan_pkt(orig_cqe, &vlan_id, &sl)) { 4149 if (bnxt_re_check_if_vlan_valid(rdev, vlan_id)) { 4150 wc->vlan_id = vlan_id; 4151 wc->sl = sl; 4152 wc->wc_flags |= IB_WC_WITH_VLAN; 4153 } 4154 } 4155 wc->port_num = 1; 4156 wc->vendor_err = orig_cqe->status; 4157 4158 wc->opcode = IB_WC_RECV; 4159 wc->status = __rawqp1_to_ib_wc_status(orig_cqe->status); 4160 wc->wc_flags |= IB_WC_GRH; 4161 4162 nw_type = bnxt_re_check_packet_type(orig_cqe->raweth_qp1_flags, 4163 orig_cqe->raweth_qp1_flags2); 4164 if (nw_type >= 0) { 4165 wc->network_hdr_type = bnxt_re_to_ib_nw_type(nw_type); 4166 wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE; 4167 } 4168 } 4169 4170 static void bnxt_re_process_res_ud_wc(struct bnxt_re_qp *qp, 4171 struct ib_wc *wc, 4172 struct bnxt_qplib_cqe *cqe) 4173 { 4174 struct bnxt_re_dev *rdev; 4175 u16 vlan_id = 0; 4176 u8 nw_type; 4177 4178 rdev = qp->rdev; 4179 wc->opcode = IB_WC_RECV; 4180 wc->status = __rc_to_ib_wc_status(cqe->status); 4181 4182 if (cqe->flags & CQ_RES_UD_FLAGS_IMM) 4183 wc->wc_flags |= IB_WC_WITH_IMM; 4184 /* report only on GSI QP for Thor */ 4185 if (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_GSI) { 4186 wc->wc_flags |= IB_WC_GRH; 4187 memcpy(wc->smac, cqe->smac, ETH_ALEN); 4188 wc->wc_flags |= IB_WC_WITH_SMAC; 4189 if (cqe->flags & CQ_RES_UD_FLAGS_META_FORMAT_VLAN) { 4190 vlan_id = (cqe->cfa_meta & 0xFFF); 4191 } 4192 /* Mark only if vlan_id is non zero */ 4193 if (vlan_id && bnxt_re_check_if_vlan_valid(rdev, vlan_id)) { 4194 wc->vlan_id = vlan_id; 4195 wc->wc_flags |= IB_WC_WITH_VLAN; 4196 } 4197 nw_type = (cqe->flags & CQ_RES_UD_FLAGS_ROCE_IP_VER_MASK) >> 4198 CQ_RES_UD_FLAGS_ROCE_IP_VER_SFT; 4199 wc->network_hdr_type = bnxt_re_to_ib_nw_type(nw_type); 4200 wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE; 4201 } 4202 4203 } 4204 4205 static int send_phantom_wqe(struct bnxt_re_qp *qp) 4206 { 4207 struct bnxt_qplib_qp *lib_qp = &qp->qplib_qp; 4208 unsigned long flags; 4209 int rc; 4210 4211 spin_lock_irqsave(&qp->sq_lock, flags); 4212 4213 rc = bnxt_re_bind_fence_mw(lib_qp); 4214 if (!rc) { 4215 lib_qp->sq.phantom_wqe_cnt++; 4216 ibdev_dbg(&qp->rdev->ibdev, 4217 "qp %#x sq->prod %#x sw_prod %#x phantom_wqe_cnt %d\n", 4218 lib_qp->id, lib_qp->sq.hwq.prod, 4219 HWQ_CMP(lib_qp->sq.hwq.prod, &lib_qp->sq.hwq), 4220 lib_qp->sq.phantom_wqe_cnt); 4221 } 4222 4223 spin_unlock_irqrestore(&qp->sq_lock, flags); 4224 return rc; 4225 } 4226 4227 int bnxt_re_poll_cq(struct ib_cq *ib_cq, int num_entries, struct ib_wc *wc) 4228 { 4229 struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq); 4230 struct bnxt_re_qp *qp, *sh_qp; 4231 struct bnxt_qplib_cqe *cqe; 4232 int i, ncqe, budget; 4233 struct bnxt_qplib_q *sq; 4234 struct bnxt_qplib_qp *lib_qp; 4235 u32 tbl_idx; 4236 struct bnxt_re_sqp_entries *sqp_entry = NULL; 4237 unsigned long flags; 4238 4239 /* User CQ; the only processing we do is to 4240 * complete any pending CQ resize operation. 4241 */ 4242 if (cq->umem) { 4243 if (cq->resize_umem) 4244 bnxt_re_resize_cq_complete(cq); 4245 return 0; 4246 } 4247 4248 spin_lock_irqsave(&cq->cq_lock, flags); 4249 budget = min_t(u32, num_entries, cq->max_cql); 4250 num_entries = budget; 4251 if (!cq->cql) { 4252 ibdev_err(&cq->rdev->ibdev, "POLL CQ : no CQL to use"); 4253 goto exit; 4254 } 4255 cqe = &cq->cql[0]; 4256 while (budget) { 4257 lib_qp = NULL; 4258 ncqe = bnxt_qplib_poll_cq(&cq->qplib_cq, cqe, budget, &lib_qp); 4259 if (lib_qp) { 4260 sq = &lib_qp->sq; 4261 if (sq->send_phantom) { 4262 qp = container_of(lib_qp, 4263 struct bnxt_re_qp, qplib_qp); 4264 if (send_phantom_wqe(qp) == -ENOMEM) 4265 ibdev_err(&cq->rdev->ibdev, 4266 "Phantom failed! Scheduled to send again\n"); 4267 else 4268 sq->send_phantom = false; 4269 } 4270 } 4271 if (ncqe < budget) 4272 ncqe += bnxt_qplib_process_flush_list(&cq->qplib_cq, 4273 cqe + ncqe, 4274 budget - ncqe); 4275 4276 if (!ncqe) 4277 break; 4278 4279 for (i = 0; i < ncqe; i++, cqe++) { 4280 /* Transcribe each qplib_wqe back to ib_wc */ 4281 memset(wc, 0, sizeof(*wc)); 4282 4283 wc->wr_id = cqe->wr_id; 4284 wc->byte_len = cqe->length; 4285 qp = container_of 4286 ((struct bnxt_qplib_qp *) 4287 (unsigned long)(cqe->qp_handle), 4288 struct bnxt_re_qp, qplib_qp); 4289 wc->qp = &qp->ib_qp; 4290 if (cqe->flags & CQ_RES_RC_FLAGS_IMM) 4291 wc->ex.imm_data = cpu_to_be32(cqe->immdata); 4292 else 4293 wc->ex.invalidate_rkey = cqe->invrkey; 4294 wc->src_qp = cqe->src_qp; 4295 memcpy(wc->smac, cqe->smac, ETH_ALEN); 4296 wc->port_num = 1; 4297 wc->vendor_err = cqe->status; 4298 4299 switch (cqe->opcode) { 4300 case CQ_BASE_CQE_TYPE_REQ: 4301 sh_qp = qp->rdev->gsi_ctx.gsi_sqp; 4302 if (sh_qp && 4303 qp->qplib_qp.id == sh_qp->qplib_qp.id) { 4304 /* Handle this completion with 4305 * the stored completion 4306 */ 4307 memset(wc, 0, sizeof(*wc)); 4308 continue; 4309 } 4310 bnxt_re_process_req_wc(wc, cqe); 4311 break; 4312 case CQ_BASE_CQE_TYPE_RES_RAWETH_QP1: 4313 if (!cqe->status) { 4314 int rc = 0; 4315 4316 rc = bnxt_re_process_raw_qp_pkt_rx 4317 (qp, cqe); 4318 if (!rc) { 4319 memset(wc, 0, sizeof(*wc)); 4320 continue; 4321 } 4322 cqe->status = -1; 4323 } 4324 /* Errors need not be looped back. 4325 * But change the wr_id to the one 4326 * stored in the table 4327 */ 4328 tbl_idx = cqe->wr_id; 4329 sqp_entry = &cq->rdev->gsi_ctx.sqp_tbl[tbl_idx]; 4330 wc->wr_id = sqp_entry->wrid; 4331 bnxt_re_process_res_rawqp1_wc(wc, cqe); 4332 break; 4333 case CQ_BASE_CQE_TYPE_RES_RC: 4334 bnxt_re_process_res_rc_wc(wc, cqe); 4335 break; 4336 case CQ_BASE_CQE_TYPE_RES_UD: 4337 sh_qp = qp->rdev->gsi_ctx.gsi_sqp; 4338 if (sh_qp && 4339 qp->qplib_qp.id == sh_qp->qplib_qp.id) { 4340 /* Handle this completion with 4341 * the stored completion 4342 */ 4343 if (cqe->status) { 4344 continue; 4345 } else { 4346 bnxt_re_process_res_shadow_qp_wc 4347 (qp, wc, cqe); 4348 break; 4349 } 4350 } 4351 bnxt_re_process_res_ud_wc(qp, wc, cqe); 4352 break; 4353 default: 4354 ibdev_err(&cq->rdev->ibdev, 4355 "POLL CQ : type 0x%x not handled", 4356 cqe->opcode); 4357 continue; 4358 } 4359 wc++; 4360 budget--; 4361 } 4362 } 4363 exit: 4364 spin_unlock_irqrestore(&cq->cq_lock, flags); 4365 return num_entries - budget; 4366 } 4367 4368 int bnxt_re_req_notify_cq(struct ib_cq *ib_cq, 4369 enum ib_cq_notify_flags ib_cqn_flags) 4370 { 4371 struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq); 4372 int type = 0, rc = 0; 4373 unsigned long flags; 4374 4375 spin_lock_irqsave(&cq->cq_lock, flags); 4376 /* Trigger on the very next completion */ 4377 if (ib_cqn_flags & IB_CQ_NEXT_COMP) 4378 type = DBC_DBC_TYPE_CQ_ARMALL; 4379 /* Trigger on the next solicited completion */ 4380 else if (ib_cqn_flags & IB_CQ_SOLICITED) 4381 type = DBC_DBC_TYPE_CQ_ARMSE; 4382 4383 /* Poll to see if there are missed events */ 4384 if ((ib_cqn_flags & IB_CQ_REPORT_MISSED_EVENTS) && 4385 !(bnxt_qplib_is_cq_empty(&cq->qplib_cq))) { 4386 rc = 1; 4387 goto exit; 4388 } 4389 bnxt_qplib_req_notify_cq(&cq->qplib_cq, type); 4390 4391 exit: 4392 spin_unlock_irqrestore(&cq->cq_lock, flags); 4393 return rc; 4394 } 4395 4396 /* Memory Regions */ 4397 struct ib_mr *bnxt_re_get_dma_mr(struct ib_pd *ib_pd, int mr_access_flags) 4398 { 4399 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 4400 struct bnxt_re_dev *rdev = pd->rdev; 4401 struct bnxt_re_mr *mr; 4402 u32 active_mrs; 4403 int rc; 4404 4405 mr = kzalloc_obj(*mr); 4406 if (!mr) 4407 return ERR_PTR(-ENOMEM); 4408 4409 mr->rdev = rdev; 4410 mr->qplib_mr.pd = &pd->qplib_pd; 4411 mr->qplib_mr.access_flags = __from_ib_access_flags(mr_access_flags); 4412 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR; 4413 4414 if (mr_access_flags & IB_ACCESS_RELAXED_ORDERING) 4415 bnxt_re_check_and_set_relaxed_ordering(rdev, &mr->qplib_mr); 4416 4417 /* Allocate and register 0 as the address */ 4418 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr); 4419 if (rc) 4420 goto fail; 4421 4422 mr->qplib_mr.hwq.level = PBL_LVL_MAX; 4423 mr->qplib_mr.total_size = -1; /* Infinte length */ 4424 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, NULL, 0, 4425 PAGE_SIZE, false); 4426 if (rc) 4427 goto fail_mr; 4428 4429 mr->ib_mr.lkey = mr->qplib_mr.lkey; 4430 if (mr_access_flags & (IB_ACCESS_REMOTE_WRITE | IB_ACCESS_REMOTE_READ | 4431 IB_ACCESS_REMOTE_ATOMIC)) 4432 mr->ib_mr.rkey = mr->ib_mr.lkey; 4433 active_mrs = atomic_inc_return(&rdev->stats.res.mr_count); 4434 if (active_mrs > rdev->stats.res.mr_watermark) 4435 rdev->stats.res.mr_watermark = active_mrs; 4436 4437 return &mr->ib_mr; 4438 4439 fail_mr: 4440 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 4441 fail: 4442 kfree(mr); 4443 return ERR_PTR(rc); 4444 } 4445 4446 int bnxt_re_dereg_mr(struct ib_mr *ib_mr, struct ib_udata *udata) 4447 { 4448 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr); 4449 struct bnxt_re_dev *rdev = mr->rdev; 4450 int rc; 4451 4452 rc = ib_is_udata_in_empty(udata); 4453 if (rc) 4454 return rc; 4455 4456 rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 4457 if (rc) { 4458 ibdev_err(&rdev->ibdev, "Dereg MR failed: %#x\n", rc); 4459 return rc; 4460 } 4461 4462 if (mr->pages) { 4463 rc = bnxt_qplib_free_fast_reg_page_list(&rdev->qplib_res, 4464 &mr->qplib_frpl); 4465 kfree(mr->pages); 4466 mr->npages = 0; 4467 mr->pages = NULL; 4468 } 4469 ib_umem_release(mr->ib_umem); 4470 4471 kfree(mr); 4472 atomic_dec(&rdev->stats.res.mr_count); 4473 if (rc) 4474 return rc; 4475 return ib_respond_empty_udata(udata); 4476 } 4477 4478 static int bnxt_re_set_page(struct ib_mr *ib_mr, u64 addr) 4479 { 4480 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr); 4481 4482 if (unlikely(mr->npages == mr->qplib_frpl.max_pg_ptrs)) 4483 return -ENOMEM; 4484 4485 mr->pages[mr->npages++] = addr; 4486 return 0; 4487 } 4488 4489 int bnxt_re_map_mr_sg(struct ib_mr *ib_mr, struct scatterlist *sg, int sg_nents, 4490 unsigned int *sg_offset) 4491 { 4492 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr); 4493 4494 mr->npages = 0; 4495 return ib_sg_to_pages(ib_mr, sg, sg_nents, sg_offset, bnxt_re_set_page); 4496 } 4497 4498 struct ib_mr *bnxt_re_alloc_mr(struct ib_pd *ib_pd, enum ib_mr_type type, 4499 u32 max_num_sg) 4500 { 4501 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 4502 struct bnxt_re_dev *rdev = pd->rdev; 4503 struct bnxt_re_mr *mr = NULL; 4504 u32 active_mrs; 4505 int rc; 4506 4507 if (type != IB_MR_TYPE_MEM_REG) { 4508 ibdev_dbg(&rdev->ibdev, "MR type 0x%x not supported", type); 4509 return ERR_PTR(-EINVAL); 4510 } 4511 if (max_num_sg > MAX_PBL_LVL_1_PGS) 4512 return ERR_PTR(-EINVAL); 4513 4514 mr = kzalloc_obj(*mr); 4515 if (!mr) 4516 return ERR_PTR(-ENOMEM); 4517 4518 mr->rdev = rdev; 4519 mr->qplib_mr.pd = &pd->qplib_pd; 4520 mr->qplib_mr.access_flags = BNXT_QPLIB_FR_PMR; 4521 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR; 4522 4523 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr); 4524 if (rc) 4525 goto bail; 4526 4527 mr->ib_mr.lkey = mr->qplib_mr.lkey; 4528 mr->ib_mr.rkey = mr->ib_mr.lkey; 4529 4530 mr->pages = kzalloc_objs(u64, max_num_sg); 4531 if (!mr->pages) { 4532 rc = -ENOMEM; 4533 goto fail; 4534 } 4535 rc = bnxt_qplib_alloc_fast_reg_page_list(&rdev->qplib_res, 4536 &mr->qplib_frpl, max_num_sg); 4537 if (rc) { 4538 ibdev_err(&rdev->ibdev, 4539 "Failed to allocate HW FR page list"); 4540 goto fail_mr; 4541 } 4542 4543 active_mrs = atomic_inc_return(&rdev->stats.res.mr_count); 4544 if (active_mrs > rdev->stats.res.mr_watermark) 4545 rdev->stats.res.mr_watermark = active_mrs; 4546 return &mr->ib_mr; 4547 4548 fail_mr: 4549 kfree(mr->pages); 4550 fail: 4551 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 4552 bail: 4553 kfree(mr); 4554 return ERR_PTR(rc); 4555 } 4556 4557 struct ib_mw *bnxt_re_alloc_mw(struct ib_pd *ib_pd, enum ib_mw_type type, 4558 struct ib_udata *udata) 4559 { 4560 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 4561 struct bnxt_re_dev *rdev = pd->rdev; 4562 struct bnxt_re_mw *mw; 4563 u32 active_mws; 4564 int rc; 4565 4566 rc = ib_is_udata_in_empty(udata); 4567 if (rc) 4568 return ERR_PTR(rc); 4569 4570 mw = kzalloc_obj(*mw); 4571 if (!mw) 4572 return ERR_PTR(-ENOMEM); 4573 mw->rdev = rdev; 4574 mw->qplib_mw.pd = &pd->qplib_pd; 4575 4576 mw->qplib_mw.type = (type == IB_MW_TYPE_1 ? 4577 CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1 : 4578 CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B); 4579 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mw->qplib_mw); 4580 if (rc) { 4581 ibdev_err(&rdev->ibdev, "Allocate MW failed!"); 4582 goto fail; 4583 } 4584 mw->ib_mw.rkey = mw->qplib_mw.rkey; 4585 4586 active_mws = atomic_inc_return(&rdev->stats.res.mw_count); 4587 if (active_mws > rdev->stats.res.mw_watermark) 4588 rdev->stats.res.mw_watermark = active_mws; 4589 return &mw->ib_mw; 4590 4591 fail: 4592 kfree(mw); 4593 return ERR_PTR(rc); 4594 } 4595 4596 int bnxt_re_dealloc_mw(struct ib_mw *ib_mw) 4597 { 4598 struct bnxt_re_mw *mw = container_of(ib_mw, struct bnxt_re_mw, ib_mw); 4599 struct bnxt_re_dev *rdev = mw->rdev; 4600 int rc; 4601 4602 rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &mw->qplib_mw); 4603 if (rc) { 4604 ibdev_err(&rdev->ibdev, "Free MW failed: %#x\n", rc); 4605 return rc; 4606 } 4607 4608 kfree(mw); 4609 atomic_dec(&rdev->stats.res.mw_count); 4610 return rc; 4611 } 4612 4613 static struct ib_mr *__bnxt_re_user_reg_mr(struct ib_pd *ib_pd, u64 length, u64 virt_addr, 4614 int mr_access_flags, struct ib_umem *umem) 4615 { 4616 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 4617 struct bnxt_re_dev *rdev = pd->rdev; 4618 unsigned long page_size; 4619 struct bnxt_re_mr *mr; 4620 int umem_pgs, rc; 4621 u32 active_mrs; 4622 4623 if (length > BNXT_RE_MAX_MR_SIZE) { 4624 ibdev_err(&rdev->ibdev, "MR Size: %lld > Max supported:%lld\n", 4625 length, BNXT_RE_MAX_MR_SIZE); 4626 return ERR_PTR(-ENOMEM); 4627 } 4628 4629 page_size = ib_umem_find_best_pgsz(umem, BNXT_RE_PAGE_SIZE_SUPPORTED, virt_addr); 4630 if (!page_size) { 4631 ibdev_err(&rdev->ibdev, "umem page size unsupported!"); 4632 return ERR_PTR(-EINVAL); 4633 } 4634 4635 mr = kzalloc_obj(*mr); 4636 if (!mr) 4637 return ERR_PTR(-ENOMEM); 4638 4639 mr->rdev = rdev; 4640 mr->qplib_mr.pd = &pd->qplib_pd; 4641 mr->qplib_mr.access_flags = __from_ib_access_flags(mr_access_flags); 4642 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_MR; 4643 4644 if (!_is_alloc_mr_unified(rdev->dev_attr->dev_cap_flags)) { 4645 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr); 4646 if (rc) { 4647 ibdev_err(&rdev->ibdev, "Failed to allocate MR rc = %d", rc); 4648 rc = -EIO; 4649 goto free_mr; 4650 } 4651 /* The fixed portion of the rkey is the same as the lkey */ 4652 mr->ib_mr.rkey = mr->qplib_mr.rkey; 4653 } else { 4654 mr->qplib_mr.flags = CMDQ_REGISTER_MR_FLAGS_ALLOC_MR; 4655 } 4656 mr->ib_umem = umem; 4657 mr->qplib_mr.va = virt_addr; 4658 mr->qplib_mr.total_size = length; 4659 4660 if (mr_access_flags & IB_ACCESS_RELAXED_ORDERING) 4661 bnxt_re_check_and_set_relaxed_ordering(rdev, &mr->qplib_mr); 4662 4663 umem_pgs = ib_umem_num_dma_blocks(umem, page_size); 4664 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, umem, 4665 umem_pgs, page_size, 4666 _is_alloc_mr_unified(rdev->dev_attr->dev_cap_flags)); 4667 if (rc) { 4668 ibdev_err(&rdev->ibdev, "Failed to register user MR - rc = %d\n", rc); 4669 rc = -EIO; 4670 goto free_mrw; 4671 } 4672 4673 mr->ib_mr.lkey = mr->qplib_mr.lkey; 4674 mr->ib_mr.rkey = mr->qplib_mr.lkey; 4675 active_mrs = atomic_inc_return(&rdev->stats.res.mr_count); 4676 if (active_mrs > rdev->stats.res.mr_watermark) 4677 rdev->stats.res.mr_watermark = active_mrs; 4678 4679 return &mr->ib_mr; 4680 4681 free_mrw: 4682 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 4683 free_mr: 4684 kfree(mr); 4685 return ERR_PTR(rc); 4686 } 4687 4688 struct ib_mr *bnxt_re_reg_user_mr(struct ib_pd *ib_pd, u64 start, u64 length, 4689 u64 virt_addr, int mr_access_flags, 4690 struct ib_dmah *dmah, 4691 struct ib_udata *udata) 4692 { 4693 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 4694 struct bnxt_re_dev *rdev = pd->rdev; 4695 struct ib_umem *umem; 4696 struct ib_mr *ib_mr; 4697 int ret; 4698 4699 ret = ib_is_udata_in_empty(udata); 4700 if (ret) 4701 return ERR_PTR(ret); 4702 4703 if (dmah) 4704 return ERR_PTR(-EOPNOTSUPP); 4705 4706 umem = ib_umem_get_va(&rdev->ibdev, start, length, mr_access_flags); 4707 if (IS_ERR(umem)) 4708 return ERR_CAST(umem); 4709 4710 ib_mr = __bnxt_re_user_reg_mr(ib_pd, length, virt_addr, mr_access_flags, umem); 4711 if (IS_ERR(ib_mr)) 4712 ib_umem_release(umem); 4713 return ib_mr; 4714 } 4715 4716 struct ib_mr *bnxt_re_reg_user_mr_dmabuf(struct ib_pd *ib_pd, u64 start, 4717 u64 length, u64 virt_addr, int fd, 4718 int mr_access_flags, 4719 struct ib_dmah *dmah, 4720 struct uverbs_attr_bundle *attrs) 4721 { 4722 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 4723 struct bnxt_re_dev *rdev = pd->rdev; 4724 struct ib_umem_dmabuf *umem_dmabuf; 4725 struct ib_umem *umem; 4726 struct ib_mr *ib_mr; 4727 4728 if (dmah) 4729 return ERR_PTR(-EOPNOTSUPP); 4730 4731 umem_dmabuf = ib_umem_dmabuf_get_pinned(&rdev->ibdev, start, length, 4732 fd, mr_access_flags); 4733 if (IS_ERR(umem_dmabuf)) 4734 return ERR_CAST(umem_dmabuf); 4735 4736 umem = &umem_dmabuf->umem; 4737 4738 ib_mr = __bnxt_re_user_reg_mr(ib_pd, length, virt_addr, mr_access_flags, umem); 4739 if (IS_ERR(ib_mr)) 4740 ib_umem_release(umem); 4741 return ib_mr; 4742 } 4743 4744 int bnxt_re_alloc_ucontext(struct ib_ucontext *ctx, struct ib_udata *udata) 4745 { 4746 struct ib_device *ibdev = ctx->device; 4747 struct bnxt_re_ucontext *uctx = 4748 container_of(ctx, struct bnxt_re_ucontext, ib_uctx); 4749 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 4750 struct bnxt_qplib_dev_attr *dev_attr = rdev->dev_attr; 4751 struct bnxt_re_user_mmap_entry *entry; 4752 struct bnxt_re_uctx_resp resp = {}; 4753 struct bnxt_re_uctx_req ureq = {}; 4754 u32 chip_met_rev_num = 0; 4755 int rc; 4756 4757 ibdev_dbg(ibdev, "ABI version requested %u", ibdev->ops.uverbs_abi_ver); 4758 4759 if (ibdev->ops.uverbs_abi_ver != BNXT_RE_ABI_VERSION) { 4760 ibdev_dbg(ibdev, " is different from the device %d ", 4761 BNXT_RE_ABI_VERSION); 4762 return -EPERM; 4763 } 4764 4765 uctx->rdev = rdev; 4766 4767 uctx->shpg = (void *)get_zeroed_page(GFP_KERNEL); 4768 if (!uctx->shpg) { 4769 rc = -ENOMEM; 4770 goto fail; 4771 } 4772 spin_lock_init(&uctx->sh_lock); 4773 mutex_init(&uctx->wcdpi_lock); 4774 4775 resp.comp_mask = BNXT_RE_UCNTX_CMASK_HAVE_CCTX; 4776 chip_met_rev_num = rdev->chip_ctx->chip_num; 4777 chip_met_rev_num |= ((u32)rdev->chip_ctx->chip_rev & 0xFF) << 4778 BNXT_RE_CHIP_ID0_CHIP_REV_SFT; 4779 chip_met_rev_num |= ((u32)rdev->chip_ctx->chip_metal & 0xFF) << 4780 BNXT_RE_CHIP_ID0_CHIP_MET_SFT; 4781 resp.chip_id0 = chip_met_rev_num; 4782 /*Temp, Use xa_alloc instead */ 4783 resp.dev_id = rdev->en_dev->pdev->devfn; 4784 resp.max_qp = rdev->qplib_ctx.qpc_count; 4785 resp.pg_size = PAGE_SIZE; 4786 resp.cqe_sz = sizeof(struct cq_base); 4787 resp.max_cqd = dev_attr->max_cq_wqes; 4788 4789 if (rdev->chip_ctx->modes.db_push) 4790 resp.comp_mask |= BNXT_RE_UCNTX_CMASK_WC_DPI_ENABLED; 4791 4792 entry = bnxt_re_mmap_entry_insert(uctx, 0, BNXT_RE_MMAP_SH_PAGE, NULL); 4793 if (!entry) { 4794 rc = -ENOMEM; 4795 goto cfail; 4796 } 4797 uctx->shpage_mmap = &entry->rdma_entry; 4798 if (rdev->pacing.dbr_pacing) 4799 resp.comp_mask |= BNXT_RE_UCNTX_CMASK_DBR_PACING_ENABLED; 4800 4801 if (_is_host_msn_table(rdev->qplib_res.dattr->dev_cap_flags2)) 4802 resp.comp_mask |= BNXT_RE_UCNTX_CMASK_MSN_TABLE_ENABLED; 4803 4804 if (_is_modify_qp_rate_limit_supported(dev_attr->dev_cap_flags2)) 4805 resp.comp_mask |= BNXT_RE_UCNTX_CMASK_QP_RATE_LIMIT_ENABLED; 4806 4807 if (udata->inlen) { 4808 rc = ib_copy_validate_udata_in_cm( 4809 udata, ureq, comp_mask, 4810 BNXT_RE_COMP_MASK_REQ_UCNTX_POW2_SUPPORT | 4811 BNXT_RE_COMP_MASK_REQ_UCNTX_VAR_WQE_SUPPORT); 4812 if (rc) 4813 goto cfail; 4814 if (ureq.comp_mask & BNXT_RE_COMP_MASK_REQ_UCNTX_POW2_SUPPORT) { 4815 resp.comp_mask |= BNXT_RE_UCNTX_CMASK_POW2_DISABLED; 4816 uctx->cmask |= BNXT_RE_UCNTX_CAP_POW2_DISABLED; 4817 } 4818 if (ureq.comp_mask & BNXT_RE_COMP_MASK_REQ_UCNTX_VAR_WQE_SUPPORT) { 4819 resp.comp_mask |= BNXT_RE_UCNTX_CMASK_HAVE_MODE; 4820 resp.mode = rdev->chip_ctx->modes.wqe_mode; 4821 if (resp.mode == BNXT_QPLIB_WQE_MODE_VARIABLE) 4822 uctx->cmask |= BNXT_RE_UCNTX_CAP_VAR_WQE_ENABLED; 4823 } 4824 } 4825 4826 rc = ib_respond_udata(udata, resp); 4827 if (rc) 4828 goto cfail; 4829 4830 return 0; 4831 cfail: 4832 free_page((unsigned long)uctx->shpg); 4833 uctx->shpg = NULL; 4834 fail: 4835 return rc; 4836 } 4837 4838 void bnxt_re_dealloc_ucontext(struct ib_ucontext *ib_uctx) 4839 { 4840 struct bnxt_re_ucontext *uctx = container_of(ib_uctx, 4841 struct bnxt_re_ucontext, 4842 ib_uctx); 4843 4844 struct bnxt_re_dev *rdev = uctx->rdev; 4845 4846 rdma_user_mmap_entry_remove(uctx->shpage_mmap); 4847 uctx->shpage_mmap = NULL; 4848 if (uctx->shpg) 4849 free_page((unsigned long)uctx->shpg); 4850 4851 if (uctx->dpi.dbr) { 4852 /* Free DPI only if this is the first PD allocated by the 4853 * application and mark the context dpi as NULL 4854 */ 4855 bnxt_qplib_dealloc_dpi(&rdev->qplib_res, &uctx->dpi); 4856 uctx->dpi.dbr = NULL; 4857 } 4858 } 4859 4860 static int bnxt_re_setup_vnic(struct bnxt_re_dev *rdev, struct bnxt_re_qp *qp) 4861 { 4862 int rc; 4863 4864 rc = bnxt_re_hwrm_alloc_vnic(rdev); 4865 if (rc) 4866 return rc; 4867 4868 rc = bnxt_re_hwrm_cfg_vnic(rdev, qp->qplib_qp.id); 4869 if (rc) 4870 goto out_free_vnic; 4871 4872 return 0; 4873 out_free_vnic: 4874 bnxt_re_hwrm_free_vnic(rdev); 4875 return rc; 4876 } 4877 4878 struct ib_flow *bnxt_re_create_flow(struct ib_qp *ib_qp, 4879 struct ib_flow_attr *attr, 4880 struct ib_udata *udata) 4881 { 4882 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 4883 struct bnxt_re_dev *rdev = qp->rdev; 4884 struct bnxt_re_flow *flow; 4885 int rc; 4886 4887 rc = ib_is_udata_in_empty(udata); 4888 if (rc) 4889 return ERR_PTR(rc); 4890 4891 if (attr->type != IB_FLOW_ATTR_SNIFFER || 4892 !rdev->rcfw.roce_mirror) 4893 return ERR_PTR(-EOPNOTSUPP); 4894 4895 mutex_lock(&rdev->qp_lock); 4896 if (rdev->sniffer_flow_created) { 4897 ibdev_err(&rdev->ibdev, "RoCE Mirroring is already Configured\n"); 4898 mutex_unlock(&rdev->qp_lock); 4899 return ERR_PTR(-EBUSY); 4900 } 4901 4902 flow = kzalloc_obj(*flow); 4903 if (!flow) { 4904 mutex_unlock(&rdev->qp_lock); 4905 return ERR_PTR(-ENOMEM); 4906 } 4907 4908 flow->rdev = rdev; 4909 4910 rc = bnxt_re_setup_vnic(rdev, qp); 4911 if (rc) 4912 goto out_free_flow; 4913 4914 rc = bnxt_qplib_create_flow(&rdev->qplib_res); 4915 if (rc) 4916 goto out_free_vnic; 4917 4918 rdev->sniffer_flow_created = 1; 4919 mutex_unlock(&rdev->qp_lock); 4920 4921 return &flow->ib_flow; 4922 4923 out_free_vnic: 4924 bnxt_re_hwrm_free_vnic(rdev); 4925 out_free_flow: 4926 mutex_unlock(&rdev->qp_lock); 4927 kfree(flow); 4928 return ERR_PTR(rc); 4929 } 4930 4931 int bnxt_re_destroy_flow(struct ib_flow *flow_id) 4932 { 4933 struct bnxt_re_flow *flow = 4934 container_of(flow_id, struct bnxt_re_flow, ib_flow); 4935 struct bnxt_re_dev *rdev = flow->rdev; 4936 int rc; 4937 4938 mutex_lock(&rdev->qp_lock); 4939 rc = bnxt_qplib_destroy_flow(&rdev->qplib_res); 4940 if (rc) 4941 ibdev_dbg(&rdev->ibdev, "failed to destroy_flow rc = %d\n", rc); 4942 rdev->sniffer_flow_created = 0; 4943 4944 bnxt_re_hwrm_free_vnic(rdev); 4945 mutex_unlock(&rdev->qp_lock); 4946 kfree(flow); 4947 4948 return rc; 4949 } 4950 4951 /* Helper function to mmap the virtual memory from user app */ 4952 int bnxt_re_mmap(struct ib_ucontext *ib_uctx, struct vm_area_struct *vma) 4953 { 4954 struct bnxt_re_ucontext *uctx = container_of(ib_uctx, 4955 struct bnxt_re_ucontext, 4956 ib_uctx); 4957 struct bnxt_re_user_mmap_entry *bnxt_entry; 4958 struct rdma_user_mmap_entry *rdma_entry; 4959 int ret = 0; 4960 u64 pfn; 4961 4962 rdma_entry = rdma_user_mmap_entry_get(&uctx->ib_uctx, vma); 4963 if (!rdma_entry) 4964 return -EINVAL; 4965 4966 bnxt_entry = container_of(rdma_entry, struct bnxt_re_user_mmap_entry, 4967 rdma_entry); 4968 4969 switch (bnxt_entry->mmap_flag) { 4970 case BNXT_RE_MMAP_WC_DB: 4971 pfn = bnxt_entry->mem_offset >> PAGE_SHIFT; 4972 ret = rdma_user_mmap_io(ib_uctx, vma, pfn, PAGE_SIZE, 4973 pgprot_writecombine(vma->vm_page_prot), 4974 rdma_entry); 4975 break; 4976 case BNXT_RE_MMAP_UC_DB: 4977 pfn = bnxt_entry->mem_offset >> PAGE_SHIFT; 4978 ret = rdma_user_mmap_io(ib_uctx, vma, pfn, PAGE_SIZE, 4979 pgprot_noncached(vma->vm_page_prot), 4980 rdma_entry); 4981 break; 4982 case BNXT_RE_MMAP_SH_PAGE: 4983 ret = vm_insert_page(vma, vma->vm_start, virt_to_page(uctx->shpg)); 4984 break; 4985 case BNXT_RE_MMAP_DBR_BAR: 4986 pfn = bnxt_entry->mem_offset >> PAGE_SHIFT; 4987 ret = rdma_user_mmap_io(ib_uctx, vma, pfn, PAGE_SIZE, 4988 pgprot_noncached(vma->vm_page_prot), 4989 rdma_entry); 4990 break; 4991 case BNXT_RE_MMAP_DBR_PAGE: 4992 case BNXT_RE_MMAP_TOGGLE_PAGE: 4993 /* Driver doesn't expect write access for user space */ 4994 if (vma->vm_flags & VM_WRITE) 4995 ret = -EFAULT; 4996 else 4997 ret = vm_insert_page(vma, vma->vm_start, 4998 virt_to_page((void *)bnxt_entry->mem_offset)); 4999 break; 5000 default: 5001 ret = -EINVAL; 5002 break; 5003 } 5004 5005 rdma_user_mmap_entry_put(rdma_entry); 5006 return ret; 5007 } 5008 5009 void bnxt_re_mmap_free(struct rdma_user_mmap_entry *rdma_entry) 5010 { 5011 struct bnxt_re_user_mmap_entry *bnxt_entry; 5012 5013 bnxt_entry = container_of(rdma_entry, struct bnxt_re_user_mmap_entry, 5014 rdma_entry); 5015 5016 if (bnxt_entry->dpi_valid) 5017 bnxt_qplib_free_uc_dpi(&bnxt_entry->uctx->rdev->qplib_res, 5018 &bnxt_entry->dpi); 5019 5020 kfree(bnxt_entry); 5021 } 5022 5023 int bnxt_re_process_mad(struct ib_device *ibdev, int mad_flags, 5024 u32 port_num, const struct ib_wc *in_wc, 5025 const struct ib_grh *in_grh, 5026 const struct ib_mad *in_mad, struct ib_mad *out_mad, 5027 size_t *out_mad_size, u16 *out_mad_pkey_index) 5028 { 5029 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 5030 struct ib_class_port_info cpi = {}; 5031 int ret = IB_MAD_RESULT_SUCCESS; 5032 int rc = 0; 5033 5034 if (in_mad->mad_hdr.mgmt_class != IB_MGMT_CLASS_PERF_MGMT) 5035 return ret; 5036 5037 switch (in_mad->mad_hdr.attr_id) { 5038 case IB_PMA_CLASS_PORT_INFO: 5039 cpi.capability_mask = IB_PMA_CLASS_CAP_EXT_WIDTH; 5040 memcpy((out_mad->data + 40), &cpi, sizeof(cpi)); 5041 break; 5042 case IB_PMA_PORT_COUNTERS_EXT: 5043 rc = bnxt_re_assign_pma_port_ext_counters(rdev, out_mad); 5044 break; 5045 case IB_PMA_PORT_COUNTERS: 5046 rc = bnxt_re_assign_pma_port_counters(rdev, out_mad); 5047 break; 5048 default: 5049 rc = -EINVAL; 5050 break; 5051 } 5052 if (rc) 5053 return IB_MAD_RESULT_FAILURE; 5054 ret |= IB_MAD_RESULT_REPLY; 5055 return ret; 5056 } 5057