1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright(c) 2020-2021 Intel Corporation. */
3 #ifndef __CXL_MEM_H__
4 #define __CXL_MEM_H__
5 #include <uapi/linux/cxl_mem.h>
6 #include <linux/pci.h>
7 #include <linux/cdev.h>
8 #include <linux/uuid.h>
9 #include <linux/node.h>
10 #include <cxl/event.h>
11 #include <cxl/mailbox.h>
12 #include "cxl.h"
13
14 /* CXL 2.0 8.2.8.5.1.1 Memory Device Status Register */
15 #define CXLMDEV_STATUS_OFFSET 0x0
16 #define CXLMDEV_DEV_FATAL BIT(0)
17 #define CXLMDEV_FW_HALT BIT(1)
18 #define CXLMDEV_STATUS_MEDIA_STATUS_MASK GENMASK(3, 2)
19 #define CXLMDEV_MS_NOT_READY 0
20 #define CXLMDEV_MS_READY 1
21 #define CXLMDEV_MS_ERROR 2
22 #define CXLMDEV_MS_DISABLED 3
23 #define CXLMDEV_READY(status) \
24 (FIELD_GET(CXLMDEV_STATUS_MEDIA_STATUS_MASK, status) == \
25 CXLMDEV_MS_READY)
26 #define CXLMDEV_MBOX_IF_READY BIT(4)
27 #define CXLMDEV_RESET_NEEDED_MASK GENMASK(7, 5)
28 #define CXLMDEV_RESET_NEEDED_NOT 0
29 #define CXLMDEV_RESET_NEEDED_COLD 1
30 #define CXLMDEV_RESET_NEEDED_WARM 2
31 #define CXLMDEV_RESET_NEEDED_HOT 3
32 #define CXLMDEV_RESET_NEEDED_CXL 4
33 #define CXLMDEV_RESET_NEEDED(status) \
34 (FIELD_GET(CXLMDEV_RESET_NEEDED_MASK, status) != \
35 CXLMDEV_RESET_NEEDED_NOT)
36
37 /**
38 * struct cxl_memdev - CXL bus object representing a Type-3 Memory Device
39 * @dev: driver core device object
40 * @cdev: char dev core object for ioctl operations
41 * @cxlds: The device state backing this device
42 * @detach_work: active memdev lost a port in its ancestry
43 * @cxl_nvb: coordinate removal of @cxl_nvd if present
44 * @cxl_nvd: optional bridge to an nvdimm if the device supports pmem
45 * @endpoint: connection to the CXL port topology for this memory device
46 * @attach: creator of this memdev depends on CXL link attach to operate
47 * @id: id number of this memdev instance.
48 * @depth: endpoint port depth
49 * @scrub_cycle: current scrub cycle set for this device
50 * @scrub_region_id: id number of a backed region (if any) for which current scrub cycle set
51 * @err_rec_array: List of xarrarys to store the memdev error records to
52 * check attributes for a memory repair operation are from
53 * current boot.
54 */
55 struct cxl_memdev {
56 struct device dev;
57 struct cdev cdev;
58 struct cxl_dev_state *cxlds;
59 struct work_struct detach_work;
60 struct cxl_nvdimm_bridge *cxl_nvb;
61 struct cxl_nvdimm *cxl_nvd;
62 struct cxl_port *endpoint;
63 const struct cxl_memdev_attach *attach;
64 int id;
65 int depth;
66 u8 scrub_cycle;
67 int scrub_region_id;
68 struct cxl_mem_err_rec *err_rec_array;
69 };
70
to_cxl_memdev(struct device * dev)71 static inline struct cxl_memdev *to_cxl_memdev(struct device *dev)
72 {
73 return container_of(dev, struct cxl_memdev, dev);
74 }
75
cxled_to_port(struct cxl_endpoint_decoder * cxled)76 static inline struct cxl_port *cxled_to_port(struct cxl_endpoint_decoder *cxled)
77 {
78 return to_cxl_port(cxled->cxld.dev.parent);
79 }
80
cxlrd_to_port(struct cxl_root_decoder * cxlrd)81 static inline struct cxl_port *cxlrd_to_port(struct cxl_root_decoder *cxlrd)
82 {
83 return to_cxl_port(cxlrd->cxlsd.cxld.dev.parent);
84 }
85
86 static inline struct cxl_memdev *
cxled_to_memdev(struct cxl_endpoint_decoder * cxled)87 cxled_to_memdev(struct cxl_endpoint_decoder *cxled)
88 {
89 struct cxl_port *port = to_cxl_port(cxled->cxld.dev.parent);
90
91 return to_cxl_memdev(port->uport_dev);
92 }
93
94 bool is_cxl_memdev(const struct device *dev);
is_cxl_endpoint(struct cxl_port * port)95 static inline bool is_cxl_endpoint(struct cxl_port *port)
96 {
97 return is_cxl_memdev(port->uport_dev);
98 }
99
100 struct cxl_memdev_attach {
101 int (*probe)(struct cxl_memdev *cxlmd);
102 };
103
104 /**
105 * struct cxl_attach_region - coordinate mapping a region at memdev registration
106 * @attach: common core attachment descriptor
107 * @hpa_range: physical address range of the region
108 *
109 * For the common simple case of a CXL device with private (non-general purpose
110 * / "accelerator") memory, enumerate firmware instantiated region, or
111 * instantiate a region for the device's capacity. Destroy the region on detach.
112 */
113 struct cxl_attach_region {
114 struct cxl_memdev_attach attach;
115 struct range hpa_range;
116 };
117
118 #ifdef CONFIG_CXL_REGION
119 int cxl_memdev_attach_region(struct cxl_memdev *cxlmd);
120 #else
cxl_memdev_attach_region(struct cxl_memdev * cxlmd)121 static inline int cxl_memdev_attach_region(struct cxl_memdev *cxlmd)
122 {
123 return -EOPNOTSUPP;
124 }
125 #endif
126
127 struct cxl_memdev *devm_cxl_add_classdev(struct cxl_dev_state *cxlds);
128 struct cxl_memdev *__devm_cxl_add_memdev(struct cxl_dev_state *cxlds,
129 const struct cxl_memdev_attach *attach);
130 int devm_cxl_sanitize_setup_notifier(struct device *host,
131 struct cxl_memdev *cxlmd);
132 struct cxl_memdev_state;
133 int devm_cxl_setup_fw_upload(struct device *host, struct cxl_memdev_state *mds);
134 int devm_cxl_dpa_reserve(struct cxl_endpoint_decoder *cxled,
135 resource_size_t base, resource_size_t len,
136 resource_size_t skipped);
137
138 struct cxl_dpa_info {
139 u64 size;
140 struct cxl_dpa_part_info {
141 struct range range;
142 enum cxl_partition_mode mode;
143 } part[CXL_NR_PARTITIONS_MAX];
144 int nr_partitions;
145 };
146
147 int cxl_dpa_setup(struct cxl_dev_state *cxlds, const struct cxl_dpa_info *info);
148
cxl_ep_load(struct cxl_port * port,struct cxl_memdev * cxlmd)149 static inline struct cxl_ep *cxl_ep_load(struct cxl_port *port,
150 struct cxl_memdev *cxlmd)
151 {
152 if (!port)
153 return NULL;
154
155 return xa_load(&port->endpoints, (unsigned long)&cxlmd->dev);
156 }
157
158 /*
159 * Per CXL 3.0 Section 8.2.8.4.5.1
160 */
161 #define CMD_CMD_RC_TABLE \
162 C(SUCCESS, 0, NULL), \
163 C(BACKGROUND, -ENXIO, "background cmd started successfully"), \
164 C(INPUT, -ENXIO, "cmd input was invalid"), \
165 C(UNSUPPORTED, -ENXIO, "cmd is not supported"), \
166 C(INTERNAL, -ENXIO, "internal device error"), \
167 C(RETRY, -ENXIO, "temporary error, retry once"), \
168 C(BUSY, -ENXIO, "ongoing background operation"), \
169 C(MEDIADISABLED, -ENXIO, "media access is disabled"), \
170 C(FWINPROGRESS, -ENXIO, "one FW package can be transferred at a time"), \
171 C(FWOOO, -ENXIO, "FW package content was transferred out of order"), \
172 C(FWAUTH, -ENXIO, "FW package authentication failed"), \
173 C(FWSLOT, -ENXIO, "FW slot is not supported for requested operation"), \
174 C(FWROLLBACK, -ENXIO, "rolled back to the previous active FW"), \
175 C(FWRESET, -ENXIO, "FW failed to activate, needs cold reset"), \
176 C(HANDLE, -ENXIO, "one or more Event Record Handles were invalid"), \
177 C(PADDR, -EFAULT, "physical address specified is invalid"), \
178 C(POISONLMT, -EBUSY, "poison injection limit has been reached"), \
179 C(MEDIAFAILURE, -ENXIO, "permanent issue with the media"), \
180 C(ABORT, -ENXIO, "background cmd was aborted by device"), \
181 C(SECURITY, -ENXIO, "not valid in the current security state"), \
182 C(PASSPHRASE, -ENXIO, "phrase doesn't match current set passphrase"), \
183 C(MBUNSUPPORTED, -ENXIO, "unsupported on the mailbox it was issued on"),\
184 C(PAYLOADLEN, -ENXIO, "invalid payload length"), \
185 C(LOG, -ENXIO, "invalid or unsupported log page"), \
186 C(INTERRUPTED, -ENXIO, "asynchronous event occurred"), \
187 C(FEATUREVERSION, -ENXIO, "unsupported feature version"), \
188 C(FEATURESELVALUE, -ENXIO, "unsupported feature selection value"), \
189 C(FEATURETRANSFERIP, -ENXIO, "feature transfer in progress"), \
190 C(FEATURETRANSFEROOO, -ENXIO, "feature transfer out of order"), \
191 C(RESOURCEEXHAUSTED, -ENXIO, "resources are exhausted"), \
192 C(EXTLIST, -ENXIO, "invalid Extent List"), \
193
194 #undef C
195 #define C(a, b, c) CXL_MBOX_CMD_RC_##a
196 enum { CMD_CMD_RC_TABLE };
197 #undef C
198 #define C(a, b, c) { b, c }
199 struct cxl_mbox_cmd_rc {
200 int err;
201 const char *desc;
202 };
203
204 static const
205 struct cxl_mbox_cmd_rc cxl_mbox_cmd_rctable[] ={ CMD_CMD_RC_TABLE };
206 #undef C
207
cxl_mbox_cmd_rc2str(struct cxl_mbox_cmd * mbox_cmd)208 static inline const char *cxl_mbox_cmd_rc2str(struct cxl_mbox_cmd *mbox_cmd)
209 {
210 return cxl_mbox_cmd_rctable[mbox_cmd->return_code].desc;
211 }
212
cxl_mbox_cmd_rc2errno(struct cxl_mbox_cmd * mbox_cmd)213 static inline int cxl_mbox_cmd_rc2errno(struct cxl_mbox_cmd *mbox_cmd)
214 {
215 return cxl_mbox_cmd_rctable[mbox_cmd->return_code].err;
216 }
217
218 /*
219 * CXL 2.0 - Memory capacity multiplier
220 * See Section 8.2.9.5
221 *
222 * Volatile, Persistent, and Partition capacities are specified to be in
223 * multiples of 256MB - define a multiplier to convert to/from bytes.
224 */
225 #define CXL_CAPACITY_MULTIPLIER SZ_256M
226
227 /*
228 * Event Interrupt Policy
229 *
230 * CXL rev 3.0 section 8.2.9.2.4; Table 8-52
231 */
232 enum cxl_event_int_mode {
233 CXL_INT_NONE = 0x00,
234 CXL_INT_MSI_MSIX = 0x01,
235 CXL_INT_FW = 0x02
236 };
237 struct cxl_event_interrupt_policy {
238 u8 info_settings;
239 u8 warn_settings;
240 u8 failure_settings;
241 u8 fatal_settings;
242 } __packed;
243
244 /**
245 * struct cxl_event_state - Event log driver state
246 *
247 * @buf: Buffer to receive event data
248 * @log_lock: Serialize event_buf and log use
249 */
250 struct cxl_event_state {
251 struct cxl_get_event_payload *buf;
252 struct mutex log_lock;
253 };
254
255 /* Device enabled poison commands */
256 enum poison_cmd_enabled_bits {
257 CXL_POISON_ENABLED_LIST,
258 CXL_POISON_ENABLED_INJECT,
259 CXL_POISON_ENABLED_CLEAR,
260 CXL_POISON_ENABLED_SCAN_CAPS,
261 CXL_POISON_ENABLED_SCAN_MEDIA,
262 CXL_POISON_ENABLED_SCAN_RESULTS,
263 CXL_POISON_ENABLED_MAX
264 };
265
266 /* Device enabled security commands */
267 enum security_cmd_enabled_bits {
268 CXL_SEC_ENABLED_SANITIZE,
269 CXL_SEC_ENABLED_SECURE_ERASE,
270 CXL_SEC_ENABLED_GET_SECURITY_STATE,
271 CXL_SEC_ENABLED_SET_PASSPHRASE,
272 CXL_SEC_ENABLED_DISABLE_PASSPHRASE,
273 CXL_SEC_ENABLED_UNLOCK,
274 CXL_SEC_ENABLED_FREEZE_SECURITY,
275 CXL_SEC_ENABLED_PASSPHRASE_SECURE_ERASE,
276 CXL_SEC_ENABLED_MAX
277 };
278
279 /**
280 * struct cxl_poison_state - Driver poison state info
281 *
282 * @max_errors: Maximum media error records held in device cache
283 * @enabled_cmds: All poison commands enabled in the CEL
284 * @list_out: The poison list payload returned by device
285 * @mutex: Protect reads of the poison list
286 *
287 * Reads of the poison list are synchronized to ensure that a reader
288 * does not get an incomplete list because their request overlapped
289 * (was interrupted or preceded by) another read request of the same
290 * DPA range. CXL Spec 3.0 Section 8.2.9.8.4.1
291 */
292 struct cxl_poison_state {
293 u32 max_errors;
294 DECLARE_BITMAP(enabled_cmds, CXL_POISON_ENABLED_MAX);
295 struct cxl_mbox_poison_out *list_out;
296 struct mutex mutex; /* Protect reads of poison list */
297 };
298
299 /*
300 * Get FW Info
301 * CXL rev 3.0 section 8.2.9.3.1; Table 8-56
302 */
303 struct cxl_mbox_get_fw_info {
304 u8 num_slots;
305 u8 slot_info;
306 u8 activation_cap;
307 u8 reserved[13];
308 char slot_1_revision[16];
309 char slot_2_revision[16];
310 char slot_3_revision[16];
311 char slot_4_revision[16];
312 } __packed;
313
314 #define CXL_FW_INFO_SLOT_INFO_CUR_MASK GENMASK(2, 0)
315 #define CXL_FW_INFO_SLOT_INFO_NEXT_MASK GENMASK(5, 3)
316 #define CXL_FW_INFO_SLOT_INFO_NEXT_SHIFT 3
317 #define CXL_FW_INFO_ACTIVATION_CAP_HAS_LIVE_ACTIVATE BIT(0)
318
319 /*
320 * Transfer FW Input Payload
321 * CXL rev 3.0 section 8.2.9.3.2; Table 8-57
322 */
323 struct cxl_mbox_transfer_fw {
324 u8 action;
325 u8 slot;
326 u8 reserved[2];
327 __le32 offset;
328 u8 reserved2[0x78];
329 u8 data[];
330 } __packed;
331
332 #define CXL_FW_TRANSFER_ACTION_FULL 0x0
333 #define CXL_FW_TRANSFER_ACTION_INITIATE 0x1
334 #define CXL_FW_TRANSFER_ACTION_CONTINUE 0x2
335 #define CXL_FW_TRANSFER_ACTION_END 0x3
336 #define CXL_FW_TRANSFER_ACTION_ABORT 0x4
337
338 /*
339 * CXL rev 3.0 section 8.2.9.3.2 mandates 128-byte alignment for FW packages
340 * and for each part transferred in a Transfer FW command.
341 */
342 #define CXL_FW_TRANSFER_ALIGNMENT 128
343
344 /*
345 * Activate FW Input Payload
346 * CXL rev 3.0 section 8.2.9.3.3; Table 8-58
347 */
348 struct cxl_mbox_activate_fw {
349 u8 action;
350 u8 slot;
351 } __packed;
352
353 #define CXL_FW_ACTIVATE_ONLINE 0x0
354 #define CXL_FW_ACTIVATE_OFFLINE 0x1
355
356 /* FW state bits */
357 #define CXL_FW_STATE_BITS 32
358 #define CXL_FW_CANCEL 0
359
360 /**
361 * struct cxl_fw_state - Firmware upload / activation state
362 *
363 * @state: fw_uploader state bitmask
364 * @oneshot: whether the fw upload fits in a single transfer
365 * @num_slots: Number of FW slots available
366 * @cur_slot: Slot number currently active
367 * @next_slot: Slot number for the new firmware
368 */
369 struct cxl_fw_state {
370 DECLARE_BITMAP(state, CXL_FW_STATE_BITS);
371 bool oneshot;
372 int num_slots;
373 int cur_slot;
374 int next_slot;
375 };
376
377 /**
378 * struct cxl_security_state - Device security state
379 *
380 * @state: state of last security operation
381 * @enabled_cmds: All security commands enabled in the CEL
382 * @poll_tmo_secs: polling timeout
383 * @sanitize_active: sanitize completion pending
384 * @poll_dwork: polling work item
385 * @sanitize_node: sanitation sysfs file to notify
386 */
387 struct cxl_security_state {
388 unsigned long state;
389 DECLARE_BITMAP(enabled_cmds, CXL_SEC_ENABLED_MAX);
390 int poll_tmo_secs;
391 bool sanitize_active;
392 struct delayed_work poll_dwork;
393 struct kernfs_node *sanitize_node;
394 };
395
cxl_pmem_size(struct cxl_dev_state * cxlds)396 static inline resource_size_t cxl_pmem_size(struct cxl_dev_state *cxlds)
397 {
398 /*
399 * Static PMEM may be at partition index 0 when there is no static RAM
400 * capacity.
401 */
402 for (int i = 0; i < cxlds->nr_partitions; i++)
403 if (cxlds->part[i].mode == CXL_PARTMODE_PMEM)
404 return resource_size(&cxlds->part[i].res);
405 return 0;
406 }
407
mbox_to_cxlds(struct cxl_mailbox * cxl_mbox)408 static inline struct cxl_dev_state *mbox_to_cxlds(struct cxl_mailbox *cxl_mbox)
409 {
410 return dev_get_drvdata(cxl_mbox->host);
411 }
412
413 /**
414 * struct cxl_memdev_state - Generic Type-3 Memory Device Class driver data
415 *
416 * CXL 8.1.12.1 PCI Header - Class Code Register Memory Device defines
417 * common memory device functionality like the presence of a mailbox and
418 * the functionality related to that like Identify Memory Device and Get
419 * Partition Info
420 * @cxlds: Core driver state common across Type-2 and Type-3 devices
421 * @lsa_size: Size of Label Storage Area
422 * (CXL 2.0 8.2.9.5.1.1 Identify Memory Device)
423 * @firmware_version: Firmware version for the memory device.
424 * @total_bytes: sum of all possible capacities
425 * @volatile_only_bytes: hard volatile capacity
426 * @persistent_only_bytes: hard persistent capacity
427 * @partition_align_bytes: alignment size for partition-able capacity
428 * @active_volatile_bytes: sum of hard + soft volatile
429 * @active_persistent_bytes: sum of hard + soft persistent
430 * @event: event log driver state
431 * @poison: poison driver state info
432 * @security: security driver state info
433 * @fw: firmware upload / activation state
434 *
435 * See CXL 3.0 8.2.9.8.2 Capacity Configuration and Label Storage for
436 * details on capacity parameters.
437 */
438 struct cxl_memdev_state {
439 struct cxl_dev_state cxlds;
440 size_t lsa_size;
441 char firmware_version[0x10];
442 u64 total_bytes;
443 u64 volatile_only_bytes;
444 u64 persistent_only_bytes;
445 u64 partition_align_bytes;
446 u64 active_volatile_bytes;
447 u64 active_persistent_bytes;
448
449 struct cxl_event_state event;
450 struct cxl_poison_state poison;
451 struct cxl_security_state security;
452 struct cxl_fw_state fw;
453 };
454
455 static inline struct cxl_memdev_state *
to_cxl_memdev_state(struct cxl_dev_state * cxlds)456 to_cxl_memdev_state(struct cxl_dev_state *cxlds)
457 {
458 if (cxlds->type != CXL_DEVTYPE_CLASSMEM)
459 return NULL;
460 return container_of(cxlds, struct cxl_memdev_state, cxlds);
461 }
462
463 enum cxl_opcode {
464 CXL_MBOX_OP_INVALID = 0x0000,
465 CXL_MBOX_OP_RAW = CXL_MBOX_OP_INVALID,
466 CXL_MBOX_OP_GET_EVENT_RECORD = 0x0100,
467 CXL_MBOX_OP_CLEAR_EVENT_RECORD = 0x0101,
468 CXL_MBOX_OP_GET_EVT_INT_POLICY = 0x0102,
469 CXL_MBOX_OP_SET_EVT_INT_POLICY = 0x0103,
470 CXL_MBOX_OP_GET_FW_INFO = 0x0200,
471 CXL_MBOX_OP_TRANSFER_FW = 0x0201,
472 CXL_MBOX_OP_ACTIVATE_FW = 0x0202,
473 CXL_MBOX_OP_GET_TIMESTAMP = 0x0300,
474 CXL_MBOX_OP_SET_TIMESTAMP = 0x0301,
475 CXL_MBOX_OP_GET_SUPPORTED_LOGS = 0x0400,
476 CXL_MBOX_OP_GET_LOG = 0x0401,
477 CXL_MBOX_OP_GET_LOG_CAPS = 0x0402,
478 CXL_MBOX_OP_CLEAR_LOG = 0x0403,
479 CXL_MBOX_OP_GET_SUP_LOG_SUBLIST = 0x0405,
480 CXL_MBOX_OP_GET_SUPPORTED_FEATURES = 0x0500,
481 CXL_MBOX_OP_GET_FEATURE = 0x0501,
482 CXL_MBOX_OP_SET_FEATURE = 0x0502,
483 CXL_MBOX_OP_DO_MAINTENANCE = 0x0600,
484 CXL_MBOX_OP_IDENTIFY = 0x4000,
485 CXL_MBOX_OP_GET_PARTITION_INFO = 0x4100,
486 CXL_MBOX_OP_SET_PARTITION_INFO = 0x4101,
487 CXL_MBOX_OP_GET_LSA = 0x4102,
488 CXL_MBOX_OP_SET_LSA = 0x4103,
489 CXL_MBOX_OP_GET_HEALTH_INFO = 0x4200,
490 CXL_MBOX_OP_GET_ALERT_CONFIG = 0x4201,
491 CXL_MBOX_OP_SET_ALERT_CONFIG = 0x4202,
492 CXL_MBOX_OP_GET_SHUTDOWN_STATE = 0x4203,
493 CXL_MBOX_OP_SET_SHUTDOWN_STATE = 0x4204,
494 CXL_MBOX_OP_GET_POISON = 0x4300,
495 CXL_MBOX_OP_INJECT_POISON = 0x4301,
496 CXL_MBOX_OP_CLEAR_POISON = 0x4302,
497 CXL_MBOX_OP_GET_SCAN_MEDIA_CAPS = 0x4303,
498 CXL_MBOX_OP_SCAN_MEDIA = 0x4304,
499 CXL_MBOX_OP_GET_SCAN_MEDIA = 0x4305,
500 CXL_MBOX_OP_SANITIZE = 0x4400,
501 CXL_MBOX_OP_SECURE_ERASE = 0x4401,
502 CXL_MBOX_OP_GET_SECURITY_STATE = 0x4500,
503 CXL_MBOX_OP_SET_PASSPHRASE = 0x4501,
504 CXL_MBOX_OP_DISABLE_PASSPHRASE = 0x4502,
505 CXL_MBOX_OP_UNLOCK = 0x4503,
506 CXL_MBOX_OP_FREEZE_SECURITY = 0x4504,
507 CXL_MBOX_OP_PASSPHRASE_SECURE_ERASE = 0x4505,
508 CXL_MBOX_OP_MAX = 0x10000
509 };
510
511 #define DEFINE_CXL_CEL_UUID \
512 UUID_INIT(0xda9c0b5, 0xbf41, 0x4b78, 0x8f, 0x79, 0x96, 0xb1, 0x62, \
513 0x3b, 0x3f, 0x17)
514
515 #define DEFINE_CXL_VENDOR_DEBUG_UUID \
516 UUID_INIT(0x5e1819d9, 0x11a9, 0x400c, 0x81, 0x1f, 0xd6, 0x07, 0x19, \
517 0x40, 0x3d, 0x86)
518
519 struct cxl_mbox_get_supported_logs {
520 __le16 entries;
521 u8 rsvd[6];
522 struct cxl_gsl_entry {
523 uuid_t uuid;
524 __le32 size;
525 } __packed entry[];
526 } __packed;
527
528 struct cxl_cel_entry {
529 __le16 opcode;
530 __le16 effect;
531 } __packed;
532
533 struct cxl_mbox_get_log {
534 uuid_t uuid;
535 __le32 offset;
536 __le32 length;
537 } __packed;
538
539 /* See CXL 2.0 Table 175 Identify Memory Device Output Payload */
540 struct cxl_mbox_identify {
541 char fw_revision[0x10];
542 __le64 total_capacity;
543 __le64 volatile_capacity;
544 __le64 persistent_capacity;
545 __le64 partition_align;
546 __le16 info_event_log_size;
547 __le16 warning_event_log_size;
548 __le16 failure_event_log_size;
549 __le16 fatal_event_log_size;
550 __le32 lsa_size;
551 u8 poison_list_max_mer[3];
552 __le16 inject_poison_limit;
553 u8 poison_caps;
554 u8 qos_telemetry_caps;
555 } __packed;
556
557 /*
558 * General Media Event Record UUID
559 * CXL rev 3.0 Section 8.2.9.2.1.1; Table 8-43
560 */
561 #define CXL_EVENT_GEN_MEDIA_UUID \
562 UUID_INIT(0xfbcd0a77, 0xc260, 0x417f, 0x85, 0xa9, 0x08, 0x8b, 0x16, \
563 0x21, 0xeb, 0xa6)
564
565 /*
566 * DRAM Event Record UUID
567 * CXL rev 3.0 section 8.2.9.2.1.2; Table 8-44
568 */
569 #define CXL_EVENT_DRAM_UUID \
570 UUID_INIT(0x601dcbb3, 0x9c06, 0x4eab, 0xb8, 0xaf, 0x4e, 0x9b, 0xfb, \
571 0x5c, 0x96, 0x24)
572
573 /*
574 * Memory Module Event Record UUID
575 * CXL rev 3.0 section 8.2.9.2.1.3; Table 8-45
576 */
577 #define CXL_EVENT_MEM_MODULE_UUID \
578 UUID_INIT(0xfe927475, 0xdd59, 0x4339, 0xa5, 0x86, 0x79, 0xba, 0xb1, \
579 0x13, 0xb7, 0x74)
580
581 /*
582 * Memory Sparing Event Record UUID
583 * CXL rev 3.2 section 8.2.10.2.1.4: Table 8-60
584 */
585 #define CXL_EVENT_MEM_SPARING_UUID \
586 UUID_INIT(0xe71f3a40, 0x2d29, 0x4092, 0x8a, 0x39, 0x4d, 0x1c, 0x96, \
587 0x6c, 0x7c, 0x65)
588
589 /*
590 * Get Event Records output payload
591 * CXL rev 3.0 section 8.2.9.2.2; Table 8-50
592 */
593 #define CXL_GET_EVENT_FLAG_OVERFLOW BIT(0)
594 #define CXL_GET_EVENT_FLAG_MORE_RECORDS BIT(1)
595 struct cxl_get_event_payload {
596 u8 flags;
597 u8 reserved1;
598 __le16 overflow_err_count;
599 __le64 first_overflow_timestamp;
600 __le64 last_overflow_timestamp;
601 __le16 record_count;
602 u8 reserved2[10];
603 struct cxl_event_record_raw records[];
604 } __packed;
605
606 /*
607 * CXL rev 3.0 section 8.2.9.2.2; Table 8-49
608 */
609 enum cxl_event_log_type {
610 CXL_EVENT_TYPE_INFO = 0x00,
611 CXL_EVENT_TYPE_WARN,
612 CXL_EVENT_TYPE_FAIL,
613 CXL_EVENT_TYPE_FATAL,
614 CXL_EVENT_TYPE_MAX
615 };
616
617 /*
618 * Clear Event Records input payload
619 * CXL rev 3.0 section 8.2.9.2.3; Table 8-51
620 */
621 struct cxl_mbox_clear_event_payload {
622 u8 event_log; /* enum cxl_event_log_type */
623 u8 clear_flags;
624 u8 nr_recs;
625 u8 reserved[3];
626 __le16 handles[];
627 } __packed;
628 #define CXL_CLEAR_EVENT_MAX_HANDLES U8_MAX
629
630 struct cxl_mbox_get_partition_info {
631 __le64 active_volatile_cap;
632 __le64 active_persistent_cap;
633 __le64 next_volatile_cap;
634 __le64 next_persistent_cap;
635 } __packed;
636
637 struct cxl_mbox_get_lsa {
638 __le32 offset;
639 __le32 length;
640 } __packed;
641
642 struct cxl_mbox_set_lsa {
643 __le32 offset;
644 __le32 reserved;
645 u8 data[];
646 } __packed;
647
648 struct cxl_mbox_set_partition_info {
649 __le64 volatile_capacity;
650 u8 flags;
651 } __packed;
652
653 #define CXL_SET_PARTITION_IMMEDIATE_FLAG BIT(0)
654
655 /* Get Health Info Output Payload CXL 3.2 Spec 8.2.10.9.3.1 Table 8-148 */
656 struct cxl_mbox_get_health_info_out {
657 u8 health_status;
658 u8 media_status;
659 u8 additional_status;
660 u8 life_used;
661 __le16 device_temperature;
662 __le32 dirty_shutdown_cnt;
663 __le32 corrected_volatile_error_cnt;
664 __le32 corrected_persistent_error_cnt;
665 } __packed;
666
667 /* Set Shutdown State Input Payload CXL 3.2 Spec 8.2.10.9.3.5 Table 8-152 */
668 struct cxl_mbox_set_shutdown_state_in {
669 u8 state;
670 } __packed;
671
672 /* Set Timestamp CXL 3.0 Spec 8.2.9.4.2 */
673 struct cxl_mbox_set_timestamp_in {
674 __le64 timestamp;
675
676 } __packed;
677
678 /* Get Poison List CXL 3.0 Spec 8.2.9.8.4.1 */
679 struct cxl_mbox_poison_in {
680 __le64 offset;
681 __le64 length;
682 } __packed;
683
684 struct cxl_mbox_poison_out {
685 u8 flags;
686 u8 rsvd1;
687 __le64 overflow_ts;
688 __le16 count;
689 u8 rsvd2[20];
690 struct cxl_poison_record {
691 __le64 address;
692 __le32 length;
693 __le32 rsvd;
694 } __packed record[];
695 } __packed;
696
697 /*
698 * Get Poison List address field encodes the starting
699 * address of poison, and the source of the poison.
700 */
701 #define CXL_POISON_START_MASK GENMASK_ULL(63, 6)
702 #define CXL_POISON_SOURCE_MASK GENMASK(2, 0)
703
704 /* Get Poison List record length is in units of 64 bytes */
705 #define CXL_POISON_LEN_MULT 64
706
707 /* Kernel defined maximum for a list of poison errors */
708 #define CXL_POISON_LIST_MAX 1024
709
710 /* Get Poison List: Payload out flags */
711 #define CXL_POISON_FLAG_MORE BIT(0)
712 #define CXL_POISON_FLAG_OVERFLOW BIT(1)
713 #define CXL_POISON_FLAG_SCANNING BIT(2)
714
715 /* Get Poison List: Poison Source */
716 #define CXL_POISON_SOURCE_UNKNOWN 0
717 #define CXL_POISON_SOURCE_EXTERNAL 1
718 #define CXL_POISON_SOURCE_INTERNAL 2
719 #define CXL_POISON_SOURCE_INJECTED 3
720 #define CXL_POISON_SOURCE_VENDOR 7
721
722 /* Inject & Clear Poison CXL 3.0 Spec 8.2.9.8.4.2/3 */
723 struct cxl_mbox_inject_poison {
724 __le64 address;
725 };
726
727 /* Clear Poison CXL 3.0 Spec 8.2.9.8.4.3 */
728 struct cxl_mbox_clear_poison {
729 __le64 address;
730 u8 write_data[CXL_POISON_LEN_MULT];
731 } __packed;
732
733 /**
734 * struct cxl_mem_command - Driver representation of a memory device command
735 * @info: Command information as it exists for the UAPI
736 * @opcode: The actual bits used for the mailbox protocol
737 * @flags: Set of flags effecting driver behavior.
738 *
739 * * %CXL_CMD_FLAG_FORCE_ENABLE: In cases of error, commands with this flag
740 * will be enabled by the driver regardless of what hardware may have
741 * advertised.
742 *
743 * The cxl_mem_command is the driver's internal representation of commands that
744 * are supported by the driver. Some of these commands may not be supported by
745 * the hardware. The driver will use @info to validate the fields passed in by
746 * the user then submit the @opcode to the hardware.
747 *
748 * See struct cxl_command_info.
749 */
750 struct cxl_mem_command {
751 struct cxl_command_info info;
752 enum cxl_opcode opcode;
753 u32 flags;
754 #define CXL_CMD_FLAG_FORCE_ENABLE BIT(0)
755 };
756
757 #define CXL_PMEM_SEC_STATE_USER_PASS_SET 0x01
758 #define CXL_PMEM_SEC_STATE_MASTER_PASS_SET 0x02
759 #define CXL_PMEM_SEC_STATE_LOCKED 0x04
760 #define CXL_PMEM_SEC_STATE_FROZEN 0x08
761 #define CXL_PMEM_SEC_STATE_USER_PLIMIT 0x10
762 #define CXL_PMEM_SEC_STATE_MASTER_PLIMIT 0x20
763
764 /* set passphrase input payload */
765 struct cxl_set_pass {
766 u8 type;
767 u8 reserved[31];
768 /* CXL field using NVDIMM define, same length */
769 u8 old_pass[NVDIMM_PASSPHRASE_LEN];
770 u8 new_pass[NVDIMM_PASSPHRASE_LEN];
771 } __packed;
772
773 /* disable passphrase input payload */
774 struct cxl_disable_pass {
775 u8 type;
776 u8 reserved[31];
777 u8 pass[NVDIMM_PASSPHRASE_LEN];
778 } __packed;
779
780 /* passphrase secure erase payload */
781 struct cxl_pass_erase {
782 u8 type;
783 u8 reserved[31];
784 u8 pass[NVDIMM_PASSPHRASE_LEN];
785 } __packed;
786
787 enum {
788 CXL_PMEM_SEC_PASS_MASTER = 0,
789 CXL_PMEM_SEC_PASS_USER,
790 };
791
792 int cxl_internal_send_cmd(struct cxl_mailbox *cxl_mbox,
793 struct cxl_mbox_cmd *cmd);
794 int cxl_dev_state_identify(struct cxl_memdev_state *mds);
795 int cxl_await_media_ready(struct cxl_dev_state *cxlds);
796 int cxl_enumerate_cmds(struct cxl_memdev_state *mds);
797 int cxl_mem_dpa_fetch(struct cxl_memdev_state *mds, struct cxl_dpa_info *info);
798 struct cxl_memdev_state *cxl_memdev_state_create(struct device *dev, u64 serial,
799 u16 dvsec);
800 void set_exclusive_cxl_commands(struct cxl_memdev_state *mds,
801 unsigned long *cmds);
802 void clear_exclusive_cxl_commands(struct cxl_memdev_state *mds,
803 unsigned long *cmds);
804 void cxl_mem_get_event_records(struct cxl_memdev_state *mds, u32 status);
805 void cxl_event_trace_record(struct cxl_memdev *cxlmd,
806 enum cxl_event_log_type type,
807 enum cxl_event_type event_type,
808 const uuid_t *uuid, union cxl_event *evt);
809 int cxl_get_dirty_count(struct cxl_memdev_state *mds, u32 *count);
810 int cxl_arm_dirty_shutdown(struct cxl_memdev_state *mds);
811 int cxl_set_timestamp(struct cxl_memdev_state *mds);
812 int cxl_poison_state_init(struct cxl_memdev_state *mds);
813 int cxl_mem_get_poison(struct cxl_memdev *cxlmd, u64 offset, u64 len,
814 struct cxl_region *cxlr);
815 int cxl_trigger_poison_list(struct cxl_memdev *cxlmd);
816 int cxl_inject_poison(struct cxl_memdev *cxlmd, u64 dpa);
817 int cxl_clear_poison(struct cxl_memdev *cxlmd, u64 dpa);
818 int cxl_inject_poison_locked(struct cxl_memdev *cxlmd, u64 dpa);
819 int cxl_clear_poison_locked(struct cxl_memdev *cxlmd, u64 dpa);
820
821 #ifdef CONFIG_CXL_EDAC_MEM_FEATURES
822 int devm_cxl_memdev_edac_register(struct cxl_memdev *cxlmd);
823 int devm_cxl_region_edac_register(struct cxl_region *cxlr);
824 int cxl_store_rec_gen_media(struct cxl_memdev *cxlmd, union cxl_event *evt);
825 int cxl_store_rec_dram(struct cxl_memdev *cxlmd, union cxl_event *evt);
826 #else
devm_cxl_memdev_edac_register(struct cxl_memdev * cxlmd)827 static inline int devm_cxl_memdev_edac_register(struct cxl_memdev *cxlmd)
828 { return 0; }
devm_cxl_region_edac_register(struct cxl_region * cxlr)829 static inline int devm_cxl_region_edac_register(struct cxl_region *cxlr)
830 { return 0; }
cxl_store_rec_gen_media(struct cxl_memdev * cxlmd,union cxl_event * evt)831 static inline int cxl_store_rec_gen_media(struct cxl_memdev *cxlmd,
832 union cxl_event *evt)
833 { return 0; }
cxl_store_rec_dram(struct cxl_memdev * cxlmd,union cxl_event * evt)834 static inline int cxl_store_rec_dram(struct cxl_memdev *cxlmd,
835 union cxl_event *evt)
836 { return 0; }
837 #endif
838
839 #ifdef CONFIG_CXL_SUSPEND
840 void cxl_mem_active_inc(void);
841 void cxl_mem_active_dec(void);
842 #else
cxl_mem_active_inc(void)843 static inline void cxl_mem_active_inc(void)
844 {
845 }
cxl_mem_active_dec(void)846 static inline void cxl_mem_active_dec(void)
847 {
848 }
849 #endif
850
851 int cxl_mem_sanitize(struct cxl_memdev *cxlmd, u16 cmd);
852
853 /**
854 * struct cxl_hdm - HDM Decoder registers and cached / decoded capabilities
855 * @regs: mapped registers, see devm_cxl_setup_hdm()
856 * @decoder_count: number of decoders for this port
857 * @target_count: for switch decoders, max downstream port targets
858 * @interleave_mask: interleave granularity capability, see check_interleave_cap()
859 * @iw_cap_mask: bitmask of supported interleave ways, see check_interleave_cap()
860 * @port: mapped cxl_port, see devm_cxl_setup_hdm()
861 */
862 struct cxl_hdm {
863 struct cxl_component_regs regs;
864 int decoder_count;
865 unsigned int target_count;
866 unsigned int interleave_mask;
867 unsigned long iw_cap_mask;
868 struct cxl_port *port;
869 };
870
871 struct seq_file;
872 struct dentry *cxl_debugfs_create_dir(const char *dir);
873 void cxl_dpa_debug(struct seq_file *file, struct cxl_dev_state *cxlds);
874 #endif /* __CXL_MEM_H__ */
875