1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2021 Analog Devices, Inc.
4 * Author: Cosmin Tanislav <cosmin.tanislav@analog.com>
5 */
6
7 #include <linux/bitfield.h>
8 #include <linux/bitops.h>
9 #include <linux/iio/buffer.h>
10 #include <linux/iio/events.h>
11 #include <linux/iio/iio.h>
12 #include <linux/iio/kfifo_buf.h>
13 #include <linux/iio/sysfs.h>
14 #include <linux/interrupt.h>
15 #include <linux/irq.h>
16 #include <linux/mod_devicetable.h>
17 #include <linux/regmap.h>
18 #include <linux/regulator/consumer.h>
19 #include <linux/unaligned.h>
20
21 #include "adxl367.h"
22
23 #define ADXL367_REG_DEVID 0x00
24 #define ADXL367_DEVID_AD 0xAD
25
26 #define ADXL367_REG_STATUS 0x0B
27 #define ADXL367_STATUS_INACT_MASK BIT(5)
28 #define ADXL367_STATUS_ACT_MASK BIT(4)
29 #define ADXL367_STATUS_FIFO_FULL_MASK BIT(2)
30
31 #define ADXL367_FIFO_ENT_H_MASK GENMASK(1, 0)
32
33 #define ADXL367_REG_X_DATA_H 0x0E
34 #define ADXL367_REG_Y_DATA_H 0x10
35 #define ADXL367_REG_Z_DATA_H 0x12
36 #define ADXL367_REG_TEMP_DATA_H 0x14
37 #define ADXL367_REG_EX_ADC_DATA_H 0x16
38 #define ADXL367_DATA_MASK GENMASK(15, 2)
39
40 #define ADXL367_TEMP_25C 165
41 #define ADXL367_TEMP_PER_C 54
42
43 #define ADXL367_VOLTAGE_OFFSET 8192
44 #define ADXL367_VOLTAGE_MAX_MV 1000
45 #define ADXL367_VOLTAGE_MAX_RAW GENMASK(13, 0)
46
47 #define ADXL367_REG_RESET 0x1F
48 #define ADXL367_RESET_CODE 0x52
49
50 #define ADXL367_REG_THRESH_ACT_H 0x20
51 #define ADXL367_REG_THRESH_INACT_H 0x23
52 #define ADXL367_THRESH_MAX GENMASK(12, 0)
53 #define ADXL367_THRESH_VAL_H_MASK GENMASK(12, 6)
54 #define ADXL367_THRESH_H_MASK GENMASK(6, 0)
55 #define ADXL367_THRESH_VAL_L_MASK GENMASK(5, 0)
56 #define ADXL367_THRESH_L_MASK GENMASK(7, 2)
57
58 #define ADXL367_REG_TIME_ACT 0x22
59 #define ADXL367_REG_TIME_INACT_H 0x25
60 #define ADXL367_TIME_ACT_MAX GENMASK(7, 0)
61 #define ADXL367_TIME_INACT_MAX GENMASK(15, 0)
62 #define ADXL367_TIME_INACT_VAL_H_MASK GENMASK(15, 8)
63 #define ADXL367_TIME_INACT_H_MASK GENMASK(7, 0)
64 #define ADXL367_TIME_INACT_VAL_L_MASK GENMASK(7, 0)
65 #define ADXL367_TIME_INACT_L_MASK GENMASK(7, 0)
66
67 #define ADXL367_REG_ACT_INACT_CTL 0x27
68 #define ADXL367_ACT_EN_MASK GENMASK(1, 0)
69 #define ADXL367_ACT_LINKLOOP_MASK GENMASK(5, 4)
70
71 #define ADXL367_REG_FIFO_CTL 0x28
72 #define ADXL367_FIFO_CTL_FORMAT_MASK GENMASK(6, 3)
73 #define ADXL367_FIFO_CTL_MODE_MASK GENMASK(1, 0)
74
75 #define ADXL367_REG_FIFO_SAMPLES 0x29
76 #define ADXL367_FIFO_SIZE 512
77 #define ADXL367_FIFO_MAX_WATERMARK 511
78
79 #define ADXL367_SAMPLES_VAL_H_MASK BIT(8)
80 #define ADXL367_SAMPLES_H_MASK BIT(2)
81 #define ADXL367_SAMPLES_VAL_L_MASK GENMASK(7, 0)
82 #define ADXL367_SAMPLES_L_MASK GENMASK(7, 0)
83
84 #define ADXL367_REG_INT1_MAP 0x2A
85 #define ADXL367_INT_INACT_MASK BIT(5)
86 #define ADXL367_INT_ACT_MASK BIT(4)
87 #define ADXL367_INT_FIFO_WATERMARK_MASK BIT(2)
88
89 #define ADXL367_REG_FILTER_CTL 0x2C
90 #define ADXL367_FILTER_CTL_RANGE_MASK GENMASK(7, 6)
91 #define ADXL367_2G_RANGE_1G 4095
92 #define ADXL367_2G_RANGE_100MG 409
93 #define ADXL367_FILTER_CTL_ODR_MASK GENMASK(2, 0)
94
95 #define ADXL367_REG_POWER_CTL 0x2D
96 #define ADXL367_POWER_CTL_MODE_MASK GENMASK(1, 0)
97
98 #define ADXL367_REG_ADC_CTL 0x3C
99 #define ADXL367_REG_TEMP_CTL 0x3D
100 #define ADXL367_ADC_EN_MASK BIT(0)
101
102 enum adxl367_range {
103 ADXL367_2G_RANGE,
104 ADXL367_4G_RANGE,
105 ADXL367_8G_RANGE,
106 };
107
108 enum adxl367_fifo_mode {
109 ADXL367_FIFO_MODE_DISABLED = 0b00,
110 ADXL367_FIFO_MODE_STREAM = 0b10,
111 };
112
113 enum adxl367_fifo_format {
114 ADXL367_FIFO_FORMAT_XYZ,
115 ADXL367_FIFO_FORMAT_X,
116 ADXL367_FIFO_FORMAT_Y,
117 ADXL367_FIFO_FORMAT_Z,
118 ADXL367_FIFO_FORMAT_XYZT,
119 ADXL367_FIFO_FORMAT_XT,
120 ADXL367_FIFO_FORMAT_YT,
121 ADXL367_FIFO_FORMAT_ZT,
122 ADXL367_FIFO_FORMAT_XYZA,
123 ADXL367_FIFO_FORMAT_XA,
124 ADXL367_FIFO_FORMAT_YA,
125 ADXL367_FIFO_FORMAT_ZA,
126 };
127
128 enum adxl367_op_mode {
129 ADXL367_OP_STANDBY = 0b00,
130 ADXL367_OP_MEASURE = 0b10,
131 };
132
133 enum adxl367_act_proc_mode {
134 ADXL367_LOOPED = 0b11,
135 };
136
137 enum adxl367_act_en_mode {
138 ADXL367_ACT_DISABLED = 0b00,
139 ADCL367_ACT_REF_ENABLED = 0b11,
140 };
141
142 enum adxl367_activity_type {
143 ADXL367_ACTIVITY,
144 ADXL367_INACTIVITY,
145 };
146
147 enum adxl367_odr {
148 ADXL367_ODR_12P5HZ,
149 ADXL367_ODR_25HZ,
150 ADXL367_ODR_50HZ,
151 ADXL367_ODR_100HZ,
152 ADXL367_ODR_200HZ,
153 ADXL367_ODR_400HZ,
154 };
155
156 struct adxl367_state {
157 const struct adxl367_ops *ops;
158 void *context;
159
160 struct device *dev;
161 struct regmap *regmap;
162
163 /*
164 * Synchronize access to members of driver state, and ensure atomicity
165 * of consecutive regmap operations.
166 */
167 struct mutex lock;
168
169 enum adxl367_odr odr;
170 enum adxl367_range range;
171
172 unsigned int act_threshold;
173 unsigned int act_time_ms;
174 unsigned int inact_threshold;
175 unsigned int inact_time_ms;
176
177 unsigned int fifo_set_size;
178 unsigned int fifo_watermark;
179
180 __be16 fifo_buf[ADXL367_FIFO_SIZE] __aligned(IIO_DMA_MINALIGN);
181 __be16 sample_buf;
182 u8 act_threshold_buf[2];
183 u8 inact_time_buf[2];
184 u8 status_buf[3];
185 };
186
187 static const unsigned int adxl367_threshold_h_reg_tbl[] = {
188 [ADXL367_ACTIVITY] = ADXL367_REG_THRESH_ACT_H,
189 [ADXL367_INACTIVITY] = ADXL367_REG_THRESH_INACT_H,
190 };
191
192 static const unsigned int adxl367_act_en_shift_tbl[] = {
193 [ADXL367_ACTIVITY] = 0,
194 [ADXL367_INACTIVITY] = 2,
195 };
196
197 static const unsigned int adxl367_act_int_mask_tbl[] = {
198 [ADXL367_ACTIVITY] = ADXL367_INT_ACT_MASK,
199 [ADXL367_INACTIVITY] = ADXL367_INT_INACT_MASK,
200 };
201
202 static const int adxl367_samp_freq_tbl[][2] = {
203 [ADXL367_ODR_12P5HZ] = {12, 500000},
204 [ADXL367_ODR_25HZ] = {25, 0},
205 [ADXL367_ODR_50HZ] = {50, 0},
206 [ADXL367_ODR_100HZ] = {100, 0},
207 [ADXL367_ODR_200HZ] = {200, 0},
208 [ADXL367_ODR_400HZ] = {400, 0},
209 };
210
211 /* (g * 2) * 9.80665 * 1000000 / (2^14 - 1) */
212 static const int adxl367_range_scale_tbl[][2] = {
213 [ADXL367_2G_RANGE] = {0, 2394347},
214 [ADXL367_4G_RANGE] = {0, 4788695},
215 [ADXL367_8G_RANGE] = {0, 9577391},
216 };
217
218 static const int adxl367_range_scale_factor_tbl[] = {
219 [ADXL367_2G_RANGE] = 1,
220 [ADXL367_4G_RANGE] = 2,
221 [ADXL367_8G_RANGE] = 4,
222 };
223
224 enum {
225 ADXL367_X_CHANNEL_INDEX,
226 ADXL367_Y_CHANNEL_INDEX,
227 ADXL367_Z_CHANNEL_INDEX,
228 ADXL367_TEMP_CHANNEL_INDEX,
229 ADXL367_EX_ADC_CHANNEL_INDEX
230 };
231
232 #define ADXL367_X_CHANNEL_MASK BIT(ADXL367_X_CHANNEL_INDEX)
233 #define ADXL367_Y_CHANNEL_MASK BIT(ADXL367_Y_CHANNEL_INDEX)
234 #define ADXL367_Z_CHANNEL_MASK BIT(ADXL367_Z_CHANNEL_INDEX)
235 #define ADXL367_TEMP_CHANNEL_MASK BIT(ADXL367_TEMP_CHANNEL_INDEX)
236 #define ADXL367_EX_ADC_CHANNEL_MASK BIT(ADXL367_EX_ADC_CHANNEL_INDEX)
237
238 static const enum adxl367_fifo_format adxl367_fifo_formats[] = {
239 ADXL367_FIFO_FORMAT_X,
240 ADXL367_FIFO_FORMAT_Y,
241 ADXL367_FIFO_FORMAT_Z,
242 ADXL367_FIFO_FORMAT_XT,
243 ADXL367_FIFO_FORMAT_YT,
244 ADXL367_FIFO_FORMAT_ZT,
245 ADXL367_FIFO_FORMAT_XA,
246 ADXL367_FIFO_FORMAT_YA,
247 ADXL367_FIFO_FORMAT_ZA,
248 ADXL367_FIFO_FORMAT_XYZ,
249 ADXL367_FIFO_FORMAT_XYZT,
250 ADXL367_FIFO_FORMAT_XYZA,
251 };
252
253 static const unsigned long adxl367_channel_masks[] = {
254 ADXL367_X_CHANNEL_MASK,
255 ADXL367_Y_CHANNEL_MASK,
256 ADXL367_Z_CHANNEL_MASK,
257 ADXL367_X_CHANNEL_MASK | ADXL367_TEMP_CHANNEL_MASK,
258 ADXL367_Y_CHANNEL_MASK | ADXL367_TEMP_CHANNEL_MASK,
259 ADXL367_Z_CHANNEL_MASK | ADXL367_TEMP_CHANNEL_MASK,
260 ADXL367_X_CHANNEL_MASK | ADXL367_EX_ADC_CHANNEL_MASK,
261 ADXL367_Y_CHANNEL_MASK | ADXL367_EX_ADC_CHANNEL_MASK,
262 ADXL367_Z_CHANNEL_MASK | ADXL367_EX_ADC_CHANNEL_MASK,
263 ADXL367_X_CHANNEL_MASK | ADXL367_Y_CHANNEL_MASK | ADXL367_Z_CHANNEL_MASK,
264 ADXL367_X_CHANNEL_MASK | ADXL367_Y_CHANNEL_MASK | ADXL367_Z_CHANNEL_MASK |
265 ADXL367_TEMP_CHANNEL_MASK,
266 ADXL367_X_CHANNEL_MASK | ADXL367_Y_CHANNEL_MASK | ADXL367_Z_CHANNEL_MASK |
267 ADXL367_EX_ADC_CHANNEL_MASK,
268 0,
269 };
270
adxl367_set_measure_en(struct adxl367_state * st,bool en)271 static int adxl367_set_measure_en(struct adxl367_state *st, bool en)
272 {
273 enum adxl367_op_mode op_mode = en ? ADXL367_OP_MEASURE
274 : ADXL367_OP_STANDBY;
275 int ret;
276
277 ret = regmap_update_bits(st->regmap, ADXL367_REG_POWER_CTL,
278 ADXL367_POWER_CTL_MODE_MASK,
279 FIELD_PREP(ADXL367_POWER_CTL_MODE_MASK,
280 op_mode));
281 if (ret)
282 return ret;
283
284 /*
285 * Wait for acceleration output to settle after entering
286 * measure mode.
287 */
288 if (en)
289 msleep(100);
290
291 return 0;
292 }
293
adxl367_scale_act_thresholds(struct adxl367_state * st,enum adxl367_range old_range,enum adxl367_range new_range)294 static void adxl367_scale_act_thresholds(struct adxl367_state *st,
295 enum adxl367_range old_range,
296 enum adxl367_range new_range)
297 {
298 st->act_threshold = st->act_threshold
299 * adxl367_range_scale_factor_tbl[old_range]
300 / adxl367_range_scale_factor_tbl[new_range];
301 st->inact_threshold = st->inact_threshold
302 * adxl367_range_scale_factor_tbl[old_range]
303 / adxl367_range_scale_factor_tbl[new_range];
304 }
305
_adxl367_set_act_threshold(struct adxl367_state * st,enum adxl367_activity_type act,unsigned int threshold)306 static int _adxl367_set_act_threshold(struct adxl367_state *st,
307 enum adxl367_activity_type act,
308 unsigned int threshold)
309 {
310 u8 reg = adxl367_threshold_h_reg_tbl[act];
311 int ret;
312
313 if (threshold > ADXL367_THRESH_MAX)
314 return -EINVAL;
315
316 st->act_threshold_buf[0] = FIELD_PREP(ADXL367_THRESH_H_MASK,
317 FIELD_GET(ADXL367_THRESH_VAL_H_MASK,
318 threshold));
319 st->act_threshold_buf[1] = FIELD_PREP(ADXL367_THRESH_L_MASK,
320 FIELD_GET(ADXL367_THRESH_VAL_L_MASK,
321 threshold));
322
323 ret = regmap_bulk_write(st->regmap, reg, st->act_threshold_buf,
324 sizeof(st->act_threshold_buf));
325 if (ret)
326 return ret;
327
328 if (act == ADXL367_ACTIVITY)
329 st->act_threshold = threshold;
330 else
331 st->inact_threshold = threshold;
332
333 return 0;
334 }
335
adxl367_set_act_threshold(struct adxl367_state * st,enum adxl367_activity_type act,unsigned int threshold)336 static int adxl367_set_act_threshold(struct adxl367_state *st,
337 enum adxl367_activity_type act,
338 unsigned int threshold)
339 {
340 int ret;
341
342 guard(mutex)(&st->lock);
343
344 ret = adxl367_set_measure_en(st, false);
345 if (ret)
346 return ret;
347
348 ret = _adxl367_set_act_threshold(st, act, threshold);
349 if (ret)
350 return ret;
351
352 return adxl367_set_measure_en(st, true);
353 }
354
adxl367_set_act_proc_mode(struct adxl367_state * st,enum adxl367_act_proc_mode mode)355 static int adxl367_set_act_proc_mode(struct adxl367_state *st,
356 enum adxl367_act_proc_mode mode)
357 {
358 return regmap_update_bits(st->regmap, ADXL367_REG_ACT_INACT_CTL,
359 ADXL367_ACT_LINKLOOP_MASK,
360 FIELD_PREP(ADXL367_ACT_LINKLOOP_MASK,
361 mode));
362 }
363
adxl367_set_act_interrupt_en(struct adxl367_state * st,enum adxl367_activity_type act,bool en)364 static int adxl367_set_act_interrupt_en(struct adxl367_state *st,
365 enum adxl367_activity_type act,
366 bool en)
367 {
368 unsigned int mask = adxl367_act_int_mask_tbl[act];
369
370 return regmap_update_bits(st->regmap, ADXL367_REG_INT1_MAP,
371 mask, en ? mask : 0);
372 }
373
adxl367_get_act_interrupt_en(struct adxl367_state * st,enum adxl367_activity_type act,bool * en)374 static int adxl367_get_act_interrupt_en(struct adxl367_state *st,
375 enum adxl367_activity_type act,
376 bool *en)
377 {
378 unsigned int mask = adxl367_act_int_mask_tbl[act];
379 unsigned int val;
380 int ret;
381
382 ret = regmap_read(st->regmap, ADXL367_REG_INT1_MAP, &val);
383 if (ret)
384 return ret;
385
386 *en = !!(val & mask);
387
388 return 0;
389 }
390
adxl367_set_act_en(struct adxl367_state * st,enum adxl367_activity_type act,enum adxl367_act_en_mode en)391 static int adxl367_set_act_en(struct adxl367_state *st,
392 enum adxl367_activity_type act,
393 enum adxl367_act_en_mode en)
394 {
395 unsigned int ctl_shift = adxl367_act_en_shift_tbl[act];
396
397 return regmap_update_bits(st->regmap, ADXL367_REG_ACT_INACT_CTL,
398 ADXL367_ACT_EN_MASK << ctl_shift,
399 en << ctl_shift);
400 }
401
adxl367_set_fifo_watermark_interrupt_en(struct adxl367_state * st,bool en)402 static int adxl367_set_fifo_watermark_interrupt_en(struct adxl367_state *st,
403 bool en)
404 {
405 return regmap_update_bits(st->regmap, ADXL367_REG_INT1_MAP,
406 ADXL367_INT_FIFO_WATERMARK_MASK,
407 en ? ADXL367_INT_FIFO_WATERMARK_MASK : 0);
408 }
409
adxl367_get_fifo_mode(struct adxl367_state * st,enum adxl367_fifo_mode * fifo_mode)410 static int adxl367_get_fifo_mode(struct adxl367_state *st,
411 enum adxl367_fifo_mode *fifo_mode)
412 {
413 unsigned int val;
414 int ret;
415
416 ret = regmap_read(st->regmap, ADXL367_REG_FIFO_CTL, &val);
417 if (ret)
418 return ret;
419
420 *fifo_mode = FIELD_GET(ADXL367_FIFO_CTL_MODE_MASK, val);
421
422 return 0;
423 }
424
adxl367_set_fifo_mode(struct adxl367_state * st,enum adxl367_fifo_mode fifo_mode)425 static int adxl367_set_fifo_mode(struct adxl367_state *st,
426 enum adxl367_fifo_mode fifo_mode)
427 {
428 return regmap_update_bits(st->regmap, ADXL367_REG_FIFO_CTL,
429 ADXL367_FIFO_CTL_MODE_MASK,
430 FIELD_PREP(ADXL367_FIFO_CTL_MODE_MASK,
431 fifo_mode));
432 }
433
adxl367_set_fifo_format(struct adxl367_state * st,enum adxl367_fifo_format fifo_format)434 static int adxl367_set_fifo_format(struct adxl367_state *st,
435 enum adxl367_fifo_format fifo_format)
436 {
437 return regmap_update_bits(st->regmap, ADXL367_REG_FIFO_CTL,
438 ADXL367_FIFO_CTL_FORMAT_MASK,
439 FIELD_PREP(ADXL367_FIFO_CTL_FORMAT_MASK,
440 fifo_format));
441 }
442
adxl367_set_fifo_watermark(struct adxl367_state * st,unsigned int fifo_watermark)443 static int adxl367_set_fifo_watermark(struct adxl367_state *st,
444 unsigned int fifo_watermark)
445 {
446 unsigned int fifo_samples = fifo_watermark * st->fifo_set_size;
447 unsigned int fifo_samples_h, fifo_samples_l;
448 int ret;
449
450 if (fifo_samples > ADXL367_FIFO_MAX_WATERMARK)
451 fifo_samples = ADXL367_FIFO_MAX_WATERMARK;
452
453 fifo_samples /= st->fifo_set_size;
454
455 fifo_samples_h = FIELD_PREP(ADXL367_SAMPLES_H_MASK,
456 FIELD_GET(ADXL367_SAMPLES_VAL_H_MASK,
457 fifo_samples));
458 fifo_samples_l = FIELD_PREP(ADXL367_SAMPLES_L_MASK,
459 FIELD_GET(ADXL367_SAMPLES_VAL_L_MASK,
460 fifo_samples));
461
462 ret = regmap_update_bits(st->regmap, ADXL367_REG_FIFO_CTL,
463 ADXL367_SAMPLES_H_MASK, fifo_samples_h);
464 if (ret)
465 return ret;
466
467 ret = regmap_update_bits(st->regmap, ADXL367_REG_FIFO_SAMPLES,
468 ADXL367_SAMPLES_L_MASK, fifo_samples_l);
469 if (ret)
470 return ret;
471
472 st->fifo_watermark = fifo_watermark;
473
474 return 0;
475 }
476
adxl367_set_range(struct iio_dev * indio_dev,enum adxl367_range range)477 static int adxl367_set_range(struct iio_dev *indio_dev,
478 enum adxl367_range range)
479 {
480 struct adxl367_state *st = iio_priv(indio_dev);
481 int ret;
482
483 guard(mutex)(&st->lock);
484
485 ret = adxl367_set_measure_en(st, false);
486 if (ret)
487 return ret;
488
489 ret = regmap_update_bits(st->regmap, ADXL367_REG_FILTER_CTL,
490 ADXL367_FILTER_CTL_RANGE_MASK,
491 FIELD_PREP(ADXL367_FILTER_CTL_RANGE_MASK,
492 range));
493 if (ret)
494 return ret;
495
496 adxl367_scale_act_thresholds(st, st->range, range);
497
498 /* Activity thresholds depend on range */
499 ret = _adxl367_set_act_threshold(st, ADXL367_ACTIVITY,
500 st->act_threshold);
501 if (ret)
502 return ret;
503
504 ret = _adxl367_set_act_threshold(st, ADXL367_INACTIVITY,
505 st->inact_threshold);
506 if (ret)
507 return ret;
508
509 ret = adxl367_set_measure_en(st, true);
510 if (ret)
511 return ret;
512
513 st->range = range;
514
515 return 0;
516 }
517
adxl367_time_ms_to_samples(struct adxl367_state * st,unsigned int ms)518 static int adxl367_time_ms_to_samples(struct adxl367_state *st, unsigned int ms)
519 {
520 int freq_hz = adxl367_samp_freq_tbl[st->odr][0];
521 int freq_microhz = adxl367_samp_freq_tbl[st->odr][1];
522 /* Scale to decihertz to prevent precision loss in 12.5Hz case. */
523 int freq_dhz = freq_hz * 10 + freq_microhz / 100000;
524
525 return DIV_ROUND_CLOSEST(ms * freq_dhz, 10000);
526 }
527
_adxl367_set_act_time_ms(struct adxl367_state * st,unsigned int ms)528 static int _adxl367_set_act_time_ms(struct adxl367_state *st, unsigned int ms)
529 {
530 unsigned int val = adxl367_time_ms_to_samples(st, ms);
531 int ret;
532
533 if (val > ADXL367_TIME_ACT_MAX)
534 val = ADXL367_TIME_ACT_MAX;
535
536 ret = regmap_write(st->regmap, ADXL367_REG_TIME_ACT, val);
537 if (ret)
538 return ret;
539
540 st->act_time_ms = ms;
541
542 return 0;
543 }
544
_adxl367_set_inact_time_ms(struct adxl367_state * st,unsigned int ms)545 static int _adxl367_set_inact_time_ms(struct adxl367_state *st, unsigned int ms)
546 {
547 unsigned int val = adxl367_time_ms_to_samples(st, ms);
548 int ret;
549
550 if (val > ADXL367_TIME_INACT_MAX)
551 val = ADXL367_TIME_INACT_MAX;
552
553 st->inact_time_buf[0] = FIELD_PREP(ADXL367_TIME_INACT_H_MASK,
554 FIELD_GET(ADXL367_TIME_INACT_VAL_H_MASK,
555 val));
556 st->inact_time_buf[1] = FIELD_PREP(ADXL367_TIME_INACT_L_MASK,
557 FIELD_GET(ADXL367_TIME_INACT_VAL_L_MASK,
558 val));
559
560 ret = regmap_bulk_write(st->regmap, ADXL367_REG_TIME_INACT_H,
561 st->inact_time_buf, sizeof(st->inact_time_buf));
562 if (ret)
563 return ret;
564
565 st->inact_time_ms = ms;
566
567 return 0;
568 }
569
adxl367_set_act_time_ms(struct adxl367_state * st,enum adxl367_activity_type act,unsigned int ms)570 static int adxl367_set_act_time_ms(struct adxl367_state *st,
571 enum adxl367_activity_type act,
572 unsigned int ms)
573 {
574 int ret;
575
576 guard(mutex)(&st->lock);
577
578 ret = adxl367_set_measure_en(st, false);
579 if (ret)
580 return ret;
581
582 if (act == ADXL367_ACTIVITY)
583 ret = _adxl367_set_act_time_ms(st, ms);
584 else
585 ret = _adxl367_set_inact_time_ms(st, ms);
586
587 if (ret)
588 return ret;
589
590 return adxl367_set_measure_en(st, true);
591 }
592
_adxl367_set_odr(struct adxl367_state * st,enum adxl367_odr odr)593 static int _adxl367_set_odr(struct adxl367_state *st, enum adxl367_odr odr)
594 {
595 int ret;
596
597 ret = regmap_update_bits(st->regmap, ADXL367_REG_FILTER_CTL,
598 ADXL367_FILTER_CTL_ODR_MASK,
599 FIELD_PREP(ADXL367_FILTER_CTL_ODR_MASK,
600 odr));
601 if (ret)
602 return ret;
603
604 st->odr = odr;
605
606 /* Activity timers depend on ODR */
607 ret = _adxl367_set_act_time_ms(st, st->act_time_ms);
608 if (ret)
609 return ret;
610
611 return _adxl367_set_inact_time_ms(st, st->inact_time_ms);
612 }
613
adxl367_set_odr(struct iio_dev * indio_dev,enum adxl367_odr odr)614 static int adxl367_set_odr(struct iio_dev *indio_dev, enum adxl367_odr odr)
615 {
616 struct adxl367_state *st = iio_priv(indio_dev);
617 int ret;
618
619 guard(mutex)(&st->lock);
620
621 ret = adxl367_set_measure_en(st, false);
622 if (ret)
623 return ret;
624
625 ret = _adxl367_set_odr(st, odr);
626 if (ret)
627 return ret;
628
629 return adxl367_set_measure_en(st, true);
630 }
631
adxl367_set_temp_adc_en(struct adxl367_state * st,unsigned int reg,bool en)632 static int adxl367_set_temp_adc_en(struct adxl367_state *st, unsigned int reg,
633 bool en)
634 {
635 return regmap_update_bits(st->regmap, reg, ADXL367_ADC_EN_MASK,
636 en ? ADXL367_ADC_EN_MASK : 0);
637 }
638
adxl367_set_temp_adc_reg_en(struct adxl367_state * st,unsigned int reg,bool en)639 static int adxl367_set_temp_adc_reg_en(struct adxl367_state *st,
640 unsigned int reg, bool en)
641 {
642 int ret;
643
644 switch (reg) {
645 case ADXL367_REG_TEMP_DATA_H:
646 ret = adxl367_set_temp_adc_en(st, ADXL367_REG_TEMP_CTL, en);
647 break;
648 case ADXL367_REG_EX_ADC_DATA_H:
649 ret = adxl367_set_temp_adc_en(st, ADXL367_REG_ADC_CTL, en);
650 break;
651 default:
652 return 0;
653 }
654
655 if (ret)
656 return ret;
657
658 if (en)
659 msleep(100);
660
661 return 0;
662 }
663
adxl367_set_temp_adc_mask_en(struct adxl367_state * st,const unsigned long * active_scan_mask,bool en)664 static int adxl367_set_temp_adc_mask_en(struct adxl367_state *st,
665 const unsigned long *active_scan_mask,
666 bool en)
667 {
668 if (*active_scan_mask & ADXL367_TEMP_CHANNEL_MASK)
669 return adxl367_set_temp_adc_en(st, ADXL367_REG_TEMP_CTL, en);
670 else if (*active_scan_mask & ADXL367_EX_ADC_CHANNEL_MASK)
671 return adxl367_set_temp_adc_en(st, ADXL367_REG_ADC_CTL, en);
672
673 return 0;
674 }
675
adxl367_find_odr(struct adxl367_state * st,int val,int val2,enum adxl367_odr * odr)676 static int adxl367_find_odr(struct adxl367_state *st, int val, int val2,
677 enum adxl367_odr *odr)
678 {
679 size_t size = ARRAY_SIZE(adxl367_samp_freq_tbl);
680 int i;
681
682 for (i = 0; i < size; i++)
683 if (val == adxl367_samp_freq_tbl[i][0] &&
684 val2 == adxl367_samp_freq_tbl[i][1])
685 break;
686
687 if (i == size)
688 return -EINVAL;
689
690 *odr = i;
691
692 return 0;
693 }
694
adxl367_find_range(struct adxl367_state * st,int val,int val2,enum adxl367_range * range)695 static int adxl367_find_range(struct adxl367_state *st, int val, int val2,
696 enum adxl367_range *range)
697 {
698 size_t size = ARRAY_SIZE(adxl367_range_scale_tbl);
699 int i;
700
701 for (i = 0; i < size; i++)
702 if (val == adxl367_range_scale_tbl[i][0] &&
703 val2 == adxl367_range_scale_tbl[i][1])
704 break;
705
706 if (i == size)
707 return -EINVAL;
708
709 *range = i;
710
711 return 0;
712 }
713
adxl367_read_sample(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val)714 static int adxl367_read_sample(struct iio_dev *indio_dev,
715 struct iio_chan_spec const *chan,
716 int *val)
717 {
718 struct adxl367_state *st = iio_priv(indio_dev);
719 u16 sample;
720 int ret;
721
722 guard(mutex)(&st->lock);
723
724 ret = adxl367_set_temp_adc_reg_en(st, chan->address, true);
725 if (ret)
726 return ret;
727
728 ret = regmap_bulk_read(st->regmap, chan->address, &st->sample_buf,
729 sizeof(st->sample_buf));
730 if (ret)
731 return ret;
732
733 sample = FIELD_GET(ADXL367_DATA_MASK, be16_to_cpu(st->sample_buf));
734 *val = sign_extend32(sample, chan->scan_type.realbits - 1);
735
736 ret = adxl367_set_temp_adc_reg_en(st, chan->address, false);
737 if (ret)
738 return ret;
739
740 return IIO_VAL_INT;
741 }
742
adxl367_get_status(struct adxl367_state * st,u8 * status,u16 * fifo_entries)743 static int adxl367_get_status(struct adxl367_state *st, u8 *status,
744 u16 *fifo_entries)
745 {
746 int ret;
747
748 /* Read STATUS, FIFO_ENT_L and FIFO_ENT_H */
749 ret = regmap_bulk_read(st->regmap, ADXL367_REG_STATUS,
750 st->status_buf, sizeof(st->status_buf));
751 if (ret)
752 return ret;
753
754 st->status_buf[2] &= ADXL367_FIFO_ENT_H_MASK;
755
756 *status = st->status_buf[0];
757 *fifo_entries = get_unaligned_le16(&st->status_buf[1]);
758
759 return 0;
760 }
761
adxl367_push_event(struct iio_dev * indio_dev,u8 status)762 static bool adxl367_push_event(struct iio_dev *indio_dev, u8 status)
763 {
764 unsigned int ev_dir;
765
766 if (FIELD_GET(ADXL367_STATUS_ACT_MASK, status))
767 ev_dir = IIO_EV_DIR_RISING;
768 else if (FIELD_GET(ADXL367_STATUS_INACT_MASK, status))
769 ev_dir = IIO_EV_DIR_FALLING;
770 else
771 return false;
772
773 iio_push_event(indio_dev,
774 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X_OR_Y_OR_Z,
775 IIO_EV_TYPE_THRESH, ev_dir),
776 iio_get_time_ns(indio_dev));
777
778 return true;
779 }
780
adxl367_push_fifo_data(struct iio_dev * indio_dev,u8 status,u16 fifo_entries)781 static bool adxl367_push_fifo_data(struct iio_dev *indio_dev, u8 status,
782 u16 fifo_entries)
783 {
784 struct adxl367_state *st = iio_priv(indio_dev);
785 int ret;
786 int i;
787
788 if (!FIELD_GET(ADXL367_STATUS_FIFO_FULL_MASK, status))
789 return false;
790
791 fifo_entries -= fifo_entries % st->fifo_set_size;
792
793 ret = st->ops->read_fifo(st->context, st->fifo_buf, fifo_entries);
794 if (ret) {
795 dev_err(st->dev, "Failed to read FIFO: %d\n", ret);
796 return true;
797 }
798
799 for (i = 0; i < fifo_entries; i += st->fifo_set_size)
800 iio_push_to_buffers(indio_dev, &st->fifo_buf[i]);
801
802 return true;
803 }
804
adxl367_irq_handler(int irq,void * private)805 static irqreturn_t adxl367_irq_handler(int irq, void *private)
806 {
807 struct iio_dev *indio_dev = private;
808 struct adxl367_state *st = iio_priv(indio_dev);
809 u16 fifo_entries;
810 bool handled;
811 u8 status;
812 int ret;
813
814 ret = adxl367_get_status(st, &status, &fifo_entries);
815 if (ret)
816 return IRQ_NONE;
817
818 handled = adxl367_push_event(indio_dev, status);
819 handled |= adxl367_push_fifo_data(indio_dev, status, fifo_entries);
820
821 return handled ? IRQ_HANDLED : IRQ_NONE;
822 }
823
adxl367_reg_access(struct iio_dev * indio_dev,unsigned int reg,unsigned int writeval,unsigned int * readval)824 static int adxl367_reg_access(struct iio_dev *indio_dev,
825 unsigned int reg,
826 unsigned int writeval,
827 unsigned int *readval)
828 {
829 struct adxl367_state *st = iio_priv(indio_dev);
830
831 if (readval)
832 return regmap_read(st->regmap, reg, readval);
833 else
834 return regmap_write(st->regmap, reg, writeval);
835 }
836
adxl367_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long info)837 static int adxl367_read_raw(struct iio_dev *indio_dev,
838 struct iio_chan_spec const *chan,
839 int *val, int *val2, long info)
840 {
841 struct adxl367_state *st = iio_priv(indio_dev);
842 int ret;
843
844 switch (info) {
845 case IIO_CHAN_INFO_RAW:
846 if (!iio_device_claim_direct(indio_dev))
847 return -EBUSY;
848 ret = adxl367_read_sample(indio_dev, chan, val);
849 iio_device_release_direct(indio_dev);
850 return ret;
851 case IIO_CHAN_INFO_SCALE:
852 switch (chan->type) {
853 case IIO_ACCEL: {
854 guard(mutex)(&st->lock);
855 *val = adxl367_range_scale_tbl[st->range][0];
856 *val2 = adxl367_range_scale_tbl[st->range][1];
857 return IIO_VAL_INT_PLUS_NANO;
858 }
859 case IIO_TEMP:
860 *val = 1000;
861 *val2 = ADXL367_TEMP_PER_C;
862 return IIO_VAL_FRACTIONAL;
863 case IIO_VOLTAGE:
864 *val = ADXL367_VOLTAGE_MAX_MV;
865 *val2 = ADXL367_VOLTAGE_MAX_RAW;
866 return IIO_VAL_FRACTIONAL;
867 default:
868 return -EINVAL;
869 }
870 case IIO_CHAN_INFO_OFFSET:
871 switch (chan->type) {
872 case IIO_TEMP:
873 *val = 25 * ADXL367_TEMP_PER_C - ADXL367_TEMP_25C;
874 return IIO_VAL_INT;
875 case IIO_VOLTAGE:
876 *val = ADXL367_VOLTAGE_OFFSET;
877 return IIO_VAL_INT;
878 default:
879 return -EINVAL;
880 }
881 case IIO_CHAN_INFO_SAMP_FREQ: {
882 guard(mutex)(&st->lock);
883 *val = adxl367_samp_freq_tbl[st->odr][0];
884 *val2 = adxl367_samp_freq_tbl[st->odr][1];
885 return IIO_VAL_INT_PLUS_MICRO;
886 }
887 default:
888 return -EINVAL;
889 }
890 }
891
adxl367_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long info)892 static int adxl367_write_raw(struct iio_dev *indio_dev,
893 struct iio_chan_spec const *chan,
894 int val, int val2, long info)
895 {
896 struct adxl367_state *st = iio_priv(indio_dev);
897 int ret;
898
899 switch (info) {
900 case IIO_CHAN_INFO_SAMP_FREQ: {
901 enum adxl367_odr odr;
902
903 ret = adxl367_find_odr(st, val, val2, &odr);
904 if (ret)
905 return ret;
906
907 if (!iio_device_claim_direct(indio_dev))
908 return -EBUSY;
909
910 ret = adxl367_set_odr(indio_dev, odr);
911 iio_device_release_direct(indio_dev);
912 return ret;
913 }
914 case IIO_CHAN_INFO_SCALE: {
915 enum adxl367_range range;
916
917 ret = adxl367_find_range(st, val, val2, &range);
918 if (ret)
919 return ret;
920
921 if (!iio_device_claim_direct(indio_dev))
922 return -EBUSY;
923
924 ret = adxl367_set_range(indio_dev, range);
925 iio_device_release_direct(indio_dev);
926 return ret;
927 }
928 default:
929 return -EINVAL;
930 }
931 }
932
adxl367_write_raw_get_fmt(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,long info)933 static int adxl367_write_raw_get_fmt(struct iio_dev *indio_dev,
934 struct iio_chan_spec const *chan,
935 long info)
936 {
937 switch (info) {
938 case IIO_CHAN_INFO_SCALE:
939 if (chan->type != IIO_ACCEL)
940 return -EINVAL;
941
942 return IIO_VAL_INT_PLUS_NANO;
943 default:
944 return IIO_VAL_INT_PLUS_MICRO;
945 }
946 }
947
adxl367_read_avail(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,const int ** vals,int * type,int * length,long info)948 static int adxl367_read_avail(struct iio_dev *indio_dev,
949 struct iio_chan_spec const *chan,
950 const int **vals, int *type, int *length,
951 long info)
952 {
953 switch (info) {
954 case IIO_CHAN_INFO_SCALE:
955 if (chan->type != IIO_ACCEL)
956 return -EINVAL;
957
958 *vals = (int *)adxl367_range_scale_tbl;
959 *type = IIO_VAL_INT_PLUS_NANO;
960 *length = ARRAY_SIZE(adxl367_range_scale_tbl) * 2;
961 return IIO_AVAIL_LIST;
962 case IIO_CHAN_INFO_SAMP_FREQ:
963 *vals = (int *)adxl367_samp_freq_tbl;
964 *type = IIO_VAL_INT_PLUS_MICRO;
965 *length = ARRAY_SIZE(adxl367_samp_freq_tbl) * 2;
966 return IIO_AVAIL_LIST;
967 default:
968 return -EINVAL;
969 }
970 }
971
adxl367_read_event_value(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int * val,int * val2)972 static int adxl367_read_event_value(struct iio_dev *indio_dev,
973 const struct iio_chan_spec *chan,
974 enum iio_event_type type,
975 enum iio_event_direction dir,
976 enum iio_event_info info,
977 int *val, int *val2)
978 {
979 struct adxl367_state *st = iio_priv(indio_dev);
980
981 guard(mutex)(&st->lock);
982 switch (info) {
983 case IIO_EV_INFO_VALUE: {
984 switch (dir) {
985 case IIO_EV_DIR_RISING:
986 *val = st->act_threshold;
987 return IIO_VAL_INT;
988 case IIO_EV_DIR_FALLING:
989 *val = st->inact_threshold;
990 return IIO_VAL_INT;
991 default:
992 return -EINVAL;
993 }
994 }
995 case IIO_EV_INFO_PERIOD:
996 switch (dir) {
997 case IIO_EV_DIR_RISING:
998 *val = st->act_time_ms;
999 *val2 = 1000;
1000 return IIO_VAL_FRACTIONAL;
1001 case IIO_EV_DIR_FALLING:
1002 *val = st->inact_time_ms;
1003 *val2 = 1000;
1004 return IIO_VAL_FRACTIONAL;
1005 default:
1006 return -EINVAL;
1007 }
1008 default:
1009 return -EINVAL;
1010 }
1011 }
1012
adxl367_write_event_value(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int val,int val2)1013 static int adxl367_write_event_value(struct iio_dev *indio_dev,
1014 const struct iio_chan_spec *chan,
1015 enum iio_event_type type,
1016 enum iio_event_direction dir,
1017 enum iio_event_info info,
1018 int val, int val2)
1019 {
1020 struct adxl367_state *st = iio_priv(indio_dev);
1021
1022 switch (info) {
1023 case IIO_EV_INFO_VALUE:
1024 if (val < 0)
1025 return -EINVAL;
1026
1027 switch (dir) {
1028 case IIO_EV_DIR_RISING:
1029 return adxl367_set_act_threshold(st, ADXL367_ACTIVITY, val);
1030 case IIO_EV_DIR_FALLING:
1031 return adxl367_set_act_threshold(st, ADXL367_INACTIVITY, val);
1032 default:
1033 return -EINVAL;
1034 }
1035 case IIO_EV_INFO_PERIOD:
1036 if (val < 0)
1037 return -EINVAL;
1038
1039 val = val * 1000 + DIV_ROUND_UP(val2, 1000);
1040 switch (dir) {
1041 case IIO_EV_DIR_RISING:
1042 return adxl367_set_act_time_ms(st, ADXL367_ACTIVITY, val);
1043 case IIO_EV_DIR_FALLING:
1044 return adxl367_set_act_time_ms(st, ADXL367_INACTIVITY, val);
1045 default:
1046 return -EINVAL;
1047 }
1048 default:
1049 return -EINVAL;
1050 }
1051 }
1052
adxl367_read_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir)1053 static int adxl367_read_event_config(struct iio_dev *indio_dev,
1054 const struct iio_chan_spec *chan,
1055 enum iio_event_type type,
1056 enum iio_event_direction dir)
1057 {
1058 struct adxl367_state *st = iio_priv(indio_dev);
1059 bool en;
1060 int ret;
1061
1062 switch (dir) {
1063 case IIO_EV_DIR_RISING:
1064 ret = adxl367_get_act_interrupt_en(st, ADXL367_ACTIVITY, &en);
1065 return ret ?: en;
1066 case IIO_EV_DIR_FALLING:
1067 ret = adxl367_get_act_interrupt_en(st, ADXL367_INACTIVITY, &en);
1068 return ret ?: en;
1069 default:
1070 return -EINVAL;
1071 }
1072 }
1073
__adxl367_write_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,bool state)1074 static int __adxl367_write_event_config(struct iio_dev *indio_dev,
1075 const struct iio_chan_spec *chan,
1076 enum iio_event_type type,
1077 enum iio_event_direction dir,
1078 bool state)
1079 {
1080 struct adxl367_state *st = iio_priv(indio_dev);
1081 enum adxl367_activity_type act;
1082 int ret;
1083
1084 switch (dir) {
1085 case IIO_EV_DIR_RISING:
1086 act = ADXL367_ACTIVITY;
1087 break;
1088 case IIO_EV_DIR_FALLING:
1089 act = ADXL367_INACTIVITY;
1090 break;
1091 default:
1092 return -EINVAL;
1093 }
1094
1095 guard(mutex)(&st->lock);
1096
1097 ret = adxl367_set_measure_en(st, false);
1098 if (ret)
1099 return ret;
1100
1101 ret = adxl367_set_act_interrupt_en(st, act, state);
1102 if (ret)
1103 return ret;
1104
1105 ret = adxl367_set_act_en(st, act, state ? ADCL367_ACT_REF_ENABLED
1106 : ADXL367_ACT_DISABLED);
1107 if (ret)
1108 return ret;
1109
1110 return adxl367_set_measure_en(st, true);
1111 }
1112
adxl367_write_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,bool state)1113 static int adxl367_write_event_config(struct iio_dev *indio_dev,
1114 const struct iio_chan_spec *chan,
1115 enum iio_event_type type,
1116 enum iio_event_direction dir,
1117 bool state)
1118 {
1119 int ret;
1120
1121 if (!iio_device_claim_direct(indio_dev))
1122 return -EBUSY;
1123
1124 ret = __adxl367_write_event_config(indio_dev, chan, type, dir, state);
1125 iio_device_release_direct(indio_dev);
1126 return ret;
1127 }
1128
adxl367_get_fifo_enabled(struct device * dev,struct device_attribute * attr,char * buf)1129 static ssize_t adxl367_get_fifo_enabled(struct device *dev,
1130 struct device_attribute *attr,
1131 char *buf)
1132 {
1133 struct adxl367_state *st = iio_priv(dev_to_iio_dev(dev));
1134 enum adxl367_fifo_mode fifo_mode;
1135 int ret;
1136
1137 ret = adxl367_get_fifo_mode(st, &fifo_mode);
1138 if (ret)
1139 return ret;
1140
1141 return sysfs_emit(buf, "%d\n", fifo_mode != ADXL367_FIFO_MODE_DISABLED);
1142 }
1143
adxl367_get_fifo_watermark(struct device * dev,struct device_attribute * attr,char * buf)1144 static ssize_t adxl367_get_fifo_watermark(struct device *dev,
1145 struct device_attribute *attr,
1146 char *buf)
1147 {
1148 struct adxl367_state *st = iio_priv(dev_to_iio_dev(dev));
1149 unsigned int fifo_watermark;
1150
1151 guard(mutex)(&st->lock);
1152 fifo_watermark = st->fifo_watermark;
1153
1154 return sysfs_emit(buf, "%d\n", fifo_watermark);
1155 }
1156
1157 IIO_STATIC_CONST_DEVICE_ATTR(hwfifo_watermark_min, "1");
1158 IIO_STATIC_CONST_DEVICE_ATTR(hwfifo_watermark_max,
1159 __stringify(ADXL367_FIFO_MAX_WATERMARK));
1160 static IIO_DEVICE_ATTR(hwfifo_watermark, 0444,
1161 adxl367_get_fifo_watermark, NULL, 0);
1162 static IIO_DEVICE_ATTR(hwfifo_enabled, 0444,
1163 adxl367_get_fifo_enabled, NULL, 0);
1164
1165 static const struct iio_dev_attr *adxl367_fifo_attributes[] = {
1166 &iio_dev_attr_hwfifo_watermark_min,
1167 &iio_dev_attr_hwfifo_watermark_max,
1168 &iio_dev_attr_hwfifo_watermark,
1169 &iio_dev_attr_hwfifo_enabled,
1170 NULL,
1171 };
1172
adxl367_set_watermark(struct iio_dev * indio_dev,unsigned int val)1173 static int adxl367_set_watermark(struct iio_dev *indio_dev, unsigned int val)
1174 {
1175 struct adxl367_state *st = iio_priv(indio_dev);
1176 int ret;
1177
1178 if (val > ADXL367_FIFO_MAX_WATERMARK)
1179 return -EINVAL;
1180
1181 guard(mutex)(&st->lock);
1182
1183 ret = adxl367_set_measure_en(st, false);
1184 if (ret)
1185 return ret;
1186
1187 ret = adxl367_set_fifo_watermark(st, val);
1188 if (ret)
1189 return ret;
1190
1191 return adxl367_set_measure_en(st, true);
1192 }
1193
adxl367_find_mask_fifo_format(const unsigned long * scan_mask,enum adxl367_fifo_format * fifo_format)1194 static bool adxl367_find_mask_fifo_format(const unsigned long *scan_mask,
1195 enum adxl367_fifo_format *fifo_format)
1196 {
1197 size_t size = ARRAY_SIZE(adxl367_fifo_formats);
1198 int i;
1199
1200 for (i = 0; i < size; i++)
1201 if (*scan_mask == adxl367_channel_masks[i])
1202 break;
1203
1204 if (i == size)
1205 return false;
1206
1207 *fifo_format = adxl367_fifo_formats[i];
1208
1209 return true;
1210 }
1211
adxl367_update_scan_mode(struct iio_dev * indio_dev,const unsigned long * active_scan_mask)1212 static int adxl367_update_scan_mode(struct iio_dev *indio_dev,
1213 const unsigned long *active_scan_mask)
1214 {
1215 struct adxl367_state *st = iio_priv(indio_dev);
1216 enum adxl367_fifo_format fifo_format;
1217 int ret;
1218
1219 if (!adxl367_find_mask_fifo_format(active_scan_mask, &fifo_format))
1220 return -EINVAL;
1221
1222 guard(mutex)(&st->lock);
1223
1224 ret = adxl367_set_measure_en(st, false);
1225 if (ret)
1226 return ret;
1227
1228 ret = adxl367_set_fifo_format(st, fifo_format);
1229 if (ret)
1230 return ret;
1231
1232 ret = adxl367_set_measure_en(st, true);
1233 if (ret)
1234 return ret;
1235
1236 st->fifo_set_size = bitmap_weight(active_scan_mask,
1237 iio_get_masklength(indio_dev));
1238
1239 return 0;
1240 }
1241
adxl367_buffer_postenable(struct iio_dev * indio_dev)1242 static int adxl367_buffer_postenable(struct iio_dev *indio_dev)
1243 {
1244 struct adxl367_state *st = iio_priv(indio_dev);
1245 int ret;
1246
1247 guard(mutex)(&st->lock);
1248
1249 ret = adxl367_set_temp_adc_mask_en(st, indio_dev->active_scan_mask,
1250 true);
1251 if (ret)
1252 return ret;
1253
1254 ret = adxl367_set_measure_en(st, false);
1255 if (ret)
1256 return ret;
1257
1258 ret = adxl367_set_fifo_watermark_interrupt_en(st, true);
1259 if (ret)
1260 return ret;
1261
1262 ret = adxl367_set_fifo_mode(st, ADXL367_FIFO_MODE_STREAM);
1263 if (ret)
1264 return ret;
1265
1266 return adxl367_set_measure_en(st, true);
1267 }
1268
adxl367_buffer_predisable(struct iio_dev * indio_dev)1269 static int adxl367_buffer_predisable(struct iio_dev *indio_dev)
1270 {
1271 struct adxl367_state *st = iio_priv(indio_dev);
1272 int ret;
1273
1274 guard(mutex)(&st->lock);
1275
1276 ret = adxl367_set_measure_en(st, false);
1277 if (ret)
1278 return ret;
1279
1280 ret = adxl367_set_fifo_mode(st, ADXL367_FIFO_MODE_DISABLED);
1281 if (ret)
1282 return ret;
1283
1284 ret = adxl367_set_fifo_watermark_interrupt_en(st, false);
1285 if (ret)
1286 return ret;
1287
1288 ret = adxl367_set_measure_en(st, true);
1289 if (ret)
1290 return ret;
1291
1292 return adxl367_set_temp_adc_mask_en(st, indio_dev->active_scan_mask,
1293 false);
1294 }
1295
1296 static const struct iio_buffer_setup_ops adxl367_buffer_ops = {
1297 .postenable = adxl367_buffer_postenable,
1298 .predisable = adxl367_buffer_predisable,
1299 };
1300
1301 static const struct iio_info adxl367_info = {
1302 .read_raw = adxl367_read_raw,
1303 .write_raw = adxl367_write_raw,
1304 .write_raw_get_fmt = adxl367_write_raw_get_fmt,
1305 .read_avail = adxl367_read_avail,
1306 .read_event_config = adxl367_read_event_config,
1307 .write_event_config = adxl367_write_event_config,
1308 .read_event_value = adxl367_read_event_value,
1309 .write_event_value = adxl367_write_event_value,
1310 .debugfs_reg_access = adxl367_reg_access,
1311 .hwfifo_set_watermark = adxl367_set_watermark,
1312 .update_scan_mode = adxl367_update_scan_mode,
1313 };
1314
1315 static const struct iio_event_spec adxl367_events[] = {
1316 {
1317 .type = IIO_EV_TYPE_MAG_REFERENCED,
1318 .dir = IIO_EV_DIR_RISING,
1319 .mask_shared_by_type = BIT(IIO_EV_INFO_ENABLE) |
1320 BIT(IIO_EV_INFO_PERIOD) |
1321 BIT(IIO_EV_INFO_VALUE),
1322 },
1323 {
1324 .type = IIO_EV_TYPE_MAG_REFERENCED,
1325 .dir = IIO_EV_DIR_FALLING,
1326 .mask_shared_by_type = BIT(IIO_EV_INFO_ENABLE) |
1327 BIT(IIO_EV_INFO_PERIOD) |
1328 BIT(IIO_EV_INFO_VALUE),
1329 },
1330 };
1331
1332 #define ADXL367_ACCEL_CHANNEL(index, reg, axis) { \
1333 .type = IIO_ACCEL, \
1334 .address = (reg), \
1335 .modified = 1, \
1336 .channel2 = IIO_MOD_##axis, \
1337 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
1338 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
1339 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE), \
1340 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
1341 .info_mask_shared_by_all_available = \
1342 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
1343 .event_spec = adxl367_events, \
1344 .num_event_specs = ARRAY_SIZE(adxl367_events), \
1345 .scan_index = (index), \
1346 .scan_type = { \
1347 .sign = 's', \
1348 .realbits = 14, \
1349 .storagebits = 16, \
1350 .endianness = IIO_BE, \
1351 }, \
1352 }
1353
1354 #define ADXL367_CHANNEL(index, reg, _type) { \
1355 .type = (_type), \
1356 .address = (reg), \
1357 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1358 BIT(IIO_CHAN_INFO_OFFSET) | \
1359 BIT(IIO_CHAN_INFO_SCALE), \
1360 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
1361 .scan_index = (index), \
1362 .scan_type = { \
1363 .sign = 's', \
1364 .realbits = 14, \
1365 .storagebits = 16, \
1366 .endianness = IIO_BE, \
1367 }, \
1368 }
1369
1370 static const struct iio_chan_spec adxl367_channels[] = {
1371 ADXL367_ACCEL_CHANNEL(ADXL367_X_CHANNEL_INDEX, ADXL367_REG_X_DATA_H, X),
1372 ADXL367_ACCEL_CHANNEL(ADXL367_Y_CHANNEL_INDEX, ADXL367_REG_Y_DATA_H, Y),
1373 ADXL367_ACCEL_CHANNEL(ADXL367_Z_CHANNEL_INDEX, ADXL367_REG_Z_DATA_H, Z),
1374 ADXL367_CHANNEL(ADXL367_TEMP_CHANNEL_INDEX, ADXL367_REG_TEMP_DATA_H,
1375 IIO_TEMP),
1376 ADXL367_CHANNEL(ADXL367_EX_ADC_CHANNEL_INDEX, ADXL367_REG_EX_ADC_DATA_H,
1377 IIO_VOLTAGE),
1378 };
1379
adxl367_verify_devid(struct adxl367_state * st)1380 static int adxl367_verify_devid(struct adxl367_state *st)
1381 {
1382 unsigned int val;
1383 int ret;
1384
1385 ret = regmap_read(st->regmap, ADXL367_REG_DEVID, &val);
1386 if (ret)
1387 return dev_err_probe(st->dev, ret, "Failed to read dev id\n");
1388
1389 if (val != ADXL367_DEVID_AD)
1390 return dev_err_probe(st->dev, -ENODEV,
1391 "Invalid dev id 0x%02X, expected 0x%02X\n",
1392 val, ADXL367_DEVID_AD);
1393
1394 return 0;
1395 }
1396
adxl367_setup(struct adxl367_state * st)1397 static int adxl367_setup(struct adxl367_state *st)
1398 {
1399 int ret;
1400
1401 ret = _adxl367_set_act_threshold(st, ADXL367_ACTIVITY,
1402 ADXL367_2G_RANGE_1G);
1403 if (ret)
1404 return ret;
1405
1406 ret = _adxl367_set_act_threshold(st, ADXL367_INACTIVITY,
1407 ADXL367_2G_RANGE_100MG);
1408 if (ret)
1409 return ret;
1410
1411 ret = adxl367_set_act_proc_mode(st, ADXL367_LOOPED);
1412 if (ret)
1413 return ret;
1414
1415 ret = _adxl367_set_odr(st, ADXL367_ODR_400HZ);
1416 if (ret)
1417 return ret;
1418
1419 ret = _adxl367_set_act_time_ms(st, 10);
1420 if (ret)
1421 return ret;
1422
1423 ret = _adxl367_set_inact_time_ms(st, 10000);
1424 if (ret)
1425 return ret;
1426
1427 return adxl367_set_measure_en(st, true);
1428 }
1429
adxl367_probe(struct device * dev,const struct adxl367_ops * ops,void * context,struct regmap * regmap,int irq)1430 int adxl367_probe(struct device *dev, const struct adxl367_ops *ops,
1431 void *context, struct regmap *regmap, int irq)
1432 {
1433 static const char * const regulator_names[] = { "vdd", "vddio" };
1434 struct iio_dev *indio_dev;
1435 struct adxl367_state *st;
1436 int ret;
1437
1438 indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
1439 if (!indio_dev)
1440 return -ENOMEM;
1441
1442 st = iio_priv(indio_dev);
1443 st->dev = dev;
1444 st->regmap = regmap;
1445 st->context = context;
1446 st->ops = ops;
1447
1448 mutex_init(&st->lock);
1449
1450 indio_dev->channels = adxl367_channels;
1451 indio_dev->num_channels = ARRAY_SIZE(adxl367_channels);
1452 indio_dev->available_scan_masks = adxl367_channel_masks;
1453 indio_dev->name = "adxl367";
1454 indio_dev->info = &adxl367_info;
1455 indio_dev->modes = INDIO_DIRECT_MODE;
1456
1457 ret = devm_regulator_bulk_get_enable(st->dev,
1458 ARRAY_SIZE(regulator_names),
1459 regulator_names);
1460 if (ret)
1461 return dev_err_probe(st->dev, ret,
1462 "Failed to get regulators\n");
1463
1464 ret = regmap_write(st->regmap, ADXL367_REG_RESET, ADXL367_RESET_CODE);
1465 if (ret)
1466 return ret;
1467
1468 fsleep(15000);
1469
1470 ret = adxl367_verify_devid(st);
1471 if (ret)
1472 return ret;
1473
1474 ret = adxl367_setup(st);
1475 if (ret)
1476 return ret;
1477
1478 ret = devm_iio_kfifo_buffer_setup_ext(st->dev, indio_dev,
1479 &adxl367_buffer_ops,
1480 adxl367_fifo_attributes);
1481 if (ret)
1482 return ret;
1483
1484 ret = devm_request_threaded_irq(st->dev, irq, NULL,
1485 adxl367_irq_handler, IRQF_ONESHOT,
1486 indio_dev->name, indio_dev);
1487 if (ret)
1488 return dev_err_probe(st->dev, ret, "Failed to request irq\n");
1489
1490 return devm_iio_device_register(dev, indio_dev);
1491 }
1492 EXPORT_SYMBOL_NS_GPL(adxl367_probe, "IIO_ADXL367");
1493
1494 MODULE_AUTHOR("Cosmin Tanislav <cosmin.tanislav@analog.com>");
1495 MODULE_DESCRIPTION("Analog Devices ADXL367 3-axis accelerometer driver");
1496 MODULE_LICENSE("GPL");
1497