1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // This file is provided under a dual BSD/GPLv2 license. When using or 4 // redistributing this file, you may do so under either license. 5 // 6 // Copyright(c) 2021, 2023 Advanced Micro Devices, Inc. All rights reserved. 7 // 8 // Authors: Vijendar Mukunda <Vijendar.Mukunda@amd.com> 9 // Ajit Kumar Pandey <AjitKumar.Pandey@amd.com> 10 11 /* 12 * Hardware interface for generic AMD ACP processor 13 */ 14 15 #include <linux/io.h> 16 #include <linux/module.h> 17 #include <linux/pci.h> 18 19 #include <asm/amd/node.h> 20 21 #include "../ops.h" 22 #include "acp.h" 23 #include "acp-dsp-offset.h" 24 25 static bool enable_fw_debug; 26 module_param(enable_fw_debug, bool, 0444); 27 MODULE_PARM_DESC(enable_fw_debug, "Enable Firmware debug"); 28 29 static struct acp_quirk_entry quirk_valve_galileo = { 30 .signed_fw_image = true, 31 .skip_iram_dram_size_mod = true, 32 .post_fw_run_delay = true, 33 }; 34 35 const struct dmi_system_id acp_sof_quirk_table[] = { 36 { 37 /* Steam Deck OLED device */ 38 .matches = { 39 DMI_MATCH(DMI_SYS_VENDOR, "Valve"), 40 DMI_MATCH(DMI_PRODUCT_NAME, "Galileo"), 41 }, 42 .driver_data = &quirk_valve_galileo, 43 }, 44 {} 45 }; 46 EXPORT_SYMBOL_GPL(acp_sof_quirk_table); 47 48 static void init_dma_descriptor(struct acp_dev_data *adata) 49 { 50 struct snd_sof_dev *sdev = adata->dev; 51 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 52 struct acp_dev_data *acp_data = sdev->pdata->hw_pdata; 53 unsigned int addr; 54 unsigned int acp_dma_desc_base_addr, acp_dma_desc_max_num_dscr; 55 56 addr = desc->sram_pte_offset + sdev->debug_box.offset + 57 offsetof(struct scratch_reg_conf, dma_desc); 58 59 switch (acp_data->pci_rev) { 60 case ACP70_PCI_ID: 61 case ACP71_PCI_ID: 62 case ACP72_PCI_ID: 63 acp_dma_desc_base_addr = ACP70_DMA_DESC_BASE_ADDR; 64 acp_dma_desc_max_num_dscr = ACP70_DMA_DESC_MAX_NUM_DSCR; 65 break; 66 default: 67 acp_dma_desc_base_addr = ACP_DMA_DESC_BASE_ADDR; 68 acp_dma_desc_max_num_dscr = ACP_DMA_DESC_MAX_NUM_DSCR; 69 } 70 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_desc_base_addr, addr); 71 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_desc_max_num_dscr, ACP_MAX_DESC_CNT); 72 } 73 74 static void configure_dma_descriptor(struct acp_dev_data *adata, unsigned short idx, 75 struct dma_descriptor *dscr_info) 76 { 77 struct snd_sof_dev *sdev = adata->dev; 78 unsigned int offset; 79 80 offset = ACP_SCRATCH_REG_0 + sdev->debug_box.offset + 81 offsetof(struct scratch_reg_conf, dma_desc) + 82 idx * sizeof(struct dma_descriptor); 83 84 snd_sof_dsp_write(sdev, ACP_DSP_BAR, offset, dscr_info->src_addr); 85 snd_sof_dsp_write(sdev, ACP_DSP_BAR, offset + 0x4, dscr_info->dest_addr); 86 snd_sof_dsp_write(sdev, ACP_DSP_BAR, offset + 0x8, dscr_info->tx_cnt.u32_all); 87 } 88 89 static int config_dma_channel(struct acp_dev_data *adata, unsigned int ch, 90 unsigned int idx, unsigned int dscr_count) 91 { 92 struct snd_sof_dev *sdev = adata->dev; 93 struct acp_dev_data *acp_data = sdev->pdata->hw_pdata; 94 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 95 unsigned int val, status; 96 unsigned int acp_dma_cntl_0, acp_dma_ch_rst_sts, acp_dma_dscr_err_sts_0; 97 unsigned int acp_dma_dscr_cnt_0, acp_dma_prio_0, acp_dma_dscr_strt_idx_0; 98 int ret; 99 100 switch (acp_data->pci_rev) { 101 case ACP70_PCI_ID: 102 case ACP71_PCI_ID: 103 case ACP72_PCI_ID: 104 acp_dma_cntl_0 = ACP70_DMA_CNTL_0; 105 acp_dma_ch_rst_sts = ACP70_DMA_CH_RST_STS; 106 acp_dma_dscr_err_sts_0 = ACP70_DMA_ERR_STS_0; 107 acp_dma_dscr_cnt_0 = ACP70_DMA_DSCR_CNT_0; 108 acp_dma_prio_0 = ACP70_DMA_PRIO_0; 109 acp_dma_dscr_strt_idx_0 = ACP70_DMA_DSCR_STRT_IDX_0; 110 break; 111 default: 112 acp_dma_cntl_0 = ACP_DMA_CNTL_0; 113 acp_dma_ch_rst_sts = ACP_DMA_CH_RST_STS; 114 acp_dma_dscr_err_sts_0 = ACP_DMA_ERR_STS_0; 115 acp_dma_dscr_cnt_0 = ACP_DMA_DSCR_CNT_0; 116 acp_dma_prio_0 = ACP_DMA_PRIO_0; 117 acp_dma_dscr_strt_idx_0 = ACP_DMA_DSCR_STRT_IDX_0; 118 } 119 120 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_cntl_0 + ch * sizeof(u32), 121 ACP_DMA_CH_RST | ACP_DMA_CH_GRACEFUL_RST_EN); 122 123 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, acp_dma_ch_rst_sts, val, 124 val & (1 << ch), ACP_REG_POLL_INTERVAL, 125 ACP_REG_POLL_TIMEOUT_US); 126 if (ret < 0) { 127 status = snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->acp_error_stat); 128 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, acp_dma_dscr_err_sts_0 + 129 ch * sizeof(u32)); 130 131 dev_err(sdev->dev, "ACP_DMA_ERR_STS :0x%x ACP_ERROR_STATUS :0x%x\n", val, status); 132 return ret; 133 } 134 135 snd_sof_dsp_write(sdev, ACP_DSP_BAR, (acp_dma_cntl_0 + ch * sizeof(u32)), 0); 136 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_dscr_cnt_0 + ch * sizeof(u32), dscr_count); 137 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_dscr_strt_idx_0 + ch * sizeof(u32), idx); 138 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_prio_0 + ch * sizeof(u32), 0); 139 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_cntl_0 + ch * sizeof(u32), ACP_DMA_CH_RUN); 140 141 return ret; 142 } 143 144 static int acpbus_dma_start(struct acp_dev_data *adata, unsigned int ch, 145 unsigned int dscr_count, struct dma_descriptor *dscr_info) 146 { 147 struct snd_sof_dev *sdev = adata->dev; 148 int ret; 149 u16 dscr; 150 151 if (!dscr_info || !dscr_count) 152 return -EINVAL; 153 154 for (dscr = 0; dscr < dscr_count; dscr++) 155 configure_dma_descriptor(adata, dscr, dscr_info++); 156 157 ret = config_dma_channel(adata, ch, 0, dscr_count); 158 if (ret < 0) 159 dev_err(sdev->dev, "config dma ch failed:%d\n", ret); 160 161 return ret; 162 } 163 164 int configure_and_run_dma(struct acp_dev_data *adata, unsigned int src_addr, 165 unsigned int dest_addr, int dsp_data_size) 166 { 167 struct snd_sof_dev *sdev = adata->dev; 168 unsigned int desc_count, index; 169 int ret; 170 171 for (desc_count = 0; desc_count < ACP_MAX_DESC && dsp_data_size >= 0; 172 desc_count++, dsp_data_size -= ACP_PAGE_SIZE) { 173 adata->dscr_info[desc_count].src_addr = src_addr + desc_count * ACP_PAGE_SIZE; 174 adata->dscr_info[desc_count].dest_addr = dest_addr + desc_count * ACP_PAGE_SIZE; 175 adata->dscr_info[desc_count].tx_cnt.bits.count = ACP_PAGE_SIZE; 176 if (dsp_data_size < ACP_PAGE_SIZE) 177 adata->dscr_info[desc_count].tx_cnt.bits.count = dsp_data_size; 178 } 179 180 ret = acpbus_dma_start(adata, 0, desc_count, adata->dscr_info); 181 if (ret) 182 dev_err(sdev->dev, "acpbus_dma_start failed\n"); 183 184 /* Clear descriptor array */ 185 for (index = 0; index < desc_count; index++) 186 memset(&adata->dscr_info[index], 0x00, sizeof(struct dma_descriptor)); 187 188 return ret; 189 } 190 191 /* 192 * psp_mbox_ready- function to poll ready bit of psp mbox 193 * @adata: acp device data 194 * @ack: bool variable to check ready bit status or psp ack 195 */ 196 197 static int psp_mbox_ready(struct acp_dev_data *adata, bool ack) 198 { 199 struct snd_sof_dev *sdev = adata->dev; 200 int ret, data; 201 202 ret = read_poll_timeout(smn_read_register, data, data > 0 && data & MBOX_READY_MASK, 203 MBOX_DELAY_US, ACP_PSP_TIMEOUT_US, false, MP0_C2PMSG_114_REG); 204 205 if (!ret) 206 return 0; 207 208 dev_err(sdev->dev, "PSP error status %x\n", data & MBOX_STATUS_MASK); 209 210 if (ack) 211 return -ETIMEDOUT; 212 213 return -EBUSY; 214 } 215 216 /* 217 * psp_send_cmd - function to send psp command over mbox 218 * @adata: acp device data 219 * @cmd: non zero integer value for command type 220 */ 221 222 static int psp_send_cmd(struct acp_dev_data *adata, int cmd) 223 { 224 struct snd_sof_dev *sdev = adata->dev; 225 int ret; 226 int data; 227 228 if (!cmd) 229 return -EINVAL; 230 231 /* Get a non-zero Doorbell value from PSP */ 232 ret = read_poll_timeout(smn_read_register, data, data > 0, MBOX_DELAY_US, 233 ACP_PSP_TIMEOUT_US, false, MP0_C2PMSG_73_REG); 234 235 if (ret) { 236 dev_err(sdev->dev, "Failed to get Doorbell from MBOX %x\n", MP0_C2PMSG_73_REG); 237 return ret; 238 } 239 240 /* Check if PSP is ready for new command */ 241 ret = psp_mbox_ready(adata, 0); 242 if (ret) 243 return ret; 244 245 ret = amd_smn_write(0, MP0_C2PMSG_114_REG, cmd); 246 if (ret) 247 return ret; 248 249 /* Ring the Doorbell for PSP */ 250 ret = amd_smn_write(0, MP0_C2PMSG_73_REG, data); 251 if (ret) 252 return ret; 253 254 /* Check MBOX ready as PSP ack */ 255 ret = psp_mbox_ready(adata, 1); 256 257 return ret; 258 } 259 260 int configure_and_run_sha_dma(struct acp_dev_data *adata, void *image_addr, 261 unsigned int start_addr, unsigned int dest_addr, 262 unsigned int image_length) 263 { 264 struct snd_sof_dev *sdev = adata->dev; 265 unsigned int tx_count, fw_qualifier, val; 266 int ret; 267 268 if (!image_addr) { 269 dev_err(sdev->dev, "SHA DMA image address is NULL\n"); 270 return -EINVAL; 271 } 272 273 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD); 274 if (val & ACP_SHA_RUN) { 275 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD, ACP_SHA_RESET); 276 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD_STS, 277 val, val & ACP_SHA_RESET, 278 ACP_REG_POLL_INTERVAL, 279 ACP_REG_POLL_TIMEOUT_US); 280 if (ret < 0) { 281 dev_err(sdev->dev, "SHA DMA Failed to Reset\n"); 282 return ret; 283 } 284 } 285 286 if (adata->quirks && adata->quirks->signed_fw_image) 287 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_INCLUDE_HDR, ACP_SHA_HEADER); 288 289 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_STRT_ADDR, start_addr); 290 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_DESTINATION_ADDR, dest_addr); 291 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_MSG_LENGTH, image_length); 292 293 /* psp_send_cmd only required for vangogh platform */ 294 if (adata->pci_rev == ACP_VANGOGH_PCI_ID && 295 !(adata->quirks && adata->quirks->skip_iram_dram_size_mod)) { 296 /* Modify IRAM and DRAM size */ 297 ret = psp_send_cmd(adata, MBOX_ACP_IRAM_DRAM_FENCE_COMMAND | IRAM_DRAM_FENCE_2); 298 if (ret) 299 return ret; 300 ret = psp_send_cmd(adata, MBOX_ACP_IRAM_DRAM_FENCE_COMMAND | MBOX_ISREADY_FLAG); 301 if (ret) 302 return ret; 303 } 304 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD, ACP_SHA_RUN); 305 306 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SHA_TRANSFER_BYTE_CNT, 307 tx_count, tx_count == image_length, 308 ACP_REG_POLL_INTERVAL, ACP_DMA_COMPLETE_TIMEOUT_US); 309 if (ret < 0) { 310 dev_err(sdev->dev, "SHA DMA Failed to Transfer Length %x\n", tx_count); 311 return ret; 312 } 313 314 /* psp_send_cmd only required for renoir platform*/ 315 if (adata->pci_rev == ACP_RN_PCI_ID) { 316 ret = psp_send_cmd(adata, MBOX_ACP_SHA_DMA_COMMAND); 317 if (ret) 318 return ret; 319 } 320 321 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SHA_DSP_FW_QUALIFIER, 322 fw_qualifier, fw_qualifier & DSP_FW_RUN_ENABLE, 323 ACP_REG_POLL_INTERVAL, ACP_DMA_COMPLETE_TIMEOUT_US); 324 if (ret < 0) { 325 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SHA_PSP_ACK); 326 dev_err(sdev->dev, "PSP validation failed: fw_qualifier = %#x, ACP_SHA_PSP_ACK = %#x\n", 327 fw_qualifier, val); 328 return ret; 329 } 330 331 return 0; 332 } 333 334 int acp_dma_status(struct acp_dev_data *adata, unsigned char ch) 335 { 336 struct snd_sof_dev *sdev = adata->dev; 337 unsigned int val; 338 unsigned int acp_dma_ch_sts; 339 int ret = 0; 340 341 switch (adata->pci_rev) { 342 case ACP70_PCI_ID: 343 case ACP71_PCI_ID: 344 case ACP72_PCI_ID: 345 acp_dma_ch_sts = ACP70_DMA_CH_STS; 346 break; 347 default: 348 acp_dma_ch_sts = ACP_DMA_CH_STS; 349 } 350 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_DMA_CNTL_0 + ch * sizeof(u32)); 351 if (val & ACP_DMA_CH_RUN) { 352 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, acp_dma_ch_sts, val, !val, 353 ACP_REG_POLL_INTERVAL, 354 ACP_DMA_COMPLETE_TIMEOUT_US); 355 if (ret < 0) 356 dev_err(sdev->dev, "DMA_CHANNEL %d status timeout\n", ch); 357 } 358 359 return ret; 360 } 361 362 void memcpy_from_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *dst, size_t bytes) 363 { 364 unsigned int reg_offset = offset + ACP_SCRATCH_REG_0; 365 int i, j; 366 367 for (i = 0, j = 0; i < bytes; i = i + 4, j++) 368 dst[j] = snd_sof_dsp_read(sdev, ACP_DSP_BAR, reg_offset + i); 369 } 370 371 void memcpy_to_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *src, size_t bytes) 372 { 373 unsigned int reg_offset = offset + ACP_SCRATCH_REG_0; 374 int i, j; 375 376 for (i = 0, j = 0; i < bytes; i = i + 4, j++) 377 snd_sof_dsp_write(sdev, ACP_DSP_BAR, reg_offset + i, src[j]); 378 } 379 380 static int acp_init_scratch_mem_ipc_flags(struct snd_sof_dev *sdev) 381 { 382 u32 dsp_msg_write, dsp_ack_write, host_msg_write, host_ack_write; 383 384 dsp_msg_write = sdev->debug_box.offset + 385 offsetof(struct scratch_ipc_conf, sof_dsp_msg_write); 386 dsp_ack_write = sdev->debug_box.offset + 387 offsetof(struct scratch_ipc_conf, sof_dsp_ack_write); 388 host_msg_write = sdev->debug_box.offset + 389 offsetof(struct scratch_ipc_conf, sof_host_msg_write); 390 host_ack_write = sdev->debug_box.offset + 391 offsetof(struct scratch_ipc_conf, sof_host_ack_write); 392 /* Initialize host message write flag */ 393 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SCRATCH_REG_0 + host_msg_write, 0); 394 395 /* Initialize host ack write flag */ 396 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SCRATCH_REG_0 + host_ack_write, 0); 397 398 /* Initialize DSP message write flag */ 399 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SCRATCH_REG_0 + dsp_msg_write, 0); 400 401 /* Initialize DSP ack write flag */ 402 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SCRATCH_REG_0 + dsp_ack_write, 0); 403 404 return 0; 405 } 406 407 static int acp_memory_init(struct snd_sof_dev *sdev) 408 { 409 struct acp_dev_data *adata = sdev->pdata->hw_pdata; 410 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 411 412 snd_sof_dsp_update_bits(sdev, ACP_DSP_BAR, desc->dsp_intr_base + DSP_SW_INTR_CNTL_OFFSET, 413 ACP_DSP_INTR_EN_MASK, ACP_DSP_INTR_EN_MASK); 414 acp_init_scratch_mem_ipc_flags(sdev); 415 init_dma_descriptor(adata); 416 417 return 0; 418 } 419 420 static void amd_sof_handle_acp70_sdw_wake_event(struct acp_dev_data *adata) 421 { 422 struct amd_sdw_manager *amd_manager; 423 424 if (adata->acp70_sdw0_wake_event) { 425 amd_manager = dev_get_drvdata(&adata->sdw->pdev[0]->dev); 426 if (amd_manager) 427 pm_request_resume(amd_manager->dev); 428 adata->acp70_sdw0_wake_event = 0; 429 } 430 431 if (adata->acp70_sdw1_wake_event) { 432 amd_manager = dev_get_drvdata(&adata->sdw->pdev[1]->dev); 433 if (amd_manager) 434 pm_request_resume(amd_manager->dev); 435 adata->acp70_sdw1_wake_event = 0; 436 } 437 } 438 439 static int amd_sof_check_and_handle_acp70_sdw_wake_irq(struct snd_sof_dev *sdev) 440 { 441 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 442 struct acp_dev_data *adata = sdev->pdata->hw_pdata; 443 u32 ext_intr_stat1; 444 int irq_flag = 0; 445 bool sdw_wake_irq = false; 446 447 ext_intr_stat1 = snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->ext_intr_stat1); 448 if (ext_intr_stat1 & ACP70_SDW0_HOST_WAKE_STAT) { 449 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat1, 450 ACP70_SDW0_HOST_WAKE_STAT); 451 adata->acp70_sdw0_wake_event = true; 452 sdw_wake_irq = true; 453 } 454 455 if (ext_intr_stat1 & ACP70_SDW1_HOST_WAKE_STAT) { 456 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat1, 457 ACP70_SDW1_HOST_WAKE_STAT); 458 adata->acp70_sdw1_wake_event = true; 459 sdw_wake_irq = true; 460 } 461 462 if (ext_intr_stat1 & ACP70_SDW0_PME_STAT) { 463 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP70_SW0_WAKE_EN, 0); 464 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat1, ACP70_SDW0_PME_STAT); 465 adata->acp70_sdw0_wake_event = true; 466 sdw_wake_irq = true; 467 } 468 469 if (ext_intr_stat1 & ACP70_SDW1_PME_STAT) { 470 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP70_SW1_WAKE_EN, 0); 471 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat1, ACP70_SDW1_PME_STAT); 472 adata->acp70_sdw1_wake_event = true; 473 sdw_wake_irq = true; 474 } 475 476 if (sdw_wake_irq) { 477 amd_sof_handle_acp70_sdw_wake_event(adata); 478 irq_flag = 1; 479 } 480 return irq_flag; 481 } 482 483 static irqreturn_t acp_irq_thread(int irq, void *context) 484 { 485 struct snd_sof_dev *sdev = context; 486 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 487 unsigned int count = ACP_HW_SEM_RETRY_COUNT; 488 489 spin_lock_irq(&sdev->ipc_lock); 490 /* Wait until acquired HW Semaphore lock or timeout */ 491 while (snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->hw_semaphore_offset) && --count) 492 ; 493 spin_unlock_irq(&sdev->ipc_lock); 494 495 if (!count) { 496 dev_err(sdev->dev, "%s: Failed to acquire HW lock\n", __func__); 497 return IRQ_NONE; 498 } 499 500 sof_ops(sdev)->irq_thread(irq, sdev); 501 /* Unlock or Release HW Semaphore */ 502 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->hw_semaphore_offset, 0x0); 503 504 return IRQ_HANDLED; 505 }; 506 507 static irqreturn_t acp_irq_handler(int irq, void *dev_id) 508 { 509 struct amd_sdw_manager *amd_manager; 510 struct snd_sof_dev *sdev = dev_id; 511 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 512 struct acp_dev_data *adata = sdev->pdata->hw_pdata; 513 unsigned int base = desc->dsp_intr_base; 514 unsigned int val; 515 int irq_flag = 0, wake_irq_flag = 0; 516 517 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, base + DSP_SW_INTR_STAT_OFFSET); 518 if (val & ACP_DSP_TO_HOST_IRQ) { 519 snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + DSP_SW_INTR_STAT_OFFSET, 520 ACP_DSP_TO_HOST_IRQ); 521 return IRQ_WAKE_THREAD; 522 } 523 524 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->ext_intr_stat); 525 if (val & ACP_SDW0_IRQ_MASK) { 526 amd_manager = dev_get_drvdata(&adata->sdw->pdev[0]->dev); 527 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat, ACP_SDW0_IRQ_MASK); 528 if (amd_manager) 529 schedule_work(&amd_manager->amd_sdw_irq_thread); 530 irq_flag = 1; 531 } 532 533 if (val & ACP_ERROR_IRQ_MASK) { 534 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat, ACP_ERROR_IRQ_MASK); 535 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->acp_sw0_i2s_err_reason, 0); 536 /* ACP_SW1_I2S_ERROR_REASON is newly added register from rmb platform onwards */ 537 if (adata->pci_rev >= ACP_RMB_PCI_ID) 538 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SW1_I2S_ERROR_REASON, 0); 539 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->acp_error_stat, 0); 540 irq_flag = 1; 541 } 542 543 if (desc->ext_intr_stat1) { 544 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->ext_intr_stat1); 545 if (val & ACP_SDW1_IRQ_MASK) { 546 amd_manager = dev_get_drvdata(&adata->sdw->pdev[1]->dev); 547 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat1, 548 ACP_SDW1_IRQ_MASK); 549 if (amd_manager) 550 schedule_work(&amd_manager->amd_sdw_irq_thread); 551 irq_flag = 1; 552 } 553 switch (adata->pci_rev) { 554 case ACP70_PCI_ID: 555 case ACP71_PCI_ID: 556 case ACP72_PCI_ID: 557 wake_irq_flag = amd_sof_check_and_handle_acp70_sdw_wake_irq(sdev); 558 break; 559 } 560 } 561 if (irq_flag || wake_irq_flag) 562 return IRQ_HANDLED; 563 else 564 return IRQ_NONE; 565 } 566 567 static int acp_power_on(struct snd_sof_dev *sdev) 568 { 569 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 570 struct acp_dev_data *adata = sdev->pdata->hw_pdata; 571 unsigned int base = desc->pgfsm_base; 572 unsigned int val; 573 unsigned int acp_pgfsm_status_mask, acp_pgfsm_cntl_mask; 574 int ret; 575 576 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, base + PGFSM_STATUS_OFFSET); 577 578 if (val == ACP_POWERED_ON) 579 return 0; 580 581 switch (adata->pci_rev) { 582 case ACP_RN_PCI_ID: 583 case ACP_VANGOGH_PCI_ID: 584 acp_pgfsm_status_mask = ACP3X_PGFSM_STATUS_MASK; 585 acp_pgfsm_cntl_mask = ACP3X_PGFSM_CNTL_POWER_ON_MASK; 586 break; 587 case ACP_RMB_PCI_ID: 588 case ACP63_PCI_ID: 589 acp_pgfsm_status_mask = ACP6X_PGFSM_STATUS_MASK; 590 acp_pgfsm_cntl_mask = ACP6X_PGFSM_CNTL_POWER_ON_MASK; 591 break; 592 case ACP70_PCI_ID: 593 case ACP71_PCI_ID: 594 case ACP72_PCI_ID: 595 acp_pgfsm_status_mask = ACP70_PGFSM_STATUS_MASK; 596 acp_pgfsm_cntl_mask = ACP70_PGFSM_CNTL_POWER_ON_MASK; 597 break; 598 default: 599 return -EINVAL; 600 } 601 602 if (val & acp_pgfsm_status_mask) 603 snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + PGFSM_CONTROL_OFFSET, 604 acp_pgfsm_cntl_mask); 605 606 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, base + PGFSM_STATUS_OFFSET, val, 607 !val, ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US); 608 if (ret < 0) 609 dev_err(sdev->dev, "timeout in ACP_PGFSM_STATUS read\n"); 610 611 return ret; 612 } 613 614 static int acp_reset(struct snd_sof_dev *sdev) 615 { 616 unsigned int val; 617 int ret; 618 619 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, ACP_ASSERT_RESET); 620 621 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, val, 622 val & ACP_SOFT_RESET_DONE_MASK, 623 ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US); 624 if (ret < 0) { 625 dev_err(sdev->dev, "timeout asserting reset\n"); 626 return ret; 627 } 628 629 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, ACP_RELEASE_RESET); 630 631 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, val, !val, 632 ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US); 633 if (ret < 0) 634 dev_err(sdev->dev, "timeout in releasing reset\n"); 635 636 return ret; 637 } 638 639 static int acp_dsp_reset(struct snd_sof_dev *sdev) 640 { 641 unsigned int val; 642 int ret; 643 644 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, ACP_DSP_ASSERT_RESET); 645 646 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, val, 647 val & ACP_DSP_SOFT_RESET_DONE_MASK, 648 ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US); 649 if (ret < 0) { 650 dev_err(sdev->dev, "timeout asserting reset\n"); 651 return ret; 652 } 653 654 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, ACP_DSP_RELEASE_RESET); 655 656 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, val, !val, 657 ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US); 658 if (ret < 0) 659 dev_err(sdev->dev, "timeout in releasing reset\n"); 660 661 return ret; 662 } 663 664 static int acp_init(struct snd_sof_dev *sdev) 665 { 666 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 667 struct acp_dev_data *acp_data; 668 unsigned int sdw0_wake_en, sdw1_wake_en; 669 int ret; 670 671 /* power on */ 672 acp_data = sdev->pdata->hw_pdata; 673 ret = acp_power_on(sdev); 674 if (ret) { 675 dev_err(sdev->dev, "ACP power on failed\n"); 676 return ret; 677 } 678 679 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_CONTROL, 0x01); 680 /* Reset */ 681 ret = acp_reset(sdev); 682 if (ret) 683 return ret; 684 685 if (desc->acp_clkmux_sel) 686 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->acp_clkmux_sel, ACP_CLOCK_ACLK); 687 688 if (desc->ext_intr_enb) 689 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_enb, 0x01); 690 691 if (desc->ext_intr_cntl) 692 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_cntl, ACP_ERROR_IRQ_MASK); 693 694 switch (acp_data->pci_rev) { 695 case ACP70_PCI_ID: 696 case ACP71_PCI_ID: 697 case ACP72_PCI_ID: 698 sdw0_wake_en = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP70_SW0_WAKE_EN); 699 sdw1_wake_en = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP70_SW1_WAKE_EN); 700 if (sdw0_wake_en || sdw1_wake_en) 701 snd_sof_dsp_update_bits(sdev, ACP_DSP_BAR, ACP70_EXTERNAL_INTR_CNTL1, 702 ACP70_SDW_HOST_WAKE_MASK, ACP70_SDW_HOST_WAKE_MASK); 703 704 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP70_PME_EN, 1); 705 break; 706 } 707 return 0; 708 } 709 710 static bool check_acp_sdw_enable_status(struct snd_sof_dev *sdev) 711 { 712 struct acp_dev_data *acp_data; 713 u32 sdw0_en, sdw1_en; 714 715 acp_data = sdev->pdata->hw_pdata; 716 if (!acp_data->sdw) 717 return false; 718 719 sdw0_en = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SW0_EN); 720 sdw1_en = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SW1_EN); 721 acp_data->sdw_en_stat = sdw0_en || sdw1_en; 722 return acp_data->sdw_en_stat; 723 } 724 725 int amd_sof_acp_suspend(struct snd_sof_dev *sdev, u32 target_state) 726 { 727 struct acp_dev_data *acp_data; 728 int ret; 729 bool enable = false; 730 731 acp_data = sdev->pdata->hw_pdata; 732 /* When acp_reset() function is invoked, it will apply ACP SOFT reset and 733 * DSP reset. ACP Soft reset sequence will cause all ACP IP registers will 734 * be reset to default values which will break the ClockStop Mode functionality. 735 * Add a condition check to apply DSP reset when SoundWire ClockStop mode 736 * is selected. For the rest of the scenarios, apply acp reset sequence. 737 */ 738 if (check_acp_sdw_enable_status(sdev)) 739 return acp_dsp_reset(sdev); 740 741 ret = acp_reset(sdev); 742 if (ret) { 743 dev_err(sdev->dev, "ACP Reset failed\n"); 744 return ret; 745 } 746 switch (acp_data->pci_rev) { 747 case ACP70_PCI_ID: 748 case ACP71_PCI_ID: 749 case ACP72_PCI_ID: 750 enable = true; 751 break; 752 } 753 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_CONTROL, enable); 754 755 return 0; 756 } 757 EXPORT_SYMBOL_NS(amd_sof_acp_suspend, "SND_SOC_SOF_AMD_COMMON"); 758 759 int amd_sof_acp_resume(struct snd_sof_dev *sdev) 760 { 761 int ret; 762 struct acp_dev_data *acp_data; 763 764 acp_data = sdev->pdata->hw_pdata; 765 if (!acp_data->sdw_en_stat) { 766 ret = acp_init(sdev); 767 if (ret) { 768 dev_err(sdev->dev, "ACP Init failed\n"); 769 return ret; 770 } 771 return acp_memory_init(sdev); 772 } 773 switch (acp_data->pci_rev) { 774 case ACP70_PCI_ID: 775 case ACP71_PCI_ID: 776 case ACP72_PCI_ID: 777 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP70_PME_EN, 1); 778 break; 779 } 780 781 return acp_dsp_reset(sdev); 782 } 783 EXPORT_SYMBOL_NS(amd_sof_acp_resume, "SND_SOC_SOF_AMD_COMMON"); 784 785 #if IS_ENABLED(CONFIG_SND_SOC_SOF_AMD_SOUNDWIRE) 786 static int acp_sof_scan_sdw_devices(struct snd_sof_dev *sdev, u64 addr) 787 { 788 struct acpi_device *sdw_dev; 789 struct acp_dev_data *acp_data; 790 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 791 792 if (!addr) 793 return -ENODEV; 794 795 acp_data = sdev->pdata->hw_pdata; 796 sdw_dev = acpi_find_child_device(ACPI_COMPANION(sdev->dev), addr, 0); 797 if (!sdw_dev) 798 return -ENODEV; 799 800 acp_data->info.handle = sdw_dev->handle; 801 acp_data->info.count = desc->sdw_max_link_count; 802 803 return amd_sdw_scan_controller(&acp_data->info); 804 } 805 806 static int amd_sof_sdw_probe(struct snd_sof_dev *sdev) 807 { 808 struct acp_dev_data *acp_data; 809 struct sdw_amd_res sdw_res; 810 int ret; 811 812 acp_data = sdev->pdata->hw_pdata; 813 814 memset(&sdw_res, 0, sizeof(sdw_res)); 815 sdw_res.addr = acp_data->addr; 816 sdw_res.reg_range = acp_data->reg_range; 817 sdw_res.handle = acp_data->info.handle; 818 sdw_res.parent = sdev->dev; 819 sdw_res.dev = sdev->dev; 820 sdw_res.acp_lock = &acp_data->acp_lock; 821 sdw_res.count = acp_data->info.count; 822 sdw_res.link_mask = acp_data->info.link_mask; 823 sdw_res.mmio_base = sdev->bar[ACP_DSP_BAR]; 824 sdw_res.acp_rev = acp_data->pci_rev; 825 826 ret = sdw_amd_probe(&sdw_res, &acp_data->sdw); 827 if (ret) 828 dev_err(sdev->dev, "SoundWire probe failed\n"); 829 return ret; 830 } 831 832 static int amd_sof_sdw_exit(struct snd_sof_dev *sdev) 833 { 834 struct acp_dev_data *acp_data; 835 836 acp_data = sdev->pdata->hw_pdata; 837 if (acp_data->sdw) 838 sdw_amd_exit(acp_data->sdw); 839 acp_data->sdw = NULL; 840 841 return 0; 842 } 843 844 #else 845 static int acp_sof_scan_sdw_devices(struct snd_sof_dev *sdev, u64 addr) 846 { 847 return 0; 848 } 849 850 static int amd_sof_sdw_probe(struct snd_sof_dev *sdev) 851 { 852 return 0; 853 } 854 855 static int amd_sof_sdw_exit(struct snd_sof_dev *sdev) 856 { 857 return 0; 858 } 859 #endif 860 861 int amd_sof_acp_probe(struct snd_sof_dev *sdev) 862 { 863 struct pci_dev *pci = to_pci_dev(sdev->dev); 864 struct acp_dev_data *adata; 865 const struct sof_amd_acp_desc *chip; 866 const struct dmi_system_id *dmi_id; 867 unsigned int addr; 868 int ret; 869 870 chip = get_chip_info(sdev->pdata); 871 if (!chip) { 872 dev_err(sdev->dev, "no such device supported, chip id:%x\n", pci->device); 873 return -EIO; 874 } 875 adata = devm_kzalloc(sdev->dev, sizeof(struct acp_dev_data), 876 GFP_KERNEL); 877 if (!adata) 878 return -ENOMEM; 879 880 adata->dev = sdev; 881 adata->dmic_dev = platform_device_register_data(sdev->dev, "dmic-codec", 882 PLATFORM_DEVID_NONE, NULL, 0); 883 if (IS_ERR(adata->dmic_dev)) { 884 dev_err(sdev->dev, "failed to register platform for dmic codec\n"); 885 return PTR_ERR(adata->dmic_dev); 886 } 887 addr = pci_resource_start(pci, ACP_DSP_BAR); 888 sdev->bar[ACP_DSP_BAR] = devm_ioremap(sdev->dev, addr, pci_resource_len(pci, ACP_DSP_BAR)); 889 if (!sdev->bar[ACP_DSP_BAR]) { 890 dev_err(sdev->dev, "ioremap error\n"); 891 ret = -ENXIO; 892 goto unregister_dev; 893 } 894 895 pci_set_master(pci); 896 adata->addr = addr; 897 adata->reg_range = chip->reg_end_addr - chip->reg_start_addr; 898 adata->pci_rev = pci->revision; 899 mutex_init(&adata->acp_lock); 900 sdev->pdata->hw_pdata = adata; 901 902 ret = acp_init(sdev); 903 if (ret < 0) 904 goto unregister_dev; 905 906 sdev->ipc_irq = pci->irq; 907 ret = request_threaded_irq(sdev->ipc_irq, acp_irq_handler, acp_irq_thread, 908 IRQF_SHARED, "AudioDSP", sdev); 909 if (ret < 0) { 910 dev_err(sdev->dev, "failed to register IRQ %d\n", 911 sdev->ipc_irq); 912 goto unregister_dev; 913 } 914 915 /* scan SoundWire capabilities exposed by DSDT */ 916 ret = acp_sof_scan_sdw_devices(sdev, chip->sdw_acpi_dev_addr); 917 if (ret < 0) { 918 dev_dbg(sdev->dev, "skipping SoundWire, not detected with ACPI scan\n"); 919 goto skip_soundwire; 920 } 921 ret = amd_sof_sdw_probe(sdev); 922 if (ret < 0) { 923 dev_err(sdev->dev, "error: SoundWire probe error\n"); 924 free_irq(sdev->ipc_irq, sdev); 925 return ret; 926 } 927 928 skip_soundwire: 929 sdev->dsp_box.offset = 0; 930 sdev->dsp_box.size = BOX_SIZE_512; 931 932 sdev->host_box.offset = sdev->dsp_box.offset + sdev->dsp_box.size; 933 sdev->host_box.size = BOX_SIZE_512; 934 935 sdev->debug_box.offset = sdev->host_box.offset + sdev->host_box.size; 936 sdev->debug_box.size = BOX_SIZE_1024; 937 938 dmi_id = dmi_first_match(acp_sof_quirk_table); 939 if (dmi_id) { 940 adata->quirks = dmi_id->driver_data; 941 942 if (adata->quirks->signed_fw_image) { 943 adata->fw_code_bin = devm_kasprintf(sdev->dev, GFP_KERNEL, 944 "sof-%s-code.bin", 945 chip->name); 946 if (!adata->fw_code_bin) { 947 ret = -ENOMEM; 948 goto free_ipc_irq; 949 } 950 951 adata->fw_data_bin = devm_kasprintf(sdev->dev, GFP_KERNEL, 952 "sof-%s-data.bin", 953 chip->name); 954 if (!adata->fw_data_bin) { 955 ret = -ENOMEM; 956 goto free_ipc_irq; 957 } 958 } 959 } 960 961 adata->enable_fw_debug = enable_fw_debug; 962 acp_memory_init(sdev); 963 964 acp_dsp_stream_init(sdev); 965 966 return 0; 967 968 free_ipc_irq: 969 free_irq(sdev->ipc_irq, sdev); 970 unregister_dev: 971 platform_device_unregister(adata->dmic_dev); 972 return ret; 973 } 974 EXPORT_SYMBOL_NS(amd_sof_acp_probe, "SND_SOC_SOF_AMD_COMMON"); 975 976 void amd_sof_acp_remove(struct snd_sof_dev *sdev) 977 { 978 struct acp_dev_data *adata = sdev->pdata->hw_pdata; 979 980 if (adata->sdw) 981 amd_sof_sdw_exit(sdev); 982 983 if (sdev->ipc_irq) 984 free_irq(sdev->ipc_irq, sdev); 985 986 if (adata->dmic_dev) 987 platform_device_unregister(adata->dmic_dev); 988 989 acp_reset(sdev); 990 } 991 EXPORT_SYMBOL_NS(amd_sof_acp_remove, "SND_SOC_SOF_AMD_COMMON"); 992 993 MODULE_LICENSE("Dual BSD/GPL"); 994 MODULE_DESCRIPTION("AMD ACP sof driver"); 995 MODULE_IMPORT_NS("SOUNDWIRE_AMD_INIT"); 996 MODULE_IMPORT_NS("SND_AMD_SOUNDWIRE_ACPI"); 997