1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2025 Inochi Amaoto <inochiama@gmail.com> 4 */ 5 6/ { 7 #address-cells = <2>; 8 #size-cells = <2>; 9 10 cpus { 11 #address-cells = <1>; 12 #size-cells = <0>; 13 timebase-frequency = <50000000>; 14 15 cpu0: cpu@0 { 16 compatible = "thead,c920", "riscv"; 17 reg = <0>; 18 i-cache-block-size = <64>; 19 i-cache-size = <65536>; 20 i-cache-sets = <512>; 21 d-cache-block-size = <64>; 22 d-cache-size = <65536>; 23 d-cache-sets = <512>; 24 device_type = "cpu"; 25 mmu-type = "riscv,sv48"; 26 next-level-cache = <&l2_cache0>; 27 riscv,isa = "rv64imafdcv"; 28 riscv,isa-base = "rv64i"; 29 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 30 "v", "sscofpmf", "sstc", 31 "svinval", "svnapot", "svpbmt", 32 "zawrs", "zba", "zbb", "zbc", 33 "zbs", "zca", "zcb", "zcd", 34 "zfa", "zfbfmin", "zfh", "zfhmin", 35 "zicbom", "zicbop", "zicboz", 36 "zicntr", "zicond","zicsr", "zifencei", 37 "zihintntl", "zihintpause", "zihpm", 38 "zvfbfmin", "zvfbfwma", "zvfh", 39 "zvfhmin"; 40 riscv,cbom-block-size = <64>; 41 riscv,cboz-block-size = <64>; 42 43 cpu0_intc: interrupt-controller { 44 compatible = "riscv,cpu-intc"; 45 interrupt-controller; 46 #interrupt-cells = <1>; 47 }; 48 }; 49 50 cpu1: cpu@1 { 51 compatible = "thead,c920", "riscv"; 52 reg = <1>; 53 i-cache-block-size = <64>; 54 i-cache-size = <65536>; 55 i-cache-sets = <512>; 56 d-cache-block-size = <64>; 57 d-cache-size = <65536>; 58 d-cache-sets = <512>; 59 device_type = "cpu"; 60 mmu-type = "riscv,sv48"; 61 next-level-cache = <&l2_cache0>; 62 riscv,isa = "rv64imafdcv"; 63 riscv,isa-base = "rv64i"; 64 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 65 "v", "sscofpmf", "sstc", 66 "svinval", "svnapot", "svpbmt", 67 "zawrs", "zba", "zbb", "zbc", 68 "zbs", "zca", "zcb", "zcd", 69 "zfa", "zfbfmin", "zfh", "zfhmin", 70 "zicbom", "zicbop", "zicboz", 71 "zicntr", "zicond","zicsr", "zifencei", 72 "zihintntl", "zihintpause", "zihpm", 73 "zvfbfmin", "zvfbfwma", "zvfh", 74 "zvfhmin"; 75 riscv,cbom-block-size = <64>; 76 riscv,cboz-block-size = <64>; 77 78 cpu1_intc: interrupt-controller { 79 compatible = "riscv,cpu-intc"; 80 interrupt-controller; 81 #interrupt-cells = <1>; 82 }; 83 }; 84 85 cpu2: cpu@2 { 86 compatible = "thead,c920", "riscv"; 87 reg = <2>; 88 i-cache-block-size = <64>; 89 i-cache-size = <65536>; 90 i-cache-sets = <512>; 91 d-cache-block-size = <64>; 92 d-cache-size = <65536>; 93 d-cache-sets = <512>; 94 device_type = "cpu"; 95 mmu-type = "riscv,sv48"; 96 next-level-cache = <&l2_cache0>; 97 riscv,isa = "rv64imafdcv"; 98 riscv,isa-base = "rv64i"; 99 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 100 "v", "sscofpmf", "sstc", 101 "svinval", "svnapot", "svpbmt", 102 "zawrs", "zba", "zbb", "zbc", 103 "zbs", "zca", "zcb", "zcd", 104 "zfa", "zfbfmin", "zfh", "zfhmin", 105 "zicbom", "zicbop", "zicboz", 106 "zicntr", "zicond","zicsr", "zifencei", 107 "zihintntl", "zihintpause", "zihpm", 108 "zvfbfmin", "zvfbfwma", "zvfh", 109 "zvfhmin"; 110 riscv,cbom-block-size = <64>; 111 riscv,cboz-block-size = <64>; 112 113 cpu2_intc: interrupt-controller { 114 compatible = "riscv,cpu-intc"; 115 interrupt-controller; 116 #interrupt-cells = <1>; 117 }; 118 }; 119 120 cpu3: cpu@3 { 121 compatible = "thead,c920", "riscv"; 122 reg = <3>; 123 i-cache-block-size = <64>; 124 i-cache-size = <65536>; 125 i-cache-sets = <512>; 126 d-cache-block-size = <64>; 127 d-cache-size = <65536>; 128 d-cache-sets = <512>; 129 device_type = "cpu"; 130 mmu-type = "riscv,sv48"; 131 next-level-cache = <&l2_cache0>; 132 riscv,isa = "rv64imafdcv"; 133 riscv,isa-base = "rv64i"; 134 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 135 "v", "sscofpmf", "sstc", 136 "svinval", "svnapot", "svpbmt", 137 "zawrs", "zba", "zbb", "zbc", 138 "zbs", "zca", "zcb", "zcd", 139 "zfa", "zfbfmin", "zfh", "zfhmin", 140 "zicbom", "zicbop", "zicboz", 141 "zicntr", "zicond","zicsr", "zifencei", 142 "zihintntl", "zihintpause", "zihpm", 143 "zvfbfmin", "zvfbfwma", "zvfh", 144 "zvfhmin"; 145 riscv,cbom-block-size = <64>; 146 riscv,cboz-block-size = <64>; 147 148 cpu3_intc: interrupt-controller { 149 compatible = "riscv,cpu-intc"; 150 interrupt-controller; 151 #interrupt-cells = <1>; 152 }; 153 }; 154 155 cpu4: cpu@4 { 156 compatible = "thead,c920", "riscv"; 157 reg = <4>; 158 i-cache-block-size = <64>; 159 i-cache-size = <65536>; 160 i-cache-sets = <512>; 161 d-cache-block-size = <64>; 162 d-cache-size = <65536>; 163 d-cache-sets = <512>; 164 device_type = "cpu"; 165 mmu-type = "riscv,sv48"; 166 next-level-cache = <&l2_cache1>; 167 riscv,isa = "rv64imafdcv"; 168 riscv,isa-base = "rv64i"; 169 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 170 "v", "sscofpmf", "sstc", 171 "svinval", "svnapot", "svpbmt", 172 "zawrs", "zba", "zbb", "zbc", 173 "zbs", "zca", "zcb", "zcd", 174 "zfa", "zfbfmin", "zfh", "zfhmin", 175 "zicbom", "zicbop", "zicboz", 176 "zicntr", "zicond","zicsr", "zifencei", 177 "zihintntl", "zihintpause", "zihpm", 178 "zvfbfmin", "zvfbfwma", "zvfh", 179 "zvfhmin"; 180 riscv,cbom-block-size = <64>; 181 riscv,cboz-block-size = <64>; 182 183 cpu4_intc: interrupt-controller { 184 compatible = "riscv,cpu-intc"; 185 interrupt-controller; 186 #interrupt-cells = <1>; 187 }; 188 }; 189 190 cpu5: cpu@5 { 191 compatible = "thead,c920", "riscv"; 192 reg = <5>; 193 i-cache-block-size = <64>; 194 i-cache-size = <65536>; 195 i-cache-sets = <512>; 196 d-cache-block-size = <64>; 197 d-cache-size = <65536>; 198 d-cache-sets = <512>; 199 device_type = "cpu"; 200 mmu-type = "riscv,sv48"; 201 next-level-cache = <&l2_cache1>; 202 riscv,isa = "rv64imafdcv"; 203 riscv,isa-base = "rv64i"; 204 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 205 "v", "sscofpmf", "sstc", 206 "svinval", "svnapot", "svpbmt", 207 "zawrs", "zba", "zbb", "zbc", 208 "zbs", "zca", "zcb", "zcd", 209 "zfa", "zfbfmin", "zfh", "zfhmin", 210 "zicbom", "zicbop", "zicboz", 211 "zicntr", "zicond","zicsr", "zifencei", 212 "zihintntl", "zihintpause", "zihpm", 213 "zvfbfmin", "zvfbfwma", "zvfh", 214 "zvfhmin"; 215 riscv,cbom-block-size = <64>; 216 riscv,cboz-block-size = <64>; 217 218 cpu5_intc: interrupt-controller { 219 compatible = "riscv,cpu-intc"; 220 interrupt-controller; 221 #interrupt-cells = <1>; 222 }; 223 }; 224 225 cpu6: cpu@6 { 226 compatible = "thead,c920", "riscv"; 227 reg = <6>; 228 i-cache-block-size = <64>; 229 i-cache-size = <65536>; 230 i-cache-sets = <512>; 231 d-cache-block-size = <64>; 232 d-cache-size = <65536>; 233 d-cache-sets = <512>; 234 device_type = "cpu"; 235 mmu-type = "riscv,sv48"; 236 next-level-cache = <&l2_cache1>; 237 riscv,isa = "rv64imafdcv"; 238 riscv,isa-base = "rv64i"; 239 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 240 "v", "sscofpmf", "sstc", 241 "svinval", "svnapot", "svpbmt", 242 "zawrs", "zba", "zbb", "zbc", 243 "zbs", "zca", "zcb", "zcd", 244 "zfa", "zfbfmin", "zfh", "zfhmin", 245 "zicbom", "zicbop", "zicboz", 246 "zicntr", "zicond","zicsr", "zifencei", 247 "zihintntl", "zihintpause", "zihpm", 248 "zvfbfmin", "zvfbfwma", "zvfh", 249 "zvfhmin"; 250 riscv,cbom-block-size = <64>; 251 riscv,cboz-block-size = <64>; 252 253 cpu6_intc: interrupt-controller { 254 compatible = "riscv,cpu-intc"; 255 interrupt-controller; 256 #interrupt-cells = <1>; 257 }; 258 }; 259 260 cpu7: cpu@7 { 261 compatible = "thead,c920", "riscv"; 262 reg = <7>; 263 i-cache-block-size = <64>; 264 i-cache-size = <65536>; 265 i-cache-sets = <512>; 266 d-cache-block-size = <64>; 267 d-cache-size = <65536>; 268 d-cache-sets = <512>; 269 device_type = "cpu"; 270 mmu-type = "riscv,sv48"; 271 next-level-cache = <&l2_cache1>; 272 riscv,isa = "rv64imafdcv"; 273 riscv,isa-base = "rv64i"; 274 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 275 "v", "sscofpmf", "sstc", 276 "svinval", "svnapot", "svpbmt", 277 "zawrs", "zba", "zbb", "zbc", 278 "zbs", "zca", "zcb", "zcd", 279 "zfa", "zfbfmin", "zfh", "zfhmin", 280 "zicbom", "zicbop", "zicboz", 281 "zicntr", "zicond","zicsr", "zifencei", 282 "zihintntl", "zihintpause", "zihpm", 283 "zvfbfmin", "zvfbfwma", "zvfh", 284 "zvfhmin"; 285 riscv,cbom-block-size = <64>; 286 riscv,cboz-block-size = <64>; 287 288 cpu7_intc: interrupt-controller { 289 compatible = "riscv,cpu-intc"; 290 interrupt-controller; 291 #interrupt-cells = <1>; 292 }; 293 }; 294 295 cpu8: cpu@8 { 296 compatible = "thead,c920", "riscv"; 297 reg = <8>; 298 i-cache-block-size = <64>; 299 i-cache-size = <65536>; 300 i-cache-sets = <512>; 301 d-cache-block-size = <64>; 302 d-cache-size = <65536>; 303 d-cache-sets = <512>; 304 device_type = "cpu"; 305 mmu-type = "riscv,sv48"; 306 next-level-cache = <&l2_cache2>; 307 riscv,isa = "rv64imafdcv"; 308 riscv,isa-base = "rv64i"; 309 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 310 "v", "sscofpmf", "sstc", 311 "svinval", "svnapot", "svpbmt", 312 "zawrs", "zba", "zbb", "zbc", 313 "zbs", "zca", "zcb", "zcd", 314 "zfa", "zfbfmin", "zfh", "zfhmin", 315 "zicbom", "zicbop", "zicboz", 316 "zicntr", "zicond","zicsr", "zifencei", 317 "zihintntl", "zihintpause", "zihpm", 318 "zvfbfmin", "zvfbfwma", "zvfh", 319 "zvfhmin"; 320 riscv,cbom-block-size = <64>; 321 riscv,cboz-block-size = <64>; 322 323 cpu8_intc: interrupt-controller { 324 compatible = "riscv,cpu-intc"; 325 interrupt-controller; 326 #interrupt-cells = <1>; 327 }; 328 }; 329 330 cpu9: cpu@9 { 331 compatible = "thead,c920", "riscv"; 332 reg = <9>; 333 i-cache-block-size = <64>; 334 i-cache-size = <65536>; 335 i-cache-sets = <512>; 336 d-cache-block-size = <64>; 337 d-cache-size = <65536>; 338 d-cache-sets = <512>; 339 device_type = "cpu"; 340 mmu-type = "riscv,sv48"; 341 next-level-cache = <&l2_cache2>; 342 riscv,isa = "rv64imafdcv"; 343 riscv,isa-base = "rv64i"; 344 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 345 "v", "sscofpmf", "sstc", 346 "svinval", "svnapot", "svpbmt", 347 "zawrs", "zba", "zbb", "zbc", 348 "zbs", "zca", "zcb", "zcd", 349 "zfa", "zfbfmin", "zfh", "zfhmin", 350 "zicbom", "zicbop", "zicboz", 351 "zicntr", "zicond","zicsr", "zifencei", 352 "zihintntl", "zihintpause", "zihpm", 353 "zvfbfmin", "zvfbfwma", "zvfh", 354 "zvfhmin"; 355 riscv,cbom-block-size = <64>; 356 riscv,cboz-block-size = <64>; 357 358 cpu9_intc: interrupt-controller { 359 compatible = "riscv,cpu-intc"; 360 interrupt-controller; 361 #interrupt-cells = <1>; 362 }; 363 }; 364 365 cpu10: cpu@10 { 366 compatible = "thead,c920", "riscv"; 367 reg = <10>; 368 i-cache-block-size = <64>; 369 i-cache-size = <65536>; 370 i-cache-sets = <512>; 371 d-cache-block-size = <64>; 372 d-cache-size = <65536>; 373 d-cache-sets = <512>; 374 device_type = "cpu"; 375 mmu-type = "riscv,sv48"; 376 next-level-cache = <&l2_cache2>; 377 riscv,isa = "rv64imafdcv"; 378 riscv,isa-base = "rv64i"; 379 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 380 "v", "sscofpmf", "sstc", 381 "svinval", "svnapot", "svpbmt", 382 "zawrs", "zba", "zbb", "zbc", 383 "zbs", "zca", "zcb", "zcd", 384 "zfa", "zfbfmin", "zfh", "zfhmin", 385 "zicbom", "zicbop", "zicboz", 386 "zicntr", "zicond","zicsr", "zifencei", 387 "zihintntl", "zihintpause", "zihpm", 388 "zvfbfmin", "zvfbfwma", "zvfh", 389 "zvfhmin"; 390 riscv,cbom-block-size = <64>; 391 riscv,cboz-block-size = <64>; 392 393 cpu10_intc: interrupt-controller { 394 compatible = "riscv,cpu-intc"; 395 interrupt-controller; 396 #interrupt-cells = <1>; 397 }; 398 }; 399 400 cpu11: cpu@11 { 401 compatible = "thead,c920", "riscv"; 402 reg = <11>; 403 i-cache-block-size = <64>; 404 i-cache-size = <65536>; 405 i-cache-sets = <512>; 406 d-cache-block-size = <64>; 407 d-cache-size = <65536>; 408 d-cache-sets = <512>; 409 device_type = "cpu"; 410 mmu-type = "riscv,sv48"; 411 next-level-cache = <&l2_cache2>; 412 riscv,isa = "rv64imafdcv"; 413 riscv,isa-base = "rv64i"; 414 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 415 "v", "sscofpmf", "sstc", 416 "svinval", "svnapot", "svpbmt", 417 "zawrs", "zba", "zbb", "zbc", 418 "zbs", "zca", "zcb", "zcd", 419 "zfa", "zfbfmin", "zfh", "zfhmin", 420 "zicbom", "zicbop", "zicboz", 421 "zicntr", "zicond","zicsr", "zifencei", 422 "zihintntl", "zihintpause", "zihpm", 423 "zvfbfmin", "zvfbfwma", "zvfh", 424 "zvfhmin"; 425 riscv,cbom-block-size = <64>; 426 riscv,cboz-block-size = <64>; 427 428 cpu11_intc: interrupt-controller { 429 compatible = "riscv,cpu-intc"; 430 interrupt-controller; 431 #interrupt-cells = <1>; 432 }; 433 }; 434 435 cpu12: cpu@12 { 436 compatible = "thead,c920", "riscv"; 437 reg = <12>; 438 i-cache-block-size = <64>; 439 i-cache-size = <65536>; 440 i-cache-sets = <512>; 441 d-cache-block-size = <64>; 442 d-cache-size = <65536>; 443 d-cache-sets = <512>; 444 device_type = "cpu"; 445 mmu-type = "riscv,sv48"; 446 next-level-cache = <&l2_cache3>; 447 riscv,isa = "rv64imafdcv"; 448 riscv,isa-base = "rv64i"; 449 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 450 "v", "sscofpmf", "sstc", 451 "svinval", "svnapot", "svpbmt", 452 "zawrs", "zba", "zbb", "zbc", 453 "zbs", "zca", "zcb", "zcd", 454 "zfa", "zfbfmin", "zfh", "zfhmin", 455 "zicbom", "zicbop", "zicboz", 456 "zicntr", "zicond","zicsr", "zifencei", 457 "zihintntl", "zihintpause", "zihpm", 458 "zvfbfmin", "zvfbfwma", "zvfh", 459 "zvfhmin"; 460 riscv,cbom-block-size = <64>; 461 riscv,cboz-block-size = <64>; 462 463 cpu12_intc: interrupt-controller { 464 compatible = "riscv,cpu-intc"; 465 interrupt-controller; 466 #interrupt-cells = <1>; 467 }; 468 }; 469 470 cpu13: cpu@13 { 471 compatible = "thead,c920", "riscv"; 472 reg = <13>; 473 i-cache-block-size = <64>; 474 i-cache-size = <65536>; 475 i-cache-sets = <512>; 476 d-cache-block-size = <64>; 477 d-cache-size = <65536>; 478 d-cache-sets = <512>; 479 device_type = "cpu"; 480 mmu-type = "riscv,sv48"; 481 next-level-cache = <&l2_cache3>; 482 riscv,isa = "rv64imafdcv"; 483 riscv,isa-base = "rv64i"; 484 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 485 "v", "sscofpmf", "sstc", 486 "svinval", "svnapot", "svpbmt", 487 "zawrs", "zba", "zbb", "zbc", 488 "zbs", "zca", "zcb", "zcd", 489 "zfa", "zfbfmin", "zfh", "zfhmin", 490 "zicbom", "zicbop", "zicboz", 491 "zicntr", "zicond","zicsr", "zifencei", 492 "zihintntl", "zihintpause", "zihpm", 493 "zvfbfmin", "zvfbfwma", "zvfh", 494 "zvfhmin"; 495 riscv,cbom-block-size = <64>; 496 riscv,cboz-block-size = <64>; 497 498 cpu13_intc: interrupt-controller { 499 compatible = "riscv,cpu-intc"; 500 interrupt-controller; 501 #interrupt-cells = <1>; 502 }; 503 }; 504 505 cpu14: cpu@14 { 506 compatible = "thead,c920", "riscv"; 507 reg = <14>; 508 i-cache-block-size = <64>; 509 i-cache-size = <65536>; 510 i-cache-sets = <512>; 511 d-cache-block-size = <64>; 512 d-cache-size = <65536>; 513 d-cache-sets = <512>; 514 device_type = "cpu"; 515 mmu-type = "riscv,sv48"; 516 next-level-cache = <&l2_cache3>; 517 riscv,isa = "rv64imafdcv"; 518 riscv,isa-base = "rv64i"; 519 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 520 "v", "sscofpmf", "sstc", 521 "svinval", "svnapot", "svpbmt", 522 "zawrs", "zba", "zbb", "zbc", 523 "zbs", "zca", "zcb", "zcd", 524 "zfa", "zfbfmin", "zfh", "zfhmin", 525 "zicbom", "zicbop", "zicboz", 526 "zicntr", "zicond","zicsr", "zifencei", 527 "zihintntl", "zihintpause", "zihpm", 528 "zvfbfmin", "zvfbfwma", "zvfh", 529 "zvfhmin"; 530 riscv,cbom-block-size = <64>; 531 riscv,cboz-block-size = <64>; 532 533 cpu14_intc: interrupt-controller { 534 compatible = "riscv,cpu-intc"; 535 interrupt-controller; 536 #interrupt-cells = <1>; 537 }; 538 }; 539 540 cpu15: cpu@15 { 541 compatible = "thead,c920", "riscv"; 542 reg = <15>; 543 i-cache-block-size = <64>; 544 i-cache-size = <65536>; 545 i-cache-sets = <512>; 546 d-cache-block-size = <64>; 547 d-cache-size = <65536>; 548 d-cache-sets = <512>; 549 device_type = "cpu"; 550 mmu-type = "riscv,sv48"; 551 next-level-cache = <&l2_cache3>; 552 riscv,isa = "rv64imafdcv"; 553 riscv,isa-base = "rv64i"; 554 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 555 "v", "sscofpmf", "sstc", 556 "svinval", "svnapot", "svpbmt", 557 "zawrs", "zba", "zbb", "zbc", 558 "zbs", "zca", "zcb", "zcd", 559 "zfa", "zfbfmin", "zfh", "zfhmin", 560 "zicbom", "zicbop", "zicboz", 561 "zicntr", "zicond","zicsr", "zifencei", 562 "zihintntl", "zihintpause", "zihpm", 563 "zvfbfmin", "zvfbfwma", "zvfh", 564 "zvfhmin"; 565 riscv,cbom-block-size = <64>; 566 riscv,cboz-block-size = <64>; 567 568 cpu15_intc: interrupt-controller { 569 compatible = "riscv,cpu-intc"; 570 interrupt-controller; 571 #interrupt-cells = <1>; 572 }; 573 }; 574 575 cpu16: cpu@16 { 576 compatible = "thead,c920", "riscv"; 577 reg = <16>; 578 i-cache-block-size = <64>; 579 i-cache-size = <65536>; 580 i-cache-sets = <512>; 581 d-cache-block-size = <64>; 582 d-cache-size = <65536>; 583 d-cache-sets = <512>; 584 device_type = "cpu"; 585 mmu-type = "riscv,sv48"; 586 next-level-cache = <&l2_cache4>; 587 riscv,isa = "rv64imafdcv"; 588 riscv,isa-base = "rv64i"; 589 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 590 "v", "sscofpmf", "sstc", 591 "svinval", "svnapot", "svpbmt", 592 "zawrs", "zba", "zbb", "zbc", 593 "zbs", "zca", "zcb", "zcd", 594 "zfa", "zfbfmin", "zfh", "zfhmin", 595 "zicbom", "zicbop", "zicboz", 596 "zicntr", "zicond","zicsr", "zifencei", 597 "zihintntl", "zihintpause", "zihpm", 598 "zvfbfmin", "zvfbfwma", "zvfh", 599 "zvfhmin"; 600 riscv,cbom-block-size = <64>; 601 riscv,cboz-block-size = <64>; 602 603 cpu16_intc: interrupt-controller { 604 compatible = "riscv,cpu-intc"; 605 interrupt-controller; 606 #interrupt-cells = <1>; 607 }; 608 }; 609 610 cpu17: cpu@17 { 611 compatible = "thead,c920", "riscv"; 612 reg = <17>; 613 i-cache-block-size = <64>; 614 i-cache-size = <65536>; 615 i-cache-sets = <512>; 616 d-cache-block-size = <64>; 617 d-cache-size = <65536>; 618 d-cache-sets = <512>; 619 device_type = "cpu"; 620 mmu-type = "riscv,sv48"; 621 next-level-cache = <&l2_cache4>; 622 riscv,isa = "rv64imafdcv"; 623 riscv,isa-base = "rv64i"; 624 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 625 "v", "sscofpmf", "sstc", 626 "svinval", "svnapot", "svpbmt", 627 "zawrs", "zba", "zbb", "zbc", 628 "zbs", "zca", "zcb", "zcd", 629 "zfa", "zfbfmin", "zfh", "zfhmin", 630 "zicbom", "zicbop", "zicboz", 631 "zicntr", "zicond","zicsr", "zifencei", 632 "zihintntl", "zihintpause", "zihpm", 633 "zvfbfmin", "zvfbfwma", "zvfh", 634 "zvfhmin"; 635 riscv,cbom-block-size = <64>; 636 riscv,cboz-block-size = <64>; 637 638 cpu17_intc: interrupt-controller { 639 compatible = "riscv,cpu-intc"; 640 interrupt-controller; 641 #interrupt-cells = <1>; 642 }; 643 }; 644 645 cpu18: cpu@18 { 646 compatible = "thead,c920", "riscv"; 647 reg = <18>; 648 i-cache-block-size = <64>; 649 i-cache-size = <65536>; 650 i-cache-sets = <512>; 651 d-cache-block-size = <64>; 652 d-cache-size = <65536>; 653 d-cache-sets = <512>; 654 device_type = "cpu"; 655 mmu-type = "riscv,sv48"; 656 next-level-cache = <&l2_cache4>; 657 riscv,isa = "rv64imafdcv"; 658 riscv,isa-base = "rv64i"; 659 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 660 "v", "sscofpmf", "sstc", 661 "svinval", "svnapot", "svpbmt", 662 "zawrs", "zba", "zbb", "zbc", 663 "zbs", "zca", "zcb", "zcd", 664 "zfa", "zfbfmin", "zfh", "zfhmin", 665 "zicbom", "zicbop", "zicboz", 666 "zicntr", "zicond","zicsr", "zifencei", 667 "zihintntl", "zihintpause", "zihpm", 668 "zvfbfmin", "zvfbfwma", "zvfh", 669 "zvfhmin"; 670 riscv,cbom-block-size = <64>; 671 riscv,cboz-block-size = <64>; 672 673 cpu18_intc: interrupt-controller { 674 compatible = "riscv,cpu-intc"; 675 interrupt-controller; 676 #interrupt-cells = <1>; 677 }; 678 }; 679 680 cpu19: cpu@19 { 681 compatible = "thead,c920", "riscv"; 682 reg = <19>; 683 i-cache-block-size = <64>; 684 i-cache-size = <65536>; 685 i-cache-sets = <512>; 686 d-cache-block-size = <64>; 687 d-cache-size = <65536>; 688 d-cache-sets = <512>; 689 device_type = "cpu"; 690 mmu-type = "riscv,sv48"; 691 next-level-cache = <&l2_cache4>; 692 riscv,isa = "rv64imafdcv"; 693 riscv,isa-base = "rv64i"; 694 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 695 "v", "sscofpmf", "sstc", 696 "svinval", "svnapot", "svpbmt", 697 "zawrs", "zba", "zbb", "zbc", 698 "zbs", "zca", "zcb", "zcd", 699 "zfa", "zfbfmin", "zfh", "zfhmin", 700 "zicbom", "zicbop", "zicboz", 701 "zicntr", "zicond","zicsr", "zifencei", 702 "zihintntl", "zihintpause", "zihpm", 703 "zvfbfmin", "zvfbfwma", "zvfh", 704 "zvfhmin"; 705 riscv,cbom-block-size = <64>; 706 riscv,cboz-block-size = <64>; 707 708 cpu19_intc: interrupt-controller { 709 compatible = "riscv,cpu-intc"; 710 interrupt-controller; 711 #interrupt-cells = <1>; 712 }; 713 }; 714 715 cpu20: cpu@20 { 716 compatible = "thead,c920", "riscv"; 717 reg = <20>; 718 i-cache-block-size = <64>; 719 i-cache-size = <65536>; 720 i-cache-sets = <512>; 721 d-cache-block-size = <64>; 722 d-cache-size = <65536>; 723 d-cache-sets = <512>; 724 device_type = "cpu"; 725 mmu-type = "riscv,sv48"; 726 next-level-cache = <&l2_cache5>; 727 riscv,isa = "rv64imafdcv"; 728 riscv,isa-base = "rv64i"; 729 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 730 "v", "sscofpmf", "sstc", 731 "svinval", "svnapot", "svpbmt", 732 "zawrs", "zba", "zbb", "zbc", 733 "zbs", "zca", "zcb", "zcd", 734 "zfa", "zfbfmin", "zfh", "zfhmin", 735 "zicbom", "zicbop", "zicboz", 736 "zicntr", "zicond","zicsr", "zifencei", 737 "zihintntl", "zihintpause", "zihpm", 738 "zvfbfmin", "zvfbfwma", "zvfh", 739 "zvfhmin"; 740 riscv,cbom-block-size = <64>; 741 riscv,cboz-block-size = <64>; 742 743 cpu20_intc: interrupt-controller { 744 compatible = "riscv,cpu-intc"; 745 interrupt-controller; 746 #interrupt-cells = <1>; 747 }; 748 }; 749 750 cpu21: cpu@21 { 751 compatible = "thead,c920", "riscv"; 752 reg = <21>; 753 i-cache-block-size = <64>; 754 i-cache-size = <65536>; 755 i-cache-sets = <512>; 756 d-cache-block-size = <64>; 757 d-cache-size = <65536>; 758 d-cache-sets = <512>; 759 device_type = "cpu"; 760 mmu-type = "riscv,sv48"; 761 next-level-cache = <&l2_cache5>; 762 riscv,isa = "rv64imafdcv"; 763 riscv,isa-base = "rv64i"; 764 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 765 "v", "sscofpmf", "sstc", 766 "svinval", "svnapot", "svpbmt", 767 "zawrs", "zba", "zbb", "zbc", 768 "zbs", "zca", "zcb", "zcd", 769 "zfa", "zfbfmin", "zfh", "zfhmin", 770 "zicbom", "zicbop", "zicboz", 771 "zicntr", "zicond","zicsr", "zifencei", 772 "zihintntl", "zihintpause", "zihpm", 773 "zvfbfmin", "zvfbfwma", "zvfh", 774 "zvfhmin"; 775 riscv,cbom-block-size = <64>; 776 riscv,cboz-block-size = <64>; 777 778 cpu21_intc: interrupt-controller { 779 compatible = "riscv,cpu-intc"; 780 interrupt-controller; 781 #interrupt-cells = <1>; 782 }; 783 }; 784 785 cpu22: cpu@22 { 786 compatible = "thead,c920", "riscv"; 787 reg = <22>; 788 i-cache-block-size = <64>; 789 i-cache-size = <65536>; 790 i-cache-sets = <512>; 791 d-cache-block-size = <64>; 792 d-cache-size = <65536>; 793 d-cache-sets = <512>; 794 device_type = "cpu"; 795 mmu-type = "riscv,sv48"; 796 next-level-cache = <&l2_cache5>; 797 riscv,isa = "rv64imafdcv"; 798 riscv,isa-base = "rv64i"; 799 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 800 "v", "sscofpmf", "sstc", 801 "svinval", "svnapot", "svpbmt", 802 "zawrs", "zba", "zbb", "zbc", 803 "zbs", "zca", "zcb", "zcd", 804 "zfa", "zfbfmin", "zfh", "zfhmin", 805 "zicbom", "zicbop", "zicboz", 806 "zicntr", "zicond","zicsr", "zifencei", 807 "zihintntl", "zihintpause", "zihpm", 808 "zvfbfmin", "zvfbfwma", "zvfh", 809 "zvfhmin"; 810 riscv,cbom-block-size = <64>; 811 riscv,cboz-block-size = <64>; 812 813 cpu22_intc: interrupt-controller { 814 compatible = "riscv,cpu-intc"; 815 interrupt-controller; 816 #interrupt-cells = <1>; 817 }; 818 }; 819 820 cpu23: cpu@23 { 821 compatible = "thead,c920", "riscv"; 822 reg = <23>; 823 i-cache-block-size = <64>; 824 i-cache-size = <65536>; 825 i-cache-sets = <512>; 826 d-cache-block-size = <64>; 827 d-cache-size = <65536>; 828 d-cache-sets = <512>; 829 device_type = "cpu"; 830 mmu-type = "riscv,sv48"; 831 next-level-cache = <&l2_cache5>; 832 riscv,isa = "rv64imafdcv"; 833 riscv,isa-base = "rv64i"; 834 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 835 "v", "sscofpmf", "sstc", 836 "svinval", "svnapot", "svpbmt", 837 "zawrs", "zba", "zbb", "zbc", 838 "zbs", "zca", "zcb", "zcd", 839 "zfa", "zfbfmin", "zfh", "zfhmin", 840 "zicbom", "zicbop", "zicboz", 841 "zicntr", "zicond","zicsr", "zifencei", 842 "zihintntl", "zihintpause", "zihpm", 843 "zvfbfmin", "zvfbfwma", "zvfh", 844 "zvfhmin"; 845 riscv,cbom-block-size = <64>; 846 riscv,cboz-block-size = <64>; 847 848 cpu23_intc: interrupt-controller { 849 compatible = "riscv,cpu-intc"; 850 interrupt-controller; 851 #interrupt-cells = <1>; 852 }; 853 }; 854 855 cpu24: cpu@24 { 856 compatible = "thead,c920", "riscv"; 857 reg = <24>; 858 i-cache-block-size = <64>; 859 i-cache-size = <65536>; 860 i-cache-sets = <512>; 861 d-cache-block-size = <64>; 862 d-cache-size = <65536>; 863 d-cache-sets = <512>; 864 device_type = "cpu"; 865 mmu-type = "riscv,sv48"; 866 next-level-cache = <&l2_cache6>; 867 riscv,isa = "rv64imafdcv"; 868 riscv,isa-base = "rv64i"; 869 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 870 "v", "sscofpmf", "sstc", 871 "svinval", "svnapot", "svpbmt", 872 "zawrs", "zba", "zbb", "zbc", 873 "zbs", "zca", "zcb", "zcd", 874 "zfa", "zfbfmin", "zfh", "zfhmin", 875 "zicbom", "zicbop", "zicboz", 876 "zicntr", "zicond","zicsr", "zifencei", 877 "zihintntl", "zihintpause", "zihpm", 878 "zvfbfmin", "zvfbfwma", "zvfh", 879 "zvfhmin"; 880 riscv,cbom-block-size = <64>; 881 riscv,cboz-block-size = <64>; 882 883 cpu24_intc: interrupt-controller { 884 compatible = "riscv,cpu-intc"; 885 interrupt-controller; 886 #interrupt-cells = <1>; 887 }; 888 }; 889 890 cpu25: cpu@25 { 891 compatible = "thead,c920", "riscv"; 892 reg = <25>; 893 i-cache-block-size = <64>; 894 i-cache-size = <65536>; 895 i-cache-sets = <512>; 896 d-cache-block-size = <64>; 897 d-cache-size = <65536>; 898 d-cache-sets = <512>; 899 device_type = "cpu"; 900 mmu-type = "riscv,sv48"; 901 next-level-cache = <&l2_cache6>; 902 riscv,isa = "rv64imafdcv"; 903 riscv,isa-base = "rv64i"; 904 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 905 "v", "sscofpmf", "sstc", 906 "svinval", "svnapot", "svpbmt", 907 "zawrs", "zba", "zbb", "zbc", 908 "zbs", "zca", "zcb", "zcd", 909 "zfa", "zfbfmin", "zfh", "zfhmin", 910 "zicbom", "zicbop", "zicboz", 911 "zicntr", "zicond","zicsr", "zifencei", 912 "zihintntl", "zihintpause", "zihpm", 913 "zvfbfmin", "zvfbfwma", "zvfh", 914 "zvfhmin"; 915 riscv,cbom-block-size = <64>; 916 riscv,cboz-block-size = <64>; 917 918 cpu25_intc: interrupt-controller { 919 compatible = "riscv,cpu-intc"; 920 interrupt-controller; 921 #interrupt-cells = <1>; 922 }; 923 }; 924 925 cpu26: cpu@26 { 926 compatible = "thead,c920", "riscv"; 927 reg = <26>; 928 i-cache-block-size = <64>; 929 i-cache-size = <65536>; 930 i-cache-sets = <512>; 931 d-cache-block-size = <64>; 932 d-cache-size = <65536>; 933 d-cache-sets = <512>; 934 device_type = "cpu"; 935 mmu-type = "riscv,sv48"; 936 next-level-cache = <&l2_cache6>; 937 riscv,isa = "rv64imafdcv"; 938 riscv,isa-base = "rv64i"; 939 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 940 "v", "sscofpmf", "sstc", 941 "svinval", "svnapot", "svpbmt", 942 "zawrs", "zba", "zbb", "zbc", 943 "zbs", "zca", "zcb", "zcd", 944 "zfa", "zfbfmin", "zfh", "zfhmin", 945 "zicbom", "zicbop", "zicboz", 946 "zicntr", "zicond","zicsr", "zifencei", 947 "zihintntl", "zihintpause", "zihpm", 948 "zvfbfmin", "zvfbfwma", "zvfh", 949 "zvfhmin"; 950 riscv,cbom-block-size = <64>; 951 riscv,cboz-block-size = <64>; 952 953 cpu26_intc: interrupt-controller { 954 compatible = "riscv,cpu-intc"; 955 interrupt-controller; 956 #interrupt-cells = <1>; 957 }; 958 }; 959 960 cpu27: cpu@27 { 961 compatible = "thead,c920", "riscv"; 962 reg = <27>; 963 i-cache-block-size = <64>; 964 i-cache-size = <65536>; 965 i-cache-sets = <512>; 966 d-cache-block-size = <64>; 967 d-cache-size = <65536>; 968 d-cache-sets = <512>; 969 device_type = "cpu"; 970 mmu-type = "riscv,sv48"; 971 next-level-cache = <&l2_cache6>; 972 riscv,isa = "rv64imafdcv"; 973 riscv,isa-base = "rv64i"; 974 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 975 "v", "sscofpmf", "sstc", 976 "svinval", "svnapot", "svpbmt", 977 "zawrs", "zba", "zbb", "zbc", 978 "zbs", "zca", "zcb", "zcd", 979 "zfa", "zfbfmin", "zfh", "zfhmin", 980 "zicbom", "zicbop", "zicboz", 981 "zicntr", "zicond","zicsr", "zifencei", 982 "zihintntl", "zihintpause", "zihpm", 983 "zvfbfmin", "zvfbfwma", "zvfh", 984 "zvfhmin"; 985 riscv,cbom-block-size = <64>; 986 riscv,cboz-block-size = <64>; 987 988 cpu27_intc: interrupt-controller { 989 compatible = "riscv,cpu-intc"; 990 interrupt-controller; 991 #interrupt-cells = <1>; 992 }; 993 }; 994 995 cpu28: cpu@28 { 996 compatible = "thead,c920", "riscv"; 997 reg = <28>; 998 i-cache-block-size = <64>; 999 i-cache-size = <65536>; 1000 i-cache-sets = <512>; 1001 d-cache-block-size = <64>; 1002 d-cache-size = <65536>; 1003 d-cache-sets = <512>; 1004 device_type = "cpu"; 1005 mmu-type = "riscv,sv48"; 1006 next-level-cache = <&l2_cache7>; 1007 riscv,isa = "rv64imafdcv"; 1008 riscv,isa-base = "rv64i"; 1009 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1010 "v", "sscofpmf", "sstc", 1011 "svinval", "svnapot", "svpbmt", 1012 "zawrs", "zba", "zbb", "zbc", 1013 "zbs", "zca", "zcb", "zcd", 1014 "zfa", "zfbfmin", "zfh", "zfhmin", 1015 "zicbom", "zicbop", "zicboz", 1016 "zicntr", "zicond","zicsr", "zifencei", 1017 "zihintntl", "zihintpause", "zihpm", 1018 "zvfbfmin", "zvfbfwma", "zvfh", 1019 "zvfhmin"; 1020 riscv,cbom-block-size = <64>; 1021 riscv,cboz-block-size = <64>; 1022 1023 cpu28_intc: interrupt-controller { 1024 compatible = "riscv,cpu-intc"; 1025 interrupt-controller; 1026 #interrupt-cells = <1>; 1027 }; 1028 }; 1029 1030 cpu29: cpu@29 { 1031 compatible = "thead,c920", "riscv"; 1032 reg = <29>; 1033 i-cache-block-size = <64>; 1034 i-cache-size = <65536>; 1035 i-cache-sets = <512>; 1036 d-cache-block-size = <64>; 1037 d-cache-size = <65536>; 1038 d-cache-sets = <512>; 1039 device_type = "cpu"; 1040 mmu-type = "riscv,sv48"; 1041 next-level-cache = <&l2_cache7>; 1042 riscv,isa = "rv64imafdcv"; 1043 riscv,isa-base = "rv64i"; 1044 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1045 "v", "sscofpmf", "sstc", 1046 "svinval", "svnapot", "svpbmt", 1047 "zawrs", "zba", "zbb", "zbc", 1048 "zbs", "zca", "zcb", "zcd", 1049 "zfa", "zfbfmin", "zfh", "zfhmin", 1050 "zicbom", "zicbop", "zicboz", 1051 "zicntr", "zicond","zicsr", "zifencei", 1052 "zihintntl", "zihintpause", "zihpm", 1053 "zvfbfmin", "zvfbfwma", "zvfh", 1054 "zvfhmin"; 1055 riscv,cbom-block-size = <64>; 1056 riscv,cboz-block-size = <64>; 1057 1058 cpu29_intc: interrupt-controller { 1059 compatible = "riscv,cpu-intc"; 1060 interrupt-controller; 1061 #interrupt-cells = <1>; 1062 }; 1063 }; 1064 1065 cpu30: cpu@30 { 1066 compatible = "thead,c920", "riscv"; 1067 reg = <30>; 1068 i-cache-block-size = <64>; 1069 i-cache-size = <65536>; 1070 i-cache-sets = <512>; 1071 d-cache-block-size = <64>; 1072 d-cache-size = <65536>; 1073 d-cache-sets = <512>; 1074 device_type = "cpu"; 1075 mmu-type = "riscv,sv48"; 1076 next-level-cache = <&l2_cache7>; 1077 riscv,isa = "rv64imafdcv"; 1078 riscv,isa-base = "rv64i"; 1079 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1080 "v", "sscofpmf", "sstc", 1081 "svinval", "svnapot", "svpbmt", 1082 "zawrs", "zba", "zbb", "zbc", 1083 "zbs", "zca", "zcb", "zcd", 1084 "zfa", "zfbfmin", "zfh", "zfhmin", 1085 "zicbom", "zicbop", "zicboz", 1086 "zicntr", "zicond","zicsr", "zifencei", 1087 "zihintntl", "zihintpause", "zihpm", 1088 "zvfbfmin", "zvfbfwma", "zvfh", 1089 "zvfhmin"; 1090 riscv,cbom-block-size = <64>; 1091 riscv,cboz-block-size = <64>; 1092 1093 cpu30_intc: interrupt-controller { 1094 compatible = "riscv,cpu-intc"; 1095 interrupt-controller; 1096 #interrupt-cells = <1>; 1097 }; 1098 }; 1099 1100 cpu31: cpu@31 { 1101 compatible = "thead,c920", "riscv"; 1102 reg = <31>; 1103 i-cache-block-size = <64>; 1104 i-cache-size = <65536>; 1105 i-cache-sets = <512>; 1106 d-cache-block-size = <64>; 1107 d-cache-size = <65536>; 1108 d-cache-sets = <512>; 1109 device_type = "cpu"; 1110 mmu-type = "riscv,sv48"; 1111 next-level-cache = <&l2_cache7>; 1112 riscv,isa = "rv64imafdcv"; 1113 riscv,isa-base = "rv64i"; 1114 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1115 "v", "sscofpmf", "sstc", 1116 "svinval", "svnapot", "svpbmt", 1117 "zawrs", "zba", "zbb", "zbc", 1118 "zbs", "zca", "zcb", "zcd", 1119 "zfa", "zfbfmin", "zfh", "zfhmin", 1120 "zicbom", "zicbop", "zicboz", 1121 "zicntr", "zicond","zicsr", "zifencei", 1122 "zihintntl", "zihintpause", "zihpm", 1123 "zvfbfmin", "zvfbfwma", "zvfh", 1124 "zvfhmin"; 1125 riscv,cbom-block-size = <64>; 1126 riscv,cboz-block-size = <64>; 1127 1128 cpu31_intc: interrupt-controller { 1129 compatible = "riscv,cpu-intc"; 1130 interrupt-controller; 1131 #interrupt-cells = <1>; 1132 }; 1133 }; 1134 1135 cpu32: cpu@32 { 1136 compatible = "thead,c920", "riscv"; 1137 reg = <32>; 1138 i-cache-block-size = <64>; 1139 i-cache-size = <65536>; 1140 i-cache-sets = <512>; 1141 d-cache-block-size = <64>; 1142 d-cache-size = <65536>; 1143 d-cache-sets = <512>; 1144 device_type = "cpu"; 1145 mmu-type = "riscv,sv48"; 1146 next-level-cache = <&l2_cache8>; 1147 riscv,isa = "rv64imafdcv"; 1148 riscv,isa-base = "rv64i"; 1149 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1150 "v", "sscofpmf", "sstc", 1151 "svinval", "svnapot", "svpbmt", 1152 "zawrs", "zba", "zbb", "zbc", 1153 "zbs", "zca", "zcb", "zcd", 1154 "zfa", "zfbfmin", "zfh", "zfhmin", 1155 "zicbom", "zicbop", "zicboz", 1156 "zicntr", "zicond","zicsr", "zifencei", 1157 "zihintntl", "zihintpause", "zihpm", 1158 "zvfbfmin", "zvfbfwma", "zvfh", 1159 "zvfhmin"; 1160 riscv,cbom-block-size = <64>; 1161 riscv,cboz-block-size = <64>; 1162 1163 cpu32_intc: interrupt-controller { 1164 compatible = "riscv,cpu-intc"; 1165 interrupt-controller; 1166 #interrupt-cells = <1>; 1167 }; 1168 }; 1169 1170 cpu33: cpu@33 { 1171 compatible = "thead,c920", "riscv"; 1172 reg = <33>; 1173 i-cache-block-size = <64>; 1174 i-cache-size = <65536>; 1175 i-cache-sets = <512>; 1176 d-cache-block-size = <64>; 1177 d-cache-size = <65536>; 1178 d-cache-sets = <512>; 1179 device_type = "cpu"; 1180 mmu-type = "riscv,sv48"; 1181 next-level-cache = <&l2_cache8>; 1182 riscv,isa = "rv64imafdcv"; 1183 riscv,isa-base = "rv64i"; 1184 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1185 "v", "sscofpmf", "sstc", 1186 "svinval", "svnapot", "svpbmt", 1187 "zawrs", "zba", "zbb", "zbc", 1188 "zbs", "zca", "zcb", "zcd", 1189 "zfa", "zfbfmin", "zfh", "zfhmin", 1190 "zicbom", "zicbop", "zicboz", 1191 "zicntr", "zicond","zicsr", "zifencei", 1192 "zihintntl", "zihintpause", "zihpm", 1193 "zvfbfmin", "zvfbfwma", "zvfh", 1194 "zvfhmin"; 1195 riscv,cbom-block-size = <64>; 1196 riscv,cboz-block-size = <64>; 1197 1198 cpu33_intc: interrupt-controller { 1199 compatible = "riscv,cpu-intc"; 1200 interrupt-controller; 1201 #interrupt-cells = <1>; 1202 }; 1203 }; 1204 1205 cpu34: cpu@34 { 1206 compatible = "thead,c920", "riscv"; 1207 reg = <34>; 1208 i-cache-block-size = <64>; 1209 i-cache-size = <65536>; 1210 i-cache-sets = <512>; 1211 d-cache-block-size = <64>; 1212 d-cache-size = <65536>; 1213 d-cache-sets = <512>; 1214 device_type = "cpu"; 1215 mmu-type = "riscv,sv48"; 1216 next-level-cache = <&l2_cache8>; 1217 riscv,isa = "rv64imafdcv"; 1218 riscv,isa-base = "rv64i"; 1219 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1220 "v", "sscofpmf", "sstc", 1221 "svinval", "svnapot", "svpbmt", 1222 "zawrs", "zba", "zbb", "zbc", 1223 "zbs", "zca", "zcb", "zcd", 1224 "zfa", "zfbfmin", "zfh", "zfhmin", 1225 "zicbom", "zicbop", "zicboz", 1226 "zicntr", "zicond","zicsr", "zifencei", 1227 "zihintntl", "zihintpause", "zihpm", 1228 "zvfbfmin", "zvfbfwma", "zvfh", 1229 "zvfhmin"; 1230 riscv,cbom-block-size = <64>; 1231 riscv,cboz-block-size = <64>; 1232 1233 cpu34_intc: interrupt-controller { 1234 compatible = "riscv,cpu-intc"; 1235 interrupt-controller; 1236 #interrupt-cells = <1>; 1237 }; 1238 }; 1239 1240 cpu35: cpu@35 { 1241 compatible = "thead,c920", "riscv"; 1242 reg = <35>; 1243 i-cache-block-size = <64>; 1244 i-cache-size = <65536>; 1245 i-cache-sets = <512>; 1246 d-cache-block-size = <64>; 1247 d-cache-size = <65536>; 1248 d-cache-sets = <512>; 1249 device_type = "cpu"; 1250 mmu-type = "riscv,sv48"; 1251 next-level-cache = <&l2_cache8>; 1252 riscv,isa = "rv64imafdcv"; 1253 riscv,isa-base = "rv64i"; 1254 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1255 "v", "sscofpmf", "sstc", 1256 "svinval", "svnapot", "svpbmt", 1257 "zawrs", "zba", "zbb", "zbc", 1258 "zbs", "zca", "zcb", "zcd", 1259 "zfa", "zfbfmin", "zfh", "zfhmin", 1260 "zicbom", "zicbop", "zicboz", 1261 "zicntr", "zicond","zicsr", "zifencei", 1262 "zihintntl", "zihintpause", "zihpm", 1263 "zvfbfmin", "zvfbfwma", "zvfh", 1264 "zvfhmin"; 1265 riscv,cbom-block-size = <64>; 1266 riscv,cboz-block-size = <64>; 1267 1268 cpu35_intc: interrupt-controller { 1269 compatible = "riscv,cpu-intc"; 1270 interrupt-controller; 1271 #interrupt-cells = <1>; 1272 }; 1273 }; 1274 1275 cpu36: cpu@36 { 1276 compatible = "thead,c920", "riscv"; 1277 reg = <36>; 1278 i-cache-block-size = <64>; 1279 i-cache-size = <65536>; 1280 i-cache-sets = <512>; 1281 d-cache-block-size = <64>; 1282 d-cache-size = <65536>; 1283 d-cache-sets = <512>; 1284 device_type = "cpu"; 1285 mmu-type = "riscv,sv48"; 1286 next-level-cache = <&l2_cache9>; 1287 riscv,isa = "rv64imafdcv"; 1288 riscv,isa-base = "rv64i"; 1289 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1290 "v", "sscofpmf", "sstc", 1291 "svinval", "svnapot", "svpbmt", 1292 "zawrs", "zba", "zbb", "zbc", 1293 "zbs", "zca", "zcb", "zcd", 1294 "zfa", "zfbfmin", "zfh", "zfhmin", 1295 "zicbom", "zicbop", "zicboz", 1296 "zicntr", "zicond","zicsr", "zifencei", 1297 "zihintntl", "zihintpause", "zihpm", 1298 "zvfbfmin", "zvfbfwma", "zvfh", 1299 "zvfhmin"; 1300 riscv,cbom-block-size = <64>; 1301 riscv,cboz-block-size = <64>; 1302 1303 cpu36_intc: interrupt-controller { 1304 compatible = "riscv,cpu-intc"; 1305 interrupt-controller; 1306 #interrupt-cells = <1>; 1307 }; 1308 }; 1309 1310 cpu37: cpu@37 { 1311 compatible = "thead,c920", "riscv"; 1312 reg = <37>; 1313 i-cache-block-size = <64>; 1314 i-cache-size = <65536>; 1315 i-cache-sets = <512>; 1316 d-cache-block-size = <64>; 1317 d-cache-size = <65536>; 1318 d-cache-sets = <512>; 1319 device_type = "cpu"; 1320 mmu-type = "riscv,sv48"; 1321 next-level-cache = <&l2_cache9>; 1322 riscv,isa = "rv64imafdcv"; 1323 riscv,isa-base = "rv64i"; 1324 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1325 "v", "sscofpmf", "sstc", 1326 "svinval", "svnapot", "svpbmt", 1327 "zawrs", "zba", "zbb", "zbc", 1328 "zbs", "zca", "zcb", "zcd", 1329 "zfa", "zfbfmin", "zfh", "zfhmin", 1330 "zicbom", "zicbop", "zicboz", 1331 "zicntr", "zicond","zicsr", "zifencei", 1332 "zihintntl", "zihintpause", "zihpm", 1333 "zvfbfmin", "zvfbfwma", "zvfh", 1334 "zvfhmin"; 1335 riscv,cbom-block-size = <64>; 1336 riscv,cboz-block-size = <64>; 1337 1338 cpu37_intc: interrupt-controller { 1339 compatible = "riscv,cpu-intc"; 1340 interrupt-controller; 1341 #interrupt-cells = <1>; 1342 }; 1343 }; 1344 1345 cpu38: cpu@38 { 1346 compatible = "thead,c920", "riscv"; 1347 reg = <38>; 1348 i-cache-block-size = <64>; 1349 i-cache-size = <65536>; 1350 i-cache-sets = <512>; 1351 d-cache-block-size = <64>; 1352 d-cache-size = <65536>; 1353 d-cache-sets = <512>; 1354 device_type = "cpu"; 1355 mmu-type = "riscv,sv48"; 1356 next-level-cache = <&l2_cache9>; 1357 riscv,isa = "rv64imafdcv"; 1358 riscv,isa-base = "rv64i"; 1359 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1360 "v", "sscofpmf", "sstc", 1361 "svinval", "svnapot", "svpbmt", 1362 "zawrs", "zba", "zbb", "zbc", 1363 "zbs", "zca", "zcb", "zcd", 1364 "zfa", "zfbfmin", "zfh", "zfhmin", 1365 "zicbom", "zicbop", "zicboz", 1366 "zicntr", "zicond","zicsr", "zifencei", 1367 "zihintntl", "zihintpause", "zihpm", 1368 "zvfbfmin", "zvfbfwma", "zvfh", 1369 "zvfhmin"; 1370 riscv,cbom-block-size = <64>; 1371 riscv,cboz-block-size = <64>; 1372 1373 cpu38_intc: interrupt-controller { 1374 compatible = "riscv,cpu-intc"; 1375 interrupt-controller; 1376 #interrupt-cells = <1>; 1377 }; 1378 }; 1379 1380 cpu39: cpu@39 { 1381 compatible = "thead,c920", "riscv"; 1382 reg = <39>; 1383 i-cache-block-size = <64>; 1384 i-cache-size = <65536>; 1385 i-cache-sets = <512>; 1386 d-cache-block-size = <64>; 1387 d-cache-size = <65536>; 1388 d-cache-sets = <512>; 1389 device_type = "cpu"; 1390 mmu-type = "riscv,sv48"; 1391 next-level-cache = <&l2_cache9>; 1392 riscv,isa = "rv64imafdcv"; 1393 riscv,isa-base = "rv64i"; 1394 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1395 "v", "sscofpmf", "sstc", 1396 "svinval", "svnapot", "svpbmt", 1397 "zawrs", "zba", "zbb", "zbc", 1398 "zbs", "zca", "zcb", "zcd", 1399 "zfa", "zfbfmin", "zfh", "zfhmin", 1400 "zicbom", "zicbop", "zicboz", 1401 "zicntr", "zicond","zicsr", "zifencei", 1402 "zihintntl", "zihintpause", "zihpm", 1403 "zvfbfmin", "zvfbfwma", "zvfh", 1404 "zvfhmin"; 1405 riscv,cbom-block-size = <64>; 1406 riscv,cboz-block-size = <64>; 1407 1408 cpu39_intc: interrupt-controller { 1409 compatible = "riscv,cpu-intc"; 1410 interrupt-controller; 1411 #interrupt-cells = <1>; 1412 }; 1413 }; 1414 1415 cpu40: cpu@40 { 1416 compatible = "thead,c920", "riscv"; 1417 reg = <40>; 1418 i-cache-block-size = <64>; 1419 i-cache-size = <65536>; 1420 i-cache-sets = <512>; 1421 d-cache-block-size = <64>; 1422 d-cache-size = <65536>; 1423 d-cache-sets = <512>; 1424 device_type = "cpu"; 1425 mmu-type = "riscv,sv48"; 1426 next-level-cache = <&l2_cache10>; 1427 riscv,isa = "rv64imafdcv"; 1428 riscv,isa-base = "rv64i"; 1429 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1430 "v", "sscofpmf", "sstc", 1431 "svinval", "svnapot", "svpbmt", 1432 "zawrs", "zba", "zbb", "zbc", 1433 "zbs", "zca", "zcb", "zcd", 1434 "zfa", "zfbfmin", "zfh", "zfhmin", 1435 "zicbom", "zicbop", "zicboz", 1436 "zicntr", "zicond","zicsr", "zifencei", 1437 "zihintntl", "zihintpause", "zihpm", 1438 "zvfbfmin", "zvfbfwma", "zvfh", 1439 "zvfhmin"; 1440 riscv,cbom-block-size = <64>; 1441 riscv,cboz-block-size = <64>; 1442 1443 cpu40_intc: interrupt-controller { 1444 compatible = "riscv,cpu-intc"; 1445 interrupt-controller; 1446 #interrupt-cells = <1>; 1447 }; 1448 }; 1449 1450 cpu41: cpu@41 { 1451 compatible = "thead,c920", "riscv"; 1452 reg = <41>; 1453 i-cache-block-size = <64>; 1454 i-cache-size = <65536>; 1455 i-cache-sets = <512>; 1456 d-cache-block-size = <64>; 1457 d-cache-size = <65536>; 1458 d-cache-sets = <512>; 1459 device_type = "cpu"; 1460 mmu-type = "riscv,sv48"; 1461 next-level-cache = <&l2_cache10>; 1462 riscv,isa = "rv64imafdcv"; 1463 riscv,isa-base = "rv64i"; 1464 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1465 "v", "sscofpmf", "sstc", 1466 "svinval", "svnapot", "svpbmt", 1467 "zawrs", "zba", "zbb", "zbc", 1468 "zbs", "zca", "zcb", "zcd", 1469 "zfa", "zfbfmin", "zfh", "zfhmin", 1470 "zicbom", "zicbop", "zicboz", 1471 "zicntr", "zicond","zicsr", "zifencei", 1472 "zihintntl", "zihintpause", "zihpm", 1473 "zvfbfmin", "zvfbfwma", "zvfh", 1474 "zvfhmin"; 1475 riscv,cbom-block-size = <64>; 1476 riscv,cboz-block-size = <64>; 1477 1478 cpu41_intc: interrupt-controller { 1479 compatible = "riscv,cpu-intc"; 1480 interrupt-controller; 1481 #interrupt-cells = <1>; 1482 }; 1483 }; 1484 1485 cpu42: cpu@42 { 1486 compatible = "thead,c920", "riscv"; 1487 reg = <42>; 1488 i-cache-block-size = <64>; 1489 i-cache-size = <65536>; 1490 i-cache-sets = <512>; 1491 d-cache-block-size = <64>; 1492 d-cache-size = <65536>; 1493 d-cache-sets = <512>; 1494 device_type = "cpu"; 1495 mmu-type = "riscv,sv48"; 1496 next-level-cache = <&l2_cache10>; 1497 riscv,isa = "rv64imafdcv"; 1498 riscv,isa-base = "rv64i"; 1499 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1500 "v", "sscofpmf", "sstc", 1501 "svinval", "svnapot", "svpbmt", 1502 "zawrs", "zba", "zbb", "zbc", 1503 "zbs", "zca", "zcb", "zcd", 1504 "zfa", "zfbfmin", "zfh", "zfhmin", 1505 "zicbom", "zicbop", "zicboz", 1506 "zicntr", "zicond","zicsr", "zifencei", 1507 "zihintntl", "zihintpause", "zihpm", 1508 "zvfbfmin", "zvfbfwma", "zvfh", 1509 "zvfhmin"; 1510 riscv,cbom-block-size = <64>; 1511 riscv,cboz-block-size = <64>; 1512 1513 cpu42_intc: interrupt-controller { 1514 compatible = "riscv,cpu-intc"; 1515 interrupt-controller; 1516 #interrupt-cells = <1>; 1517 }; 1518 }; 1519 1520 cpu43: cpu@43 { 1521 compatible = "thead,c920", "riscv"; 1522 reg = <43>; 1523 i-cache-block-size = <64>; 1524 i-cache-size = <65536>; 1525 i-cache-sets = <512>; 1526 d-cache-block-size = <64>; 1527 d-cache-size = <65536>; 1528 d-cache-sets = <512>; 1529 device_type = "cpu"; 1530 mmu-type = "riscv,sv48"; 1531 next-level-cache = <&l2_cache10>; 1532 riscv,isa = "rv64imafdcv"; 1533 riscv,isa-base = "rv64i"; 1534 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1535 "v", "sscofpmf", "sstc", 1536 "svinval", "svnapot", "svpbmt", 1537 "zawrs", "zba", "zbb", "zbc", 1538 "zbs", "zca", "zcb", "zcd", 1539 "zfa", "zfbfmin", "zfh", "zfhmin", 1540 "zicbom", "zicbop", "zicboz", 1541 "zicntr", "zicond","zicsr", "zifencei", 1542 "zihintntl", "zihintpause", "zihpm", 1543 "zvfbfmin", "zvfbfwma", "zvfh", 1544 "zvfhmin"; 1545 riscv,cbom-block-size = <64>; 1546 riscv,cboz-block-size = <64>; 1547 1548 cpu43_intc: interrupt-controller { 1549 compatible = "riscv,cpu-intc"; 1550 interrupt-controller; 1551 #interrupt-cells = <1>; 1552 }; 1553 }; 1554 1555 cpu44: cpu@44 { 1556 compatible = "thead,c920", "riscv"; 1557 reg = <44>; 1558 i-cache-block-size = <64>; 1559 i-cache-size = <65536>; 1560 i-cache-sets = <512>; 1561 d-cache-block-size = <64>; 1562 d-cache-size = <65536>; 1563 d-cache-sets = <512>; 1564 device_type = "cpu"; 1565 mmu-type = "riscv,sv48"; 1566 next-level-cache = <&l2_cache11>; 1567 riscv,isa = "rv64imafdcv"; 1568 riscv,isa-base = "rv64i"; 1569 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1570 "v", "sscofpmf", "sstc", 1571 "svinval", "svnapot", "svpbmt", 1572 "zawrs", "zba", "zbb", "zbc", 1573 "zbs", "zca", "zcb", "zcd", 1574 "zfa", "zfbfmin", "zfh", "zfhmin", 1575 "zicbom", "zicbop", "zicboz", 1576 "zicntr", "zicond","zicsr", "zifencei", 1577 "zihintntl", "zihintpause", "zihpm", 1578 "zvfbfmin", "zvfbfwma", "zvfh", 1579 "zvfhmin"; 1580 riscv,cbom-block-size = <64>; 1581 riscv,cboz-block-size = <64>; 1582 1583 cpu44_intc: interrupt-controller { 1584 compatible = "riscv,cpu-intc"; 1585 interrupt-controller; 1586 #interrupt-cells = <1>; 1587 }; 1588 }; 1589 1590 cpu45: cpu@45 { 1591 compatible = "thead,c920", "riscv"; 1592 reg = <45>; 1593 i-cache-block-size = <64>; 1594 i-cache-size = <65536>; 1595 i-cache-sets = <512>; 1596 d-cache-block-size = <64>; 1597 d-cache-size = <65536>; 1598 d-cache-sets = <512>; 1599 device_type = "cpu"; 1600 mmu-type = "riscv,sv48"; 1601 next-level-cache = <&l2_cache11>; 1602 riscv,isa = "rv64imafdcv"; 1603 riscv,isa-base = "rv64i"; 1604 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1605 "v", "sscofpmf", "sstc", 1606 "svinval", "svnapot", "svpbmt", 1607 "zawrs", "zba", "zbb", "zbc", 1608 "zbs", "zca", "zcb", "zcd", 1609 "zfa", "zfbfmin", "zfh", "zfhmin", 1610 "zicbom", "zicbop", "zicboz", 1611 "zicntr", "zicond","zicsr", "zifencei", 1612 "zihintntl", "zihintpause", "zihpm", 1613 "zvfbfmin", "zvfbfwma", "zvfh", 1614 "zvfhmin"; 1615 riscv,cbom-block-size = <64>; 1616 riscv,cboz-block-size = <64>; 1617 1618 cpu45_intc: interrupt-controller { 1619 compatible = "riscv,cpu-intc"; 1620 interrupt-controller; 1621 #interrupt-cells = <1>; 1622 }; 1623 }; 1624 1625 cpu46: cpu@46 { 1626 compatible = "thead,c920", "riscv"; 1627 reg = <46>; 1628 i-cache-block-size = <64>; 1629 i-cache-size = <65536>; 1630 i-cache-sets = <512>; 1631 d-cache-block-size = <64>; 1632 d-cache-size = <65536>; 1633 d-cache-sets = <512>; 1634 device_type = "cpu"; 1635 mmu-type = "riscv,sv48"; 1636 next-level-cache = <&l2_cache11>; 1637 riscv,isa = "rv64imafdcv"; 1638 riscv,isa-base = "rv64i"; 1639 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1640 "v", "sscofpmf", "sstc", 1641 "svinval", "svnapot", "svpbmt", 1642 "zawrs", "zba", "zbb", "zbc", 1643 "zbs", "zca", "zcb", "zcd", 1644 "zfa", "zfbfmin", "zfh", "zfhmin", 1645 "zicbom", "zicbop", "zicboz", 1646 "zicntr", "zicond","zicsr", "zifencei", 1647 "zihintntl", "zihintpause", "zihpm", 1648 "zvfbfmin", "zvfbfwma", "zvfh", 1649 "zvfhmin"; 1650 riscv,cbom-block-size = <64>; 1651 riscv,cboz-block-size = <64>; 1652 1653 cpu46_intc: interrupt-controller { 1654 compatible = "riscv,cpu-intc"; 1655 interrupt-controller; 1656 #interrupt-cells = <1>; 1657 }; 1658 }; 1659 1660 cpu47: cpu@47 { 1661 compatible = "thead,c920", "riscv"; 1662 reg = <47>; 1663 i-cache-block-size = <64>; 1664 i-cache-size = <65536>; 1665 i-cache-sets = <512>; 1666 d-cache-block-size = <64>; 1667 d-cache-size = <65536>; 1668 d-cache-sets = <512>; 1669 device_type = "cpu"; 1670 mmu-type = "riscv,sv48"; 1671 next-level-cache = <&l2_cache11>; 1672 riscv,isa = "rv64imafdcv"; 1673 riscv,isa-base = "rv64i"; 1674 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1675 "v", "sscofpmf", "sstc", 1676 "svinval", "svnapot", "svpbmt", 1677 "zawrs", "zba", "zbb", "zbc", 1678 "zbs", "zca", "zcb", "zcd", 1679 "zfa", "zfbfmin", "zfh", "zfhmin", 1680 "zicbom", "zicbop", "zicboz", 1681 "zicntr", "zicond","zicsr", "zifencei", 1682 "zihintntl", "zihintpause", "zihpm", 1683 "zvfbfmin", "zvfbfwma", "zvfh", 1684 "zvfhmin"; 1685 riscv,cbom-block-size = <64>; 1686 riscv,cboz-block-size = <64>; 1687 1688 cpu47_intc: interrupt-controller { 1689 compatible = "riscv,cpu-intc"; 1690 interrupt-controller; 1691 #interrupt-cells = <1>; 1692 }; 1693 }; 1694 1695 cpu48: cpu@48 { 1696 compatible = "thead,c920", "riscv"; 1697 reg = <48>; 1698 i-cache-block-size = <64>; 1699 i-cache-size = <65536>; 1700 i-cache-sets = <512>; 1701 d-cache-block-size = <64>; 1702 d-cache-size = <65536>; 1703 d-cache-sets = <512>; 1704 device_type = "cpu"; 1705 mmu-type = "riscv,sv48"; 1706 next-level-cache = <&l2_cache12>; 1707 riscv,isa = "rv64imafdcv"; 1708 riscv,isa-base = "rv64i"; 1709 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1710 "v", "sscofpmf", "sstc", 1711 "svinval", "svnapot", "svpbmt", 1712 "zawrs", "zba", "zbb", "zbc", 1713 "zbs", "zca", "zcb", "zcd", 1714 "zfa", "zfbfmin", "zfh", "zfhmin", 1715 "zicbom", "zicbop", "zicboz", 1716 "zicntr", "zicond","zicsr", "zifencei", 1717 "zihintntl", "zihintpause", "zihpm", 1718 "zvfbfmin", "zvfbfwma", "zvfh", 1719 "zvfhmin"; 1720 riscv,cbom-block-size = <64>; 1721 riscv,cboz-block-size = <64>; 1722 1723 cpu48_intc: interrupt-controller { 1724 compatible = "riscv,cpu-intc"; 1725 interrupt-controller; 1726 #interrupt-cells = <1>; 1727 }; 1728 }; 1729 1730 cpu49: cpu@49 { 1731 compatible = "thead,c920", "riscv"; 1732 reg = <49>; 1733 i-cache-block-size = <64>; 1734 i-cache-size = <65536>; 1735 i-cache-sets = <512>; 1736 d-cache-block-size = <64>; 1737 d-cache-size = <65536>; 1738 d-cache-sets = <512>; 1739 device_type = "cpu"; 1740 mmu-type = "riscv,sv48"; 1741 next-level-cache = <&l2_cache12>; 1742 riscv,isa = "rv64imafdcv"; 1743 riscv,isa-base = "rv64i"; 1744 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1745 "v", "sscofpmf", "sstc", 1746 "svinval", "svnapot", "svpbmt", 1747 "zawrs", "zba", "zbb", "zbc", 1748 "zbs", "zca", "zcb", "zcd", 1749 "zfa", "zfbfmin", "zfh", "zfhmin", 1750 "zicbom", "zicbop", "zicboz", 1751 "zicntr", "zicond","zicsr", "zifencei", 1752 "zihintntl", "zihintpause", "zihpm", 1753 "zvfbfmin", "zvfbfwma", "zvfh", 1754 "zvfhmin"; 1755 riscv,cbom-block-size = <64>; 1756 riscv,cboz-block-size = <64>; 1757 1758 cpu49_intc: interrupt-controller { 1759 compatible = "riscv,cpu-intc"; 1760 interrupt-controller; 1761 #interrupt-cells = <1>; 1762 }; 1763 }; 1764 1765 cpu50: cpu@50 { 1766 compatible = "thead,c920", "riscv"; 1767 reg = <50>; 1768 i-cache-block-size = <64>; 1769 i-cache-size = <65536>; 1770 i-cache-sets = <512>; 1771 d-cache-block-size = <64>; 1772 d-cache-size = <65536>; 1773 d-cache-sets = <512>; 1774 device_type = "cpu"; 1775 mmu-type = "riscv,sv48"; 1776 next-level-cache = <&l2_cache12>; 1777 riscv,isa = "rv64imafdcv"; 1778 riscv,isa-base = "rv64i"; 1779 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1780 "v", "sscofpmf", "sstc", 1781 "svinval", "svnapot", "svpbmt", 1782 "zawrs", "zba", "zbb", "zbc", 1783 "zbs", "zca", "zcb", "zcd", 1784 "zfa", "zfbfmin", "zfh", "zfhmin", 1785 "zicbom", "zicbop", "zicboz", 1786 "zicntr", "zicond","zicsr", "zifencei", 1787 "zihintntl", "zihintpause", "zihpm", 1788 "zvfbfmin", "zvfbfwma", "zvfh", 1789 "zvfhmin"; 1790 riscv,cbom-block-size = <64>; 1791 riscv,cboz-block-size = <64>; 1792 1793 cpu50_intc: interrupt-controller { 1794 compatible = "riscv,cpu-intc"; 1795 interrupt-controller; 1796 #interrupt-cells = <1>; 1797 }; 1798 }; 1799 1800 cpu51: cpu@51 { 1801 compatible = "thead,c920", "riscv"; 1802 reg = <51>; 1803 i-cache-block-size = <64>; 1804 i-cache-size = <65536>; 1805 i-cache-sets = <512>; 1806 d-cache-block-size = <64>; 1807 d-cache-size = <65536>; 1808 d-cache-sets = <512>; 1809 device_type = "cpu"; 1810 mmu-type = "riscv,sv48"; 1811 next-level-cache = <&l2_cache12>; 1812 riscv,isa = "rv64imafdcv"; 1813 riscv,isa-base = "rv64i"; 1814 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1815 "v", "sscofpmf", "sstc", 1816 "svinval", "svnapot", "svpbmt", 1817 "zawrs", "zba", "zbb", "zbc", 1818 "zbs", "zca", "zcb", "zcd", 1819 "zfa", "zfbfmin", "zfh", "zfhmin", 1820 "zicbom", "zicbop", "zicboz", 1821 "zicntr", "zicond","zicsr", "zifencei", 1822 "zihintntl", "zihintpause", "zihpm", 1823 "zvfbfmin", "zvfbfwma", "zvfh", 1824 "zvfhmin"; 1825 riscv,cbom-block-size = <64>; 1826 riscv,cboz-block-size = <64>; 1827 1828 cpu51_intc: interrupt-controller { 1829 compatible = "riscv,cpu-intc"; 1830 interrupt-controller; 1831 #interrupt-cells = <1>; 1832 }; 1833 }; 1834 1835 cpu52: cpu@52 { 1836 compatible = "thead,c920", "riscv"; 1837 reg = <52>; 1838 i-cache-block-size = <64>; 1839 i-cache-size = <65536>; 1840 i-cache-sets = <512>; 1841 d-cache-block-size = <64>; 1842 d-cache-size = <65536>; 1843 d-cache-sets = <512>; 1844 device_type = "cpu"; 1845 mmu-type = "riscv,sv48"; 1846 next-level-cache = <&l2_cache13>; 1847 riscv,isa = "rv64imafdcv"; 1848 riscv,isa-base = "rv64i"; 1849 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1850 "v", "sscofpmf", "sstc", 1851 "svinval", "svnapot", "svpbmt", 1852 "zawrs", "zba", "zbb", "zbc", 1853 "zbs", "zca", "zcb", "zcd", 1854 "zfa", "zfbfmin", "zfh", "zfhmin", 1855 "zicbom", "zicbop", "zicboz", 1856 "zicntr", "zicond","zicsr", "zifencei", 1857 "zihintntl", "zihintpause", "zihpm", 1858 "zvfbfmin", "zvfbfwma", "zvfh", 1859 "zvfhmin"; 1860 riscv,cbom-block-size = <64>; 1861 riscv,cboz-block-size = <64>; 1862 1863 cpu52_intc: interrupt-controller { 1864 compatible = "riscv,cpu-intc"; 1865 interrupt-controller; 1866 #interrupt-cells = <1>; 1867 }; 1868 }; 1869 1870 cpu53: cpu@53 { 1871 compatible = "thead,c920", "riscv"; 1872 reg = <53>; 1873 i-cache-block-size = <64>; 1874 i-cache-size = <65536>; 1875 i-cache-sets = <512>; 1876 d-cache-block-size = <64>; 1877 d-cache-size = <65536>; 1878 d-cache-sets = <512>; 1879 device_type = "cpu"; 1880 mmu-type = "riscv,sv48"; 1881 next-level-cache = <&l2_cache13>; 1882 riscv,isa = "rv64imafdcv"; 1883 riscv,isa-base = "rv64i"; 1884 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1885 "v", "sscofpmf", "sstc", 1886 "svinval", "svnapot", "svpbmt", 1887 "zawrs", "zba", "zbb", "zbc", 1888 "zbs", "zca", "zcb", "zcd", 1889 "zfa", "zfbfmin", "zfh", "zfhmin", 1890 "zicbom", "zicbop", "zicboz", 1891 "zicntr", "zicond","zicsr", "zifencei", 1892 "zihintntl", "zihintpause", "zihpm", 1893 "zvfbfmin", "zvfbfwma", "zvfh", 1894 "zvfhmin"; 1895 riscv,cbom-block-size = <64>; 1896 riscv,cboz-block-size = <64>; 1897 1898 cpu53_intc: interrupt-controller { 1899 compatible = "riscv,cpu-intc"; 1900 interrupt-controller; 1901 #interrupt-cells = <1>; 1902 }; 1903 }; 1904 1905 cpu54: cpu@54 { 1906 compatible = "thead,c920", "riscv"; 1907 reg = <54>; 1908 i-cache-block-size = <64>; 1909 i-cache-size = <65536>; 1910 i-cache-sets = <512>; 1911 d-cache-block-size = <64>; 1912 d-cache-size = <65536>; 1913 d-cache-sets = <512>; 1914 device_type = "cpu"; 1915 mmu-type = "riscv,sv48"; 1916 next-level-cache = <&l2_cache13>; 1917 riscv,isa = "rv64imafdcv"; 1918 riscv,isa-base = "rv64i"; 1919 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1920 "v", "sscofpmf", "sstc", 1921 "svinval", "svnapot", "svpbmt", 1922 "zawrs", "zba", "zbb", "zbc", 1923 "zbs", "zca", "zcb", "zcd", 1924 "zfa", "zfbfmin", "zfh", "zfhmin", 1925 "zicbom", "zicbop", "zicboz", 1926 "zicntr", "zicond","zicsr", "zifencei", 1927 "zihintntl", "zihintpause", "zihpm", 1928 "zvfbfmin", "zvfbfwma", "zvfh", 1929 "zvfhmin"; 1930 riscv,cbom-block-size = <64>; 1931 riscv,cboz-block-size = <64>; 1932 1933 cpu54_intc: interrupt-controller { 1934 compatible = "riscv,cpu-intc"; 1935 interrupt-controller; 1936 #interrupt-cells = <1>; 1937 }; 1938 }; 1939 1940 cpu55: cpu@55 { 1941 compatible = "thead,c920", "riscv"; 1942 reg = <55>; 1943 i-cache-block-size = <64>; 1944 i-cache-size = <65536>; 1945 i-cache-sets = <512>; 1946 d-cache-block-size = <64>; 1947 d-cache-size = <65536>; 1948 d-cache-sets = <512>; 1949 device_type = "cpu"; 1950 mmu-type = "riscv,sv48"; 1951 next-level-cache = <&l2_cache13>; 1952 riscv,isa = "rv64imafdcv"; 1953 riscv,isa-base = "rv64i"; 1954 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1955 "v", "sscofpmf", "sstc", 1956 "svinval", "svnapot", "svpbmt", 1957 "zawrs", "zba", "zbb", "zbc", 1958 "zbs", "zca", "zcb", "zcd", 1959 "zfa", "zfbfmin", "zfh", "zfhmin", 1960 "zicbom", "zicbop", "zicboz", 1961 "zicntr", "zicond","zicsr", "zifencei", 1962 "zihintntl", "zihintpause", "zihpm", 1963 "zvfbfmin", "zvfbfwma", "zvfh", 1964 "zvfhmin"; 1965 riscv,cbom-block-size = <64>; 1966 riscv,cboz-block-size = <64>; 1967 1968 cpu55_intc: interrupt-controller { 1969 compatible = "riscv,cpu-intc"; 1970 interrupt-controller; 1971 #interrupt-cells = <1>; 1972 }; 1973 }; 1974 1975 cpu56: cpu@56 { 1976 compatible = "thead,c920", "riscv"; 1977 reg = <56>; 1978 i-cache-block-size = <64>; 1979 i-cache-size = <65536>; 1980 i-cache-sets = <512>; 1981 d-cache-block-size = <64>; 1982 d-cache-size = <65536>; 1983 d-cache-sets = <512>; 1984 device_type = "cpu"; 1985 mmu-type = "riscv,sv48"; 1986 next-level-cache = <&l2_cache14>; 1987 riscv,isa = "rv64imafdcv"; 1988 riscv,isa-base = "rv64i"; 1989 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1990 "v", "sscofpmf", "sstc", 1991 "svinval", "svnapot", "svpbmt", 1992 "zawrs", "zba", "zbb", "zbc", 1993 "zbs", "zca", "zcb", "zcd", 1994 "zfa", "zfbfmin", "zfh", "zfhmin", 1995 "zicbom", "zicbop", "zicboz", 1996 "zicntr", "zicond","zicsr", "zifencei", 1997 "zihintntl", "zihintpause", "zihpm", 1998 "zvfbfmin", "zvfbfwma", "zvfh", 1999 "zvfhmin"; 2000 riscv,cbom-block-size = <64>; 2001 riscv,cboz-block-size = <64>; 2002 2003 cpu56_intc: interrupt-controller { 2004 compatible = "riscv,cpu-intc"; 2005 interrupt-controller; 2006 #interrupt-cells = <1>; 2007 }; 2008 }; 2009 2010 cpu57: cpu@57 { 2011 compatible = "thead,c920", "riscv"; 2012 reg = <57>; 2013 i-cache-block-size = <64>; 2014 i-cache-size = <65536>; 2015 i-cache-sets = <512>; 2016 d-cache-block-size = <64>; 2017 d-cache-size = <65536>; 2018 d-cache-sets = <512>; 2019 device_type = "cpu"; 2020 mmu-type = "riscv,sv48"; 2021 next-level-cache = <&l2_cache14>; 2022 riscv,isa = "rv64imafdcv"; 2023 riscv,isa-base = "rv64i"; 2024 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 2025 "v", "sscofpmf", "sstc", 2026 "svinval", "svnapot", "svpbmt", 2027 "zawrs", "zba", "zbb", "zbc", 2028 "zbs", "zca", "zcb", "zcd", 2029 "zfa", "zfbfmin", "zfh", "zfhmin", 2030 "zicbom", "zicbop", "zicboz", 2031 "zicntr", "zicond","zicsr", "zifencei", 2032 "zihintntl", "zihintpause", "zihpm", 2033 "zvfbfmin", "zvfbfwma", "zvfh", 2034 "zvfhmin"; 2035 riscv,cbom-block-size = <64>; 2036 riscv,cboz-block-size = <64>; 2037 2038 cpu57_intc: interrupt-controller { 2039 compatible = "riscv,cpu-intc"; 2040 interrupt-controller; 2041 #interrupt-cells = <1>; 2042 }; 2043 }; 2044 2045 cpu58: cpu@58 { 2046 compatible = "thead,c920", "riscv"; 2047 reg = <58>; 2048 i-cache-block-size = <64>; 2049 i-cache-size = <65536>; 2050 i-cache-sets = <512>; 2051 d-cache-block-size = <64>; 2052 d-cache-size = <65536>; 2053 d-cache-sets = <512>; 2054 device_type = "cpu"; 2055 mmu-type = "riscv,sv48"; 2056 next-level-cache = <&l2_cache14>; 2057 riscv,isa = "rv64imafdcv"; 2058 riscv,isa-base = "rv64i"; 2059 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 2060 "v", "sscofpmf", "sstc", 2061 "svinval", "svnapot", "svpbmt", 2062 "zawrs", "zba", "zbb", "zbc", 2063 "zbs", "zca", "zcb", "zcd", 2064 "zfa", "zfbfmin", "zfh", "zfhmin", 2065 "zicbom", "zicbop", "zicboz", 2066 "zicntr", "zicond","zicsr", "zifencei", 2067 "zihintntl", "zihintpause", "zihpm", 2068 "zvfbfmin", "zvfbfwma", "zvfh", 2069 "zvfhmin"; 2070 riscv,cbom-block-size = <64>; 2071 riscv,cboz-block-size = <64>; 2072 2073 cpu58_intc: interrupt-controller { 2074 compatible = "riscv,cpu-intc"; 2075 interrupt-controller; 2076 #interrupt-cells = <1>; 2077 }; 2078 }; 2079 2080 cpu59: cpu@59 { 2081 compatible = "thead,c920", "riscv"; 2082 reg = <59>; 2083 i-cache-block-size = <64>; 2084 i-cache-size = <65536>; 2085 i-cache-sets = <512>; 2086 d-cache-block-size = <64>; 2087 d-cache-size = <65536>; 2088 d-cache-sets = <512>; 2089 device_type = "cpu"; 2090 mmu-type = "riscv,sv48"; 2091 next-level-cache = <&l2_cache14>; 2092 riscv,isa = "rv64imafdcv"; 2093 riscv,isa-base = "rv64i"; 2094 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 2095 "v", "sscofpmf", "sstc", 2096 "svinval", "svnapot", "svpbmt", 2097 "zawrs", "zba", "zbb", "zbc", 2098 "zbs", "zca", "zcb", "zcd", 2099 "zfa", "zfbfmin", "zfh", "zfhmin", 2100 "zicbom", "zicbop", "zicboz", 2101 "zicntr", "zicond","zicsr", "zifencei", 2102 "zihintntl", "zihintpause", "zihpm", 2103 "zvfbfmin", "zvfbfwma", "zvfh", 2104 "zvfhmin"; 2105 riscv,cbom-block-size = <64>; 2106 riscv,cboz-block-size = <64>; 2107 2108 cpu59_intc: interrupt-controller { 2109 compatible = "riscv,cpu-intc"; 2110 interrupt-controller; 2111 #interrupt-cells = <1>; 2112 }; 2113 }; 2114 2115 cpu60: cpu@60 { 2116 compatible = "thead,c920", "riscv"; 2117 reg = <60>; 2118 i-cache-block-size = <64>; 2119 i-cache-size = <65536>; 2120 i-cache-sets = <512>; 2121 d-cache-block-size = <64>; 2122 d-cache-size = <65536>; 2123 d-cache-sets = <512>; 2124 device_type = "cpu"; 2125 mmu-type = "riscv,sv48"; 2126 next-level-cache = <&l2_cache15>; 2127 riscv,isa = "rv64imafdcv"; 2128 riscv,isa-base = "rv64i"; 2129 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 2130 "v", "sscofpmf", "sstc", 2131 "svinval", "svnapot", "svpbmt", 2132 "zawrs", "zba", "zbb", "zbc", 2133 "zbs", "zca", "zcb", "zcd", 2134 "zfa", "zfbfmin", "zfh", "zfhmin", 2135 "zicbom", "zicbop", "zicboz", 2136 "zicntr", "zicond","zicsr", "zifencei", 2137 "zihintntl", "zihintpause", "zihpm", 2138 "zvfbfmin", "zvfbfwma", "zvfh", 2139 "zvfhmin"; 2140 riscv,cbom-block-size = <64>; 2141 riscv,cboz-block-size = <64>; 2142 2143 cpu60_intc: interrupt-controller { 2144 compatible = "riscv,cpu-intc"; 2145 interrupt-controller; 2146 #interrupt-cells = <1>; 2147 }; 2148 }; 2149 2150 cpu61: cpu@61 { 2151 compatible = "thead,c920", "riscv"; 2152 reg = <61>; 2153 i-cache-block-size = <64>; 2154 i-cache-size = <65536>; 2155 i-cache-sets = <512>; 2156 d-cache-block-size = <64>; 2157 d-cache-size = <65536>; 2158 d-cache-sets = <512>; 2159 device_type = "cpu"; 2160 mmu-type = "riscv,sv48"; 2161 next-level-cache = <&l2_cache15>; 2162 riscv,isa = "rv64imafdcv"; 2163 riscv,isa-base = "rv64i"; 2164 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 2165 "v", "sscofpmf", "sstc", 2166 "svinval", "svnapot", "svpbmt", 2167 "zawrs", "zba", "zbb", "zbc", 2168 "zbs", "zca", "zcb", "zcd", 2169 "zfa", "zfbfmin", "zfh", "zfhmin", 2170 "zicbom", "zicbop", "zicboz", 2171 "zicntr", "zicond","zicsr", "zifencei", 2172 "zihintntl", "zihintpause", "zihpm", 2173 "zvfbfmin", "zvfbfwma", "zvfh", 2174 "zvfhmin"; 2175 riscv,cbom-block-size = <64>; 2176 riscv,cboz-block-size = <64>; 2177 2178 cpu61_intc: interrupt-controller { 2179 compatible = "riscv,cpu-intc"; 2180 interrupt-controller; 2181 #interrupt-cells = <1>; 2182 }; 2183 }; 2184 2185 cpu62: cpu@62 { 2186 compatible = "thead,c920", "riscv"; 2187 reg = <62>; 2188 i-cache-block-size = <64>; 2189 i-cache-size = <65536>; 2190 i-cache-sets = <512>; 2191 d-cache-block-size = <64>; 2192 d-cache-size = <65536>; 2193 d-cache-sets = <512>; 2194 device_type = "cpu"; 2195 mmu-type = "riscv,sv48"; 2196 next-level-cache = <&l2_cache15>; 2197 riscv,isa = "rv64imafdcv"; 2198 riscv,isa-base = "rv64i"; 2199 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 2200 "v", "sscofpmf", "sstc", 2201 "svinval", "svnapot", "svpbmt", 2202 "zawrs", "zba", "zbb", "zbc", 2203 "zbs", "zca", "zcb", "zcd", 2204 "zfa", "zfbfmin", "zfh", "zfhmin", 2205 "zicbom", "zicbop", "zicboz", 2206 "zicntr", "zicond","zicsr", "zifencei", 2207 "zihintntl", "zihintpause", "zihpm", 2208 "zvfbfmin", "zvfbfwma", "zvfh", 2209 "zvfhmin"; 2210 riscv,cbom-block-size = <64>; 2211 riscv,cboz-block-size = <64>; 2212 2213 cpu62_intc: interrupt-controller { 2214 compatible = "riscv,cpu-intc"; 2215 interrupt-controller; 2216 #interrupt-cells = <1>; 2217 }; 2218 }; 2219 2220 cpu63: cpu@63 { 2221 compatible = "thead,c920", "riscv"; 2222 reg = <63>; 2223 i-cache-block-size = <64>; 2224 i-cache-size = <65536>; 2225 i-cache-sets = <512>; 2226 d-cache-block-size = <64>; 2227 d-cache-size = <65536>; 2228 d-cache-sets = <512>; 2229 device_type = "cpu"; 2230 mmu-type = "riscv,sv48"; 2231 next-level-cache = <&l2_cache15>; 2232 riscv,isa = "rv64imafdcv"; 2233 riscv,isa-base = "rv64i"; 2234 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 2235 "v", "sscofpmf", "sstc", 2236 "svinval", "svnapot", "svpbmt", 2237 "zawrs", "zba", "zbb", "zbc", 2238 "zbs", "zca", "zcb", "zcd", 2239 "zfa", "zfbfmin", "zfh", "zfhmin", 2240 "zicbom", "zicbop", "zicboz", 2241 "zicntr", "zicond","zicsr", "zifencei", 2242 "zihintntl", "zihintpause", "zihpm", 2243 "zvfbfmin", "zvfbfwma", "zvfh", 2244 "zvfhmin"; 2245 riscv,cbom-block-size = <64>; 2246 riscv,cboz-block-size = <64>; 2247 2248 cpu63_intc: interrupt-controller { 2249 compatible = "riscv,cpu-intc"; 2250 interrupt-controller; 2251 #interrupt-cells = <1>; 2252 }; 2253 }; 2254 2255 cpu-map { 2256 socket0 { 2257 cluster0 { 2258 core0 { 2259 cpu = <&cpu0>; 2260 }; 2261 2262 core1 { 2263 cpu = <&cpu1>; 2264 }; 2265 2266 core2 { 2267 cpu = <&cpu2>; 2268 }; 2269 2270 core3 { 2271 cpu = <&cpu3>; 2272 }; 2273 }; 2274 2275 cluster1 { 2276 core0 { 2277 cpu = <&cpu4>; 2278 }; 2279 2280 core1 { 2281 cpu = <&cpu5>; 2282 }; 2283 2284 core2 { 2285 cpu = <&cpu6>; 2286 }; 2287 2288 core3 { 2289 cpu = <&cpu7>; 2290 }; 2291 }; 2292 2293 cluster2 { 2294 core0 { 2295 cpu = <&cpu8>; 2296 }; 2297 2298 core1 { 2299 cpu = <&cpu9>; 2300 }; 2301 2302 core2 { 2303 cpu = <&cpu10>; 2304 }; 2305 2306 core3 { 2307 cpu = <&cpu11>; 2308 }; 2309 }; 2310 2311 cluster3 { 2312 core0 { 2313 cpu = <&cpu12>; 2314 }; 2315 2316 core1 { 2317 cpu = <&cpu13>; 2318 }; 2319 2320 core2 { 2321 cpu = <&cpu14>; 2322 }; 2323 2324 core3 { 2325 cpu = <&cpu15>; 2326 }; 2327 }; 2328 2329 cluster4 { 2330 core0 { 2331 cpu = <&cpu16>; 2332 }; 2333 2334 core1 { 2335 cpu = <&cpu17>; 2336 }; 2337 2338 core2 { 2339 cpu = <&cpu18>; 2340 }; 2341 2342 core3 { 2343 cpu = <&cpu19>; 2344 }; 2345 }; 2346 2347 cluster5 { 2348 core0 { 2349 cpu = <&cpu20>; 2350 }; 2351 2352 core1 { 2353 cpu = <&cpu21>; 2354 }; 2355 2356 core2 { 2357 cpu = <&cpu22>; 2358 }; 2359 2360 core3 { 2361 cpu = <&cpu23>; 2362 }; 2363 }; 2364 2365 cluster6 { 2366 core0 { 2367 cpu = <&cpu24>; 2368 }; 2369 2370 core1 { 2371 cpu = <&cpu25>; 2372 }; 2373 2374 core2 { 2375 cpu = <&cpu26>; 2376 }; 2377 2378 core3 { 2379 cpu = <&cpu27>; 2380 }; 2381 }; 2382 2383 cluster7 { 2384 core0 { 2385 cpu = <&cpu28>; 2386 }; 2387 2388 core1 { 2389 cpu = <&cpu29>; 2390 }; 2391 2392 core2 { 2393 cpu = <&cpu30>; 2394 }; 2395 2396 core3 { 2397 cpu = <&cpu31>; 2398 }; 2399 }; 2400 2401 cluster8 { 2402 core0 { 2403 cpu = <&cpu32>; 2404 }; 2405 2406 core1 { 2407 cpu = <&cpu33>; 2408 }; 2409 2410 core2 { 2411 cpu = <&cpu34>; 2412 }; 2413 2414 core3 { 2415 cpu = <&cpu35>; 2416 }; 2417 }; 2418 2419 cluster9 { 2420 core0 { 2421 cpu = <&cpu36>; 2422 }; 2423 2424 core1 { 2425 cpu = <&cpu37>; 2426 }; 2427 2428 core2 { 2429 cpu = <&cpu38>; 2430 }; 2431 2432 core3 { 2433 cpu = <&cpu39>; 2434 }; 2435 }; 2436 2437 cluster10 { 2438 core0 { 2439 cpu = <&cpu40>; 2440 }; 2441 2442 core1 { 2443 cpu = <&cpu41>; 2444 }; 2445 2446 core2 { 2447 cpu = <&cpu42>; 2448 }; 2449 2450 core3 { 2451 cpu = <&cpu43>; 2452 }; 2453 }; 2454 2455 cluster11 { 2456 core0 { 2457 cpu = <&cpu44>; 2458 }; 2459 2460 core1 { 2461 cpu = <&cpu45>; 2462 }; 2463 2464 core2 { 2465 cpu = <&cpu46>; 2466 }; 2467 2468 core3 { 2469 cpu = <&cpu47>; 2470 }; 2471 }; 2472 2473 cluster12 { 2474 core0 { 2475 cpu = <&cpu48>; 2476 }; 2477 2478 core1 { 2479 cpu = <&cpu49>; 2480 }; 2481 2482 core2 { 2483 cpu = <&cpu50>; 2484 }; 2485 2486 core3 { 2487 cpu = <&cpu51>; 2488 }; 2489 }; 2490 2491 cluster13 { 2492 core0 { 2493 cpu = <&cpu52>; 2494 }; 2495 2496 core1 { 2497 cpu = <&cpu53>; 2498 }; 2499 2500 core2 { 2501 cpu = <&cpu54>; 2502 }; 2503 2504 core3 { 2505 cpu = <&cpu55>; 2506 }; 2507 }; 2508 2509 cluster14 { 2510 core0 { 2511 cpu = <&cpu56>; 2512 }; 2513 2514 core1 { 2515 cpu = <&cpu57>; 2516 }; 2517 2518 core2 { 2519 cpu = <&cpu58>; 2520 }; 2521 2522 core3 { 2523 cpu = <&cpu59>; 2524 }; 2525 }; 2526 2527 cluster15 { 2528 core0 { 2529 cpu = <&cpu60>; 2530 }; 2531 2532 core1 { 2533 cpu = <&cpu61>; 2534 }; 2535 2536 core2 { 2537 cpu = <&cpu62>; 2538 }; 2539 2540 core3 { 2541 cpu = <&cpu63>; 2542 }; 2543 }; 2544 }; 2545 }; 2546 2547 l2_cache0: cache-controller-0 { 2548 compatible = "cache"; 2549 cache-block-size = <64>; 2550 cache-level = <2>; 2551 cache-size = <2097152>; 2552 cache-sets = <2048>; 2553 cache-unified; 2554 next-level-cache = <&l3_cache>; 2555 }; 2556 2557 l2_cache1: cache-controller-1 { 2558 compatible = "cache"; 2559 cache-block-size = <64>; 2560 cache-level = <2>; 2561 cache-size = <2097152>; 2562 cache-sets = <2048>; 2563 cache-unified; 2564 next-level-cache = <&l3_cache>; 2565 }; 2566 2567 l2_cache2: cache-controller-2 { 2568 compatible = "cache"; 2569 cache-block-size = <64>; 2570 cache-level = <2>; 2571 cache-size = <2097152>; 2572 cache-sets = <2048>; 2573 cache-unified; 2574 next-level-cache = <&l3_cache>; 2575 }; 2576 2577 l2_cache3: cache-controller-3 { 2578 compatible = "cache"; 2579 cache-block-size = <64>; 2580 cache-level = <2>; 2581 cache-size = <2097152>; 2582 cache-sets = <2048>; 2583 cache-unified; 2584 next-level-cache = <&l3_cache>; 2585 }; 2586 2587 l2_cache4: cache-controller-4 { 2588 compatible = "cache"; 2589 cache-block-size = <64>; 2590 cache-level = <2>; 2591 cache-size = <2097152>; 2592 cache-sets = <2048>; 2593 cache-unified; 2594 next-level-cache = <&l3_cache>; 2595 }; 2596 2597 l2_cache5: cache-controller-5 { 2598 compatible = "cache"; 2599 cache-block-size = <64>; 2600 cache-level = <2>; 2601 cache-size = <2097152>; 2602 cache-sets = <2048>; 2603 cache-unified; 2604 next-level-cache = <&l3_cache>; 2605 }; 2606 2607 l2_cache6: cache-controller-6 { 2608 compatible = "cache"; 2609 cache-block-size = <64>; 2610 cache-level = <2>; 2611 cache-size = <2097152>; 2612 cache-sets = <2048>; 2613 cache-unified; 2614 next-level-cache = <&l3_cache>; 2615 }; 2616 2617 l2_cache7: cache-controller-7 { 2618 compatible = "cache"; 2619 cache-block-size = <64>; 2620 cache-level = <2>; 2621 cache-size = <2097152>; 2622 cache-sets = <2048>; 2623 cache-unified; 2624 next-level-cache = <&l3_cache>; 2625 }; 2626 2627 l2_cache8: cache-controller-8 { 2628 compatible = "cache"; 2629 cache-block-size = <64>; 2630 cache-level = <2>; 2631 cache-size = <2097152>; 2632 cache-sets = <2048>; 2633 cache-unified; 2634 next-level-cache = <&l3_cache>; 2635 }; 2636 2637 l2_cache9: cache-controller-9 { 2638 compatible = "cache"; 2639 cache-block-size = <64>; 2640 cache-level = <2>; 2641 cache-size = <2097152>; 2642 cache-sets = <2048>; 2643 cache-unified; 2644 next-level-cache = <&l3_cache>; 2645 }; 2646 2647 l2_cache10: cache-controller-10 { 2648 compatible = "cache"; 2649 cache-block-size = <64>; 2650 cache-level = <2>; 2651 cache-size = <2097152>; 2652 cache-sets = <2048>; 2653 cache-unified; 2654 next-level-cache = <&l3_cache>; 2655 }; 2656 2657 l2_cache11: cache-controller-11 { 2658 compatible = "cache"; 2659 cache-block-size = <64>; 2660 cache-level = <2>; 2661 cache-size = <2097152>; 2662 cache-sets = <2048>; 2663 cache-unified; 2664 next-level-cache = <&l3_cache>; 2665 }; 2666 2667 l2_cache12: cache-controller-12 { 2668 compatible = "cache"; 2669 cache-block-size = <64>; 2670 cache-level = <2>; 2671 cache-size = <2097152>; 2672 cache-sets = <2048>; 2673 cache-unified; 2674 next-level-cache = <&l3_cache>; 2675 }; 2676 2677 l2_cache13: cache-controller-13 { 2678 compatible = "cache"; 2679 cache-block-size = <64>; 2680 cache-level = <2>; 2681 cache-size = <2097152>; 2682 cache-sets = <2048>; 2683 cache-unified; 2684 next-level-cache = <&l3_cache>; 2685 }; 2686 2687 l2_cache14: cache-controller-14 { 2688 compatible = "cache"; 2689 cache-block-size = <64>; 2690 cache-level = <2>; 2691 cache-size = <2097152>; 2692 cache-sets = <2048>; 2693 cache-unified; 2694 next-level-cache = <&l3_cache>; 2695 }; 2696 2697 l2_cache15: cache-controller-15 { 2698 compatible = "cache"; 2699 cache-block-size = <64>; 2700 cache-level = <2>; 2701 cache-size = <2097152>; 2702 cache-sets = <2048>; 2703 cache-unified; 2704 next-level-cache = <&l3_cache>; 2705 }; 2706 2707 l3_cache: cache-controller-16 { 2708 compatible = "cache"; 2709 cache-block-size = <64>; 2710 cache-level = <3>; 2711 cache-size = <67108864>; 2712 cache-sets = <4096>; 2713 cache-unified; 2714 }; 2715 }; 2716 2717 soc { 2718 intc: interrupt-controller@6d40000000 { 2719 compatible = "sophgo,sg2044-plic", "thead,c900-plic"; 2720 #address-cells = <0>; 2721 #interrupt-cells = <2>; 2722 reg = <0x6d 0x40000000 0x0 0x4000000>; 2723 interrupt-controller; 2724 interrupts-extended = 2725 <&cpu0_intc 11>, <&cpu0_intc 9>, 2726 <&cpu1_intc 11>, <&cpu1_intc 9>, 2727 <&cpu2_intc 11>, <&cpu2_intc 9>, 2728 <&cpu3_intc 11>, <&cpu3_intc 9>, 2729 <&cpu4_intc 11>, <&cpu4_intc 9>, 2730 <&cpu5_intc 11>, <&cpu5_intc 9>, 2731 <&cpu6_intc 11>, <&cpu6_intc 9>, 2732 <&cpu7_intc 11>, <&cpu7_intc 9>, 2733 <&cpu8_intc 11>, <&cpu8_intc 9>, 2734 <&cpu9_intc 11>, <&cpu9_intc 9>, 2735 <&cpu10_intc 11>, <&cpu10_intc 9>, 2736 <&cpu11_intc 11>, <&cpu11_intc 9>, 2737 <&cpu12_intc 11>, <&cpu12_intc 9>, 2738 <&cpu13_intc 11>, <&cpu13_intc 9>, 2739 <&cpu14_intc 11>, <&cpu14_intc 9>, 2740 <&cpu15_intc 11>, <&cpu15_intc 9>, 2741 <&cpu16_intc 11>, <&cpu16_intc 9>, 2742 <&cpu17_intc 11>, <&cpu17_intc 9>, 2743 <&cpu18_intc 11>, <&cpu18_intc 9>, 2744 <&cpu19_intc 11>, <&cpu19_intc 9>, 2745 <&cpu20_intc 11>, <&cpu20_intc 9>, 2746 <&cpu21_intc 11>, <&cpu21_intc 9>, 2747 <&cpu22_intc 11>, <&cpu22_intc 9>, 2748 <&cpu23_intc 11>, <&cpu23_intc 9>, 2749 <&cpu24_intc 11>, <&cpu24_intc 9>, 2750 <&cpu25_intc 11>, <&cpu25_intc 9>, 2751 <&cpu26_intc 11>, <&cpu26_intc 9>, 2752 <&cpu27_intc 11>, <&cpu27_intc 9>, 2753 <&cpu28_intc 11>, <&cpu28_intc 9>, 2754 <&cpu29_intc 11>, <&cpu29_intc 9>, 2755 <&cpu30_intc 11>, <&cpu30_intc 9>, 2756 <&cpu31_intc 11>, <&cpu31_intc 9>, 2757 <&cpu32_intc 11>, <&cpu32_intc 9>, 2758 <&cpu33_intc 11>, <&cpu33_intc 9>, 2759 <&cpu34_intc 11>, <&cpu34_intc 9>, 2760 <&cpu35_intc 11>, <&cpu35_intc 9>, 2761 <&cpu36_intc 11>, <&cpu36_intc 9>, 2762 <&cpu37_intc 11>, <&cpu37_intc 9>, 2763 <&cpu38_intc 11>, <&cpu38_intc 9>, 2764 <&cpu39_intc 11>, <&cpu39_intc 9>, 2765 <&cpu40_intc 11>, <&cpu40_intc 9>, 2766 <&cpu41_intc 11>, <&cpu41_intc 9>, 2767 <&cpu42_intc 11>, <&cpu42_intc 9>, 2768 <&cpu43_intc 11>, <&cpu43_intc 9>, 2769 <&cpu44_intc 11>, <&cpu44_intc 9>, 2770 <&cpu45_intc 11>, <&cpu45_intc 9>, 2771 <&cpu46_intc 11>, <&cpu46_intc 9>, 2772 <&cpu47_intc 11>, <&cpu47_intc 9>, 2773 <&cpu48_intc 11>, <&cpu48_intc 9>, 2774 <&cpu49_intc 11>, <&cpu49_intc 9>, 2775 <&cpu50_intc 11>, <&cpu50_intc 9>, 2776 <&cpu51_intc 11>, <&cpu51_intc 9>, 2777 <&cpu52_intc 11>, <&cpu52_intc 9>, 2778 <&cpu53_intc 11>, <&cpu53_intc 9>, 2779 <&cpu54_intc 11>, <&cpu54_intc 9>, 2780 <&cpu55_intc 11>, <&cpu55_intc 9>, 2781 <&cpu56_intc 11>, <&cpu56_intc 9>, 2782 <&cpu57_intc 11>, <&cpu57_intc 9>, 2783 <&cpu58_intc 11>, <&cpu58_intc 9>, 2784 <&cpu59_intc 11>, <&cpu59_intc 9>, 2785 <&cpu60_intc 11>, <&cpu60_intc 9>, 2786 <&cpu61_intc 11>, <&cpu61_intc 9>, 2787 <&cpu62_intc 11>, <&cpu62_intc 9>, 2788 <&cpu63_intc 11>, <&cpu63_intc 9>; 2789 riscv,ndev = <863>; 2790 }; 2791 2792 aclint_mswi: interrupt-controller@6d44000000 { 2793 compatible = "sophgo,sg2044-aclint-mswi", "thead,c900-aclint-mswi"; 2794 reg = <0x6d 0x44000000 0x0 0x4000>; 2795 interrupts-extended = <&cpu0_intc 3>, 2796 <&cpu1_intc 3>, 2797 <&cpu2_intc 3>, 2798 <&cpu3_intc 3>, 2799 <&cpu4_intc 3>, 2800 <&cpu5_intc 3>, 2801 <&cpu6_intc 3>, 2802 <&cpu7_intc 3>, 2803 <&cpu8_intc 3>, 2804 <&cpu9_intc 3>, 2805 <&cpu10_intc 3>, 2806 <&cpu11_intc 3>, 2807 <&cpu12_intc 3>, 2808 <&cpu13_intc 3>, 2809 <&cpu14_intc 3>, 2810 <&cpu15_intc 3>, 2811 <&cpu16_intc 3>, 2812 <&cpu17_intc 3>, 2813 <&cpu18_intc 3>, 2814 <&cpu19_intc 3>, 2815 <&cpu20_intc 3>, 2816 <&cpu21_intc 3>, 2817 <&cpu22_intc 3>, 2818 <&cpu23_intc 3>, 2819 <&cpu24_intc 3>, 2820 <&cpu25_intc 3>, 2821 <&cpu26_intc 3>, 2822 <&cpu27_intc 3>, 2823 <&cpu28_intc 3>, 2824 <&cpu29_intc 3>, 2825 <&cpu30_intc 3>, 2826 <&cpu31_intc 3>, 2827 <&cpu32_intc 3>, 2828 <&cpu33_intc 3>, 2829 <&cpu34_intc 3>, 2830 <&cpu35_intc 3>, 2831 <&cpu36_intc 3>, 2832 <&cpu37_intc 3>, 2833 <&cpu38_intc 3>, 2834 <&cpu39_intc 3>, 2835 <&cpu40_intc 3>, 2836 <&cpu41_intc 3>, 2837 <&cpu42_intc 3>, 2838 <&cpu43_intc 3>, 2839 <&cpu44_intc 3>, 2840 <&cpu45_intc 3>, 2841 <&cpu46_intc 3>, 2842 <&cpu47_intc 3>, 2843 <&cpu48_intc 3>, 2844 <&cpu49_intc 3>, 2845 <&cpu50_intc 3>, 2846 <&cpu51_intc 3>, 2847 <&cpu52_intc 3>, 2848 <&cpu53_intc 3>, 2849 <&cpu54_intc 3>, 2850 <&cpu55_intc 3>, 2851 <&cpu56_intc 3>, 2852 <&cpu57_intc 3>, 2853 <&cpu58_intc 3>, 2854 <&cpu59_intc 3>, 2855 <&cpu60_intc 3>, 2856 <&cpu61_intc 3>, 2857 <&cpu62_intc 3>, 2858 <&cpu63_intc 3>; 2859 }; 2860 2861 aclint_mtimer: timer@6d44004000 { 2862 compatible = "sophgo,sg2044-aclint-mtimer", "thead,c900-aclint-mtimer"; 2863 reg = <0x6d 0x44004000 0x0 0x8000>; 2864 reg-names = "mtimecmp"; 2865 interrupts-extended = <&cpu0_intc 7>, 2866 <&cpu1_intc 7>, 2867 <&cpu2_intc 7>, 2868 <&cpu3_intc 7>, 2869 <&cpu4_intc 7>, 2870 <&cpu5_intc 7>, 2871 <&cpu6_intc 7>, 2872 <&cpu7_intc 7>, 2873 <&cpu8_intc 7>, 2874 <&cpu9_intc 7>, 2875 <&cpu10_intc 7>, 2876 <&cpu11_intc 7>, 2877 <&cpu12_intc 7>, 2878 <&cpu13_intc 7>, 2879 <&cpu14_intc 7>, 2880 <&cpu15_intc 7>, 2881 <&cpu16_intc 7>, 2882 <&cpu17_intc 7>, 2883 <&cpu18_intc 7>, 2884 <&cpu19_intc 7>, 2885 <&cpu20_intc 7>, 2886 <&cpu21_intc 7>, 2887 <&cpu22_intc 7>, 2888 <&cpu23_intc 7>, 2889 <&cpu24_intc 7>, 2890 <&cpu25_intc 7>, 2891 <&cpu26_intc 7>, 2892 <&cpu27_intc 7>, 2893 <&cpu28_intc 7>, 2894 <&cpu29_intc 7>, 2895 <&cpu30_intc 7>, 2896 <&cpu31_intc 7>, 2897 <&cpu32_intc 7>, 2898 <&cpu33_intc 7>, 2899 <&cpu34_intc 7>, 2900 <&cpu35_intc 7>, 2901 <&cpu36_intc 7>, 2902 <&cpu37_intc 7>, 2903 <&cpu38_intc 7>, 2904 <&cpu39_intc 7>, 2905 <&cpu40_intc 7>, 2906 <&cpu41_intc 7>, 2907 <&cpu42_intc 7>, 2908 <&cpu43_intc 7>, 2909 <&cpu44_intc 7>, 2910 <&cpu45_intc 7>, 2911 <&cpu46_intc 7>, 2912 <&cpu47_intc 7>, 2913 <&cpu48_intc 7>, 2914 <&cpu49_intc 7>, 2915 <&cpu50_intc 7>, 2916 <&cpu51_intc 7>, 2917 <&cpu52_intc 7>, 2918 <&cpu53_intc 7>, 2919 <&cpu54_intc 7>, 2920 <&cpu55_intc 7>, 2921 <&cpu56_intc 7>, 2922 <&cpu57_intc 7>, 2923 <&cpu58_intc 7>, 2924 <&cpu59_intc 7>, 2925 <&cpu60_intc 7>, 2926 <&cpu61_intc 7>, 2927 <&cpu62_intc 7>, 2928 <&cpu63_intc 7>; 2929 }; 2930 2931 aclint_sswi: interrupt-controller@6d4400c000 { 2932 compatible = "sophgo,sg2044-aclint-sswi", "thead,c900-aclint-sswi"; 2933 reg = <0x6d 0x4400c000 0x0 0x1000>; 2934 #interrupt-cells = <0>; 2935 interrupt-controller; 2936 interrupts-extended = <&cpu0_intc 1>, 2937 <&cpu1_intc 1>, 2938 <&cpu2_intc 1>, 2939 <&cpu3_intc 1>, 2940 <&cpu4_intc 1>, 2941 <&cpu5_intc 1>, 2942 <&cpu6_intc 1>, 2943 <&cpu7_intc 1>, 2944 <&cpu8_intc 1>, 2945 <&cpu9_intc 1>, 2946 <&cpu10_intc 1>, 2947 <&cpu11_intc 1>, 2948 <&cpu12_intc 1>, 2949 <&cpu13_intc 1>, 2950 <&cpu14_intc 1>, 2951 <&cpu15_intc 1>, 2952 <&cpu16_intc 1>, 2953 <&cpu17_intc 1>, 2954 <&cpu18_intc 1>, 2955 <&cpu19_intc 1>, 2956 <&cpu20_intc 1>, 2957 <&cpu21_intc 1>, 2958 <&cpu22_intc 1>, 2959 <&cpu23_intc 1>, 2960 <&cpu24_intc 1>, 2961 <&cpu25_intc 1>, 2962 <&cpu26_intc 1>, 2963 <&cpu27_intc 1>, 2964 <&cpu28_intc 1>, 2965 <&cpu29_intc 1>, 2966 <&cpu30_intc 1>, 2967 <&cpu31_intc 1>, 2968 <&cpu32_intc 1>, 2969 <&cpu33_intc 1>, 2970 <&cpu34_intc 1>, 2971 <&cpu35_intc 1>, 2972 <&cpu36_intc 1>, 2973 <&cpu37_intc 1>, 2974 <&cpu38_intc 1>, 2975 <&cpu39_intc 1>, 2976 <&cpu40_intc 1>, 2977 <&cpu41_intc 1>, 2978 <&cpu42_intc 1>, 2979 <&cpu43_intc 1>, 2980 <&cpu44_intc 1>, 2981 <&cpu45_intc 1>, 2982 <&cpu46_intc 1>, 2983 <&cpu47_intc 1>, 2984 <&cpu48_intc 1>, 2985 <&cpu49_intc 1>, 2986 <&cpu50_intc 1>, 2987 <&cpu51_intc 1>, 2988 <&cpu52_intc 1>, 2989 <&cpu53_intc 1>, 2990 <&cpu54_intc 1>, 2991 <&cpu55_intc 1>, 2992 <&cpu56_intc 1>, 2993 <&cpu57_intc 1>, 2994 <&cpu58_intc 1>, 2995 <&cpu59_intc 1>, 2996 <&cpu60_intc 1>, 2997 <&cpu61_intc 1>, 2998 <&cpu62_intc 1>, 2999 <&cpu63_intc 1>; 3000 }; 3001 }; 3002}; 3003