1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Definitions for kernel modules using asus-armoury driver 4 * 5 * Copyright (c) 2024 Luke Jones <luke@ljones.dev> 6 */ 7 8 #ifndef _ASUS_ARMOURY_H_ 9 #define _ASUS_ARMOURY_H_ 10 11 #include <linux/dmi.h> 12 #include <linux/platform_device.h> 13 #include <linux/sysfs.h> 14 #include <linux/types.h> 15 16 #define DRIVER_NAME "asus-armoury" 17 18 /** 19 * armoury_attr_uint_store() - Send an uint to WMI method if within min/max. 20 * @kobj: Pointer to the driver object. 21 * @attr: Pointer to the attribute calling this function. 22 * @buf: The buffer to read from, this is parsed to `uint` type. 23 * @count: Required by sysfs attribute macros, pass in from the callee attr. 24 * @min: Minimum accepted value. Below this returns -EINVAL. 25 * @max: Maximum accepted value. Above this returns -EINVAL. 26 * @store_value: Pointer to where the parsed value should be stored. 27 * @wmi_dev: The WMI function ID to use. 28 * 29 * This function is intended to be generic so it can be called from any "_store" 30 * attribute which works only with integers. 31 * 32 * Integers to be sent to the WMI method is inclusive range checked and 33 * an error returned if out of range. 34 * 35 * If the value is valid and WMI is success then the sysfs attribute is notified 36 * and if asus_bios_requires_reboot() is true then reboot attribute 37 * is also notified. 38 * 39 * Returns: Either count, or an error. 40 */ 41 ssize_t armoury_attr_uint_store(struct kobject *kobj, struct kobj_attribute *attr, 42 const char *buf, size_t count, u32 min, u32 max, 43 u32 *store_value, u32 wmi_dev); 44 45 /** 46 * armoury_attr_uint_show() - Receive an uint from a WMI method. 47 * @kobj: Pointer to the driver object. 48 * @attr: Pointer to the attribute calling this function. 49 * @buf: The buffer to write to, as an `uint` type. 50 * @wmi_dev: The WMI function ID to use. 51 * 52 * This function is intended to be generic so it can be called from any "_show" 53 * attribute which works only with integers. 54 * 55 * Returns: Either count, or an error. 56 */ 57 ssize_t armoury_attr_uint_show(struct kobject *kobj, struct kobj_attribute *attr, 58 char *buf, u32 wmi_dev); 59 60 #define __ASUS_ATTR_RO(_func, _name) \ 61 { \ 62 .attr = { .name = __stringify(_name), .mode = 0444 }, \ 63 .show = _func##_##_name##_show, \ 64 } 65 66 #define __ASUS_ATTR_RO_AS(_name, _show) \ 67 { \ 68 .attr = { .name = __stringify(_name), .mode = 0444 }, \ 69 .show = _show, \ 70 } 71 72 #define __ASUS_ATTR_RW(_func, _name) \ 73 __ATTR(_name, 0644, _func##_##_name##_show, _func##_##_name##_store) 74 75 #define __WMI_STORE_INT(_attr, _min, _max, _wmi) \ 76 static ssize_t _attr##_store(struct kobject *kobj, \ 77 struct kobj_attribute *attr, \ 78 const char *buf, size_t count) \ 79 { \ 80 return armoury_attr_uint_store(kobj, attr, buf, count, _min, \ 81 _max, NULL, _wmi); \ 82 } 83 84 #define ASUS_WMI_SHOW_INT(_attr, _wmi) \ 85 static ssize_t _attr##_show(struct kobject *kobj, \ 86 struct kobj_attribute *attr, char *buf) \ 87 { \ 88 return armoury_attr_uint_show(kobj, attr, buf, _wmi); \ 89 } 90 91 /* Create functions and attributes for use in other macros or on their own */ 92 93 /* Shows a formatted static variable */ 94 #define __ATTR_SHOW_FMT(_prop, _attrname, _fmt, _val) \ 95 static ssize_t _attrname##_##_prop##_show( \ 96 struct kobject *kobj, struct kobj_attribute *attr, char *buf) \ 97 { \ 98 return sysfs_emit(buf, _fmt, _val); \ 99 } \ 100 static struct kobj_attribute attr_##_attrname##_##_prop = \ 101 __ASUS_ATTR_RO(_attrname, _prop) 102 103 #define __ATTR_RO_INT_GROUP_ENUM(_attrname, _wmi, _fsname, _possible, _dispname)\ 104 ASUS_WMI_SHOW_INT(_attrname##_current_value, _wmi); \ 105 static struct kobj_attribute attr_##_attrname##_current_value = \ 106 __ASUS_ATTR_RO(_attrname, current_value); \ 107 __ATTR_SHOW_FMT(display_name, _attrname, "%s\n", _dispname); \ 108 __ATTR_SHOW_FMT(possible_values, _attrname, "%s\n", _possible); \ 109 static struct kobj_attribute attr_##_attrname##_type = \ 110 __ASUS_ATTR_RO_AS(type, enum_type_show); \ 111 static struct attribute *_attrname##_attrs[] = { \ 112 &attr_##_attrname##_current_value.attr, \ 113 &attr_##_attrname##_display_name.attr, \ 114 &attr_##_attrname##_possible_values.attr, \ 115 &attr_##_attrname##_type.attr, \ 116 NULL \ 117 }; \ 118 static const struct attribute_group _attrname##_attr_group = { \ 119 .name = _fsname, .attrs = _attrname##_attrs \ 120 } 121 122 #define __ATTR_RW_INT_GROUP_ENUM(_attrname, _minv, _maxv, _wmi, _fsname,\ 123 _possible, _dispname) \ 124 __WMI_STORE_INT(_attrname##_current_value, _minv, _maxv, _wmi); \ 125 ASUS_WMI_SHOW_INT(_attrname##_current_value, _wmi); \ 126 static struct kobj_attribute attr_##_attrname##_current_value = \ 127 __ASUS_ATTR_RW(_attrname, current_value); \ 128 __ATTR_SHOW_FMT(display_name, _attrname, "%s\n", _dispname); \ 129 __ATTR_SHOW_FMT(possible_values, _attrname, "%s\n", _possible); \ 130 static struct kobj_attribute attr_##_attrname##_type = \ 131 __ASUS_ATTR_RO_AS(type, enum_type_show); \ 132 static struct attribute *_attrname##_attrs[] = { \ 133 &attr_##_attrname##_current_value.attr, \ 134 &attr_##_attrname##_display_name.attr, \ 135 &attr_##_attrname##_possible_values.attr, \ 136 &attr_##_attrname##_type.attr, \ 137 NULL \ 138 }; \ 139 static const struct attribute_group _attrname##_attr_group = { \ 140 .name = _fsname, .attrs = _attrname##_attrs \ 141 } 142 143 /* Boolean style enumeration, base macro. Requires adding show/store */ 144 #define __ATTR_GROUP_ENUM(_attrname, _fsname, _possible, _dispname) \ 145 __ATTR_SHOW_FMT(display_name, _attrname, "%s\n", _dispname); \ 146 __ATTR_SHOW_FMT(possible_values, _attrname, "%s\n", _possible); \ 147 static struct kobj_attribute attr_##_attrname##_type = \ 148 __ASUS_ATTR_RO_AS(type, enum_type_show); \ 149 static struct attribute *_attrname##_attrs[] = { \ 150 &attr_##_attrname##_current_value.attr, \ 151 &attr_##_attrname##_display_name.attr, \ 152 &attr_##_attrname##_possible_values.attr, \ 153 &attr_##_attrname##_type.attr, \ 154 NULL \ 155 }; \ 156 static const struct attribute_group _attrname##_attr_group = { \ 157 .name = _fsname, .attrs = _attrname##_attrs \ 158 } 159 160 #define ASUS_ATTR_GROUP_BOOL_RO(_attrname, _fsname, _wmi, _dispname) \ 161 __ATTR_RO_INT_GROUP_ENUM(_attrname, _wmi, _fsname, "0;1", _dispname) 162 163 164 #define ASUS_ATTR_GROUP_BOOL_RW(_attrname, _fsname, _wmi, _dispname) \ 165 __ATTR_RW_INT_GROUP_ENUM(_attrname, 0, 1, _wmi, _fsname, "0;1", _dispname) 166 167 #define ASUS_ATTR_GROUP_ENUM_INT_RO(_attrname, _fsname, _wmi, _possible, _dispname) \ 168 __ATTR_RO_INT_GROUP_ENUM(_attrname, _wmi, _fsname, _possible, _dispname) 169 170 /* 171 * Requires <name>_current_value_show(), <name>_current_value_show() 172 */ 173 #define ASUS_ATTR_GROUP_BOOL(_attrname, _fsname, _dispname) \ 174 static struct kobj_attribute attr_##_attrname##_current_value = \ 175 __ASUS_ATTR_RW(_attrname, current_value); \ 176 __ATTR_GROUP_ENUM(_attrname, _fsname, "0;1", _dispname) 177 178 /* 179 * Requires <name>_current_value_show(), <name>_current_value_show() 180 * and <name>_possible_values_show() 181 */ 182 #define ASUS_ATTR_GROUP_ENUM(_attrname, _fsname, _dispname) \ 183 __ATTR_SHOW_FMT(display_name, _attrname, "%s\n", _dispname); \ 184 static struct kobj_attribute attr_##_attrname##_current_value = \ 185 __ASUS_ATTR_RW(_attrname, current_value); \ 186 static struct kobj_attribute attr_##_attrname##_possible_values = \ 187 __ASUS_ATTR_RO(_attrname, possible_values); \ 188 static struct kobj_attribute attr_##_attrname##_type = \ 189 __ASUS_ATTR_RO_AS(type, enum_type_show); \ 190 static struct attribute *_attrname##_attrs[] = { \ 191 &attr_##_attrname##_current_value.attr, \ 192 &attr_##_attrname##_display_name.attr, \ 193 &attr_##_attrname##_possible_values.attr, \ 194 &attr_##_attrname##_type.attr, \ 195 NULL \ 196 }; \ 197 static const struct attribute_group _attrname##_attr_group = { \ 198 .name = _fsname, .attrs = _attrname##_attrs \ 199 } 200 201 #define ASUS_ATTR_GROUP_INT_VALUE_ONLY_RO(_attrname, _fsname, _wmi, _dispname) \ 202 ASUS_WMI_SHOW_INT(_attrname##_current_value, _wmi); \ 203 static struct kobj_attribute attr_##_attrname##_current_value = \ 204 __ASUS_ATTR_RO(_attrname, current_value); \ 205 __ATTR_SHOW_FMT(display_name, _attrname, "%s\n", _dispname); \ 206 static struct kobj_attribute attr_##_attrname##_type = \ 207 __ASUS_ATTR_RO_AS(type, int_type_show); \ 208 static struct attribute *_attrname##_attrs[] = { \ 209 &attr_##_attrname##_current_value.attr, \ 210 &attr_##_attrname##_display_name.attr, \ 211 &attr_##_attrname##_type.attr, NULL \ 212 }; \ 213 static const struct attribute_group _attrname##_attr_group = { \ 214 .name = _fsname, .attrs = _attrname##_attrs \ 215 } 216 217 /* 218 * ROG PPT attributes need a little different in setup as they 219 * require rog_tunables members. 220 */ 221 222 #define __ROG_TUNABLE_SHOW(_prop, _attrname, _val) \ 223 static ssize_t _attrname##_##_prop##_show( \ 224 struct kobject *kobj, struct kobj_attribute *attr, char *buf) \ 225 { \ 226 struct rog_tunables *tunables = get_current_tunables(); \ 227 \ 228 if (!tunables || !tunables->power_limits) \ 229 return -ENODEV; \ 230 \ 231 return sysfs_emit(buf, "%d\n", tunables->power_limits->_val); \ 232 } \ 233 static struct kobj_attribute attr_##_attrname##_##_prop = \ 234 __ASUS_ATTR_RO(_attrname, _prop) 235 236 #define __ROG_TUNABLE_SHOW_DEFAULT(_attrname) \ 237 static ssize_t _attrname##_default_value_show( \ 238 struct kobject *kobj, struct kobj_attribute *attr, char *buf) \ 239 { \ 240 struct rog_tunables *tunables = get_current_tunables(); \ 241 \ 242 if (!tunables || !tunables->power_limits) \ 243 return -ENODEV; \ 244 \ 245 return sysfs_emit( \ 246 buf, "%d\n", \ 247 tunables->power_limits->_attrname##_def ? \ 248 tunables->power_limits->_attrname##_def : \ 249 tunables->power_limits->_attrname##_max); \ 250 } \ 251 static struct kobj_attribute attr_##_attrname##_default_value = \ 252 __ASUS_ATTR_RO(_attrname, default_value) 253 254 #define __ROG_TUNABLE_RW(_attr, _wmi) \ 255 static ssize_t _attr##_current_value_store( \ 256 struct kobject *kobj, struct kobj_attribute *attr, \ 257 const char *buf, size_t count) \ 258 { \ 259 struct rog_tunables *tunables = get_current_tunables(); \ 260 \ 261 if (!tunables || !tunables->power_limits) \ 262 return -ENODEV; \ 263 \ 264 if (tunables->power_limits->_attr##_min == \ 265 tunables->power_limits->_attr##_max) \ 266 return -EINVAL; \ 267 \ 268 return armoury_attr_uint_store(kobj, attr, buf, count, \ 269 tunables->power_limits->_attr##_min, \ 270 tunables->power_limits->_attr##_max, \ 271 &tunables->_attr, _wmi); \ 272 } \ 273 static ssize_t _attr##_current_value_show( \ 274 struct kobject *kobj, struct kobj_attribute *attr, char *buf) \ 275 { \ 276 struct rog_tunables *tunables = get_current_tunables(); \ 277 \ 278 if (!tunables) \ 279 return -ENODEV; \ 280 \ 281 return sysfs_emit(buf, "%u\n", tunables->_attr); \ 282 } \ 283 static struct kobj_attribute attr_##_attr##_current_value = \ 284 __ASUS_ATTR_RW(_attr, current_value) 285 286 #define ASUS_ATTR_GROUP_ROG_TUNABLE(_attrname, _fsname, _wmi, _dispname) \ 287 __ROG_TUNABLE_RW(_attrname, _wmi); \ 288 __ROG_TUNABLE_SHOW_DEFAULT(_attrname); \ 289 __ROG_TUNABLE_SHOW(min_value, _attrname, _attrname##_min); \ 290 __ROG_TUNABLE_SHOW(max_value, _attrname, _attrname##_max); \ 291 __ATTR_SHOW_FMT(scalar_increment, _attrname, "%d\n", 1); \ 292 __ATTR_SHOW_FMT(display_name, _attrname, "%s\n", _dispname); \ 293 static struct kobj_attribute attr_##_attrname##_type = \ 294 __ASUS_ATTR_RO_AS(type, int_type_show); \ 295 static struct attribute *_attrname##_attrs[] = { \ 296 &attr_##_attrname##_current_value.attr, \ 297 &attr_##_attrname##_default_value.attr, \ 298 &attr_##_attrname##_min_value.attr, \ 299 &attr_##_attrname##_max_value.attr, \ 300 &attr_##_attrname##_scalar_increment.attr, \ 301 &attr_##_attrname##_display_name.attr, \ 302 &attr_##_attrname##_type.attr, \ 303 NULL \ 304 }; \ 305 static const struct attribute_group _attrname##_attr_group = { \ 306 .name = _fsname, .attrs = _attrname##_attrs \ 307 } 308 309 /* Default is always the maximum value unless *_def is specified */ 310 struct power_limits { 311 u8 ppt_pl1_spl_min; 312 u8 ppt_pl1_spl_def; 313 u8 ppt_pl1_spl_max; 314 u8 ppt_pl2_sppt_min; 315 u8 ppt_pl2_sppt_def; 316 u8 ppt_pl2_sppt_max; 317 u8 ppt_pl3_fppt_min; 318 u8 ppt_pl3_fppt_def; 319 u8 ppt_pl3_fppt_max; 320 u8 ppt_apu_sppt_min; 321 u8 ppt_apu_sppt_def; 322 u8 ppt_apu_sppt_max; 323 u8 ppt_platform_sppt_min; 324 u8 ppt_platform_sppt_def; 325 u8 ppt_platform_sppt_max; 326 /* Nvidia GPU specific, default is always max */ 327 u8 nv_dynamic_boost_def; // unused. exists for macro 328 u8 nv_dynamic_boost_min; 329 u8 nv_dynamic_boost_max; 330 u8 nv_temp_target_def; // unused. exists for macro 331 u8 nv_temp_target_min; 332 u8 nv_temp_target_max; 333 u8 nv_tgp_def; // unused. exists for macro 334 u8 nv_tgp_min; 335 u8 nv_tgp_max; 336 }; 337 338 struct power_data { 339 const struct power_limits *ac_data; 340 const struct power_limits *dc_data; 341 bool requires_fan_curve; 342 }; 343 344 /* 345 * For each available attribute there must be a min and a max. 346 * _def is not required and will be assumed to be default == max if missing. 347 */ 348 static const struct dmi_system_id power_limits[] = { 349 { 350 .matches = { 351 DMI_MATCH(DMI_BOARD_NAME, "FA401EA"), 352 }, 353 .driver_data = &(struct power_data) { 354 .ac_data = &(struct power_limits) { 355 .ppt_pl1_spl_min = 15, 356 .ppt_pl1_spl_max = 95, 357 .ppt_pl2_sppt_min = 35, 358 .ppt_pl2_sppt_max = 100, 359 .ppt_pl3_fppt_min = 35, 360 .ppt_pl3_fppt_max = 115, 361 }, 362 .dc_data = &(struct power_limits) { 363 .ppt_pl1_spl_min = 15, 364 .ppt_pl1_spl_max = 71, 365 .ppt_pl2_sppt_min = 35, 366 .ppt_pl2_sppt_max = 71, 367 .ppt_pl3_fppt_min = 35, 368 .ppt_pl3_fppt_max = 71, 369 }, 370 }, 371 }, 372 { 373 .matches = { 374 DMI_MATCH(DMI_BOARD_NAME, "FA401UM"), 375 }, 376 .driver_data = &(struct power_data) { 377 .ac_data = &(struct power_limits) { 378 .ppt_pl1_spl_min = 15, 379 .ppt_pl1_spl_max = 80, 380 .ppt_pl2_sppt_min = 35, 381 .ppt_pl2_sppt_max = 80, 382 .ppt_pl3_fppt_min = 35, 383 .ppt_pl3_fppt_max = 80, 384 .nv_dynamic_boost_min = 5, 385 .nv_dynamic_boost_max = 15, 386 .nv_temp_target_min = 75, 387 .nv_temp_target_max = 87, 388 }, 389 .dc_data = &(struct power_limits) { 390 .ppt_pl1_spl_min = 25, 391 .ppt_pl1_spl_max = 35, 392 .ppt_pl2_sppt_min = 31, 393 .ppt_pl2_sppt_max = 44, 394 .ppt_pl3_fppt_min = 45, 395 .ppt_pl3_fppt_max = 65, 396 .nv_temp_target_min = 75, 397 .nv_temp_target_max = 87, 398 }, 399 }, 400 }, 401 { 402 .matches = { 403 DMI_MATCH(DMI_BOARD_NAME, "FA401UV"), 404 }, 405 .driver_data = &(struct power_data) { 406 .ac_data = &(struct power_limits) { 407 .ppt_pl1_spl_min = 15, 408 .ppt_pl1_spl_max = 80, 409 .ppt_pl2_sppt_min = 35, 410 .ppt_pl2_sppt_max = 80, 411 .ppt_pl3_fppt_min = 35, 412 .ppt_pl3_fppt_max = 80, 413 .nv_dynamic_boost_min = 5, 414 .nv_dynamic_boost_max = 25, 415 .nv_temp_target_min = 75, 416 .nv_temp_target_max = 87, 417 .nv_tgp_min = 55, 418 .nv_tgp_max = 75, 419 }, 420 .dc_data = &(struct power_limits) { 421 .ppt_pl1_spl_min = 25, 422 .ppt_pl1_spl_max = 35, 423 .ppt_pl2_sppt_min = 31, 424 .ppt_pl2_sppt_max = 44, 425 .ppt_pl3_fppt_min = 45, 426 .ppt_pl3_fppt_max = 65, 427 .nv_temp_target_min = 75, 428 .nv_temp_target_max = 87, 429 }, 430 }, 431 }, 432 { 433 .matches = { 434 DMI_MATCH(DMI_BOARD_NAME, "FA401W"), 435 }, 436 .driver_data = &(struct power_data) { 437 .ac_data = &(struct power_limits) { 438 .ppt_pl1_spl_min = 15, 439 .ppt_pl1_spl_max = 80, 440 .ppt_pl2_sppt_min = 35, 441 .ppt_pl2_sppt_max = 80, 442 .ppt_pl3_fppt_min = 35, 443 .ppt_pl3_fppt_max = 80, 444 .nv_dynamic_boost_min = 5, 445 .nv_dynamic_boost_max = 25, 446 .nv_temp_target_min = 75, 447 .nv_temp_target_max = 87, 448 .nv_tgp_min = 55, 449 .nv_tgp_max = 75, 450 }, 451 .dc_data = &(struct power_limits) { 452 .ppt_pl1_spl_min = 25, 453 .ppt_pl1_spl_max = 30, 454 .ppt_pl2_sppt_min = 31, 455 .ppt_pl2_sppt_max = 44, 456 .ppt_pl3_fppt_min = 45, 457 .ppt_pl3_fppt_max = 65, 458 .nv_temp_target_min = 75, 459 .nv_temp_target_max = 87, 460 }, 461 }, 462 }, 463 { 464 .matches = { 465 DMI_MATCH(DMI_BOARD_NAME, "FA507N"), 466 }, 467 .driver_data = &(struct power_data) { 468 .ac_data = &(struct power_limits) { 469 .ppt_pl1_spl_min = 15, 470 .ppt_pl1_spl_max = 80, 471 .ppt_pl2_sppt_min = 35, 472 .ppt_pl2_sppt_max = 80, 473 .ppt_pl3_fppt_min = 35, 474 .ppt_pl3_fppt_max = 80, 475 .nv_dynamic_boost_min = 5, 476 .nv_dynamic_boost_max = 25, 477 .nv_temp_target_min = 75, 478 .nv_temp_target_max = 87, 479 }, 480 .dc_data = &(struct power_limits) { 481 .ppt_pl1_spl_min = 15, 482 .ppt_pl1_spl_def = 45, 483 .ppt_pl1_spl_max = 65, 484 .ppt_pl2_sppt_min = 35, 485 .ppt_pl2_sppt_def = 54, 486 .ppt_pl2_sppt_max = 65, 487 .ppt_pl3_fppt_min = 35, 488 .ppt_pl3_fppt_max = 65, 489 .nv_temp_target_min = 75, 490 .nv_temp_target_max = 87, 491 }, 492 }, 493 }, 494 { 495 .matches = { 496 DMI_MATCH(DMI_BOARD_NAME, "FA507UV"), 497 }, 498 .driver_data = &(struct power_data) { 499 .ac_data = &(struct power_limits) { 500 .ppt_pl1_spl_min = 15, 501 .ppt_pl1_spl_max = 80, 502 .ppt_pl2_sppt_min = 35, 503 .ppt_pl2_sppt_max = 80, 504 .ppt_pl3_fppt_min = 35, 505 .ppt_pl3_fppt_max = 80, 506 .nv_dynamic_boost_min = 5, 507 .nv_dynamic_boost_max = 25, 508 .nv_temp_target_min = 75, 509 .nv_temp_target_max = 87, 510 .nv_tgp_min = 55, 511 .nv_tgp_max = 115, 512 }, 513 .dc_data = &(struct power_limits) { 514 .ppt_pl1_spl_min = 15, 515 .ppt_pl1_spl_def = 45, 516 .ppt_pl1_spl_max = 65, 517 .ppt_pl2_sppt_min = 35, 518 .ppt_pl2_sppt_def = 54, 519 .ppt_pl2_sppt_max = 65, 520 .ppt_pl3_fppt_min = 35, 521 .ppt_pl3_fppt_max = 65, 522 .nv_temp_target_min = 75, 523 .nv_temp_target_max = 87, 524 }, 525 }, 526 }, 527 { 528 .matches = { 529 DMI_MATCH(DMI_BOARD_NAME, "FA507R"), 530 }, 531 .driver_data = &(struct power_data) { 532 .ac_data = &(struct power_limits) { 533 .ppt_pl1_spl_min = 15, 534 .ppt_pl1_spl_max = 80, 535 .ppt_pl2_sppt_min = 35, 536 .ppt_pl2_sppt_max = 80, 537 .ppt_pl3_fppt_min = 35, 538 .ppt_pl3_fppt_max = 80, 539 .nv_dynamic_boost_min = 5, 540 .nv_dynamic_boost_max = 25, 541 .nv_temp_target_min = 75, 542 .nv_temp_target_max = 87, 543 }, 544 .dc_data = &(struct power_limits) { 545 .ppt_pl1_spl_min = 15, 546 .ppt_pl1_spl_def = 45, 547 .ppt_pl1_spl_max = 65, 548 .ppt_pl2_sppt_min = 35, 549 .ppt_pl2_sppt_def = 54, 550 .ppt_pl2_sppt_max = 65, 551 .ppt_pl3_fppt_min = 35, 552 .ppt_pl3_fppt_max = 65, 553 .nv_temp_target_min = 75, 554 .nv_temp_target_max = 87, 555 }, 556 }, 557 }, 558 { 559 .matches = { 560 DMI_MATCH(DMI_BOARD_NAME, "FA507X"), 561 }, 562 .driver_data = &(struct power_data) { 563 .ac_data = &(struct power_limits) { 564 .ppt_pl1_spl_min = 15, 565 .ppt_pl1_spl_max = 80, 566 .ppt_pl2_sppt_min = 35, 567 .ppt_pl2_sppt_max = 80, 568 .ppt_pl3_fppt_min = 35, 569 .ppt_pl3_fppt_max = 80, 570 .nv_dynamic_boost_min = 5, 571 .nv_dynamic_boost_max = 20, 572 .nv_temp_target_min = 75, 573 .nv_temp_target_max = 87, 574 .nv_tgp_min = 55, 575 .nv_tgp_max = 85, 576 }, 577 .dc_data = &(struct power_limits) { 578 .ppt_pl1_spl_min = 15, 579 .ppt_pl1_spl_def = 45, 580 .ppt_pl1_spl_max = 65, 581 .ppt_pl2_sppt_min = 35, 582 .ppt_pl2_sppt_def = 54, 583 .ppt_pl2_sppt_max = 65, 584 .ppt_pl3_fppt_min = 35, 585 .ppt_pl3_fppt_max = 65, 586 .nv_temp_target_min = 75, 587 .nv_temp_target_max = 87, 588 }, 589 }, 590 }, 591 { 592 .matches = { 593 DMI_MATCH(DMI_BOARD_NAME, "FA507Z"), 594 }, 595 .driver_data = &(struct power_data) { 596 .ac_data = &(struct power_limits) { 597 .ppt_pl1_spl_min = 28, 598 .ppt_pl1_spl_max = 65, 599 .ppt_pl2_sppt_min = 28, 600 .ppt_pl2_sppt_max = 105, 601 .nv_dynamic_boost_min = 5, 602 .nv_dynamic_boost_max = 15, 603 .nv_temp_target_min = 75, 604 .nv_temp_target_max = 87, 605 .nv_tgp_min = 55, 606 .nv_tgp_max = 85, 607 }, 608 .dc_data = &(struct power_limits) { 609 .ppt_pl1_spl_min = 25, 610 .ppt_pl1_spl_max = 45, 611 .ppt_pl2_sppt_min = 35, 612 .ppt_pl2_sppt_max = 60, 613 .nv_temp_target_min = 75, 614 .nv_temp_target_max = 87, 615 }, 616 }, 617 }, 618 { 619 .matches = { 620 DMI_MATCH(DMI_BOARD_NAME, "FA607NU"), 621 }, 622 .driver_data = &(struct power_data) { 623 .ac_data = &(struct power_limits) { 624 .ppt_pl1_spl_min = 15, 625 .ppt_pl1_spl_max = 80, 626 .ppt_pl2_sppt_min = 35, 627 .ppt_pl2_sppt_max = 80, 628 .ppt_pl3_fppt_min = 35, 629 .ppt_pl3_fppt_max = 80, 630 .nv_dynamic_boost_min = 5, 631 .nv_dynamic_boost_max = 25, 632 .nv_temp_target_min = 75, 633 .nv_temp_target_max = 87, 634 }, 635 .dc_data = &(struct power_limits) { 636 .ppt_pl1_spl_min = 25, 637 .ppt_pl1_spl_def = 45, 638 .ppt_pl1_spl_max = 65, 639 .ppt_pl2_sppt_min = 25, 640 .ppt_pl2_sppt_def = 54, 641 .ppt_pl2_sppt_max = 65, 642 .ppt_pl3_fppt_min = 25, 643 .ppt_pl3_fppt_max = 65, 644 .nv_temp_target_min = 75, 645 .nv_temp_target_max = 87, 646 }, 647 }, 648 }, 649 { 650 .matches = { 651 DMI_MATCH(DMI_BOARD_NAME, "FA607P"), 652 }, 653 .driver_data = &(struct power_data) { 654 .ac_data = &(struct power_limits) { 655 .ppt_pl1_spl_min = 30, 656 .ppt_pl1_spl_def = 100, 657 .ppt_pl1_spl_max = 135, 658 .ppt_pl2_sppt_min = 30, 659 .ppt_pl2_sppt_def = 115, 660 .ppt_pl2_sppt_max = 135, 661 .ppt_pl3_fppt_min = 30, 662 .ppt_pl3_fppt_max = 135, 663 .nv_dynamic_boost_min = 5, 664 .nv_dynamic_boost_max = 25, 665 .nv_temp_target_min = 75, 666 .nv_temp_target_max = 87, 667 .nv_tgp_min = 55, 668 .nv_tgp_max = 115, 669 }, 670 .dc_data = &(struct power_limits) { 671 .ppt_pl1_spl_min = 25, 672 .ppt_pl1_spl_def = 45, 673 .ppt_pl1_spl_max = 80, 674 .ppt_pl2_sppt_min = 25, 675 .ppt_pl2_sppt_def = 60, 676 .ppt_pl2_sppt_max = 80, 677 .ppt_pl3_fppt_min = 25, 678 .ppt_pl3_fppt_max = 80, 679 .nv_temp_target_min = 75, 680 .nv_temp_target_max = 87, 681 }, 682 }, 683 }, 684 { 685 .matches = { 686 DMI_MATCH(DMI_BOARD_NAME, "FA608UM"), 687 }, 688 .driver_data = &(struct power_data) { 689 .ac_data = &(struct power_limits) { 690 .ppt_pl1_spl_min = 15, 691 .ppt_pl1_spl_def = 45, 692 .ppt_pl1_spl_max = 90, 693 .ppt_pl2_sppt_min = 35, 694 .ppt_pl2_sppt_def = 54, 695 .ppt_pl2_sppt_max = 90, 696 .ppt_pl3_fppt_min = 35, 697 .ppt_pl3_fppt_def = 65, 698 .ppt_pl3_fppt_max = 90, 699 .nv_dynamic_boost_min = 10, 700 .nv_dynamic_boost_max = 15, 701 .nv_temp_target_min = 75, 702 .nv_temp_target_max = 87, 703 .nv_tgp_min = 55, 704 .nv_tgp_max = 100, 705 }, 706 .dc_data = &(struct power_limits) { 707 .ppt_pl1_spl_min = 15, 708 .ppt_pl1_spl_def = 45, 709 .ppt_pl1_spl_max = 65, 710 .ppt_pl2_sppt_min = 35, 711 .ppt_pl2_sppt_def = 54, 712 .ppt_pl2_sppt_max = 65, 713 .ppt_pl3_fppt_min = 35, 714 .ppt_pl3_fppt_max = 65, 715 .nv_temp_target_min = 75, 716 .nv_temp_target_max = 87, 717 }, 718 }, 719 }, 720 { 721 .matches = { 722 DMI_MATCH(DMI_BOARD_NAME, "FA608WI"), 723 }, 724 .driver_data = &(struct power_data) { 725 .ac_data = &(struct power_limits) { 726 .ppt_pl1_spl_min = 15, 727 .ppt_pl1_spl_def = 90, 728 .ppt_pl1_spl_max = 90, 729 .ppt_pl2_sppt_min = 35, 730 .ppt_pl2_sppt_def = 90, 731 .ppt_pl2_sppt_max = 90, 732 .ppt_pl3_fppt_min = 35, 733 .ppt_pl3_fppt_def = 90, 734 .ppt_pl3_fppt_max = 90, 735 .nv_dynamic_boost_min = 5, 736 .nv_dynamic_boost_max = 25, 737 .nv_temp_target_min = 75, 738 .nv_temp_target_max = 87, 739 .nv_tgp_min = 55, 740 .nv_tgp_max = 115, 741 }, 742 .dc_data = &(struct power_limits) { 743 .ppt_pl1_spl_min = 15, 744 .ppt_pl1_spl_def = 45, 745 .ppt_pl1_spl_max = 65, 746 .ppt_pl2_sppt_min = 35, 747 .ppt_pl2_sppt_def = 54, 748 .ppt_pl2_sppt_max = 65, 749 .ppt_pl3_fppt_min = 35, 750 .ppt_pl3_fppt_def = 65, 751 .ppt_pl3_fppt_max = 65, 752 .nv_temp_target_min = 75, 753 .nv_temp_target_max = 87, 754 }, 755 }, 756 }, 757 { 758 .matches = { 759 DMI_MATCH(DMI_BOARD_NAME, "FA617NS"), 760 }, 761 .driver_data = &(struct power_data) { 762 .ac_data = &(struct power_limits) { 763 .ppt_apu_sppt_min = 15, 764 .ppt_apu_sppt_max = 80, 765 .ppt_platform_sppt_min = 30, 766 .ppt_platform_sppt_max = 120, 767 }, 768 .dc_data = &(struct power_limits) { 769 .ppt_apu_sppt_min = 25, 770 .ppt_apu_sppt_max = 35, 771 .ppt_platform_sppt_min = 45, 772 .ppt_platform_sppt_max = 100, 773 }, 774 }, 775 }, 776 { 777 .matches = { 778 DMI_MATCH(DMI_BOARD_NAME, "FA617NT"), 779 }, 780 .driver_data = &(struct power_data) { 781 .ac_data = &(struct power_limits) { 782 .ppt_apu_sppt_min = 15, 783 .ppt_apu_sppt_max = 80, 784 .ppt_platform_sppt_min = 30, 785 .ppt_platform_sppt_max = 115, 786 }, 787 .dc_data = &(struct power_limits) { 788 .ppt_apu_sppt_min = 15, 789 .ppt_apu_sppt_max = 45, 790 .ppt_platform_sppt_min = 30, 791 .ppt_platform_sppt_max = 50, 792 }, 793 }, 794 }, 795 { 796 .matches = { 797 DMI_MATCH(DMI_BOARD_NAME, "FA617XS"), 798 }, 799 .driver_data = &(struct power_data) { 800 .ac_data = &(struct power_limits) { 801 .ppt_apu_sppt_min = 15, 802 .ppt_apu_sppt_max = 80, 803 .ppt_platform_sppt_min = 30, 804 .ppt_platform_sppt_max = 120, 805 .nv_temp_target_min = 75, 806 .nv_temp_target_max = 87, 807 }, 808 .dc_data = &(struct power_limits) { 809 .ppt_apu_sppt_min = 25, 810 .ppt_apu_sppt_max = 35, 811 .ppt_platform_sppt_min = 45, 812 .ppt_platform_sppt_max = 100, 813 .nv_temp_target_min = 75, 814 .nv_temp_target_max = 87, 815 }, 816 }, 817 }, 818 { 819 .matches = { 820 DMI_MATCH(DMI_BOARD_NAME, "FA617XT"), 821 }, 822 .driver_data = &(struct power_data) { 823 .ac_data = &(struct power_limits) { 824 .ppt_apu_sppt_min = 15, 825 .ppt_apu_sppt_max = 80, 826 .ppt_platform_sppt_min = 30, 827 .ppt_platform_sppt_max = 145, 828 }, 829 .dc_data = &(struct power_limits) { 830 .ppt_apu_sppt_min = 25, 831 .ppt_apu_sppt_max = 35, 832 .ppt_platform_sppt_min = 45, 833 .ppt_platform_sppt_max = 100, 834 }, 835 }, 836 }, 837 { 838 .matches = { 839 DMI_MATCH(DMI_BOARD_NAME, "FX507VI"), 840 }, 841 .driver_data = &(struct power_data) { 842 .ac_data = &(struct power_limits) { 843 .ppt_pl1_spl_min = 28, 844 .ppt_pl1_spl_max = 135, 845 .ppt_pl2_sppt_min = 28, 846 .ppt_pl2_sppt_max = 135, 847 .nv_dynamic_boost_min = 5, 848 .nv_dynamic_boost_max = 25, 849 .nv_temp_target_min = 75, 850 .nv_temp_target_max = 87, 851 }, 852 .dc_data = &(struct power_limits) { 853 .ppt_pl1_spl_min = 25, 854 .ppt_pl1_spl_max = 45, 855 .ppt_pl2_sppt_min = 35, 856 .ppt_pl2_sppt_max = 60, 857 .nv_temp_target_min = 75, 858 .nv_temp_target_max = 87, 859 }, 860 .requires_fan_curve = true, 861 }, 862 }, 863 { 864 .matches = { 865 DMI_MATCH(DMI_BOARD_NAME, "FX507VV"), 866 }, 867 .driver_data = &(struct power_data) { 868 .ac_data = &(struct power_limits) { 869 .ppt_pl1_spl_min = 28, 870 .ppt_pl1_spl_def = 115, 871 .ppt_pl1_spl_max = 135, 872 .ppt_pl2_sppt_min = 28, 873 .ppt_pl2_sppt_max = 135, 874 .nv_dynamic_boost_min = 5, 875 .nv_dynamic_boost_max = 25, 876 .nv_temp_target_min = 75, 877 .nv_temp_target_max = 87, 878 }, 879 .dc_data = &(struct power_limits) { 880 .ppt_pl1_spl_min = 25, 881 .ppt_pl1_spl_max = 45, 882 .ppt_pl2_sppt_min = 35, 883 .ppt_pl2_sppt_max = 60, 884 .nv_temp_target_min = 75, 885 .nv_temp_target_max = 87, 886 }, 887 .requires_fan_curve = true, 888 }, 889 }, 890 { 891 .matches = { 892 DMI_MATCH(DMI_BOARD_NAME, "FX507Z"), 893 }, 894 .driver_data = &(struct power_data) { 895 .ac_data = &(struct power_limits) { 896 .ppt_pl1_spl_min = 28, 897 .ppt_pl1_spl_max = 90, 898 .ppt_pl2_sppt_min = 28, 899 .ppt_pl2_sppt_max = 135, 900 .nv_dynamic_boost_min = 5, 901 .nv_dynamic_boost_max = 15, 902 }, 903 .dc_data = &(struct power_limits) { 904 .ppt_pl1_spl_min = 25, 905 .ppt_pl1_spl_max = 45, 906 .ppt_pl2_sppt_min = 35, 907 .ppt_pl2_sppt_max = 60, 908 }, 909 .requires_fan_curve = true, 910 }, 911 }, 912 { 913 .matches = { 914 DMI_MATCH(DMI_BOARD_NAME, "FX607VU"), 915 }, 916 .driver_data = &(struct power_data) { 917 .ac_data = &(struct power_limits) { 918 .ppt_pl1_spl_min = 28, 919 .ppt_pl1_spl_def = 115, 920 .ppt_pl1_spl_max = 135, 921 .ppt_pl2_sppt_min = 28, 922 .ppt_pl2_sppt_max = 135, 923 .nv_dynamic_boost_min = 5, 924 .nv_dynamic_boost_max = 25, 925 .nv_temp_target_min = 75, 926 .nv_temp_target_max = 87, 927 }, 928 .dc_data = &(struct power_limits) { 929 .ppt_pl1_spl_min = 25, 930 .ppt_pl1_spl_max = 45, 931 .ppt_pl2_sppt_min = 35, 932 .ppt_pl2_sppt_max = 60, 933 .nv_temp_target_min = 75, 934 .nv_temp_target_max = 87, 935 }, 936 .requires_fan_curve = true, 937 }, 938 }, 939 { 940 .matches = { 941 DMI_MATCH(DMI_BOARD_NAME, "GA401Q"), 942 }, 943 .driver_data = &(struct power_data) { 944 .ac_data = &(struct power_limits) { 945 .ppt_pl1_spl_min = 15, 946 .ppt_pl1_spl_max = 80, 947 .ppt_pl2_sppt_min = 15, 948 .ppt_pl2_sppt_max = 80, 949 }, 950 .dc_data = NULL, 951 }, 952 }, 953 { 954 .matches = { 955 // This model is full AMD. No Nvidia dGPU. 956 DMI_MATCH(DMI_BOARD_NAME, "GA402R"), 957 }, 958 .driver_data = &(struct power_data) { 959 .ac_data = &(struct power_limits) { 960 .ppt_apu_sppt_min = 15, 961 .ppt_apu_sppt_max = 80, 962 .ppt_platform_sppt_min = 30, 963 .ppt_platform_sppt_max = 115, 964 }, 965 .dc_data = &(struct power_limits) { 966 .ppt_apu_sppt_min = 25, 967 .ppt_apu_sppt_def = 30, 968 .ppt_apu_sppt_max = 45, 969 .ppt_platform_sppt_min = 40, 970 .ppt_platform_sppt_max = 60, 971 }, 972 }, 973 }, 974 { 975 .matches = { 976 DMI_MATCH(DMI_BOARD_NAME, "GA402X"), 977 }, 978 .driver_data = &(struct power_data) { 979 .ac_data = &(struct power_limits) { 980 .ppt_pl1_spl_min = 15, 981 .ppt_pl1_spl_def = 35, 982 .ppt_pl1_spl_max = 80, 983 .ppt_pl2_sppt_min = 25, 984 .ppt_pl2_sppt_def = 65, 985 .ppt_pl2_sppt_max = 80, 986 .ppt_pl3_fppt_min = 35, 987 .ppt_pl3_fppt_max = 80, 988 .nv_temp_target_min = 75, 989 .nv_temp_target_max = 87, 990 }, 991 .dc_data = &(struct power_limits) { 992 .ppt_pl1_spl_min = 15, 993 .ppt_pl1_spl_max = 35, 994 .ppt_pl2_sppt_min = 25, 995 .ppt_pl2_sppt_max = 35, 996 .ppt_pl3_fppt_min = 35, 997 .ppt_pl3_fppt_max = 65, 998 .nv_temp_target_min = 75, 999 .nv_temp_target_max = 87, 1000 }, 1001 .requires_fan_curve = true, 1002 }, 1003 }, 1004 { 1005 .matches = { 1006 DMI_MATCH(DMI_BOARD_NAME, "GA403UI"), 1007 }, 1008 .driver_data = &(struct power_data) { 1009 .ac_data = &(struct power_limits) { 1010 .ppt_pl1_spl_min = 15, 1011 .ppt_pl1_spl_max = 80, 1012 .ppt_pl2_sppt_min = 25, 1013 .ppt_pl2_sppt_max = 80, 1014 .ppt_pl3_fppt_min = 35, 1015 .ppt_pl3_fppt_max = 80, 1016 .nv_dynamic_boost_min = 5, 1017 .nv_dynamic_boost_max = 25, 1018 .nv_temp_target_min = 75, 1019 .nv_temp_target_max = 87, 1020 .nv_tgp_min = 55, 1021 .nv_tgp_max = 65, 1022 }, 1023 .dc_data = &(struct power_limits) { 1024 .ppt_pl1_spl_min = 15, 1025 .ppt_pl1_spl_max = 35, 1026 .ppt_pl2_sppt_min = 25, 1027 .ppt_pl2_sppt_max = 35, 1028 .ppt_pl3_fppt_min = 35, 1029 .ppt_pl3_fppt_max = 65, 1030 .nv_temp_target_min = 75, 1031 .nv_temp_target_max = 87, 1032 }, 1033 .requires_fan_curve = true, 1034 }, 1035 }, 1036 { 1037 .matches = { 1038 DMI_MATCH(DMI_BOARD_NAME, "GA403UV"), 1039 }, 1040 .driver_data = &(struct power_data) { 1041 .ac_data = &(struct power_limits) { 1042 .ppt_pl1_spl_min = 15, 1043 .ppt_pl1_spl_max = 80, 1044 .ppt_pl2_sppt_min = 25, 1045 .ppt_pl2_sppt_max = 80, 1046 .ppt_pl3_fppt_min = 35, 1047 .ppt_pl3_fppt_max = 80, 1048 .nv_dynamic_boost_min = 5, 1049 .nv_dynamic_boost_max = 25, 1050 .nv_temp_target_min = 75, 1051 .nv_temp_target_max = 87, 1052 .nv_tgp_min = 55, 1053 .nv_tgp_max = 65, 1054 }, 1055 .dc_data = &(struct power_limits) { 1056 .ppt_pl1_spl_min = 15, 1057 .ppt_pl1_spl_max = 35, 1058 .ppt_pl2_sppt_min = 25, 1059 .ppt_pl2_sppt_max = 35, 1060 .ppt_pl3_fppt_min = 35, 1061 .ppt_pl3_fppt_max = 65, 1062 .nv_temp_target_min = 75, 1063 .nv_temp_target_max = 87, 1064 }, 1065 .requires_fan_curve = true, 1066 }, 1067 }, 1068 { 1069 .matches = { 1070 DMI_MATCH(DMI_BOARD_NAME, "GA403WM"), 1071 }, 1072 .driver_data = &(struct power_data) { 1073 .ac_data = &(struct power_limits) { 1074 .ppt_pl1_spl_min = 15, 1075 .ppt_pl1_spl_max = 80, 1076 .ppt_pl2_sppt_min = 25, 1077 .ppt_pl2_sppt_max = 80, 1078 .ppt_pl3_fppt_min = 35, 1079 .ppt_pl3_fppt_max = 80, 1080 .nv_dynamic_boost_min = 0, 1081 .nv_dynamic_boost_max = 15, 1082 .nv_temp_target_min = 75, 1083 .nv_temp_target_max = 87, 1084 .nv_tgp_min = 55, 1085 .nv_tgp_max = 85, 1086 }, 1087 .dc_data = &(struct power_limits) { 1088 .ppt_pl1_spl_min = 15, 1089 .ppt_pl1_spl_max = 35, 1090 .ppt_pl2_sppt_min = 25, 1091 .ppt_pl2_sppt_max = 35, 1092 .ppt_pl3_fppt_min = 35, 1093 .ppt_pl3_fppt_max = 65, 1094 .nv_temp_target_min = 75, 1095 .nv_temp_target_max = 87, 1096 }, 1097 .requires_fan_curve = true, 1098 }, 1099 }, 1100 { 1101 .matches = { 1102 DMI_MATCH(DMI_BOARD_NAME, "GA403WR"), 1103 }, 1104 .driver_data = &(struct power_data) { 1105 .ac_data = &(struct power_limits) { 1106 .ppt_pl1_spl_min = 15, 1107 .ppt_pl1_spl_max = 80, 1108 .ppt_pl2_sppt_min = 25, 1109 .ppt_pl2_sppt_max = 80, 1110 .ppt_pl3_fppt_min = 35, 1111 .ppt_pl3_fppt_max = 80, 1112 .nv_dynamic_boost_min = 0, 1113 .nv_dynamic_boost_max = 25, 1114 .nv_temp_target_min = 75, 1115 .nv_temp_target_max = 87, 1116 .nv_tgp_min = 80, 1117 .nv_tgp_max = 95, 1118 }, 1119 .dc_data = &(struct power_limits) { 1120 .ppt_pl1_spl_min = 15, 1121 .ppt_pl1_spl_max = 35, 1122 .ppt_pl2_sppt_min = 25, 1123 .ppt_pl2_sppt_max = 35, 1124 .ppt_pl3_fppt_min = 35, 1125 .ppt_pl3_fppt_max = 65, 1126 .nv_temp_target_min = 75, 1127 .nv_temp_target_max = 87, 1128 }, 1129 .requires_fan_curve = true, 1130 }, 1131 }, 1132 { 1133 .matches = { 1134 DMI_MATCH(DMI_BOARD_NAME, "GA403WW"), 1135 }, 1136 .driver_data = &(struct power_data) { 1137 .ac_data = &(struct power_limits) { 1138 .ppt_pl1_spl_min = 15, 1139 .ppt_pl1_spl_max = 80, 1140 .ppt_pl2_sppt_min = 25, 1141 .ppt_pl2_sppt_max = 80, 1142 .ppt_pl3_fppt_min = 35, 1143 .ppt_pl3_fppt_max = 80, 1144 .nv_dynamic_boost_min = 0, 1145 .nv_dynamic_boost_max = 25, 1146 .nv_temp_target_min = 75, 1147 .nv_temp_target_max = 87, 1148 .nv_tgp_min = 80, 1149 .nv_tgp_max = 95, 1150 }, 1151 .dc_data = &(struct power_limits) { 1152 .ppt_pl1_spl_min = 15, 1153 .ppt_pl1_spl_max = 35, 1154 .ppt_pl2_sppt_min = 25, 1155 .ppt_pl2_sppt_max = 35, 1156 .ppt_pl3_fppt_min = 35, 1157 .ppt_pl3_fppt_max = 65, 1158 .nv_temp_target_min = 75, 1159 .nv_temp_target_max = 87, 1160 }, 1161 .requires_fan_curve = true, 1162 }, 1163 }, 1164 { 1165 .matches = { 1166 DMI_MATCH(DMI_BOARD_NAME, "GA503QM"), 1167 }, 1168 .driver_data = &(struct power_data) { 1169 .ac_data = &(struct power_limits) { 1170 .ppt_pl1_spl_min = 15, 1171 .ppt_pl1_spl_def = 35, 1172 .ppt_pl1_spl_max = 80, 1173 .ppt_pl2_sppt_min = 65, 1174 .ppt_pl2_sppt_max = 80, 1175 }, 1176 }, 1177 }, 1178 { 1179 .matches = { 1180 DMI_MATCH(DMI_BOARD_NAME, "GA503QR"), 1181 }, 1182 .driver_data = &(struct power_data) { 1183 .ac_data = &(struct power_limits) { 1184 .ppt_pl1_spl_min = 15, 1185 .ppt_pl1_spl_def = 35, 1186 .ppt_pl1_spl_max = 80, 1187 .ppt_pl2_sppt_min = 65, 1188 .ppt_pl2_sppt_max = 80, 1189 }, 1190 }, 1191 }, 1192 { 1193 .matches = { 1194 DMI_MATCH(DMI_BOARD_NAME, "GA503R"), 1195 }, 1196 .driver_data = &(struct power_data) { 1197 .ac_data = &(struct power_limits) { 1198 .ppt_pl1_spl_min = 15, 1199 .ppt_pl1_spl_def = 35, 1200 .ppt_pl1_spl_max = 80, 1201 .ppt_pl2_sppt_min = 35, 1202 .ppt_pl2_sppt_def = 65, 1203 .ppt_pl2_sppt_max = 80, 1204 .ppt_pl3_fppt_min = 35, 1205 .ppt_pl3_fppt_max = 80, 1206 .nv_dynamic_boost_min = 5, 1207 .nv_dynamic_boost_max = 20, 1208 .nv_temp_target_min = 75, 1209 .nv_temp_target_max = 87, 1210 }, 1211 .dc_data = &(struct power_limits) { 1212 .ppt_pl1_spl_min = 15, 1213 .ppt_pl1_spl_def = 25, 1214 .ppt_pl1_spl_max = 65, 1215 .ppt_pl2_sppt_min = 35, 1216 .ppt_pl2_sppt_def = 54, 1217 .ppt_pl2_sppt_max = 60, 1218 .ppt_pl3_fppt_min = 35, 1219 .ppt_pl3_fppt_max = 65, 1220 }, 1221 }, 1222 }, 1223 { 1224 .matches = { 1225 DMI_MATCH(DMI_BOARD_NAME, "GA605W"), 1226 }, 1227 .driver_data = &(struct power_data) { 1228 .ac_data = &(struct power_limits) { 1229 .ppt_pl1_spl_min = 15, 1230 .ppt_pl1_spl_max = 80, 1231 .ppt_pl2_sppt_min = 35, 1232 .ppt_pl2_sppt_max = 80, 1233 .ppt_pl3_fppt_min = 35, 1234 .ppt_pl3_fppt_max = 80, 1235 .nv_dynamic_boost_min = 5, 1236 .nv_dynamic_boost_max = 20, 1237 .nv_temp_target_min = 75, 1238 .nv_temp_target_max = 87, 1239 .nv_tgp_min = 55, 1240 .nv_tgp_max = 85, 1241 }, 1242 .dc_data = &(struct power_limits) { 1243 .ppt_pl1_spl_min = 25, 1244 .ppt_pl1_spl_max = 35, 1245 .ppt_pl2_sppt_min = 31, 1246 .ppt_pl2_sppt_max = 44, 1247 .ppt_pl3_fppt_min = 45, 1248 .ppt_pl3_fppt_max = 65, 1249 .nv_temp_target_min = 75, 1250 .nv_temp_target_max = 87, 1251 }, 1252 .requires_fan_curve = true, 1253 }, 1254 }, 1255 { 1256 .matches = { 1257 DMI_MATCH(DMI_BOARD_NAME, "GU603Z"), 1258 }, 1259 .driver_data = &(struct power_data) { 1260 .ac_data = &(struct power_limits) { 1261 .ppt_pl1_spl_min = 25, 1262 .ppt_pl1_spl_max = 60, 1263 .ppt_pl2_sppt_min = 25, 1264 .ppt_pl2_sppt_max = 135, 1265 .nv_dynamic_boost_min = 5, 1266 .nv_dynamic_boost_max = 20, 1267 .nv_temp_target_min = 75, 1268 .nv_temp_target_max = 87, 1269 }, 1270 .dc_data = &(struct power_limits) { 1271 .ppt_pl1_spl_min = 25, 1272 .ppt_pl1_spl_max = 40, 1273 .ppt_pl2_sppt_min = 25, 1274 .ppt_pl2_sppt_max = 40, 1275 .nv_temp_target_min = 75, 1276 .nv_temp_target_max = 87, 1277 } 1278 }, 1279 }, 1280 { 1281 .matches = { 1282 DMI_MATCH(DMI_BOARD_NAME, "GU604V"), 1283 }, 1284 .driver_data = &(struct power_data) { 1285 .ac_data = &(struct power_limits) { 1286 .ppt_pl1_spl_min = 65, 1287 .ppt_pl1_spl_max = 120, 1288 .ppt_pl2_sppt_min = 65, 1289 .ppt_pl2_sppt_max = 150, 1290 .nv_dynamic_boost_min = 5, 1291 .nv_dynamic_boost_max = 25, 1292 .nv_temp_target_min = 75, 1293 .nv_temp_target_max = 87, 1294 }, 1295 .dc_data = &(struct power_limits) { 1296 .ppt_pl1_spl_min = 25, 1297 .ppt_pl1_spl_max = 40, 1298 .ppt_pl2_sppt_min = 35, 1299 .ppt_pl2_sppt_def = 40, 1300 .ppt_pl2_sppt_max = 60, 1301 .nv_temp_target_min = 75, 1302 .nv_temp_target_max = 87, 1303 }, 1304 }, 1305 }, 1306 { 1307 .matches = { 1308 DMI_MATCH(DMI_BOARD_NAME, "GU605CP"), 1309 }, 1310 .driver_data = &(struct power_data) { 1311 .ac_data = &(struct power_limits) { 1312 .ppt_pl1_spl_min = 45, 1313 .ppt_pl1_spl_max = 75, 1314 .ppt_pl2_sppt_min = 56, 1315 .ppt_pl2_sppt_max = 95, 1316 .nv_dynamic_boost_min = 5, 1317 .nv_dynamic_boost_max = 15, 1318 .nv_temp_target_min = 75, 1319 .nv_temp_target_max = 87, 1320 .nv_tgp_min = 55, 1321 .nv_tgp_def = 75, 1322 .nv_tgp_max = 95, 1323 }, 1324 .dc_data = &(struct power_limits) { 1325 .ppt_pl1_spl_min = 25, 1326 .ppt_pl1_spl_max = 75, 1327 .ppt_pl2_sppt_min = 32, 1328 .ppt_pl2_sppt_max = 95, 1329 .nv_temp_target_min = 75, 1330 .nv_temp_target_max = 87, 1331 }, 1332 .requires_fan_curve = true, 1333 }, 1334 }, 1335 { 1336 .matches = { 1337 DMI_MATCH(DMI_BOARD_NAME, "GU605CR"), 1338 }, 1339 .driver_data = &(struct power_data) { 1340 .ac_data = &(struct power_limits) { 1341 .ppt_pl1_spl_min = 30, 1342 .ppt_pl1_spl_max = 85, 1343 .ppt_pl2_sppt_min = 38, 1344 .ppt_pl2_sppt_max = 110, 1345 .nv_dynamic_boost_min = 5, 1346 .nv_dynamic_boost_max = 20, 1347 .nv_temp_target_min = 75, 1348 .nv_temp_target_max = 87, 1349 .nv_tgp_min = 80, 1350 .nv_tgp_def = 90, 1351 .nv_tgp_max = 105, 1352 }, 1353 .dc_data = &(struct power_limits) { 1354 .ppt_pl1_spl_min = 30, 1355 .ppt_pl1_spl_max = 85, 1356 .ppt_pl2_sppt_min = 38, 1357 .ppt_pl2_sppt_max = 110, 1358 .nv_temp_target_min = 75, 1359 .nv_temp_target_max = 87, 1360 }, 1361 .requires_fan_curve = true, 1362 }, 1363 }, 1364 { 1365 .matches = { 1366 DMI_MATCH(DMI_BOARD_NAME, "GU605CW"), 1367 }, 1368 .driver_data = &(struct power_data) { 1369 .ac_data = &(struct power_limits) { 1370 .ppt_pl1_spl_min = 45, 1371 .ppt_pl1_spl_max = 85, 1372 .ppt_pl2_sppt_min = 56, 1373 .ppt_pl2_sppt_max = 110, 1374 .nv_dynamic_boost_min = 5, 1375 .nv_dynamic_boost_max = 20, 1376 .nv_temp_target_min = 75, 1377 .nv_temp_target_max = 87, 1378 .nv_tgp_min = 80, 1379 .nv_tgp_def = 90, 1380 .nv_tgp_max = 110, 1381 }, 1382 .dc_data = &(struct power_limits) { 1383 .ppt_pl1_spl_min = 25, 1384 .ppt_pl1_spl_max = 85, 1385 .ppt_pl2_sppt_min = 32, 1386 .ppt_pl2_sppt_max = 110, 1387 .nv_temp_target_min = 75, 1388 .nv_temp_target_max = 87, 1389 }, 1390 .requires_fan_curve = true, 1391 }, 1392 }, 1393 { 1394 .matches = { 1395 DMI_MATCH(DMI_BOARD_NAME, "GU605CX"), 1396 }, 1397 .driver_data = &(struct power_data) { 1398 .ac_data = &(struct power_limits) { 1399 .ppt_pl1_spl_min = 45, 1400 .ppt_pl1_spl_max = 85, 1401 .ppt_pl2_sppt_min = 56, 1402 .ppt_pl2_sppt_max = 110, 1403 .nv_dynamic_boost_min = 5, 1404 .nv_dynamic_boost_max = 20, 1405 .nv_temp_target_min = 7, 1406 .nv_temp_target_max = 87, 1407 .nv_tgp_min = 95, 1408 .nv_tgp_def = 100, 1409 .nv_tgp_max = 110, 1410 }, 1411 .dc_data = &(struct power_limits) { 1412 .ppt_pl1_spl_min = 25, 1413 .ppt_pl1_spl_max = 85, 1414 .ppt_pl2_sppt_min = 32, 1415 .ppt_pl2_sppt_max = 110, 1416 .nv_temp_target_min = 75, 1417 .nv_temp_target_max = 87, 1418 }, 1419 .requires_fan_curve = true, 1420 }, 1421 }, 1422 { 1423 .matches = { 1424 DMI_MATCH(DMI_BOARD_NAME, "GU605MU"), 1425 }, 1426 .driver_data = &(struct power_data) { 1427 .ac_data = &(struct power_limits) { 1428 .ppt_pl1_spl_min = 28, 1429 .ppt_pl1_spl_max = 90, 1430 .ppt_pl2_sppt_min = 28, 1431 .ppt_pl2_sppt_max = 135, 1432 .nv_dynamic_boost_min = 5, 1433 .nv_dynamic_boost_max = 20, 1434 .nv_temp_target_min = 75, 1435 .nv_temp_target_max = 87, 1436 .nv_tgp_min = 55, 1437 .nv_tgp_max = 85, 1438 }, 1439 .dc_data = &(struct power_limits) { 1440 .ppt_pl1_spl_min = 25, 1441 .ppt_pl1_spl_max = 35, 1442 .ppt_pl2_sppt_min = 38, 1443 .ppt_pl2_sppt_max = 53, 1444 .nv_temp_target_min = 75, 1445 .nv_temp_target_max = 87, 1446 }, 1447 .requires_fan_curve = true, 1448 }, 1449 }, 1450 { 1451 .matches = { 1452 DMI_MATCH(DMI_BOARD_NAME, "GU605M"), 1453 }, 1454 .driver_data = &(struct power_data) { 1455 .ac_data = &(struct power_limits) { 1456 .ppt_pl1_spl_min = 28, 1457 .ppt_pl1_spl_max = 90, 1458 .ppt_pl2_sppt_min = 28, 1459 .ppt_pl2_sppt_max = 135, 1460 .nv_dynamic_boost_min = 5, 1461 .nv_dynamic_boost_max = 20, 1462 .nv_temp_target_min = 75, 1463 .nv_temp_target_max = 87, 1464 }, 1465 .dc_data = &(struct power_limits) { 1466 .ppt_pl1_spl_min = 25, 1467 .ppt_pl1_spl_max = 35, 1468 .ppt_pl2_sppt_min = 38, 1469 .ppt_pl2_sppt_max = 53, 1470 .nv_temp_target_min = 75, 1471 .nv_temp_target_max = 87, 1472 }, 1473 .requires_fan_curve = true, 1474 }, 1475 }, 1476 { 1477 .matches = { 1478 DMI_MATCH(DMI_BOARD_NAME, "GV301Q"), 1479 }, 1480 .driver_data = &(struct power_data) { 1481 .ac_data = &(struct power_limits) { 1482 .ppt_pl1_spl_min = 15, 1483 .ppt_pl1_spl_max = 45, 1484 .ppt_pl2_sppt_min = 65, 1485 .ppt_pl2_sppt_max = 80, 1486 }, 1487 .dc_data = NULL, 1488 }, 1489 }, 1490 { 1491 .matches = { 1492 DMI_MATCH(DMI_BOARD_NAME, "GV301R"), 1493 }, 1494 .driver_data = &(struct power_data) { 1495 .ac_data = &(struct power_limits) { 1496 .ppt_pl1_spl_min = 15, 1497 .ppt_pl1_spl_max = 45, 1498 .ppt_pl2_sppt_min = 25, 1499 .ppt_pl2_sppt_max = 54, 1500 .ppt_pl3_fppt_min = 35, 1501 .ppt_pl3_fppt_max = 65, 1502 .nv_temp_target_min = 75, 1503 .nv_temp_target_max = 87, 1504 }, 1505 .dc_data = &(struct power_limits) { 1506 .ppt_pl1_spl_min = 15, 1507 .ppt_pl1_spl_max = 35, 1508 .ppt_pl2_sppt_min = 25, 1509 .ppt_pl2_sppt_max = 35, 1510 .ppt_pl3_fppt_min = 35, 1511 .ppt_pl3_fppt_max = 65, 1512 .nv_temp_target_min = 75, 1513 .nv_temp_target_max = 87, 1514 }, 1515 }, 1516 }, 1517 { 1518 .matches = { 1519 DMI_MATCH(DMI_BOARD_NAME, "GV302XU"), 1520 }, 1521 .driver_data = &(struct power_data) { 1522 .ac_data = &(struct power_limits) { 1523 .ppt_pl1_spl_min = 15, 1524 .ppt_pl1_spl_max = 55, 1525 .ppt_pl2_sppt_min = 25, 1526 .ppt_pl2_sppt_max = 60, 1527 .ppt_pl3_fppt_min = 35, 1528 .ppt_pl3_fppt_max = 65, 1529 .nv_temp_target_min = 75, 1530 .nv_temp_target_max = 87, 1531 }, 1532 .dc_data = &(struct power_limits) { 1533 .ppt_pl1_spl_min = 15, 1534 .ppt_pl1_spl_max = 35, 1535 .ppt_pl2_sppt_min = 25, 1536 .ppt_pl2_sppt_max = 35, 1537 .ppt_pl3_fppt_min = 35, 1538 .ppt_pl3_fppt_max = 65, 1539 .nv_temp_target_min = 75, 1540 .nv_temp_target_max = 87, 1541 }, 1542 }, 1543 }, 1544 { 1545 .matches = { 1546 DMI_MATCH(DMI_BOARD_NAME, "GV302XV"), 1547 }, 1548 .driver_data = &(struct power_data) { 1549 .ac_data = &(struct power_limits) { 1550 .ppt_pl1_spl_min = 15, 1551 .ppt_pl1_spl_max = 55, 1552 .ppt_pl2_sppt_min = 25, 1553 .ppt_pl2_sppt_max = 60, 1554 .ppt_pl3_fppt_min = 35, 1555 .ppt_pl3_fppt_max = 65, 1556 .nv_temp_target_min = 75, 1557 .nv_temp_target_max = 87, 1558 }, 1559 .dc_data = &(struct power_limits) { 1560 .ppt_pl1_spl_min = 15, 1561 .ppt_pl1_spl_max = 35, 1562 .ppt_pl2_sppt_min = 25, 1563 .ppt_pl2_sppt_max = 35, 1564 .ppt_pl3_fppt_min = 35, 1565 .ppt_pl3_fppt_max = 65, 1566 .nv_temp_target_min = 75, 1567 .nv_temp_target_max = 87, 1568 }, 1569 }, 1570 }, 1571 { 1572 .matches = { 1573 DMI_MATCH(DMI_BOARD_NAME, "GV601R"), 1574 }, 1575 .driver_data = &(struct power_data) { 1576 .ac_data = &(struct power_limits) { 1577 .ppt_pl1_spl_min = 15, 1578 .ppt_pl1_spl_def = 35, 1579 .ppt_pl1_spl_max = 90, 1580 .ppt_pl2_sppt_min = 35, 1581 .ppt_pl2_sppt_def = 54, 1582 .ppt_pl2_sppt_max = 100, 1583 .ppt_pl3_fppt_min = 35, 1584 .ppt_pl3_fppt_def = 80, 1585 .ppt_pl3_fppt_max = 125, 1586 .nv_dynamic_boost_min = 5, 1587 .nv_dynamic_boost_max = 25, 1588 .nv_temp_target_min = 75, 1589 .nv_temp_target_max = 87, 1590 }, 1591 .dc_data = &(struct power_limits) { 1592 .ppt_pl1_spl_min = 15, 1593 .ppt_pl1_spl_def = 28, 1594 .ppt_pl1_spl_max = 65, 1595 .ppt_pl2_sppt_min = 35, 1596 .ppt_pl2_sppt_def = 54, 1597 .ppt_pl2_sppt_max = 60, 1598 .ppt_pl3_fppt_min = 35, 1599 .ppt_pl3_fppt_def = 80, 1600 .ppt_pl3_fppt_max = 65, 1601 .nv_temp_target_min = 75, 1602 .nv_temp_target_max = 87, 1603 }, 1604 }, 1605 }, 1606 { 1607 .matches = { 1608 DMI_MATCH(DMI_BOARD_NAME, "GV601V"), 1609 }, 1610 .driver_data = &(struct power_data) { 1611 .ac_data = &(struct power_limits) { 1612 .ppt_pl1_spl_min = 28, 1613 .ppt_pl1_spl_def = 100, 1614 .ppt_pl1_spl_max = 110, 1615 .ppt_pl2_sppt_min = 28, 1616 .ppt_pl2_sppt_max = 135, 1617 .nv_dynamic_boost_min = 5, 1618 .nv_dynamic_boost_max = 20, 1619 .nv_temp_target_min = 75, 1620 .nv_temp_target_max = 87, 1621 }, 1622 .dc_data = &(struct power_limits) { 1623 .ppt_pl1_spl_min = 25, 1624 .ppt_pl1_spl_max = 40, 1625 .ppt_pl2_sppt_min = 35, 1626 .ppt_pl2_sppt_def = 40, 1627 .ppt_pl2_sppt_max = 60, 1628 .nv_temp_target_min = 75, 1629 .nv_temp_target_max = 87, 1630 }, 1631 }, 1632 }, 1633 { 1634 .matches = { 1635 DMI_MATCH(DMI_BOARD_NAME, "GX650P"), 1636 }, 1637 .driver_data = &(struct power_data) { 1638 .ac_data = &(struct power_limits) { 1639 .ppt_pl1_spl_min = 15, 1640 .ppt_pl1_spl_def = 110, 1641 .ppt_pl1_spl_max = 130, 1642 .ppt_pl2_sppt_min = 35, 1643 .ppt_pl2_sppt_def = 125, 1644 .ppt_pl2_sppt_max = 130, 1645 .ppt_pl3_fppt_min = 35, 1646 .ppt_pl3_fppt_def = 125, 1647 .ppt_pl3_fppt_max = 135, 1648 .nv_dynamic_boost_min = 5, 1649 .nv_dynamic_boost_max = 25, 1650 .nv_temp_target_min = 75, 1651 .nv_temp_target_max = 87, 1652 }, 1653 .dc_data = &(struct power_limits) { 1654 .ppt_pl1_spl_min = 15, 1655 .ppt_pl1_spl_def = 25, 1656 .ppt_pl1_spl_max = 65, 1657 .ppt_pl2_sppt_min = 35, 1658 .ppt_pl2_sppt_def = 35, 1659 .ppt_pl2_sppt_max = 65, 1660 .ppt_pl3_fppt_min = 35, 1661 .ppt_pl3_fppt_def = 42, 1662 .ppt_pl3_fppt_max = 65, 1663 .nv_temp_target_min = 75, 1664 .nv_temp_target_max = 87, 1665 }, 1666 }, 1667 }, 1668 { 1669 .matches = { 1670 DMI_MATCH(DMI_BOARD_NAME, "GX650RX"), 1671 }, 1672 .driver_data = &(struct power_data) { 1673 .ac_data = &(struct power_limits) { 1674 .ppt_pl1_spl_min = 28, 1675 .ppt_pl1_spl_def = 70, 1676 .ppt_pl1_spl_max = 90, 1677 .ppt_pl2_sppt_min = 28, 1678 .ppt_pl2_sppt_def = 70, 1679 .ppt_pl2_sppt_max = 100, 1680 .ppt_pl3_fppt_min = 28, 1681 .ppt_pl3_fppt_def = 110, 1682 .ppt_pl3_fppt_max = 125, 1683 .nv_dynamic_boost_min = 5, 1684 .nv_dynamic_boost_max = 25, 1685 .nv_temp_target_min = 76, 1686 .nv_temp_target_max = 87, 1687 }, 1688 .dc_data = &(struct power_limits) { 1689 .ppt_pl1_spl_min = 28, 1690 .ppt_pl1_spl_max = 50, 1691 .ppt_pl2_sppt_min = 28, 1692 .ppt_pl2_sppt_max = 50, 1693 .ppt_pl3_fppt_min = 28, 1694 .ppt_pl3_fppt_max = 65, 1695 .nv_temp_target_min = 76, 1696 .nv_temp_target_max = 87, 1697 }, 1698 }, 1699 }, 1700 { 1701 .matches = { 1702 DMI_MATCH(DMI_BOARD_NAME, "GZ302EA"), 1703 }, 1704 .driver_data = &(struct power_data) { 1705 .ac_data = &(struct power_limits) { 1706 .ppt_pl1_spl_min = 28, 1707 .ppt_pl1_spl_def = 60, 1708 .ppt_pl1_spl_max = 80, 1709 .ppt_pl2_sppt_min = 32, 1710 .ppt_pl2_sppt_def = 75, 1711 .ppt_pl2_sppt_max = 92, 1712 .ppt_pl3_fppt_min = 45, 1713 .ppt_pl3_fppt_def = 86, 1714 .ppt_pl3_fppt_max = 93, 1715 }, 1716 .dc_data = &(struct power_limits) { 1717 .ppt_pl1_spl_min = 28, 1718 .ppt_pl1_spl_def = 45, 1719 .ppt_pl1_spl_max = 80, 1720 .ppt_pl2_sppt_min = 32, 1721 .ppt_pl2_sppt_def = 52, 1722 .ppt_pl2_sppt_max = 92, 1723 .ppt_pl3_fppt_min = 45, 1724 .ppt_pl3_fppt_def = 71, 1725 .ppt_pl3_fppt_max = 93, 1726 }, 1727 }, 1728 }, 1729 { 1730 .matches = { 1731 DMI_MATCH(DMI_BOARD_NAME, "G513I"), 1732 }, 1733 .driver_data = &(struct power_data) { 1734 .ac_data = &(struct power_limits) { 1735 /* Yes this laptop is very limited */ 1736 .ppt_pl1_spl_min = 15, 1737 .ppt_pl1_spl_max = 80, 1738 .ppt_pl2_sppt_min = 15, 1739 .ppt_pl2_sppt_max = 80, 1740 }, 1741 .dc_data = NULL, 1742 .requires_fan_curve = true, 1743 }, 1744 }, 1745 { 1746 .matches = { 1747 DMI_MATCH(DMI_BOARD_NAME, "G513QM"), 1748 }, 1749 .driver_data = &(struct power_data) { 1750 .ac_data = &(struct power_limits) { 1751 /* Yes this laptop is very limited */ 1752 .ppt_pl1_spl_min = 15, 1753 .ppt_pl1_spl_max = 100, 1754 .ppt_pl2_sppt_min = 15, 1755 .ppt_pl2_sppt_max = 190, 1756 }, 1757 .dc_data = NULL, 1758 .requires_fan_curve = true, 1759 }, 1760 }, 1761 { 1762 .matches = { 1763 DMI_MATCH(DMI_BOARD_NAME, "G513QY"), 1764 }, 1765 .driver_data = &(struct power_data) { 1766 .ac_data = &(struct power_limits) { 1767 /* Advantage Edition Laptop, no PL1 or PL2 limits */ 1768 .ppt_apu_sppt_min = 15, 1769 .ppt_apu_sppt_max = 100, 1770 .ppt_platform_sppt_min = 70, 1771 .ppt_platform_sppt_max = 190, 1772 }, 1773 .dc_data = NULL, 1774 .requires_fan_curve = true, 1775 }, 1776 }, 1777 { 1778 .matches = { 1779 DMI_MATCH(DMI_BOARD_NAME, "G513R"), 1780 }, 1781 .driver_data = &(struct power_data) { 1782 .ac_data = &(struct power_limits) { 1783 .ppt_pl1_spl_min = 35, 1784 .ppt_pl1_spl_max = 90, 1785 .ppt_pl2_sppt_min = 54, 1786 .ppt_pl2_sppt_max = 100, 1787 .ppt_pl3_fppt_min = 54, 1788 .ppt_pl3_fppt_max = 125, 1789 .nv_dynamic_boost_min = 5, 1790 .nv_dynamic_boost_max = 25, 1791 .nv_temp_target_min = 75, 1792 .nv_temp_target_max = 87, 1793 }, 1794 .dc_data = &(struct power_limits) { 1795 .ppt_pl1_spl_min = 28, 1796 .ppt_pl1_spl_max = 50, 1797 .ppt_pl2_sppt_min = 28, 1798 .ppt_pl2_sppt_max = 50, 1799 .ppt_pl3_fppt_min = 28, 1800 .ppt_pl3_fppt_max = 65, 1801 .nv_temp_target_min = 75, 1802 .nv_temp_target_max = 87, 1803 }, 1804 .requires_fan_curve = true, 1805 }, 1806 }, 1807 { 1808 .matches = { 1809 DMI_MATCH(DMI_BOARD_NAME, "G614FP"), 1810 }, 1811 .driver_data = &(struct power_data) { 1812 .ac_data = &(struct power_limits) { 1813 .ppt_pl1_spl_min = 30, 1814 .ppt_pl1_spl_max = 120, 1815 .ppt_pl2_sppt_min = 65, 1816 .ppt_pl2_sppt_def = 140, 1817 .ppt_pl2_sppt_max = 165, 1818 .ppt_pl3_fppt_min = 65, 1819 .ppt_pl3_fppt_def = 140, 1820 .ppt_pl3_fppt_max = 165, 1821 .nv_temp_target_min = 75, 1822 .nv_temp_target_max = 87, 1823 .nv_dynamic_boost_min = 5, 1824 .nv_dynamic_boost_max = 15, 1825 .nv_tgp_min = 50, 1826 .nv_tgp_max = 100, 1827 }, 1828 .dc_data = &(struct power_limits) { 1829 .ppt_pl1_spl_min = 25, 1830 .ppt_pl1_spl_max = 65, 1831 .ppt_pl2_sppt_min = 25, 1832 .ppt_pl2_sppt_max = 65, 1833 .ppt_pl3_fppt_min = 35, 1834 .ppt_pl3_fppt_max = 75, 1835 .nv_temp_target_min = 75, 1836 .nv_temp_target_max = 87, 1837 }, 1838 .requires_fan_curve = true, 1839 }, 1840 }, 1841 { 1842 .matches = { 1843 DMI_MATCH(DMI_BOARD_NAME, "G614FR"), 1844 }, 1845 .driver_data = &(struct power_data) { 1846 .ac_data = &(struct power_limits) { 1847 .ppt_pl1_spl_min = 30, 1848 .ppt_pl1_spl_max = 120, 1849 .ppt_pl2_sppt_min = 65, 1850 .ppt_pl2_sppt_def = 140, 1851 .ppt_pl2_sppt_max = 162, 1852 .ppt_pl3_fppt_min = 65, 1853 .ppt_pl3_fppt_def = 140, 1854 .ppt_pl3_fppt_max = 162, 1855 .nv_temp_target_min = 75, 1856 .nv_temp_target_max = 87, 1857 .nv_dynamic_boost_min = 5, 1858 .nv_dynamic_boost_max = 25, 1859 .nv_tgp_min = 65, 1860 .nv_tgp_max = 115, 1861 }, 1862 .dc_data = &(struct power_limits) { 1863 .ppt_pl1_spl_min = 25, 1864 .ppt_pl1_spl_max = 65, 1865 .ppt_pl2_sppt_min = 25, 1866 .ppt_pl2_sppt_max = 65, 1867 .ppt_pl3_fppt_min = 35, 1868 .ppt_pl3_fppt_max = 75, 1869 .nv_temp_target_min = 75, 1870 .nv_temp_target_max = 87, 1871 }, 1872 .requires_fan_curve = true, 1873 }, 1874 }, 1875 { 1876 .matches = { 1877 DMI_MATCH(DMI_BOARD_NAME, "G614J"), 1878 }, 1879 .driver_data = &(struct power_data) { 1880 .ac_data = &(struct power_limits) { 1881 .ppt_pl1_spl_min = 28, 1882 .ppt_pl1_spl_max = 140, 1883 .ppt_pl2_sppt_min = 28, 1884 .ppt_pl2_sppt_max = 175, 1885 .nv_temp_target_min = 75, 1886 .nv_temp_target_max = 87, 1887 .nv_dynamic_boost_min = 5, 1888 .nv_dynamic_boost_max = 25, 1889 }, 1890 .dc_data = &(struct power_limits) { 1891 .ppt_pl1_spl_min = 25, 1892 .ppt_pl1_spl_max = 55, 1893 .ppt_pl2_sppt_min = 25, 1894 .ppt_pl2_sppt_max = 70, 1895 .nv_temp_target_min = 75, 1896 .nv_temp_target_max = 87, 1897 }, 1898 .requires_fan_curve = true, 1899 }, 1900 }, 1901 { 1902 .matches = { 1903 DMI_MATCH(DMI_BOARD_NAME, "G615LR"), 1904 }, 1905 .driver_data = &(struct power_data) { 1906 .ac_data = &(struct power_limits) { 1907 .ppt_pl1_spl_min = 28, 1908 .ppt_pl1_spl_def = 140, 1909 .ppt_pl1_spl_max = 175, 1910 .ppt_pl2_sppt_min = 28, 1911 .ppt_pl2_sppt_max = 175, 1912 .nv_temp_target_min = 75, 1913 .nv_temp_target_max = 87, 1914 .nv_dynamic_boost_min = 5, 1915 .nv_dynamic_boost_max = 25, 1916 .nv_tgp_min = 65, 1917 .nv_tgp_max = 115, 1918 }, 1919 .dc_data = &(struct power_limits) { 1920 .ppt_pl1_spl_min = 25, 1921 .ppt_pl1_spl_max = 55, 1922 .ppt_pl2_sppt_min = 25, 1923 .ppt_pl2_sppt_max = 70, 1924 .nv_temp_target_min = 75, 1925 .nv_temp_target_max = 87, 1926 }, 1927 .requires_fan_curve = true, 1928 }, 1929 }, 1930 { 1931 .matches = { 1932 DMI_MATCH(DMI_BOARD_NAME, "G634J"), 1933 }, 1934 .driver_data = &(struct power_data) { 1935 .ac_data = &(struct power_limits) { 1936 .ppt_pl1_spl_min = 28, 1937 .ppt_pl1_spl_max = 140, 1938 .ppt_pl2_sppt_min = 28, 1939 .ppt_pl2_sppt_max = 175, 1940 .nv_temp_target_min = 75, 1941 .nv_temp_target_max = 87, 1942 .nv_dynamic_boost_min = 5, 1943 .nv_dynamic_boost_max = 25, 1944 }, 1945 .dc_data = &(struct power_limits) { 1946 .ppt_pl1_spl_min = 25, 1947 .ppt_pl1_spl_max = 55, 1948 .ppt_pl2_sppt_min = 25, 1949 .ppt_pl2_sppt_max = 70, 1950 .nv_temp_target_min = 75, 1951 .nv_temp_target_max = 87, 1952 }, 1953 .requires_fan_curve = true, 1954 }, 1955 }, 1956 { 1957 .matches = { 1958 DMI_MATCH(DMI_BOARD_NAME, "G713PV"), 1959 }, 1960 .driver_data = &(struct power_data) { 1961 .ac_data = &(struct power_limits) { 1962 .ppt_pl1_spl_min = 30, 1963 .ppt_pl1_spl_def = 120, 1964 .ppt_pl1_spl_max = 130, 1965 .ppt_pl2_sppt_min = 65, 1966 .ppt_pl2_sppt_def = 125, 1967 .ppt_pl2_sppt_max = 130, 1968 .ppt_pl3_fppt_min = 65, 1969 .ppt_pl3_fppt_def = 125, 1970 .ppt_pl3_fppt_max = 130, 1971 .nv_temp_target_min = 75, 1972 .nv_temp_target_max = 87, 1973 .nv_dynamic_boost_min = 5, 1974 .nv_dynamic_boost_max = 25, 1975 }, 1976 .dc_data = &(struct power_limits) { 1977 .ppt_pl1_spl_min = 25, 1978 .ppt_pl1_spl_max = 65, 1979 .ppt_pl2_sppt_min = 25, 1980 .ppt_pl2_sppt_max = 65, 1981 .ppt_pl3_fppt_min = 35, 1982 .ppt_pl3_fppt_max = 75, 1983 .nv_temp_target_min = 75, 1984 .nv_temp_target_max = 87, 1985 }, 1986 .requires_fan_curve = true, 1987 }, 1988 }, 1989 { 1990 .matches = { 1991 DMI_MATCH(DMI_BOARD_NAME, "G733C"), 1992 }, 1993 .driver_data = &(struct power_data) { 1994 .ac_data = &(struct power_limits) { 1995 .ppt_pl1_spl_min = 28, 1996 .ppt_pl1_spl_max = 170, 1997 .ppt_pl2_sppt_min = 28, 1998 .ppt_pl2_sppt_max = 175, 1999 .nv_temp_target_min = 75, 2000 .nv_temp_target_max = 87, 2001 .nv_dynamic_boost_min = 5, 2002 .nv_dynamic_boost_max = 25, 2003 }, 2004 .dc_data = &(struct power_limits) { 2005 .ppt_pl1_spl_min = 28, 2006 .ppt_pl1_spl_max = 35, 2007 .ppt_pl2_sppt_min = 28, 2008 .ppt_pl2_sppt_max = 35, 2009 .nv_temp_target_min = 75, 2010 .nv_temp_target_max = 87, 2011 }, 2012 .requires_fan_curve = true, 2013 }, 2014 }, 2015 { 2016 .matches = { 2017 DMI_MATCH(DMI_BOARD_NAME, "G733P"), 2018 }, 2019 .driver_data = &(struct power_data) { 2020 .ac_data = &(struct power_limits) { 2021 .ppt_pl1_spl_min = 30, 2022 .ppt_pl1_spl_def = 100, 2023 .ppt_pl1_spl_max = 130, 2024 .ppt_pl2_sppt_min = 65, 2025 .ppt_pl2_sppt_def = 125, 2026 .ppt_pl2_sppt_max = 130, 2027 .ppt_pl3_fppt_min = 65, 2028 .ppt_pl3_fppt_def = 125, 2029 .ppt_pl3_fppt_max = 130, 2030 .nv_temp_target_min = 75, 2031 .nv_temp_target_max = 87, 2032 .nv_dynamic_boost_min = 5, 2033 .nv_dynamic_boost_max = 25, 2034 }, 2035 .dc_data = &(struct power_limits) { 2036 .ppt_pl1_spl_min = 25, 2037 .ppt_pl1_spl_max = 65, 2038 .ppt_pl2_sppt_min = 25, 2039 .ppt_pl2_sppt_max = 65, 2040 .ppt_pl3_fppt_min = 35, 2041 .ppt_pl3_fppt_max = 75, 2042 .nv_temp_target_min = 75, 2043 .nv_temp_target_max = 87, 2044 }, 2045 .requires_fan_curve = true, 2046 }, 2047 }, 2048 { 2049 .matches = { 2050 DMI_MATCH(DMI_BOARD_NAME, "G733QS"), 2051 }, 2052 .driver_data = &(struct power_data) { 2053 .ac_data = &(struct power_limits) { 2054 .ppt_pl1_spl_min = 15, 2055 .ppt_pl1_spl_max = 80, 2056 .ppt_pl2_sppt_min = 15, 2057 .ppt_pl2_sppt_max = 80, 2058 }, 2059 .requires_fan_curve = false, 2060 }, 2061 }, 2062 { 2063 .matches = { 2064 DMI_MATCH(DMI_BOARD_NAME, "G814J"), 2065 }, 2066 .driver_data = &(struct power_data) { 2067 .ac_data = &(struct power_limits) { 2068 .ppt_pl1_spl_min = 28, 2069 .ppt_pl1_spl_max = 140, 2070 .ppt_pl2_sppt_min = 28, 2071 .ppt_pl2_sppt_max = 140, 2072 .nv_dynamic_boost_min = 5, 2073 .nv_dynamic_boost_max = 25, 2074 }, 2075 .dc_data = &(struct power_limits) { 2076 .ppt_pl1_spl_min = 25, 2077 .ppt_pl1_spl_max = 55, 2078 .ppt_pl2_sppt_min = 25, 2079 .ppt_pl2_sppt_max = 70, 2080 }, 2081 .requires_fan_curve = true, 2082 }, 2083 }, 2084 { 2085 .matches = { 2086 DMI_MATCH(DMI_BOARD_NAME, "G834J"), 2087 }, 2088 .driver_data = &(struct power_data) { 2089 .ac_data = &(struct power_limits) { 2090 .ppt_pl1_spl_min = 28, 2091 .ppt_pl1_spl_max = 140, 2092 .ppt_pl2_sppt_min = 28, 2093 .ppt_pl2_sppt_max = 175, 2094 .nv_dynamic_boost_min = 5, 2095 .nv_dynamic_boost_max = 25, 2096 .nv_temp_target_min = 75, 2097 .nv_temp_target_max = 87, 2098 }, 2099 .dc_data = &(struct power_limits) { 2100 .ppt_pl1_spl_min = 25, 2101 .ppt_pl1_spl_max = 55, 2102 .ppt_pl2_sppt_min = 25, 2103 .ppt_pl2_sppt_max = 70, 2104 .nv_temp_target_min = 75, 2105 .nv_temp_target_max = 87, 2106 }, 2107 .requires_fan_curve = true, 2108 }, 2109 }, 2110 { 2111 .matches = { 2112 DMI_MATCH(DMI_BOARD_NAME, "G835LR"), 2113 }, 2114 .driver_data = &(struct power_data) { 2115 .ac_data = &(struct power_limits) { 2116 .ppt_pl1_spl_min = 28, 2117 .ppt_pl1_spl_def = 140, 2118 .ppt_pl1_spl_max = 175, 2119 .ppt_pl2_sppt_min = 28, 2120 .ppt_pl2_sppt_max = 175, 2121 .nv_dynamic_boost_min = 5, 2122 .nv_dynamic_boost_max = 25, 2123 .nv_temp_target_min = 75, 2124 .nv_temp_target_max = 87, 2125 .nv_tgp_min = 65, 2126 .nv_tgp_max = 115, 2127 }, 2128 .dc_data = &(struct power_limits) { 2129 .ppt_pl1_spl_min = 25, 2130 .ppt_pl1_spl_max = 55, 2131 .ppt_pl2_sppt_min = 25, 2132 .ppt_pl2_sppt_max = 70, 2133 .nv_temp_target_min = 75, 2134 .nv_temp_target_max = 87, 2135 }, 2136 .requires_fan_curve = true, 2137 }, 2138 }, 2139 { 2140 .matches = { 2141 DMI_MATCH(DMI_BOARD_NAME, "G835LW"), 2142 }, 2143 .driver_data = &(struct power_data) { 2144 .ac_data = &(struct power_limits) { 2145 .ppt_pl1_spl_min = 28, 2146 .ppt_pl1_spl_def = 140, 2147 .ppt_pl1_spl_max = 175, 2148 .ppt_pl2_sppt_min = 28, 2149 .ppt_pl2_sppt_max = 175, 2150 .nv_dynamic_boost_min = 5, 2151 .nv_dynamic_boost_max = 25, 2152 .nv_temp_target_min = 75, 2153 .nv_temp_target_max = 87, 2154 .nv_tgp_min = 80, 2155 .nv_tgp_max = 150, 2156 }, 2157 .dc_data = &(struct power_limits) { 2158 .ppt_pl1_spl_min = 25, 2159 .ppt_pl1_spl_max = 55, 2160 .ppt_pl2_sppt_min = 25, 2161 .ppt_pl2_sppt_max = 70, 2162 .nv_temp_target_min = 75, 2163 .nv_temp_target_max = 87, 2164 }, 2165 .requires_fan_curve = true, 2166 }, 2167 }, 2168 { 2169 .matches = { 2170 DMI_MATCH(DMI_BOARD_NAME, "H7606W"), 2171 }, 2172 .driver_data = &(struct power_data) { 2173 .ac_data = &(struct power_limits) { 2174 .ppt_pl1_spl_min = 15, 2175 .ppt_pl1_spl_max = 80, 2176 .ppt_pl2_sppt_min = 35, 2177 .ppt_pl2_sppt_max = 80, 2178 .ppt_pl3_fppt_min = 35, 2179 .ppt_pl3_fppt_max = 80, 2180 .nv_dynamic_boost_min = 5, 2181 .nv_dynamic_boost_max = 20, 2182 .nv_temp_target_min = 75, 2183 .nv_temp_target_max = 87, 2184 .nv_tgp_min = 55, 2185 .nv_tgp_max = 85, 2186 }, 2187 .dc_data = &(struct power_limits) { 2188 .ppt_pl1_spl_min = 25, 2189 .ppt_pl1_spl_max = 35, 2190 .ppt_pl2_sppt_min = 31, 2191 .ppt_pl2_sppt_max = 44, 2192 .ppt_pl3_fppt_min = 45, 2193 .ppt_pl3_fppt_max = 65, 2194 .nv_temp_target_min = 75, 2195 .nv_temp_target_max = 87, 2196 }, 2197 }, 2198 }, 2199 { 2200 .matches = { 2201 DMI_MATCH(DMI_BOARD_NAME, "RC71"), 2202 }, 2203 .driver_data = &(struct power_data) { 2204 .ac_data = &(struct power_limits) { 2205 .ppt_pl1_spl_min = 7, 2206 .ppt_pl1_spl_max = 30, 2207 .ppt_pl2_sppt_min = 15, 2208 .ppt_pl2_sppt_max = 43, 2209 .ppt_pl3_fppt_min = 15, 2210 .ppt_pl3_fppt_max = 53, 2211 }, 2212 .dc_data = &(struct power_limits) { 2213 .ppt_pl1_spl_min = 7, 2214 .ppt_pl1_spl_def = 15, 2215 .ppt_pl1_spl_max = 25, 2216 .ppt_pl2_sppt_min = 15, 2217 .ppt_pl2_sppt_def = 20, 2218 .ppt_pl2_sppt_max = 30, 2219 .ppt_pl3_fppt_min = 15, 2220 .ppt_pl3_fppt_def = 25, 2221 .ppt_pl3_fppt_max = 35, 2222 }, 2223 }, 2224 }, 2225 { 2226 .matches = { 2227 DMI_MATCH(DMI_BOARD_NAME, "RC72"), 2228 }, 2229 .driver_data = &(struct power_data) { 2230 .ac_data = &(struct power_limits) { 2231 .ppt_pl1_spl_min = 7, 2232 .ppt_pl1_spl_max = 30, 2233 .ppt_pl2_sppt_min = 15, 2234 .ppt_pl2_sppt_max = 43, 2235 .ppt_pl3_fppt_min = 15, 2236 .ppt_pl3_fppt_max = 53, 2237 }, 2238 .dc_data = &(struct power_limits) { 2239 .ppt_pl1_spl_min = 7, 2240 .ppt_pl1_spl_def = 17, 2241 .ppt_pl1_spl_max = 25, 2242 .ppt_pl2_sppt_min = 15, 2243 .ppt_pl2_sppt_def = 24, 2244 .ppt_pl2_sppt_max = 30, 2245 .ppt_pl3_fppt_min = 15, 2246 .ppt_pl3_fppt_def = 30, 2247 .ppt_pl3_fppt_max = 35, 2248 }, 2249 }, 2250 }, 2251 { 2252 .matches = { 2253 DMI_MATCH(DMI_BOARD_NAME, "RC73XA"), 2254 }, 2255 .driver_data = &(struct power_data) { 2256 .ac_data = &(struct power_limits) { 2257 .ppt_pl1_spl_min = 7, 2258 .ppt_pl1_spl_max = 35, 2259 .ppt_pl2_sppt_min = 14, 2260 .ppt_pl2_sppt_max = 45, 2261 .ppt_pl3_fppt_min = 19, 2262 .ppt_pl3_fppt_max = 55, 2263 }, 2264 .dc_data = &(struct power_limits) { 2265 .ppt_pl1_spl_min = 7, 2266 .ppt_pl1_spl_def = 17, 2267 .ppt_pl1_spl_max = 35, 2268 .ppt_pl2_sppt_min = 13, 2269 .ppt_pl2_sppt_def = 21, 2270 .ppt_pl2_sppt_max = 45, 2271 .ppt_pl3_fppt_min = 19, 2272 .ppt_pl3_fppt_def = 26, 2273 .ppt_pl3_fppt_max = 55, 2274 }, 2275 }, 2276 }, 2277 {} 2278 }; 2279 2280 #endif /* _ASUS_ARMOURY_H_ */ 2281