xref: /linux/sound/arm/pxa2xx-ac97-lib.c (revision 05a54fa773284d1a7923cdfdd8f0c8dabb98bd26)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Based on sound/arm/pxa2xx-ac97.c and sound/soc/pxa/pxa2xx-ac97.c
4  * which contain:
5  *
6  * Author:	Nicolas Pitre
7  * Created:	Dec 02, 2004
8  * Copyright:	MontaVista Software Inc.
9  */
10 
11 #include <linux/kernel.h>
12 #include <linux/platform_device.h>
13 #include <linux/interrupt.h>
14 #include <linux/clk.h>
15 #include <linux/delay.h>
16 #include <linux/module.h>
17 #include <linux/io.h>
18 #include <linux/gpio.h>
19 #include <linux/of_gpio.h>
20 #include <linux/soc/pxa/cpu.h>
21 
22 #include <sound/pxa2xx-lib.h>
23 
24 #include <linux/platform_data/asoc-pxa.h>
25 
26 #include "pxa2xx-ac97-regs.h"
27 
28 static DEFINE_MUTEX(car_mutex);
29 static DECLARE_WAIT_QUEUE_HEAD(gsr_wq);
30 static volatile long gsr_bits;
31 static struct clk *ac97_clk;
32 static struct clk *ac97conf_clk;
33 static int reset_gpio;
34 static void __iomem *ac97_reg_base;
35 
36 /*
37  * Beware PXA27x bugs:
38  *
39  *   o Slot 12 read from modem space will hang controller.
40  *   o CDONE, SDONE interrupt fails after any slot 12 IO.
41  *
42  * We therefore have an hybrid approach for waiting on SDONE (interrupt or
43  * 1 jiffy timeout if interrupt never comes).
44  */
45 
46 int pxa2xx_ac97_read(int slot, unsigned short reg)
47 {
48 	int val = -ENODEV;
49 	u32 __iomem *reg_addr;
50 
51 	if (slot > 0)
52 		return -ENODEV;
53 
54 	guard(mutex)(&car_mutex);
55 
56 	/* set up primary or secondary codec space */
57 	if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS)
58 		reg_addr = ac97_reg_base +
59 			   (slot ? SMC_REG_BASE : PMC_REG_BASE);
60 	else
61 		reg_addr = ac97_reg_base +
62 			   (slot ? SAC_REG_BASE : PAC_REG_BASE);
63 	reg_addr += (reg >> 1);
64 
65 	/* start read access across the ac97 link */
66 	writel(GSR_CDONE | GSR_SDONE, ac97_reg_base + GSR);
67 	gsr_bits = 0;
68 	val = (readl(reg_addr) & 0xffff);
69 	if (reg == AC97_GPIO_STATUS)
70 		return val;
71 	if (wait_event_timeout(gsr_wq, (readl(ac97_reg_base + GSR) | gsr_bits) & GSR_SDONE, 1) <= 0 &&
72 	    !((readl(ac97_reg_base + GSR) | gsr_bits) & GSR_SDONE)) {
73 		printk(KERN_ERR "%s: read error (ac97_reg=%d GSR=%#lx)\n",
74 				__func__, reg, readl(ac97_reg_base + GSR) | gsr_bits);
75 		return -ETIMEDOUT;
76 	}
77 
78 	/* valid data now */
79 	writel(GSR_CDONE | GSR_SDONE, ac97_reg_base + GSR);
80 	gsr_bits = 0;
81 	val = (readl(reg_addr) & 0xffff);
82 	/* but we've just started another cycle... */
83 	wait_event_timeout(gsr_wq, (readl(ac97_reg_base + GSR) | gsr_bits) & GSR_SDONE, 1);
84 	return val;
85 }
86 EXPORT_SYMBOL_GPL(pxa2xx_ac97_read);
87 
88 int pxa2xx_ac97_write(int slot, unsigned short reg, unsigned short val)
89 {
90 	u32 __iomem *reg_addr;
91 	int ret = 0;
92 
93 	guard(mutex)(&car_mutex);
94 
95 	/* set up primary or secondary codec space */
96 	if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS)
97 		reg_addr = ac97_reg_base +
98 			   (slot ? SMC_REG_BASE : PMC_REG_BASE);
99 	else
100 		reg_addr = ac97_reg_base +
101 			   (slot ? SAC_REG_BASE : PAC_REG_BASE);
102 	reg_addr += (reg >> 1);
103 
104 	writel(GSR_CDONE | GSR_SDONE, ac97_reg_base + GSR);
105 	gsr_bits = 0;
106 	writel(val, reg_addr);
107 	if (wait_event_timeout(gsr_wq, (readl(ac97_reg_base + GSR) | gsr_bits) & GSR_CDONE, 1) <= 0 &&
108 	    !((readl(ac97_reg_base + GSR) | gsr_bits) & GSR_CDONE)) {
109 		printk(KERN_ERR "%s: write error (ac97_reg=%d GSR=%#lx)\n",
110 				__func__, reg, readl(ac97_reg_base + GSR) | gsr_bits);
111 		ret = -EIO;
112 	}
113 
114 	return ret;
115 }
116 EXPORT_SYMBOL_GPL(pxa2xx_ac97_write);
117 
118 #ifdef CONFIG_PXA25x
119 static inline void pxa_ac97_warm_pxa25x(void)
120 {
121 	gsr_bits = 0;
122 
123 	writel(readl(ac97_reg_base + GCR) | (GCR_WARM_RST), ac97_reg_base + GCR);
124 }
125 
126 static inline void pxa_ac97_cold_pxa25x(void)
127 {
128 	writel(readl(ac97_reg_base + GCR) & ( GCR_COLD_RST), ac97_reg_base + GCR);  /* clear everything but nCRST */
129 	writel(readl(ac97_reg_base + GCR) & (~GCR_COLD_RST), ac97_reg_base + GCR);  /* then assert nCRST */
130 
131 	gsr_bits = 0;
132 
133 	writel(GCR_COLD_RST, ac97_reg_base + GCR);
134 }
135 #endif
136 
137 #ifdef CONFIG_PXA27x
138 static inline void pxa_ac97_warm_pxa27x(void)
139 {
140 	gsr_bits = 0;
141 
142 	/* warm reset broken on Bulverde, so manually keep AC97 reset high */
143 	pxa27x_configure_ac97reset(reset_gpio, true);
144 	udelay(10);
145 	writel(readl(ac97_reg_base + GCR) | (GCR_WARM_RST), ac97_reg_base + GCR);
146 	pxa27x_configure_ac97reset(reset_gpio, false);
147 	udelay(500);
148 }
149 
150 static inline void pxa_ac97_cold_pxa27x(void)
151 {
152 	writel(readl(ac97_reg_base + GCR) & ( GCR_COLD_RST), ac97_reg_base + GCR);  /* clear everything but nCRST */
153 	writel(readl(ac97_reg_base + GCR) & (~GCR_COLD_RST), ac97_reg_base + GCR);  /* then assert nCRST */
154 
155 	gsr_bits = 0;
156 
157 	/* PXA27x Developers Manual section 13.5.2.2.1 */
158 	clk_prepare_enable(ac97conf_clk);
159 	udelay(5);
160 	clk_disable_unprepare(ac97conf_clk);
161 	writel(GCR_COLD_RST | GCR_WARM_RST, ac97_reg_base + GCR);
162 }
163 #endif
164 
165 #ifdef CONFIG_PXA3xx
166 static inline void pxa_ac97_warm_pxa3xx(void)
167 {
168 	gsr_bits = 0;
169 
170 	/* Can't use interrupts */
171 	writel(readl(ac97_reg_base + GCR) | (GCR_WARM_RST), ac97_reg_base + GCR);
172 }
173 
174 static inline void pxa_ac97_cold_pxa3xx(void)
175 {
176 	/* Hold CLKBPB for 100us */
177 	writel(0, ac97_reg_base + GCR);
178 	writel(GCR_CLKBPB, ac97_reg_base + GCR);
179 	udelay(100);
180 	writel(0, ac97_reg_base + GCR);
181 
182 	writel(readl(ac97_reg_base + GCR) & ( GCR_COLD_RST), ac97_reg_base + GCR);  /* clear everything but nCRST */
183 	writel(readl(ac97_reg_base + GCR) & (~GCR_COLD_RST), ac97_reg_base + GCR);  /* then assert nCRST */
184 
185 	gsr_bits = 0;
186 
187 	/* Can't use interrupts on PXA3xx */
188 	writel(readl(ac97_reg_base + GCR) & (~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN)), ac97_reg_base + GCR);
189 
190 	writel(GCR_WARM_RST | GCR_COLD_RST, ac97_reg_base + GCR);
191 }
192 #endif
193 
194 bool pxa2xx_ac97_try_warm_reset(void)
195 {
196 	unsigned long gsr;
197 	unsigned int timeout = 100;
198 
199 #ifdef CONFIG_PXA25x
200 	if (cpu_is_pxa25x())
201 		pxa_ac97_warm_pxa25x();
202 	else
203 #endif
204 #ifdef CONFIG_PXA27x
205 	if (cpu_is_pxa27x())
206 		pxa_ac97_warm_pxa27x();
207 	else
208 #endif
209 #ifdef CONFIG_PXA3xx
210 	if (cpu_is_pxa3xx())
211 		pxa_ac97_warm_pxa3xx();
212 	else
213 #endif
214 		snd_BUG();
215 
216 	while (!((readl(ac97_reg_base + GSR) | gsr_bits) & (GSR_PCR | GSR_SCR)) && timeout--)
217 		mdelay(1);
218 
219 	gsr = readl(ac97_reg_base + GSR) | gsr_bits;
220 	if (!(gsr & (GSR_PCR | GSR_SCR))) {
221 		printk(KERN_INFO "%s: warm reset timeout (GSR=%#lx)\n",
222 				 __func__, gsr);
223 
224 		return false;
225 	}
226 
227 	return true;
228 }
229 EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_warm_reset);
230 
231 bool pxa2xx_ac97_try_cold_reset(void)
232 {
233 	unsigned long gsr;
234 	unsigned int timeout = 1000;
235 
236 #ifdef CONFIG_PXA25x
237 	if (cpu_is_pxa25x())
238 		pxa_ac97_cold_pxa25x();
239 	else
240 #endif
241 #ifdef CONFIG_PXA27x
242 	if (cpu_is_pxa27x())
243 		pxa_ac97_cold_pxa27x();
244 	else
245 #endif
246 #ifdef CONFIG_PXA3xx
247 	if (cpu_is_pxa3xx())
248 		pxa_ac97_cold_pxa3xx();
249 	else
250 #endif
251 		snd_BUG();
252 
253 	while (!((readl(ac97_reg_base + GSR) | gsr_bits) & (GSR_PCR | GSR_SCR)) && timeout--)
254 		mdelay(1);
255 
256 	gsr = readl(ac97_reg_base + GSR) | gsr_bits;
257 	if (!(gsr & (GSR_PCR | GSR_SCR))) {
258 		printk(KERN_INFO "%s: cold reset timeout (GSR=%#lx)\n",
259 				 __func__, gsr);
260 
261 		return false;
262 	}
263 
264 	return true;
265 }
266 EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_cold_reset);
267 
268 
269 void pxa2xx_ac97_finish_reset(void)
270 {
271 	u32 gcr = readl(ac97_reg_base + GCR);
272 	gcr &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);
273 	gcr |= GCR_SDONE_IE|GCR_CDONE_IE;
274 	writel(gcr, ac97_reg_base + GCR);
275 }
276 EXPORT_SYMBOL_GPL(pxa2xx_ac97_finish_reset);
277 
278 static irqreturn_t pxa2xx_ac97_irq(int irq, void *dev_id)
279 {
280 	long status;
281 
282 	status = readl(ac97_reg_base + GSR);
283 	if (status) {
284 		writel(status, ac97_reg_base + GSR);
285 		gsr_bits |= status;
286 		wake_up(&gsr_wq);
287 
288 		/* Although we don't use those we still need to clear them
289 		   since they tend to spuriously trigger when MMC is used
290 		   (hardware bug? go figure)... */
291 		if (cpu_is_pxa27x()) {
292 			writel(MISR_EOC, ac97_reg_base + MISR);
293 			writel(PISR_EOC, ac97_reg_base + PISR);
294 			writel(MCSR_EOC, ac97_reg_base + MCSR);
295 		}
296 
297 		return IRQ_HANDLED;
298 	}
299 
300 	return IRQ_NONE;
301 }
302 
303 #ifdef CONFIG_PM
304 int pxa2xx_ac97_hw_suspend(void)
305 {
306 	writel(readl(ac97_reg_base + GCR) | (GCR_ACLINK_OFF), ac97_reg_base + GCR);
307 	clk_disable_unprepare(ac97_clk);
308 	return 0;
309 }
310 EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_suspend);
311 
312 int pxa2xx_ac97_hw_resume(void)
313 {
314 	clk_prepare_enable(ac97_clk);
315 	return 0;
316 }
317 EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_resume);
318 #endif
319 
320 int pxa2xx_ac97_hw_probe(struct platform_device *dev)
321 {
322 	int ret;
323 	int irq;
324 	pxa2xx_audio_ops_t *pdata = dev->dev.platform_data;
325 
326 	ac97_reg_base = devm_platform_ioremap_resource(dev, 0);
327 	if (IS_ERR(ac97_reg_base)) {
328 		dev_err(&dev->dev, "Missing MMIO resource\n");
329 		return PTR_ERR(ac97_reg_base);
330 	}
331 
332 	if (pdata) {
333 		switch (pdata->reset_gpio) {
334 		case 95:
335 		case 113:
336 			reset_gpio = pdata->reset_gpio;
337 			break;
338 		case 0:
339 			reset_gpio = 113;
340 			break;
341 		case -1:
342 			break;
343 		default:
344 			dev_err(&dev->dev, "Invalid reset GPIO %d\n",
345 				pdata->reset_gpio);
346 		}
347 	} else if (!pdata && dev->dev.of_node) {
348 		pdata = devm_kzalloc(&dev->dev, sizeof(*pdata), GFP_KERNEL);
349 		if (!pdata)
350 			return -ENOMEM;
351 		pdata->reset_gpio = of_get_named_gpio(dev->dev.of_node,
352 						      "reset-gpios", 0);
353 		if (pdata->reset_gpio == -ENOENT)
354 			pdata->reset_gpio = -1;
355 		else if (pdata->reset_gpio < 0)
356 			return pdata->reset_gpio;
357 		reset_gpio = pdata->reset_gpio;
358 	} else {
359 		if (cpu_is_pxa27x())
360 			reset_gpio = 113;
361 	}
362 
363 	if (cpu_is_pxa27x()) {
364 		/*
365 		 * This gpio is needed for a work-around to a bug in the ac97
366 		 * controller during warm reset.  The direction and level is set
367 		 * here so that it is an output driven high when switching from
368 		 * AC97_nRESET alt function to generic gpio.
369 		 */
370 		ret = gpio_request_one(reset_gpio, GPIOF_OUT_INIT_HIGH,
371 				       "pxa27x ac97 reset");
372 		if (ret < 0) {
373 			pr_err("%s: gpio_request_one() failed: %d\n",
374 			       __func__, ret);
375 			goto err_conf;
376 		}
377 		pxa27x_configure_ac97reset(reset_gpio, false);
378 
379 		ac97conf_clk = clk_get(&dev->dev, "AC97CONFCLK");
380 		if (IS_ERR(ac97conf_clk)) {
381 			ret = PTR_ERR(ac97conf_clk);
382 			ac97conf_clk = NULL;
383 			goto err_conf;
384 		}
385 	}
386 
387 	ac97_clk = clk_get(&dev->dev, "AC97CLK");
388 	if (IS_ERR(ac97_clk)) {
389 		ret = PTR_ERR(ac97_clk);
390 		ac97_clk = NULL;
391 		goto err_clk;
392 	}
393 
394 	ret = clk_prepare_enable(ac97_clk);
395 	if (ret)
396 		goto err_clk2;
397 
398 	irq = platform_get_irq(dev, 0);
399 	if (irq < 0) {
400 		ret = irq;
401 		goto err_irq;
402 	}
403 
404 	ret = request_irq(irq, pxa2xx_ac97_irq, 0, "AC97", NULL);
405 	if (ret < 0)
406 		goto err_irq;
407 
408 	return 0;
409 
410 err_irq:
411 	writel(readl(ac97_reg_base + GCR) | (GCR_ACLINK_OFF), ac97_reg_base + GCR);
412 err_clk2:
413 	clk_put(ac97_clk);
414 	ac97_clk = NULL;
415 err_clk:
416 	if (ac97conf_clk) {
417 		clk_put(ac97conf_clk);
418 		ac97conf_clk = NULL;
419 	}
420 err_conf:
421 	return ret;
422 }
423 EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_probe);
424 
425 void pxa2xx_ac97_hw_remove(struct platform_device *dev)
426 {
427 	if (cpu_is_pxa27x())
428 		gpio_free(reset_gpio);
429 	writel(readl(ac97_reg_base + GCR) | (GCR_ACLINK_OFF), ac97_reg_base + GCR);
430 	free_irq(platform_get_irq(dev, 0), NULL);
431 	if (ac97conf_clk) {
432 		clk_put(ac97conf_clk);
433 		ac97conf_clk = NULL;
434 	}
435 	clk_disable_unprepare(ac97_clk);
436 	clk_put(ac97_clk);
437 	ac97_clk = NULL;
438 }
439 EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_remove);
440 
441 u32 pxa2xx_ac97_read_modr(void)
442 {
443 	if (!ac97_reg_base)
444 		return 0;
445 
446 	return readl(ac97_reg_base + MODR);
447 }
448 EXPORT_SYMBOL_GPL(pxa2xx_ac97_read_modr);
449 
450 u32 pxa2xx_ac97_read_misr(void)
451 {
452 	if (!ac97_reg_base)
453 		return 0;
454 
455 	return readl(ac97_reg_base + MISR);
456 }
457 EXPORT_SYMBOL_GPL(pxa2xx_ac97_read_misr);
458 
459 MODULE_AUTHOR("Nicolas Pitre");
460 MODULE_DESCRIPTION("Intel/Marvell PXA sound library");
461 MODULE_LICENSE("GPL");
462 
463