1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 28 29 #include "dc_types.h" 30 #include "core_types.h" 31 32 #include "include/grph_object_id.h" 33 #include "include/logger_interface.h" 34 35 #include "dce_clock_source.h" 36 #include "clk_mgr.h" 37 #include "dccg.h" 38 39 #include "reg_helper.h" 40 41 #define REG(reg)\ 42 (clk_src->regs->reg) 43 44 #define CTX \ 45 clk_src->base.ctx 46 47 #define DC_LOGGER \ 48 calc_pll_cs->ctx->logger 49 #define DC_LOGGER_INIT() \ 50 struct calc_pll_clock_source *calc_pll_cs = &clk_src->calc_pll 51 52 #undef FN 53 #define FN(reg_name, field_name) \ 54 clk_src->cs_shift->field_name, clk_src->cs_mask->field_name 55 56 #define FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM 6 57 #define CALC_PLL_CLK_SRC_ERR_TOLERANCE 1 58 #define MAX_PLL_CALC_ERROR 0xFFFFFFFF 59 60 #define NUM_ELEMENTS(a) (sizeof(a) / sizeof((a)[0])) 61 62 static const struct spread_spectrum_data *get_ss_data_entry( 63 struct dce110_clk_src *clk_src, 64 enum signal_type signal, 65 uint32_t pix_clk_khz) 66 { 67 68 uint32_t entrys_num; 69 uint32_t i; 70 struct spread_spectrum_data *ss_parm = NULL; 71 struct spread_spectrum_data *ret = NULL; 72 73 switch (signal) { 74 case SIGNAL_TYPE_DVI_SINGLE_LINK: 75 case SIGNAL_TYPE_DVI_DUAL_LINK: 76 ss_parm = clk_src->dvi_ss_params; 77 entrys_num = clk_src->dvi_ss_params_cnt; 78 break; 79 80 case SIGNAL_TYPE_HDMI_TYPE_A: 81 ss_parm = clk_src->hdmi_ss_params; 82 entrys_num = clk_src->hdmi_ss_params_cnt; 83 break; 84 85 case SIGNAL_TYPE_LVDS: 86 ss_parm = clk_src->lvds_ss_params; 87 entrys_num = clk_src->lvds_ss_params_cnt; 88 break; 89 90 case SIGNAL_TYPE_DISPLAY_PORT: 91 case SIGNAL_TYPE_DISPLAY_PORT_MST: 92 case SIGNAL_TYPE_EDP: 93 case SIGNAL_TYPE_VIRTUAL: 94 ss_parm = clk_src->dp_ss_params; 95 entrys_num = clk_src->dp_ss_params_cnt; 96 break; 97 98 default: 99 ss_parm = NULL; 100 entrys_num = 0; 101 break; 102 } 103 104 if (ss_parm == NULL) 105 return ret; 106 107 for (i = 0; i < entrys_num; ++i, ++ss_parm) { 108 if (ss_parm->freq_range_khz >= pix_clk_khz) { 109 ret = ss_parm; 110 break; 111 } 112 } 113 114 return ret; 115 } 116 117 /** 118 * calculate_fb_and_fractional_fb_divider - Calculates feedback and fractional 119 * feedback dividers values 120 * 121 * @calc_pll_cs: Pointer to clock source information 122 * @target_pix_clk_100hz: Desired frequency in 100 Hz 123 * @ref_divider: Reference divider (already known) 124 * @post_divider: Post Divider (already known) 125 * @feedback_divider_param: Pointer where to store 126 * calculated feedback divider value 127 * @fract_feedback_divider_param: Pointer where to store 128 * calculated fract feedback divider value 129 * 130 * return: 131 * It fills the locations pointed by feedback_divider_param 132 * and fract_feedback_divider_param 133 * It returns - true if feedback divider not 0 134 * - false should never happen) 135 */ 136 static bool calculate_fb_and_fractional_fb_divider( 137 struct calc_pll_clock_source *calc_pll_cs, 138 uint32_t target_pix_clk_100hz, 139 uint32_t ref_divider, 140 uint32_t post_divider, 141 uint32_t *feedback_divider_param, 142 uint32_t *fract_feedback_divider_param) 143 { 144 uint64_t feedback_divider; 145 146 feedback_divider = 147 (uint64_t)target_pix_clk_100hz * ref_divider * post_divider; 148 feedback_divider *= 10; 149 /* additional factor, since we divide by 10 afterwards */ 150 feedback_divider *= (uint64_t)(calc_pll_cs->fract_fb_divider_factor); 151 feedback_divider = div_u64(feedback_divider, calc_pll_cs->ref_freq_khz * 10ull); 152 153 /*Round to the number of precision 154 * The following code replace the old code (ullfeedbackDivider + 5)/10 155 * for example if the difference between the number 156 * of fractional feedback decimal point and the fractional FB Divider precision 157 * is 2 then the equation becomes (ullfeedbackDivider + 5*100) / (10*100))*/ 158 159 feedback_divider += 5ULL * 160 calc_pll_cs->fract_fb_divider_precision_factor; 161 feedback_divider = 162 div_u64(feedback_divider, 163 calc_pll_cs->fract_fb_divider_precision_factor * 10); 164 feedback_divider *= (uint64_t) 165 (calc_pll_cs->fract_fb_divider_precision_factor); 166 167 *feedback_divider_param = 168 div_u64_rem( 169 feedback_divider, 170 calc_pll_cs->fract_fb_divider_factor, 171 fract_feedback_divider_param); 172 173 if (*feedback_divider_param != 0) 174 return true; 175 return false; 176 } 177 178 /** 179 * calc_fb_divider_checking_tolerance - Calculates Feedback and 180 * Fractional Feedback divider values 181 * for passed Reference and Post divider, 182 * checking for tolerance. 183 * @calc_pll_cs: Pointer to clock source information 184 * @pll_settings: Pointer to PLL settings 185 * @ref_divider: Reference divider (already known) 186 * @post_divider: Post Divider (already known) 187 * @tolerance: Tolerance for Calculated Pixel Clock to be within 188 * 189 * return: 190 * It fills the PLLSettings structure with PLL Dividers values 191 * if calculated values are within required tolerance 192 * It returns - true if error is within tolerance 193 * - false if error is not within tolerance 194 */ 195 static bool calc_fb_divider_checking_tolerance( 196 struct calc_pll_clock_source *calc_pll_cs, 197 struct pll_settings *pll_settings, 198 uint32_t ref_divider, 199 uint32_t post_divider, 200 uint32_t tolerance) 201 { 202 uint32_t feedback_divider; 203 uint32_t fract_feedback_divider; 204 uint32_t actual_calculated_clock_100hz; 205 uint32_t abs_err; 206 uint64_t actual_calc_clk_100hz; 207 208 calculate_fb_and_fractional_fb_divider( 209 calc_pll_cs, 210 pll_settings->adjusted_pix_clk_100hz, 211 ref_divider, 212 post_divider, 213 &feedback_divider, 214 &fract_feedback_divider); 215 216 /*Actual calculated value*/ 217 actual_calc_clk_100hz = (uint64_t)feedback_divider * 218 calc_pll_cs->fract_fb_divider_factor + 219 fract_feedback_divider; 220 actual_calc_clk_100hz *= (uint64_t)calc_pll_cs->ref_freq_khz * 10; 221 actual_calc_clk_100hz = 222 div_u64(actual_calc_clk_100hz, 223 ref_divider * post_divider * 224 calc_pll_cs->fract_fb_divider_factor); 225 226 actual_calculated_clock_100hz = (uint32_t)(actual_calc_clk_100hz); 227 228 abs_err = (actual_calculated_clock_100hz > 229 pll_settings->adjusted_pix_clk_100hz) 230 ? actual_calculated_clock_100hz - 231 pll_settings->adjusted_pix_clk_100hz 232 : pll_settings->adjusted_pix_clk_100hz - 233 actual_calculated_clock_100hz; 234 235 if (abs_err <= tolerance) { 236 /*found good values*/ 237 pll_settings->reference_freq = calc_pll_cs->ref_freq_khz; 238 pll_settings->reference_divider = ref_divider; 239 pll_settings->feedback_divider = feedback_divider; 240 pll_settings->fract_feedback_divider = fract_feedback_divider; 241 pll_settings->pix_clk_post_divider = post_divider; 242 pll_settings->calculated_pix_clk_100hz = 243 actual_calculated_clock_100hz; 244 pll_settings->vco_freq = 245 div_u64((u64)actual_calculated_clock_100hz * post_divider, 10); 246 return true; 247 } 248 return false; 249 } 250 251 static bool calc_pll_dividers_in_range( 252 struct calc_pll_clock_source *calc_pll_cs, 253 struct pll_settings *pll_settings, 254 uint32_t min_ref_divider, 255 uint32_t max_ref_divider, 256 uint32_t min_post_divider, 257 uint32_t max_post_divider, 258 uint32_t err_tolerance) 259 { 260 uint32_t ref_divider; 261 uint32_t post_divider; 262 uint32_t tolerance; 263 264 /* This is err_tolerance / 10000 = 0.0025 - acceptable error of 0.25% 265 * This is errorTolerance / 10000 = 0.0001 - acceptable error of 0.01%*/ 266 tolerance = (pll_settings->adjusted_pix_clk_100hz * err_tolerance) / 267 100000; 268 if (tolerance < CALC_PLL_CLK_SRC_ERR_TOLERANCE) 269 tolerance = CALC_PLL_CLK_SRC_ERR_TOLERANCE; 270 271 for ( 272 post_divider = max_post_divider; 273 post_divider >= min_post_divider; 274 --post_divider) { 275 for ( 276 ref_divider = min_ref_divider; 277 ref_divider <= max_ref_divider; 278 ++ref_divider) { 279 if (calc_fb_divider_checking_tolerance( 280 calc_pll_cs, 281 pll_settings, 282 ref_divider, 283 post_divider, 284 tolerance)) { 285 return true; 286 } 287 } 288 } 289 290 return false; 291 } 292 293 static uint32_t calculate_pixel_clock_pll_dividers( 294 struct calc_pll_clock_source *calc_pll_cs, 295 struct pll_settings *pll_settings) 296 { 297 uint32_t err_tolerance; 298 uint32_t min_post_divider; 299 uint32_t max_post_divider; 300 uint32_t min_ref_divider; 301 uint32_t max_ref_divider; 302 303 if (pll_settings->adjusted_pix_clk_100hz == 0) { 304 DC_LOG_ERROR( 305 "%s Bad requested pixel clock", __func__); 306 return MAX_PLL_CALC_ERROR; 307 } 308 309 /* 1) Find Post divider ranges */ 310 if (pll_settings->pix_clk_post_divider) { 311 min_post_divider = pll_settings->pix_clk_post_divider; 312 max_post_divider = pll_settings->pix_clk_post_divider; 313 } else { 314 min_post_divider = calc_pll_cs->min_pix_clock_pll_post_divider; 315 if (min_post_divider * pll_settings->adjusted_pix_clk_100hz < 316 calc_pll_cs->min_vco_khz * 10) { 317 min_post_divider = calc_pll_cs->min_vco_khz * 10 / 318 pll_settings->adjusted_pix_clk_100hz; 319 if ((min_post_divider * 320 pll_settings->adjusted_pix_clk_100hz) < 321 calc_pll_cs->min_vco_khz * 10) 322 min_post_divider++; 323 } 324 325 max_post_divider = calc_pll_cs->max_pix_clock_pll_post_divider; 326 if (max_post_divider * pll_settings->adjusted_pix_clk_100hz 327 > calc_pll_cs->max_vco_khz * 10) 328 max_post_divider = calc_pll_cs->max_vco_khz * 10 / 329 pll_settings->adjusted_pix_clk_100hz; 330 } 331 332 /* 2) Find Reference divider ranges 333 * When SS is enabled, or for Display Port even without SS, 334 * pll_settings->referenceDivider is not zero. 335 * So calculate PPLL FB and fractional FB divider 336 * using the passed reference divider*/ 337 338 if (pll_settings->reference_divider) { 339 min_ref_divider = pll_settings->reference_divider; 340 max_ref_divider = pll_settings->reference_divider; 341 } else { 342 min_ref_divider = ((calc_pll_cs->ref_freq_khz 343 / calc_pll_cs->max_pll_input_freq_khz) 344 > calc_pll_cs->min_pll_ref_divider) 345 ? calc_pll_cs->ref_freq_khz 346 / calc_pll_cs->max_pll_input_freq_khz 347 : calc_pll_cs->min_pll_ref_divider; 348 349 max_ref_divider = ((calc_pll_cs->ref_freq_khz 350 / calc_pll_cs->min_pll_input_freq_khz) 351 < calc_pll_cs->max_pll_ref_divider) 352 ? calc_pll_cs->ref_freq_khz / 353 calc_pll_cs->min_pll_input_freq_khz 354 : calc_pll_cs->max_pll_ref_divider; 355 } 356 357 /* If some parameters are invalid we could have scenario when "min">"max" 358 * which produced endless loop later. 359 * We should investigate why we get the wrong parameters. 360 * But to follow the similar logic when "adjustedPixelClock" is set to be 0 361 * it is better to return here than cause system hang/watchdog timeout later. 362 * ## SVS Wed 15 Jul 2009 */ 363 364 if (min_post_divider > max_post_divider) { 365 DC_LOG_ERROR( 366 "%s Post divider range is invalid", __func__); 367 return MAX_PLL_CALC_ERROR; 368 } 369 370 if (min_ref_divider > max_ref_divider) { 371 DC_LOG_ERROR( 372 "%s Reference divider range is invalid", __func__); 373 return MAX_PLL_CALC_ERROR; 374 } 375 376 /* 3) Try to find PLL dividers given ranges 377 * starting with minimal error tolerance. 378 * Increase error tolerance until PLL dividers found*/ 379 err_tolerance = MAX_PLL_CALC_ERROR; 380 381 while (!calc_pll_dividers_in_range( 382 calc_pll_cs, 383 pll_settings, 384 min_ref_divider, 385 max_ref_divider, 386 min_post_divider, 387 max_post_divider, 388 err_tolerance)) 389 err_tolerance += (err_tolerance > 10) 390 ? (err_tolerance / 10) 391 : 1; 392 393 return err_tolerance; 394 } 395 396 static bool pll_adjust_pix_clk( 397 struct dce110_clk_src *clk_src, 398 struct pixel_clk_params *pix_clk_params, 399 struct pll_settings *pll_settings) 400 { 401 uint32_t actual_pix_clk_100hz = 0; 402 uint32_t requested_clk_100hz = 0; 403 struct bp_adjust_pixel_clock_parameters bp_adjust_pixel_clock_params = { 404 0 }; 405 enum bp_result bp_result; 406 switch (pix_clk_params->signal_type) { 407 case SIGNAL_TYPE_HDMI_TYPE_A: { 408 requested_clk_100hz = pix_clk_params->requested_pix_clk_100hz; 409 if (pix_clk_params->pixel_encoding != PIXEL_ENCODING_YCBCR422) { 410 switch (pix_clk_params->color_depth) { 411 case COLOR_DEPTH_101010: 412 requested_clk_100hz = (requested_clk_100hz * 5) >> 2; 413 break; /* x1.25*/ 414 case COLOR_DEPTH_121212: 415 requested_clk_100hz = (requested_clk_100hz * 6) >> 2; 416 break; /* x1.5*/ 417 case COLOR_DEPTH_161616: 418 requested_clk_100hz = requested_clk_100hz * 2; 419 break; /* x2.0*/ 420 default: 421 break; 422 } 423 } 424 actual_pix_clk_100hz = requested_clk_100hz; 425 } 426 break; 427 428 case SIGNAL_TYPE_DISPLAY_PORT: 429 case SIGNAL_TYPE_DISPLAY_PORT_MST: 430 case SIGNAL_TYPE_EDP: 431 requested_clk_100hz = pix_clk_params->requested_sym_clk * 10; 432 actual_pix_clk_100hz = pix_clk_params->requested_pix_clk_100hz; 433 break; 434 435 default: 436 requested_clk_100hz = pix_clk_params->requested_pix_clk_100hz; 437 actual_pix_clk_100hz = pix_clk_params->requested_pix_clk_100hz; 438 break; 439 } 440 441 bp_adjust_pixel_clock_params.pixel_clock = requested_clk_100hz / 10; 442 bp_adjust_pixel_clock_params. 443 encoder_object_id = pix_clk_params->encoder_object_id; 444 bp_adjust_pixel_clock_params.signal_type = pix_clk_params->signal_type; 445 bp_adjust_pixel_clock_params. 446 ss_enable = pix_clk_params->flags.ENABLE_SS; 447 bp_result = clk_src->bios->funcs->adjust_pixel_clock( 448 clk_src->bios, &bp_adjust_pixel_clock_params); 449 if (bp_result == BP_RESULT_OK) { 450 pll_settings->actual_pix_clk_100hz = actual_pix_clk_100hz; 451 pll_settings->adjusted_pix_clk_100hz = 452 bp_adjust_pixel_clock_params.adjusted_pixel_clock * 10; 453 pll_settings->reference_divider = 454 bp_adjust_pixel_clock_params.reference_divider; 455 pll_settings->pix_clk_post_divider = 456 bp_adjust_pixel_clock_params.pixel_clock_post_divider; 457 458 return true; 459 } 460 461 return false; 462 } 463 464 /* 465 * Calculate PLL Dividers for given Clock Value. 466 * First will call VBIOS Adjust Exec table to check if requested Pixel clock 467 * will be Adjusted based on usage. 468 * Then it will calculate PLL Dividers for this Adjusted clock using preferred 469 * method (Maximum VCO frequency). 470 * 471 * \return 472 * Calculation error in units of 0.01% 473 */ 474 475 static uint32_t dce110_get_pix_clk_dividers_helper ( 476 struct dce110_clk_src *clk_src, 477 struct pll_settings *pll_settings, 478 struct pixel_clk_params *pix_clk_params) 479 { 480 uint32_t field = 0; 481 uint32_t pll_calc_error = MAX_PLL_CALC_ERROR; 482 DC_LOGGER_INIT(); 483 /* Check if reference clock is external (not pcie/xtalin) 484 * HW Dce80 spec: 485 * 00 - PCIE_REFCLK, 01 - XTALIN, 02 - GENERICA, 03 - GENERICB 486 * 04 - HSYNCA, 05 - GENLK_CLK, 06 - PCIE_REFCLK, 07 - DVOCLK0 */ 487 REG_GET(PLL_CNTL, PLL_REF_DIV_SRC, &field); 488 pll_settings->use_external_clk = (field > 1); 489 490 /* VBIOS by default enables DP SS (spread on IDCLK) for DCE 8.0 always 491 * (we do not care any more from SI for some older DP Sink which 492 * does not report SS support, no known issues) */ 493 if ((pix_clk_params->flags.ENABLE_SS) || 494 (dc_is_dp_signal(pix_clk_params->signal_type))) { 495 496 const struct spread_spectrum_data *ss_data = get_ss_data_entry( 497 clk_src, 498 pix_clk_params->signal_type, 499 pll_settings->adjusted_pix_clk_100hz / 10); 500 501 if (NULL != ss_data) 502 pll_settings->ss_percentage = ss_data->percentage; 503 } 504 505 /* Check VBIOS AdjustPixelClock Exec table */ 506 if (!pll_adjust_pix_clk(clk_src, pix_clk_params, pll_settings)) { 507 /* Should never happen, ASSERT and fill up values to be able 508 * to continue. */ 509 DC_LOG_ERROR( 510 "%s: Failed to adjust pixel clock!!", __func__); 511 pll_settings->actual_pix_clk_100hz = 512 pix_clk_params->requested_pix_clk_100hz; 513 pll_settings->adjusted_pix_clk_100hz = 514 pix_clk_params->requested_pix_clk_100hz; 515 516 if (dc_is_dp_signal(pix_clk_params->signal_type)) 517 pll_settings->adjusted_pix_clk_100hz = 1000000; 518 } 519 520 /* Calculate Dividers */ 521 if (pix_clk_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A) 522 /*Calculate Dividers by HDMI object, no SS case or SS case */ 523 pll_calc_error = 524 calculate_pixel_clock_pll_dividers( 525 &clk_src->calc_pll_hdmi, 526 pll_settings); 527 else 528 /*Calculate Dividers by default object, no SS case or SS case */ 529 pll_calc_error = 530 calculate_pixel_clock_pll_dividers( 531 &clk_src->calc_pll, 532 pll_settings); 533 534 return pll_calc_error; 535 } 536 537 static void dce112_get_pix_clk_dividers_helper ( 538 struct dce110_clk_src *clk_src, 539 struct pll_settings *pll_settings, 540 struct pixel_clk_params *pix_clk_params) 541 { 542 (void)clk_src; 543 uint32_t actual_pixel_clock_100hz; 544 545 actual_pixel_clock_100hz = pix_clk_params->requested_pix_clk_100hz; 546 /* Calculate Dividers */ 547 if (pix_clk_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A) { 548 switch (pix_clk_params->color_depth) { 549 case COLOR_DEPTH_101010: 550 actual_pixel_clock_100hz = (actual_pixel_clock_100hz * 5) >> 2; 551 actual_pixel_clock_100hz -= actual_pixel_clock_100hz % 10; 552 break; 553 case COLOR_DEPTH_121212: 554 actual_pixel_clock_100hz = (actual_pixel_clock_100hz * 6) >> 2; 555 actual_pixel_clock_100hz -= actual_pixel_clock_100hz % 10; 556 break; 557 case COLOR_DEPTH_161616: 558 actual_pixel_clock_100hz = actual_pixel_clock_100hz * 2; 559 break; 560 default: 561 break; 562 } 563 } 564 pll_settings->actual_pix_clk_100hz = actual_pixel_clock_100hz; 565 pll_settings->adjusted_pix_clk_100hz = actual_pixel_clock_100hz; 566 pll_settings->calculated_pix_clk_100hz = pix_clk_params->requested_pix_clk_100hz; 567 } 568 569 static uint32_t dce110_get_pix_clk_dividers( 570 struct clock_source *cs, 571 struct pixel_clk_params *pix_clk_params, 572 struct pll_settings *pll_settings) 573 { 574 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(cs); 575 uint32_t pll_calc_error = MAX_PLL_CALC_ERROR; 576 DC_LOGGER_INIT(); 577 578 if (pix_clk_params == NULL || pll_settings == NULL 579 || pix_clk_params->requested_pix_clk_100hz == 0) { 580 DC_LOG_ERROR( 581 "%s: Invalid parameters!!\n", __func__); 582 return pll_calc_error; 583 } 584 585 memset(pll_settings, 0, sizeof(*pll_settings)); 586 587 if (cs->id == CLOCK_SOURCE_ID_DP_DTO || 588 cs->id == CLOCK_SOURCE_ID_EXTERNAL) { 589 pll_settings->adjusted_pix_clk_100hz = clk_src->ext_clk_khz * 10; 590 pll_settings->calculated_pix_clk_100hz = clk_src->ext_clk_khz * 10; 591 pll_settings->actual_pix_clk_100hz = 592 pix_clk_params->requested_pix_clk_100hz; 593 return 0; 594 } 595 596 pll_calc_error = dce110_get_pix_clk_dividers_helper(clk_src, 597 pll_settings, pix_clk_params); 598 599 return pll_calc_error; 600 } 601 602 static uint32_t dce112_get_pix_clk_dividers( 603 struct clock_source *cs, 604 struct pixel_clk_params *pix_clk_params, 605 struct pll_settings *pll_settings) 606 { 607 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(cs); 608 DC_LOGGER_INIT(); 609 610 if (pix_clk_params == NULL || pll_settings == NULL 611 || pix_clk_params->requested_pix_clk_100hz == 0) { 612 DC_LOG_ERROR( 613 "%s: Invalid parameters!!\n", __func__); 614 return (uint32_t)-1; 615 } 616 617 memset(pll_settings, 0, sizeof(*pll_settings)); 618 619 if (cs->id == CLOCK_SOURCE_ID_DP_DTO || 620 cs->id == CLOCK_SOURCE_ID_EXTERNAL) { 621 pll_settings->adjusted_pix_clk_100hz = clk_src->ext_clk_khz * 10; 622 pll_settings->calculated_pix_clk_100hz = clk_src->ext_clk_khz * 10; 623 pll_settings->actual_pix_clk_100hz = 624 pix_clk_params->requested_pix_clk_100hz; 625 return (uint32_t)-1; 626 } 627 628 dce112_get_pix_clk_dividers_helper(clk_src, 629 pll_settings, pix_clk_params); 630 631 return 0; 632 } 633 634 static bool disable_spread_spectrum(struct dce110_clk_src *clk_src) 635 { 636 enum bp_result result; 637 struct bp_spread_spectrum_parameters bp_ss_params = {0}; 638 639 bp_ss_params.pll_id = clk_src->base.id; 640 641 /*Call ASICControl to process ATOMBIOS Exec table*/ 642 result = clk_src->bios->funcs->enable_spread_spectrum_on_ppll( 643 clk_src->bios, 644 &bp_ss_params, 645 false); 646 647 return result == BP_RESULT_OK; 648 } 649 650 static bool calculate_ss( 651 const struct pll_settings *pll_settings, 652 const struct spread_spectrum_data *ss_data, 653 struct delta_sigma_data *ds_data) 654 { 655 struct fixed31_32 fb_div; 656 struct fixed31_32 ss_amount; 657 struct fixed31_32 ss_nslip_amount; 658 struct fixed31_32 ss_ds_frac_amount; 659 struct fixed31_32 ss_step_size; 660 struct fixed31_32 modulation_time; 661 662 if (ds_data == NULL) 663 return false; 664 if (ss_data == NULL) 665 return false; 666 if (ss_data->percentage == 0) 667 return false; 668 if (pll_settings == NULL) 669 return false; 670 671 memset(ds_data, 0, sizeof(struct delta_sigma_data)); 672 673 /* compute SS_AMOUNT_FBDIV & SS_AMOUNT_NFRAC_SLIP & SS_AMOUNT_DSFRAC*/ 674 /* 6 decimal point support in fractional feedback divider */ 675 fb_div = dc_fixpt_from_fraction( 676 pll_settings->fract_feedback_divider, 1000000); 677 fb_div = dc_fixpt_add_int(fb_div, pll_settings->feedback_divider); 678 679 ds_data->ds_frac_amount = 0; 680 /*spreadSpectrumPercentage is in the unit of .01%, 681 * so have to divided by 100 * 100*/ 682 ss_amount = dc_fixpt_mul( 683 fb_div, dc_fixpt_from_fraction(ss_data->percentage, 684 100 * (long long)ss_data->percentage_divider)); 685 ds_data->feedback_amount = dc_fixpt_floor(ss_amount); 686 687 ss_nslip_amount = dc_fixpt_sub(ss_amount, 688 dc_fixpt_from_int(ds_data->feedback_amount)); 689 ss_nslip_amount = dc_fixpt_mul_int(ss_nslip_amount, 10); 690 ds_data->nfrac_amount = dc_fixpt_floor(ss_nslip_amount); 691 692 ss_ds_frac_amount = dc_fixpt_sub(ss_nslip_amount, 693 dc_fixpt_from_int(ds_data->nfrac_amount)); 694 ss_ds_frac_amount = dc_fixpt_mul_int(ss_ds_frac_amount, 65536); 695 ds_data->ds_frac_amount = dc_fixpt_floor(ss_ds_frac_amount); 696 697 /* compute SS_STEP_SIZE_DSFRAC */ 698 modulation_time = dc_fixpt_from_fraction( 699 pll_settings->reference_freq * (uint64_t)1000, 700 pll_settings->reference_divider * (uint64_t)ss_data->modulation_freq_hz); 701 702 if (ss_data->flags.CENTER_SPREAD) 703 modulation_time = dc_fixpt_div_int(modulation_time, 4); 704 else 705 modulation_time = dc_fixpt_div_int(modulation_time, 2); 706 707 ss_step_size = dc_fixpt_div(ss_amount, modulation_time); 708 /* SS_STEP_SIZE_DSFRAC_DEC = Int(SS_STEP_SIZE * 2 ^ 16 * 10)*/ 709 ss_step_size = dc_fixpt_mul_int(ss_step_size, 65536 * 10); 710 ds_data->ds_frac_size = dc_fixpt_floor(ss_step_size); 711 712 return true; 713 } 714 715 static bool enable_spread_spectrum( 716 struct dce110_clk_src *clk_src, 717 enum signal_type signal, struct pll_settings *pll_settings) 718 { 719 struct bp_spread_spectrum_parameters bp_params = {0}; 720 struct delta_sigma_data d_s_data; 721 const struct spread_spectrum_data *ss_data = NULL; 722 723 ss_data = get_ss_data_entry( 724 clk_src, 725 signal, 726 pll_settings->calculated_pix_clk_100hz / 10); 727 728 /* Pixel clock PLL has been programmed to generate desired pixel clock, 729 * now enable SS on pixel clock */ 730 /* TODO is it OK to return true not doing anything ??*/ 731 if (ss_data != NULL && pll_settings->ss_percentage != 0) { 732 if (calculate_ss(pll_settings, ss_data, &d_s_data)) { 733 bp_params.ds.feedback_amount = 734 d_s_data.feedback_amount; 735 bp_params.ds.nfrac_amount = 736 d_s_data.nfrac_amount; 737 bp_params.ds.ds_frac_size = d_s_data.ds_frac_size; 738 bp_params.ds_frac_amount = 739 d_s_data.ds_frac_amount; 740 bp_params.flags.DS_TYPE = 1; 741 bp_params.pll_id = clk_src->base.id; 742 bp_params.percentage = ss_data->percentage; 743 if (ss_data->flags.CENTER_SPREAD) 744 bp_params.flags.CENTER_SPREAD = 1; 745 if (ss_data->flags.EXTERNAL_SS) 746 bp_params.flags.EXTERNAL_SS = 1; 747 748 if (BP_RESULT_OK != 749 clk_src->bios->funcs-> 750 enable_spread_spectrum_on_ppll( 751 clk_src->bios, 752 &bp_params, 753 true)) 754 return false; 755 } else 756 return false; 757 } 758 return true; 759 } 760 761 static void dce110_program_pixel_clk_resync( 762 struct dce110_clk_src *clk_src, 763 enum signal_type signal_type, 764 enum dc_color_depth colordepth) 765 { 766 REG_UPDATE(RESYNC_CNTL, 767 DCCG_DEEP_COLOR_CNTL1, 0); 768 /* 769 24 bit mode: TMDS clock = 1.0 x pixel clock (1:1) 770 30 bit mode: TMDS clock = 1.25 x pixel clock (5:4) 771 36 bit mode: TMDS clock = 1.5 x pixel clock (3:2) 772 48 bit mode: TMDS clock = 2 x pixel clock (2:1) 773 */ 774 if (signal_type != SIGNAL_TYPE_HDMI_TYPE_A) 775 return; 776 777 switch (colordepth) { 778 case COLOR_DEPTH_888: 779 REG_UPDATE(RESYNC_CNTL, 780 DCCG_DEEP_COLOR_CNTL1, 0); 781 break; 782 case COLOR_DEPTH_101010: 783 REG_UPDATE(RESYNC_CNTL, 784 DCCG_DEEP_COLOR_CNTL1, 1); 785 break; 786 case COLOR_DEPTH_121212: 787 REG_UPDATE(RESYNC_CNTL, 788 DCCG_DEEP_COLOR_CNTL1, 2); 789 break; 790 case COLOR_DEPTH_161616: 791 REG_UPDATE(RESYNC_CNTL, 792 DCCG_DEEP_COLOR_CNTL1, 3); 793 break; 794 default: 795 break; 796 } 797 } 798 799 static void dce112_program_pixel_clk_resync( 800 struct dce110_clk_src *clk_src, 801 enum signal_type signal_type, 802 enum dc_color_depth colordepth, 803 bool enable_ycbcr420) 804 { 805 uint32_t deep_color_cntl = 0; 806 uint32_t double_rate_enable = 0; 807 808 /* 809 24 bit mode: TMDS clock = 1.0 x pixel clock (1:1) 810 30 bit mode: TMDS clock = 1.25 x pixel clock (5:4) 811 36 bit mode: TMDS clock = 1.5 x pixel clock (3:2) 812 48 bit mode: TMDS clock = 2 x pixel clock (2:1) 813 */ 814 if (signal_type == SIGNAL_TYPE_HDMI_TYPE_A) { 815 double_rate_enable = enable_ycbcr420 ? 1 : 0; 816 817 switch (colordepth) { 818 case COLOR_DEPTH_888: 819 deep_color_cntl = 0; 820 break; 821 case COLOR_DEPTH_101010: 822 deep_color_cntl = 1; 823 break; 824 case COLOR_DEPTH_121212: 825 deep_color_cntl = 2; 826 break; 827 case COLOR_DEPTH_161616: 828 deep_color_cntl = 3; 829 break; 830 default: 831 break; 832 } 833 } 834 835 if (clk_src->cs_mask->PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE) 836 REG_UPDATE_2(PIXCLK_RESYNC_CNTL, 837 PHYPLLA_DCCG_DEEP_COLOR_CNTL, deep_color_cntl, 838 PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, double_rate_enable); 839 else 840 REG_UPDATE(PIXCLK_RESYNC_CNTL, 841 PHYPLLA_DCCG_DEEP_COLOR_CNTL, deep_color_cntl); 842 843 } 844 845 static bool dce110_program_pix_clk( 846 struct clock_source *clock_source, 847 struct pixel_clk_params *pix_clk_params, 848 enum dp_link_encoding encoding, 849 struct pll_settings *pll_settings) 850 { 851 (void)encoding; 852 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source); 853 struct bp_pixel_clock_parameters bp_pc_params = {0}; 854 855 /* First disable SS 856 * ATOMBIOS will enable by default SS on PLL for DP, 857 * do not disable it here 858 */ 859 if (clock_source->id != CLOCK_SOURCE_ID_EXTERNAL && 860 !dc_is_dp_signal(pix_clk_params->signal_type) && 861 clock_source->ctx->dce_version <= DCE_VERSION_11_0) 862 disable_spread_spectrum(clk_src); 863 864 /*ATOMBIOS expects pixel rate adjusted by deep color ratio)*/ 865 bp_pc_params.controller_id = pix_clk_params->controller_id; 866 bp_pc_params.pll_id = clock_source->id; 867 bp_pc_params.target_pixel_clock_100hz = pll_settings->actual_pix_clk_100hz; 868 bp_pc_params.encoder_object_id = pix_clk_params->encoder_object_id; 869 bp_pc_params.signal_type = pix_clk_params->signal_type; 870 871 bp_pc_params.reference_divider = pll_settings->reference_divider; 872 bp_pc_params.feedback_divider = pll_settings->feedback_divider; 873 bp_pc_params.fractional_feedback_divider = 874 pll_settings->fract_feedback_divider; 875 bp_pc_params.pixel_clock_post_divider = 876 pll_settings->pix_clk_post_divider; 877 bp_pc_params.flags.SET_EXTERNAL_REF_DIV_SRC = 878 pll_settings->use_external_clk; 879 880 switch (pix_clk_params->color_depth) { 881 case COLOR_DEPTH_101010: 882 bp_pc_params.color_depth = TRANSMITTER_COLOR_DEPTH_30; 883 break; 884 case COLOR_DEPTH_121212: 885 bp_pc_params.color_depth = TRANSMITTER_COLOR_DEPTH_36; 886 break; 887 case COLOR_DEPTH_161616: 888 bp_pc_params.color_depth = TRANSMITTER_COLOR_DEPTH_48; 889 break; 890 default: 891 break; 892 } 893 894 if (clk_src->bios->funcs->set_pixel_clock( 895 clk_src->bios, &bp_pc_params) != BP_RESULT_OK) 896 return false; 897 /* Enable SS 898 * ATOMBIOS will enable by default SS for DP on PLL ( DP ID clock), 899 * based on HW display PLL team, SS control settings should be programmed 900 * during PLL Reset, but they do not have effect 901 * until SS_EN is asserted.*/ 902 if (clock_source->id != CLOCK_SOURCE_ID_EXTERNAL 903 && !dc_is_dp_signal(pix_clk_params->signal_type)) { 904 905 if (pix_clk_params->flags.ENABLE_SS) 906 if (!enable_spread_spectrum(clk_src, 907 pix_clk_params->signal_type, 908 pll_settings)) 909 return false; 910 911 /* Resync deep color DTO */ 912 dce110_program_pixel_clk_resync(clk_src, 913 pix_clk_params->signal_type, 914 pix_clk_params->color_depth); 915 } 916 917 return true; 918 } 919 920 static bool dce112_program_pix_clk( 921 struct clock_source *clock_source, 922 struct pixel_clk_params *pix_clk_params, 923 enum dp_link_encoding encoding, 924 struct pll_settings *pll_settings) 925 { 926 (void)encoding; 927 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source); 928 struct bp_pixel_clock_parameters bp_pc_params = {0}; 929 930 /* First disable SS 931 * ATOMBIOS will enable by default SS on PLL for DP, 932 * do not disable it here 933 */ 934 if (clock_source->id != CLOCK_SOURCE_ID_EXTERNAL && 935 !dc_is_dp_signal(pix_clk_params->signal_type) && 936 clock_source->ctx->dce_version <= DCE_VERSION_11_0) 937 disable_spread_spectrum(clk_src); 938 939 /*ATOMBIOS expects pixel rate adjusted by deep color ratio)*/ 940 bp_pc_params.controller_id = pix_clk_params->controller_id; 941 bp_pc_params.pll_id = clock_source->id; 942 bp_pc_params.target_pixel_clock_100hz = pll_settings->actual_pix_clk_100hz; 943 bp_pc_params.encoder_object_id = pix_clk_params->encoder_object_id; 944 bp_pc_params.signal_type = pix_clk_params->signal_type; 945 946 if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO) { 947 bp_pc_params.flags.SET_GENLOCK_REF_DIV_SRC = 948 pll_settings->use_external_clk; 949 bp_pc_params.flags.SET_XTALIN_REF_SRC = 950 !pll_settings->use_external_clk; 951 if (pix_clk_params->flags.SUPPORT_YCBCR420) { 952 bp_pc_params.flags.SUPPORT_YUV_420 = 1; 953 } 954 } 955 if (clk_src->bios->funcs->set_pixel_clock( 956 clk_src->bios, &bp_pc_params) != BP_RESULT_OK) 957 return false; 958 /* Resync deep color DTO */ 959 if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO) 960 dce112_program_pixel_clk_resync(clk_src, 961 pix_clk_params->signal_type, 962 pix_clk_params->color_depth, 963 pix_clk_params->flags.SUPPORT_YCBCR420); 964 965 return true; 966 } 967 968 static bool dcn31_program_pix_clk( 969 struct clock_source *clock_source, 970 struct pixel_clk_params *pix_clk_params, 971 enum dp_link_encoding encoding, 972 struct pll_settings *pll_settings) 973 { 974 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source); 975 unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0; 976 unsigned int dp_dto_ref_khz = clock_source->ctx->dc->clk_mgr->dprefclk_khz; 977 const struct pixel_rate_range_table_entry *e = 978 look_up_in_video_optimized_rate_tlb(pix_clk_params->requested_pix_clk_100hz / 10); 979 struct bp_pixel_clock_parameters bp_pc_params = {0}; 980 enum transmitter_color_depth bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_24; 981 982 // Apply ssed(spread spectrum) dpref clock for edp and dp 983 if (clock_source->ctx->dc->clk_mgr->dp_dto_source_clock_in_khz != 0 && 984 dc_is_dp_signal(pix_clk_params->signal_type) && 985 encoding == DP_8b_10b_ENCODING) 986 dp_dto_ref_khz = clock_source->ctx->dc->clk_mgr->dp_dto_source_clock_in_khz; 987 988 // For these signal types Driver to program DP_DTO without calling VBIOS Command table 989 if (dc_is_dp_signal(pix_clk_params->signal_type) || dc_is_virtual_signal(pix_clk_params->signal_type)) { 990 if (e) { 991 /* Set DTO values: phase = target clock, modulo = reference clock*/ 992 REG_WRITE(PHASE[inst], e->target_pixel_rate_khz * e->mult_factor); 993 REG_WRITE(MODULO[inst], dp_dto_ref_khz * e->div_factor); 994 } else { 995 /* Set DTO values: phase = target clock, modulo = reference clock*/ 996 REG_WRITE(PHASE[inst], pll_settings->actual_pix_clk_100hz * 100); 997 REG_WRITE(MODULO[inst], dp_dto_ref_khz * 1000); 998 } 999 /* Enable DTO */ 1000 if (clk_src->cs_mask->PIPE0_DTO_SRC_SEL) 1001 if (encoding == DP_128b_132b_ENCODING) 1002 REG_UPDATE_2(PIXEL_RATE_CNTL[inst], 1003 DP_DTO0_ENABLE, 1, 1004 PIPE0_DTO_SRC_SEL, 2); 1005 else 1006 REG_UPDATE_2(PIXEL_RATE_CNTL[inst], 1007 DP_DTO0_ENABLE, 1, 1008 PIPE0_DTO_SRC_SEL, 1); 1009 else 1010 REG_UPDATE(PIXEL_RATE_CNTL[inst], 1011 DP_DTO0_ENABLE, 1); 1012 } else { 1013 1014 if (clk_src->cs_mask->PIPE0_DTO_SRC_SEL) 1015 REG_UPDATE(PIXEL_RATE_CNTL[inst], 1016 PIPE0_DTO_SRC_SEL, 0); 1017 1018 /*ATOMBIOS expects pixel rate adjusted by deep color ratio)*/ 1019 bp_pc_params.controller_id = pix_clk_params->controller_id; 1020 bp_pc_params.pll_id = clock_source->id; 1021 bp_pc_params.target_pixel_clock_100hz = pll_settings->actual_pix_clk_100hz; 1022 bp_pc_params.encoder_object_id = pix_clk_params->encoder_object_id; 1023 bp_pc_params.signal_type = pix_clk_params->signal_type; 1024 1025 // Make sure we send the correct color depth to DMUB for HDMI 1026 if (pix_clk_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A) { 1027 switch (pix_clk_params->color_depth) { 1028 case COLOR_DEPTH_888: 1029 bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_24; 1030 break; 1031 case COLOR_DEPTH_101010: 1032 bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_30; 1033 break; 1034 case COLOR_DEPTH_121212: 1035 bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_36; 1036 break; 1037 case COLOR_DEPTH_161616: 1038 bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_48; 1039 break; 1040 default: 1041 bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_24; 1042 break; 1043 } 1044 bp_pc_params.color_depth = bp_pc_colour_depth; 1045 } 1046 1047 if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO) { 1048 bp_pc_params.flags.SET_GENLOCK_REF_DIV_SRC = 1049 pll_settings->use_external_clk; 1050 bp_pc_params.flags.SET_XTALIN_REF_SRC = 1051 !pll_settings->use_external_clk; 1052 if (pix_clk_params->flags.SUPPORT_YCBCR420) { 1053 bp_pc_params.flags.SUPPORT_YUV_420 = 1; 1054 } 1055 } 1056 if (clk_src->bios->funcs->set_pixel_clock( 1057 clk_src->bios, &bp_pc_params) != BP_RESULT_OK) 1058 return false; 1059 /* Resync deep color DTO */ 1060 if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO) 1061 dce112_program_pixel_clk_resync(clk_src, 1062 pix_clk_params->signal_type, 1063 pix_clk_params->color_depth, 1064 pix_clk_params->flags.SUPPORT_YCBCR420); 1065 } 1066 1067 return true; 1068 } 1069 1070 static bool dcn401_program_pix_clk( 1071 struct clock_source *clock_source, 1072 struct pixel_clk_params *pix_clk_params, 1073 enum dp_link_encoding encoding, 1074 struct pll_settings *pll_settings) 1075 { 1076 (void)encoding; 1077 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source); 1078 unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0; 1079 const struct pixel_rate_range_table_entry *e = 1080 look_up_in_video_optimized_rate_tlb(pix_clk_params->requested_pix_clk_100hz / 10); 1081 struct bp_pixel_clock_parameters bp_pc_params = {0}; 1082 enum transmitter_color_depth bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_24; 1083 struct dp_dto_params dto_params = { 0 }; 1084 1085 dto_params.otg_inst = inst; 1086 dto_params.signal = pix_clk_params->signal_type; 1087 1088 // all but TMDS gets Driver to program DP_DTO without calling VBIOS Command table 1089 if (!dc_is_tmds_signal(pix_clk_params->signal_type)) { 1090 long long dtbclk_p_src_clk_khz; 1091 1092 dtbclk_p_src_clk_khz = clock_source->ctx->dc->clk_mgr->dprefclk_khz; 1093 dto_params.clk_src = DPREFCLK; 1094 1095 if (e) { 1096 dto_params.pixclk_hz = e->target_pixel_rate_khz; 1097 dto_params.pixclk_hz *= e->mult_factor; 1098 dto_params.refclk_hz = dtbclk_p_src_clk_khz; 1099 dto_params.refclk_hz *= e->div_factor; 1100 } else { 1101 dto_params.pixclk_hz = pix_clk_params->requested_pix_clk_100hz; 1102 dto_params.pixclk_hz *= 100; 1103 dto_params.refclk_hz = dtbclk_p_src_clk_khz; 1104 dto_params.refclk_hz *= 1000; 1105 } 1106 1107 /* enable DP DTO */ 1108 clock_source->ctx->dc->res_pool->dccg->funcs->set_dp_dto( 1109 clock_source->ctx->dc->res_pool->dccg, 1110 &dto_params); 1111 1112 } else { 1113 if (pll_settings->actual_pix_clk_100hz > 6000000UL) 1114 return false; 1115 1116 /* disables DP DTO when provided with TMDS signal type */ 1117 clock_source->ctx->dc->res_pool->dccg->funcs->set_dp_dto( 1118 clock_source->ctx->dc->res_pool->dccg, 1119 &dto_params); 1120 1121 /*ATOMBIOS expects pixel rate adjusted by deep color ratio)*/ 1122 bp_pc_params.controller_id = pix_clk_params->controller_id; 1123 bp_pc_params.pll_id = clock_source->id; 1124 bp_pc_params.target_pixel_clock_100hz = pll_settings->actual_pix_clk_100hz; 1125 bp_pc_params.encoder_object_id = pix_clk_params->encoder_object_id; 1126 bp_pc_params.signal_type = pix_clk_params->signal_type; 1127 1128 // Make sure we send the correct color depth to DMUB for HDMI 1129 if (pix_clk_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A) { 1130 switch (pix_clk_params->color_depth) { 1131 case COLOR_DEPTH_888: 1132 bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_24; 1133 break; 1134 case COLOR_DEPTH_101010: 1135 bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_30; 1136 break; 1137 case COLOR_DEPTH_121212: 1138 bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_36; 1139 break; 1140 case COLOR_DEPTH_161616: 1141 bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_48; 1142 break; 1143 default: 1144 bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_24; 1145 break; 1146 } 1147 bp_pc_params.color_depth = bp_pc_colour_depth; 1148 } 1149 1150 if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO) { 1151 bp_pc_params.flags.SET_GENLOCK_REF_DIV_SRC = 1152 pll_settings->use_external_clk; 1153 bp_pc_params.flags.SET_XTALIN_REF_SRC = 1154 !pll_settings->use_external_clk; 1155 if (pix_clk_params->flags.SUPPORT_YCBCR420) { 1156 bp_pc_params.flags.SUPPORT_YUV_420 = 1; 1157 } 1158 } 1159 if (clk_src->bios->funcs->set_pixel_clock( 1160 clk_src->bios, &bp_pc_params) != BP_RESULT_OK) 1161 return false; 1162 /* Resync deep color DTO */ 1163 if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO) 1164 dce112_program_pixel_clk_resync(clk_src, 1165 pix_clk_params->signal_type, 1166 pix_clk_params->color_depth, 1167 pix_clk_params->flags.SUPPORT_YCBCR420); 1168 } 1169 1170 return true; 1171 } 1172 1173 static bool dce110_clock_source_power_down( 1174 struct clock_source *clk_src) 1175 { 1176 struct dce110_clk_src *dce110_clk_src = TO_DCE110_CLK_SRC(clk_src); 1177 enum bp_result bp_result; 1178 struct bp_pixel_clock_parameters bp_pixel_clock_params = {0}; 1179 1180 if (clk_src->dp_clk_src) 1181 return true; 1182 1183 /* If Pixel Clock is 0 it means Power Down Pll*/ 1184 bp_pixel_clock_params.controller_id = CONTROLLER_ID_UNDEFINED; 1185 bp_pixel_clock_params.pll_id = clk_src->id; 1186 bp_pixel_clock_params.flags.FORCE_PROGRAMMING_OF_PLL = 1; 1187 1188 /*Call ASICControl to process ATOMBIOS Exec table*/ 1189 bp_result = dce110_clk_src->bios->funcs->set_pixel_clock( 1190 dce110_clk_src->bios, 1191 &bp_pixel_clock_params); 1192 1193 return bp_result == BP_RESULT_OK; 1194 } 1195 1196 static bool get_pixel_clk_frequency_100hz( 1197 const struct clock_source *clock_source, 1198 unsigned int inst, 1199 unsigned int *pixel_clk_khz) 1200 { 1201 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source); 1202 unsigned int clock_hz = 0; 1203 unsigned int modulo_hz = 0; 1204 unsigned int dp_dto_ref_khz = clock_source->ctx->dc->clk_mgr->dprefclk_khz; 1205 1206 if (clock_source->id == CLOCK_SOURCE_ID_DP_DTO) { 1207 clock_hz = REG_READ(PHASE[inst]); 1208 1209 if (clock_source->ctx->dc->hwss.enable_vblanks_synchronization && 1210 clock_source->ctx->dc->config.vblank_alignment_max_frame_time_diff > 0) { 1211 /* NOTE: In case VBLANK syncronization is enabled, MODULO may 1212 * not be programmed equal to DPREFCLK 1213 */ 1214 modulo_hz = REG_READ(MODULO[inst]); 1215 if (modulo_hz) 1216 *pixel_clk_khz = div_u64((uint64_t)clock_hz* 1217 dp_dto_ref_khz*10, 1218 modulo_hz); 1219 else 1220 *pixel_clk_khz = 0; 1221 } else { 1222 /* NOTE: There is agreement with VBIOS here that MODULO is 1223 * programmed equal to DPREFCLK, in which case PHASE will be 1224 * equivalent to pixel clock. 1225 */ 1226 *pixel_clk_khz = clock_hz / 100; 1227 } 1228 return true; 1229 } 1230 1231 return false; 1232 } 1233 1234 /* this table is use to find *1.001 and /1.001 pixel rates from non-precise pixel rate */ 1235 const struct pixel_rate_range_table_entry video_optimized_pixel_rates[] = { 1236 // /1.001 rates 1237 {25170, 25180, 25200, 1000, 1001}, //25.2MHz -> 25.17 1238 {59340, 59350, 59400, 1000, 1001}, //59.4Mhz -> 59.340 1239 {74170, 74180, 74250, 1000, 1001}, //74.25Mhz -> 74.1758 1240 {89910, 90000, 90000, 1000, 1001}, //90Mhz -> 89.91 1241 {125870, 125880, 126000, 1000, 1001}, //126Mhz -> 125.87 1242 {148350, 148360, 148500, 1000, 1001}, //148.5Mhz -> 148.3516 1243 {167830, 167840, 168000, 1000, 1001}, //168Mhz -> 167.83 1244 {222520, 222530, 222750, 1000, 1001}, //222.75Mhz -> 222.527 1245 {257140, 257150, 257400, 1000, 1001}, //257.4Mhz -> 257.1429 1246 {296700, 296710, 297000, 1000, 1001}, //297Mhz -> 296.7033 1247 {342850, 342860, 343200, 1000, 1001}, //343.2Mhz -> 342.857 1248 {395600, 395610, 396000, 1000, 1001}, //396Mhz -> 395.6 1249 {409090, 409100, 409500, 1000, 1001}, //409.5Mhz -> 409.091 1250 {445050, 445060, 445500, 1000, 1001}, //445.5Mhz -> 445.055 1251 {467530, 467540, 468000, 1000, 1001}, //468Mhz -> 467.5325 1252 {519230, 519240, 519750, 1000, 1001}, //519.75Mhz -> 519.231 1253 {525970, 525980, 526500, 1000, 1001}, //526.5Mhz -> 525.974 1254 {545450, 545460, 546000, 1000, 1001}, //546Mhz -> 545.455 1255 {593400, 593410, 594000, 1000, 1001}, //594Mhz -> 593.4066 1256 {623370, 623380, 624000, 1000, 1001}, //624Mhz -> 623.377 1257 {692300, 692310, 693000, 1000, 1001}, //693Mhz -> 692.308 1258 {701290, 701300, 702000, 1000, 1001}, //702Mhz -> 701.2987 1259 {791200, 791210, 792000, 1000, 1001}, //792Mhz -> 791.209 1260 {890100, 890110, 891000, 1000, 1001}, //891Mhz -> 890.1099 1261 {1186810, 1186820, 1188000, 1000, 1001},//1188Mhz -> 1186.8131 1262 1263 // *1.001 rates 1264 {27020, 27030, 27000, 1001, 1000}, //27Mhz 1265 {54050, 54060, 54000, 1001, 1000}, //54Mhz 1266 {108100, 108110, 108000, 1001, 1000},//108Mhz 1267 }; 1268 1269 const struct pixel_rate_range_table_entry *look_up_in_video_optimized_rate_tlb( 1270 unsigned int pixel_rate_khz) 1271 { 1272 int i; 1273 1274 for (i = 0; i < NUM_ELEMENTS(video_optimized_pixel_rates); i++) { 1275 const struct pixel_rate_range_table_entry *e = &video_optimized_pixel_rates[i]; 1276 1277 if (e->range_min_khz <= pixel_rate_khz && pixel_rate_khz <= e->range_max_khz) { 1278 return e; 1279 } 1280 } 1281 1282 return NULL; 1283 } 1284 1285 static bool dcn20_program_pix_clk( 1286 struct clock_source *clock_source, 1287 struct pixel_clk_params *pix_clk_params, 1288 enum dp_link_encoding encoding, 1289 struct pll_settings *pll_settings) 1290 { 1291 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source); 1292 unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0; 1293 1294 dce112_program_pix_clk(clock_source, pix_clk_params, encoding, pll_settings); 1295 1296 if (clock_source->ctx->dc->hwss.enable_vblanks_synchronization && 1297 clock_source->ctx->dc->config.vblank_alignment_max_frame_time_diff > 0) { 1298 /* NOTE: In case VBLANK syncronization is enabled, 1299 * we need to set modulo to default DPREFCLK first 1300 * dce112_program_pix_clk does not set default DPREFCLK 1301 */ 1302 REG_WRITE(MODULO[inst], 1303 clock_source->ctx->dc->clk_mgr->dprefclk_khz*1000); 1304 } 1305 return true; 1306 } 1307 1308 static bool dcn20_override_dp_pix_clk( 1309 struct clock_source *clock_source, 1310 unsigned int inst, 1311 unsigned int pixel_clk, 1312 unsigned int ref_clk) 1313 { 1314 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source); 1315 1316 REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 0); 1317 REG_WRITE(PHASE[inst], pixel_clk); 1318 REG_WRITE(MODULO[inst], ref_clk); 1319 REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1); 1320 return true; 1321 } 1322 1323 static const struct clock_source_funcs dcn20_clk_src_funcs = { 1324 .cs_power_down = dce110_clock_source_power_down, 1325 .program_pix_clk = dcn20_program_pix_clk, 1326 .get_pix_clk_dividers = dce112_get_pix_clk_dividers, 1327 .get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz, 1328 .override_dp_pix_clk = dcn20_override_dp_pix_clk 1329 }; 1330 1331 static bool dcn3_program_pix_clk( 1332 struct clock_source *clock_source, 1333 struct pixel_clk_params *pix_clk_params, 1334 enum dp_link_encoding encoding, 1335 struct pll_settings *pll_settings) 1336 { 1337 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source); 1338 unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0; 1339 unsigned int dp_dto_ref_khz = clock_source->ctx->dc->clk_mgr->dprefclk_khz; 1340 const struct pixel_rate_range_table_entry *e = 1341 look_up_in_video_optimized_rate_tlb(pix_clk_params->requested_pix_clk_100hz / 10); 1342 1343 // For these signal types Driver to program DP_DTO without calling VBIOS Command table 1344 if (dc_is_dp_signal(pix_clk_params->signal_type)) { 1345 if (e) { 1346 /* Set DTO values: phase = target clock, modulo = reference clock*/ 1347 REG_WRITE(PHASE[inst], e->target_pixel_rate_khz * e->mult_factor); 1348 REG_WRITE(MODULO[inst], dp_dto_ref_khz * e->div_factor); 1349 } else { 1350 /* Set DTO values: phase = target clock, modulo = reference clock*/ 1351 REG_WRITE(PHASE[inst], pll_settings->actual_pix_clk_100hz * 100); 1352 REG_WRITE(MODULO[inst], dp_dto_ref_khz * 1000); 1353 } 1354 /* Enable DTO */ 1355 if (clk_src->cs_mask->PIPE0_DTO_SRC_SEL) 1356 REG_UPDATE_2(PIXEL_RATE_CNTL[inst], 1357 DP_DTO0_ENABLE, 1, 1358 PIPE0_DTO_SRC_SEL, 1); 1359 else 1360 REG_UPDATE(PIXEL_RATE_CNTL[inst], 1361 DP_DTO0_ENABLE, 1); 1362 } else 1363 // For other signal types(HDMI_TYPE_A, DVI) Driver still to call VBIOS Command table 1364 dce112_program_pix_clk(clock_source, pix_clk_params, encoding, pll_settings); 1365 1366 return true; 1367 } 1368 1369 static uint32_t dcn3_get_pix_clk_dividers( 1370 struct clock_source *cs, 1371 struct pixel_clk_params *pix_clk_params, 1372 struct pll_settings *pll_settings) 1373 { 1374 unsigned long long actual_pix_clk_100Hz = pix_clk_params ? pix_clk_params->requested_pix_clk_100hz : 0; 1375 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(cs); 1376 1377 DC_LOGGER_INIT(); 1378 1379 if (pix_clk_params == NULL || pll_settings == NULL 1380 || pix_clk_params->requested_pix_clk_100hz == 0) { 1381 DC_LOG_ERROR( 1382 "%s: Invalid parameters!!\n", __func__); 1383 return UINT_MAX; 1384 } 1385 1386 memset(pll_settings, 0, sizeof(*pll_settings)); 1387 /* Adjust for HDMI Type A deep color */ 1388 if (pix_clk_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A) { 1389 switch (pix_clk_params->color_depth) { 1390 case COLOR_DEPTH_101010: 1391 actual_pix_clk_100Hz = (actual_pix_clk_100Hz * 5) >> 2; 1392 break; 1393 case COLOR_DEPTH_121212: 1394 actual_pix_clk_100Hz = (actual_pix_clk_100Hz * 6) >> 2; 1395 break; 1396 case COLOR_DEPTH_161616: 1397 actual_pix_clk_100Hz = actual_pix_clk_100Hz * 2; 1398 break; 1399 default: 1400 break; 1401 } 1402 } 1403 pll_settings->actual_pix_clk_100hz = (unsigned int) actual_pix_clk_100Hz; 1404 pll_settings->adjusted_pix_clk_100hz = (unsigned int) actual_pix_clk_100Hz; 1405 pll_settings->calculated_pix_clk_100hz = (unsigned int) actual_pix_clk_100Hz; 1406 1407 return 0; 1408 } 1409 1410 static const struct clock_source_funcs dcn3_clk_src_funcs = { 1411 .cs_power_down = dce110_clock_source_power_down, 1412 .program_pix_clk = dcn3_program_pix_clk, 1413 .get_pix_clk_dividers = dcn3_get_pix_clk_dividers, 1414 .get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz 1415 }; 1416 1417 static const struct clock_source_funcs dcn31_clk_src_funcs = { 1418 .cs_power_down = dce110_clock_source_power_down, 1419 .program_pix_clk = dcn31_program_pix_clk, 1420 .get_pix_clk_dividers = dcn3_get_pix_clk_dividers, 1421 .get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz 1422 }; 1423 1424 static const struct clock_source_funcs dcn401_clk_src_funcs = { 1425 .cs_power_down = dce110_clock_source_power_down, 1426 .program_pix_clk = dcn401_program_pix_clk, 1427 .get_pix_clk_dividers = dcn3_get_pix_clk_dividers, 1428 .get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz 1429 }; 1430 1431 /*****************************************/ 1432 /* Constructor */ 1433 /*****************************************/ 1434 1435 static const struct clock_source_funcs dce112_clk_src_funcs = { 1436 .cs_power_down = dce110_clock_source_power_down, 1437 .program_pix_clk = dce112_program_pix_clk, 1438 .get_pix_clk_dividers = dce112_get_pix_clk_dividers, 1439 .get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz 1440 }; 1441 static const struct clock_source_funcs dce110_clk_src_funcs = { 1442 .cs_power_down = dce110_clock_source_power_down, 1443 .program_pix_clk = dce110_program_pix_clk, 1444 .get_pix_clk_dividers = dce110_get_pix_clk_dividers, 1445 .get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz 1446 }; 1447 1448 1449 static void get_ss_info_from_atombios( 1450 struct dce110_clk_src *clk_src, 1451 enum as_signal_type as_signal, 1452 struct spread_spectrum_data *spread_spectrum_data[], 1453 uint32_t *ss_entries_num) 1454 { 1455 enum bp_result bp_result = BP_RESULT_FAILURE; 1456 struct spread_spectrum_info *ss_info; 1457 struct spread_spectrum_data *ss_data; 1458 struct spread_spectrum_info *ss_info_cur; 1459 struct spread_spectrum_data *ss_data_cur; 1460 uint32_t i; 1461 DC_LOGGER_INIT(); 1462 if (ss_entries_num == NULL) { 1463 DC_LOG_SYNC( 1464 "Invalid entry !!!\n"); 1465 return; 1466 } 1467 if (spread_spectrum_data == NULL) { 1468 DC_LOG_SYNC( 1469 "Invalid array pointer!!!\n"); 1470 return; 1471 } 1472 1473 spread_spectrum_data[0] = NULL; 1474 *ss_entries_num = 0; 1475 1476 *ss_entries_num = clk_src->bios->funcs->get_ss_entry_number( 1477 clk_src->bios, 1478 as_signal); 1479 1480 if (*ss_entries_num == 0) 1481 return; 1482 1483 ss_info = kzalloc_objs(struct spread_spectrum_info, *ss_entries_num); 1484 ss_info_cur = ss_info; 1485 if (ss_info == NULL) 1486 return; 1487 1488 ss_data = kzalloc_objs(struct spread_spectrum_data, *ss_entries_num); 1489 if (ss_data == NULL) 1490 goto out_free_info; 1491 1492 for (i = 0, ss_info_cur = ss_info; 1493 i < (*ss_entries_num); 1494 ++i, ++ss_info_cur) { 1495 1496 bp_result = clk_src->bios->funcs->get_spread_spectrum_info( 1497 clk_src->bios, 1498 as_signal, 1499 i, 1500 ss_info_cur); 1501 1502 if (bp_result != BP_RESULT_OK) 1503 goto out_free_data; 1504 } 1505 1506 for (i = 0, ss_info_cur = ss_info, ss_data_cur = ss_data; 1507 i < (*ss_entries_num); 1508 ++i, ++ss_info_cur, ++ss_data_cur) { 1509 1510 if (ss_info_cur->type.STEP_AND_DELAY_INFO != false) { 1511 DC_LOG_SYNC( 1512 "Invalid ATOMBIOS SS Table!!!\n"); 1513 goto out_free_data; 1514 } 1515 1516 /* for HDMI check SS percentage, 1517 * if it is > 6 (0.06%), the ATOMBIOS table info is invalid*/ 1518 if (as_signal == AS_SIGNAL_TYPE_HDMI 1519 && ss_info_cur->spread_spectrum_percentage > 6){ 1520 /* invalid input, do nothing */ 1521 DC_LOG_SYNC( 1522 "Invalid SS percentage "); 1523 DC_LOG_SYNC( 1524 "for HDMI in ATOMBIOS info Table!!!\n"); 1525 continue; 1526 } 1527 if (ss_info_cur->spread_percentage_divider == 1000) { 1528 /* Keep previous precision from ATOMBIOS for these 1529 * in case new precision set by ATOMBIOS for these 1530 * (otherwise all code in DCE specific classes 1531 * for all previous ASICs would need 1532 * to be updated for SS calculations, 1533 * Audio SS compensation and DP DTO SS compensation 1534 * which assumes fixed SS percentage Divider = 100)*/ 1535 ss_info_cur->spread_spectrum_percentage /= 10; 1536 ss_info_cur->spread_percentage_divider = 100; 1537 } 1538 1539 ss_data_cur->freq_range_khz = ss_info_cur->target_clock_range; 1540 ss_data_cur->percentage = 1541 ss_info_cur->spread_spectrum_percentage; 1542 ss_data_cur->percentage_divider = 1543 ss_info_cur->spread_percentage_divider; 1544 ss_data_cur->modulation_freq_hz = 1545 ss_info_cur->spread_spectrum_range; 1546 1547 if (ss_info_cur->type.CENTER_MODE) 1548 ss_data_cur->flags.CENTER_SPREAD = 1; 1549 1550 if (ss_info_cur->type.EXTERNAL) 1551 ss_data_cur->flags.EXTERNAL_SS = 1; 1552 1553 } 1554 1555 *spread_spectrum_data = ss_data; 1556 kfree(ss_info); 1557 return; 1558 1559 out_free_data: 1560 kfree(ss_data); 1561 *ss_entries_num = 0; 1562 out_free_info: 1563 kfree(ss_info); 1564 } 1565 1566 static void ss_info_from_atombios_create( 1567 struct dce110_clk_src *clk_src) 1568 { 1569 get_ss_info_from_atombios( 1570 clk_src, 1571 AS_SIGNAL_TYPE_DISPLAY_PORT, 1572 &clk_src->dp_ss_params, 1573 &clk_src->dp_ss_params_cnt); 1574 get_ss_info_from_atombios( 1575 clk_src, 1576 AS_SIGNAL_TYPE_HDMI, 1577 &clk_src->hdmi_ss_params, 1578 &clk_src->hdmi_ss_params_cnt); 1579 get_ss_info_from_atombios( 1580 clk_src, 1581 AS_SIGNAL_TYPE_DVI, 1582 &clk_src->dvi_ss_params, 1583 &clk_src->dvi_ss_params_cnt); 1584 get_ss_info_from_atombios( 1585 clk_src, 1586 AS_SIGNAL_TYPE_LVDS, 1587 &clk_src->lvds_ss_params, 1588 &clk_src->lvds_ss_params_cnt); 1589 } 1590 1591 static bool calc_pll_max_vco_construct( 1592 struct calc_pll_clock_source *calc_pll_cs, 1593 struct calc_pll_clock_source_init_data *init_data) 1594 { 1595 uint32_t i; 1596 struct dc_firmware_info *fw_info; 1597 if (calc_pll_cs == NULL || 1598 init_data == NULL || 1599 init_data->bp == NULL) 1600 return false; 1601 1602 if (!init_data->bp->fw_info_valid) 1603 return false; 1604 1605 fw_info = &init_data->bp->fw_info; 1606 calc_pll_cs->ctx = init_data->ctx; 1607 calc_pll_cs->ref_freq_khz = fw_info->pll_info.crystal_frequency; 1608 calc_pll_cs->min_vco_khz = 1609 fw_info->pll_info.min_output_pxl_clk_pll_frequency; 1610 calc_pll_cs->max_vco_khz = 1611 fw_info->pll_info.max_output_pxl_clk_pll_frequency; 1612 1613 if (init_data->max_override_input_pxl_clk_pll_freq_khz != 0) 1614 calc_pll_cs->max_pll_input_freq_khz = 1615 init_data->max_override_input_pxl_clk_pll_freq_khz; 1616 else 1617 calc_pll_cs->max_pll_input_freq_khz = 1618 fw_info->pll_info.max_input_pxl_clk_pll_frequency; 1619 1620 if (init_data->min_override_input_pxl_clk_pll_freq_khz != 0) 1621 calc_pll_cs->min_pll_input_freq_khz = 1622 init_data->min_override_input_pxl_clk_pll_freq_khz; 1623 else 1624 calc_pll_cs->min_pll_input_freq_khz = 1625 fw_info->pll_info.min_input_pxl_clk_pll_frequency; 1626 1627 calc_pll_cs->min_pix_clock_pll_post_divider = 1628 init_data->min_pix_clk_pll_post_divider; 1629 calc_pll_cs->max_pix_clock_pll_post_divider = 1630 init_data->max_pix_clk_pll_post_divider; 1631 calc_pll_cs->min_pll_ref_divider = 1632 init_data->min_pll_ref_divider; 1633 calc_pll_cs->max_pll_ref_divider = 1634 init_data->max_pll_ref_divider; 1635 1636 if (init_data->num_fract_fb_divider_decimal_point == 0 || 1637 init_data->num_fract_fb_divider_decimal_point_precision > 1638 init_data->num_fract_fb_divider_decimal_point) { 1639 DC_LOG_ERROR( 1640 "The dec point num or precision is incorrect!"); 1641 return false; 1642 } 1643 if (init_data->num_fract_fb_divider_decimal_point_precision == 0) { 1644 DC_LOG_ERROR( 1645 "Incorrect fract feedback divider precision num!"); 1646 return false; 1647 } 1648 1649 calc_pll_cs->fract_fb_divider_decimal_points_num = 1650 init_data->num_fract_fb_divider_decimal_point; 1651 calc_pll_cs->fract_fb_divider_precision = 1652 init_data->num_fract_fb_divider_decimal_point_precision; 1653 calc_pll_cs->fract_fb_divider_factor = 1; 1654 for (i = 0; i < calc_pll_cs->fract_fb_divider_decimal_points_num; ++i) 1655 calc_pll_cs->fract_fb_divider_factor *= 10; 1656 1657 calc_pll_cs->fract_fb_divider_precision_factor = 1; 1658 for ( 1659 i = 0; 1660 i < (calc_pll_cs->fract_fb_divider_decimal_points_num - 1661 calc_pll_cs->fract_fb_divider_precision); 1662 ++i) 1663 calc_pll_cs->fract_fb_divider_precision_factor *= 10; 1664 1665 return true; 1666 } 1667 1668 bool dce110_clk_src_construct( 1669 struct dce110_clk_src *clk_src, 1670 struct dc_context *ctx, 1671 struct dc_bios *bios, 1672 enum clock_source_id id, 1673 const struct dce110_clk_src_regs *regs, 1674 const struct dce110_clk_src_shift *cs_shift, 1675 const struct dce110_clk_src_mask *cs_mask) 1676 { 1677 struct calc_pll_clock_source_init_data calc_pll_cs_init_data_hdmi; 1678 struct calc_pll_clock_source_init_data calc_pll_cs_init_data; 1679 1680 clk_src->base.ctx = ctx; 1681 clk_src->bios = bios; 1682 clk_src->base.id = id; 1683 clk_src->base.funcs = &dce110_clk_src_funcs; 1684 1685 clk_src->regs = regs; 1686 clk_src->cs_shift = cs_shift; 1687 clk_src->cs_mask = cs_mask; 1688 1689 if (!clk_src->bios->fw_info_valid) { 1690 ASSERT_CRITICAL(false); 1691 goto unexpected_failure; 1692 } 1693 1694 clk_src->ext_clk_khz = clk_src->bios->fw_info.external_clock_source_frequency_for_dp; 1695 1696 /* structure normally used with PLL ranges from ATOMBIOS; DS on by default */ 1697 calc_pll_cs_init_data.bp = bios; 1698 calc_pll_cs_init_data.min_pix_clk_pll_post_divider = 1; 1699 calc_pll_cs_init_data.max_pix_clk_pll_post_divider = 1700 clk_src->cs_mask->PLL_POST_DIV_PIXCLK; 1701 calc_pll_cs_init_data.min_pll_ref_divider = 1; 1702 calc_pll_cs_init_data.max_pll_ref_divider = clk_src->cs_mask->PLL_REF_DIV; 1703 /* when 0 use minInputPxlClkPLLFrequencyInKHz from firmwareInfo*/ 1704 calc_pll_cs_init_data.min_override_input_pxl_clk_pll_freq_khz = 0; 1705 /* when 0 use maxInputPxlClkPLLFrequencyInKHz from firmwareInfo*/ 1706 calc_pll_cs_init_data.max_override_input_pxl_clk_pll_freq_khz = 0; 1707 /*numberOfFractFBDividerDecimalPoints*/ 1708 calc_pll_cs_init_data.num_fract_fb_divider_decimal_point = 1709 FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM; 1710 /*number of decimal point to round off for fractional feedback divider value*/ 1711 calc_pll_cs_init_data.num_fract_fb_divider_decimal_point_precision = 1712 FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM; 1713 calc_pll_cs_init_data.ctx = ctx; 1714 1715 /*structure for HDMI, no SS or SS% <= 0.06% for 27 MHz Ref clock */ 1716 calc_pll_cs_init_data_hdmi.bp = bios; 1717 calc_pll_cs_init_data_hdmi.min_pix_clk_pll_post_divider = 1; 1718 calc_pll_cs_init_data_hdmi.max_pix_clk_pll_post_divider = 1719 clk_src->cs_mask->PLL_POST_DIV_PIXCLK; 1720 calc_pll_cs_init_data_hdmi.min_pll_ref_divider = 1; 1721 calc_pll_cs_init_data_hdmi.max_pll_ref_divider = clk_src->cs_mask->PLL_REF_DIV; 1722 /* when 0 use minInputPxlClkPLLFrequencyInKHz from firmwareInfo*/ 1723 calc_pll_cs_init_data_hdmi.min_override_input_pxl_clk_pll_freq_khz = 13500; 1724 /* when 0 use maxInputPxlClkPLLFrequencyInKHz from firmwareInfo*/ 1725 calc_pll_cs_init_data_hdmi.max_override_input_pxl_clk_pll_freq_khz = 27000; 1726 /*numberOfFractFBDividerDecimalPoints*/ 1727 calc_pll_cs_init_data_hdmi.num_fract_fb_divider_decimal_point = 1728 FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM; 1729 /*number of decimal point to round off for fractional feedback divider value*/ 1730 calc_pll_cs_init_data_hdmi.num_fract_fb_divider_decimal_point_precision = 1731 FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM; 1732 calc_pll_cs_init_data_hdmi.ctx = ctx; 1733 1734 clk_src->ref_freq_khz = clk_src->bios->fw_info.pll_info.crystal_frequency; 1735 1736 if (clk_src->base.id == CLOCK_SOURCE_ID_EXTERNAL) 1737 return true; 1738 1739 /* PLL only from here on */ 1740 ss_info_from_atombios_create(clk_src); 1741 1742 if (!calc_pll_max_vco_construct( 1743 &clk_src->calc_pll, 1744 &calc_pll_cs_init_data)) { 1745 ASSERT_CRITICAL(false); 1746 goto unexpected_failure; 1747 } 1748 1749 1750 calc_pll_cs_init_data_hdmi. 1751 min_override_input_pxl_clk_pll_freq_khz = clk_src->ref_freq_khz/2; 1752 calc_pll_cs_init_data_hdmi. 1753 max_override_input_pxl_clk_pll_freq_khz = clk_src->ref_freq_khz; 1754 1755 1756 if (!calc_pll_max_vco_construct( 1757 &clk_src->calc_pll_hdmi, &calc_pll_cs_init_data_hdmi)) { 1758 ASSERT_CRITICAL(false); 1759 goto unexpected_failure; 1760 } 1761 1762 return true; 1763 1764 unexpected_failure: 1765 return false; 1766 } 1767 1768 bool dce112_clk_src_construct( 1769 struct dce110_clk_src *clk_src, 1770 struct dc_context *ctx, 1771 struct dc_bios *bios, 1772 enum clock_source_id id, 1773 const struct dce110_clk_src_regs *regs, 1774 const struct dce110_clk_src_shift *cs_shift, 1775 const struct dce110_clk_src_mask *cs_mask) 1776 { 1777 clk_src->base.ctx = ctx; 1778 clk_src->bios = bios; 1779 clk_src->base.id = id; 1780 clk_src->base.funcs = &dce112_clk_src_funcs; 1781 1782 clk_src->regs = regs; 1783 clk_src->cs_shift = cs_shift; 1784 clk_src->cs_mask = cs_mask; 1785 1786 if (!clk_src->bios->fw_info_valid) { 1787 ASSERT_CRITICAL(false); 1788 return false; 1789 } 1790 1791 clk_src->ext_clk_khz = clk_src->bios->fw_info.external_clock_source_frequency_for_dp; 1792 1793 return true; 1794 } 1795 1796 bool dcn20_clk_src_construct( 1797 struct dce110_clk_src *clk_src, 1798 struct dc_context *ctx, 1799 struct dc_bios *bios, 1800 enum clock_source_id id, 1801 const struct dce110_clk_src_regs *regs, 1802 const struct dce110_clk_src_shift *cs_shift, 1803 const struct dce110_clk_src_mask *cs_mask) 1804 { 1805 bool ret = dce112_clk_src_construct(clk_src, ctx, bios, id, regs, cs_shift, cs_mask); 1806 1807 clk_src->base.funcs = &dcn20_clk_src_funcs; 1808 1809 return ret; 1810 } 1811 1812 bool dcn3_clk_src_construct( 1813 struct dce110_clk_src *clk_src, 1814 struct dc_context *ctx, 1815 struct dc_bios *bios, 1816 enum clock_source_id id, 1817 const struct dce110_clk_src_regs *regs, 1818 const struct dce110_clk_src_shift *cs_shift, 1819 const struct dce110_clk_src_mask *cs_mask) 1820 { 1821 bool ret = dce112_clk_src_construct(clk_src, ctx, bios, id, regs, cs_shift, cs_mask); 1822 1823 clk_src->base.funcs = &dcn3_clk_src_funcs; 1824 1825 return ret; 1826 } 1827 1828 bool dcn31_clk_src_construct( 1829 struct dce110_clk_src *clk_src, 1830 struct dc_context *ctx, 1831 struct dc_bios *bios, 1832 enum clock_source_id id, 1833 const struct dce110_clk_src_regs *regs, 1834 const struct dce110_clk_src_shift *cs_shift, 1835 const struct dce110_clk_src_mask *cs_mask) 1836 { 1837 bool ret = dce112_clk_src_construct(clk_src, ctx, bios, id, regs, cs_shift, cs_mask); 1838 1839 clk_src->base.funcs = &dcn31_clk_src_funcs; 1840 1841 return ret; 1842 } 1843 1844 bool dcn401_clk_src_construct( 1845 struct dce110_clk_src *clk_src, 1846 struct dc_context *ctx, 1847 struct dc_bios *bios, 1848 enum clock_source_id id, 1849 const struct dce110_clk_src_regs *regs, 1850 const struct dce110_clk_src_shift *cs_shift, 1851 const struct dce110_clk_src_mask *cs_mask) 1852 { 1853 bool ret = dce112_clk_src_construct(clk_src, ctx, bios, id, regs, cs_shift, cs_mask); 1854 1855 clk_src->base.funcs = &dcn401_clk_src_funcs; 1856 1857 return ret; 1858 } 1859 bool dcn301_clk_src_construct( 1860 struct dce110_clk_src *clk_src, 1861 struct dc_context *ctx, 1862 struct dc_bios *bios, 1863 enum clock_source_id id, 1864 const struct dce110_clk_src_regs *regs, 1865 const struct dce110_clk_src_shift *cs_shift, 1866 const struct dce110_clk_src_mask *cs_mask) 1867 { 1868 bool ret = dce112_clk_src_construct(clk_src, ctx, bios, id, regs, cs_shift, cs_mask); 1869 1870 clk_src->base.funcs = &dcn3_clk_src_funcs; 1871 1872 return ret; 1873 } 1874