1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2013-2014 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
5 *
6 * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved.
7 */
8
9 #include "adreno_gpu.h"
10 #include "a6xx_gpu.h"
11 #include "a6xx.xml.h"
12 #include "a6xx_gmu.xml.h"
13
14 static const struct adreno_reglist a612_hwcg[] = {
15 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222},
16 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
17 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000081},
18 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf},
19 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},
20 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
21 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
22 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
23 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
24 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
25 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
26 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
27 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
28 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
29 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
30 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
31 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
32 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01202222},
33 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
34 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00},
35 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05522022},
36 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
37 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
38 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
39 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
40 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
41 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x02222222},
42 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
43 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
44 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
45 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
46 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
47 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
48 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
49 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
50 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
51 {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
52 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
53 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
54 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
55 {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
56 {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
57 {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
58 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
59 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
60 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
61 {},
62 };
63
64 /* For a615 family (a615, a616, a618 and a619) */
65 static const struct adreno_reglist a615_hwcg[] = {
66 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
67 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
68 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
69 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
70 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
71 {REG_A6XX_RBBM_CLOCK_CNTL_TP1, 0x02222222},
72 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
73 {REG_A6XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222},
74 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
75 {REG_A6XX_RBBM_CLOCK_CNTL3_TP1, 0x22222222},
76 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
77 {REG_A6XX_RBBM_CLOCK_CNTL4_TP1, 0x00022222},
78 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
79 {REG_A6XX_RBBM_CLOCK_HYST_TP1, 0x77777777},
80 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
81 {REG_A6XX_RBBM_CLOCK_HYST2_TP1, 0x77777777},
82 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
83 {REG_A6XX_RBBM_CLOCK_HYST3_TP1, 0x77777777},
84 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
85 {REG_A6XX_RBBM_CLOCK_HYST4_TP1, 0x00077777},
86 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
87 {REG_A6XX_RBBM_CLOCK_DELAY_TP1, 0x11111111},
88 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
89 {REG_A6XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111},
90 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
91 {REG_A6XX_RBBM_CLOCK_DELAY3_TP1, 0x11111111},
92 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
93 {REG_A6XX_RBBM_CLOCK_DELAY4_TP1, 0x00011111},
94 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
95 {REG_A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222},
96 {REG_A6XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222},
97 {REG_A6XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222},
98 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
99 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
100 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
101 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x00002222},
102 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002020},
103 {REG_A6XX_RBBM_CLOCK_CNTL_CCU1, 0x00002220},
104 {REG_A6XX_RBBM_CLOCK_CNTL_CCU2, 0x00002220},
105 {REG_A6XX_RBBM_CLOCK_CNTL_CCU3, 0x00002220},
106 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
107 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1, 0x00040F00},
108 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2, 0x00040F00},
109 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3, 0x00040F00},
110 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05022022},
111 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
112 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
113 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
114 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
115 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
116 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
117 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
118 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
119 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
120 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
121 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
122 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
123 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
124 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
125 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
126 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
127 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
128 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
129 {},
130 };
131
132 static const struct adreno_reglist a620_hwcg[] = {
133 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
134 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
135 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
136 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf},
137 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
138 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
139 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
140 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
141 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
142 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
143 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
144 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
145 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
146 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
147 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
148 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
149 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
150 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
151 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
152 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00},
153 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022},
154 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
155 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
156 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
157 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
158 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
159 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
160 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
161 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
162 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
163 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
164 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
165 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
166 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
167 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
168 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
169 {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
170 {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
171 {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
172 {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000777},
173 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
174 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
175 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
176 {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
177 {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
178 {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
179 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
180 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
181 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
182 {},
183 };
184
185 static const struct adreno_reglist a630_hwcg[] = {
186 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222},
187 {REG_A6XX_RBBM_CLOCK_CNTL_SP1, 0x22222222},
188 {REG_A6XX_RBBM_CLOCK_CNTL_SP2, 0x22222222},
189 {REG_A6XX_RBBM_CLOCK_CNTL_SP3, 0x22222222},
190 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02022220},
191 {REG_A6XX_RBBM_CLOCK_CNTL2_SP1, 0x02022220},
192 {REG_A6XX_RBBM_CLOCK_CNTL2_SP2, 0x02022220},
193 {REG_A6XX_RBBM_CLOCK_CNTL2_SP3, 0x02022220},
194 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
195 {REG_A6XX_RBBM_CLOCK_DELAY_SP1, 0x00000080},
196 {REG_A6XX_RBBM_CLOCK_DELAY_SP2, 0x00000080},
197 {REG_A6XX_RBBM_CLOCK_DELAY_SP3, 0x00000080},
198 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf},
199 {REG_A6XX_RBBM_CLOCK_HYST_SP1, 0x0000f3cf},
200 {REG_A6XX_RBBM_CLOCK_HYST_SP2, 0x0000f3cf},
201 {REG_A6XX_RBBM_CLOCK_HYST_SP3, 0x0000f3cf},
202 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
203 {REG_A6XX_RBBM_CLOCK_CNTL_TP1, 0x02222222},
204 {REG_A6XX_RBBM_CLOCK_CNTL_TP2, 0x02222222},
205 {REG_A6XX_RBBM_CLOCK_CNTL_TP3, 0x02222222},
206 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
207 {REG_A6XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222},
208 {REG_A6XX_RBBM_CLOCK_CNTL2_TP2, 0x22222222},
209 {REG_A6XX_RBBM_CLOCK_CNTL2_TP3, 0x22222222},
210 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
211 {REG_A6XX_RBBM_CLOCK_CNTL3_TP1, 0x22222222},
212 {REG_A6XX_RBBM_CLOCK_CNTL3_TP2, 0x22222222},
213 {REG_A6XX_RBBM_CLOCK_CNTL3_TP3, 0x22222222},
214 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
215 {REG_A6XX_RBBM_CLOCK_CNTL4_TP1, 0x00022222},
216 {REG_A6XX_RBBM_CLOCK_CNTL4_TP2, 0x00022222},
217 {REG_A6XX_RBBM_CLOCK_CNTL4_TP3, 0x00022222},
218 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
219 {REG_A6XX_RBBM_CLOCK_HYST_TP1, 0x77777777},
220 {REG_A6XX_RBBM_CLOCK_HYST_TP2, 0x77777777},
221 {REG_A6XX_RBBM_CLOCK_HYST_TP3, 0x77777777},
222 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
223 {REG_A6XX_RBBM_CLOCK_HYST2_TP1, 0x77777777},
224 {REG_A6XX_RBBM_CLOCK_HYST2_TP2, 0x77777777},
225 {REG_A6XX_RBBM_CLOCK_HYST2_TP3, 0x77777777},
226 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
227 {REG_A6XX_RBBM_CLOCK_HYST3_TP1, 0x77777777},
228 {REG_A6XX_RBBM_CLOCK_HYST3_TP2, 0x77777777},
229 {REG_A6XX_RBBM_CLOCK_HYST3_TP3, 0x77777777},
230 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
231 {REG_A6XX_RBBM_CLOCK_HYST4_TP1, 0x00077777},
232 {REG_A6XX_RBBM_CLOCK_HYST4_TP2, 0x00077777},
233 {REG_A6XX_RBBM_CLOCK_HYST4_TP3, 0x00077777},
234 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
235 {REG_A6XX_RBBM_CLOCK_DELAY_TP1, 0x11111111},
236 {REG_A6XX_RBBM_CLOCK_DELAY_TP2, 0x11111111},
237 {REG_A6XX_RBBM_CLOCK_DELAY_TP3, 0x11111111},
238 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
239 {REG_A6XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111},
240 {REG_A6XX_RBBM_CLOCK_DELAY2_TP2, 0x11111111},
241 {REG_A6XX_RBBM_CLOCK_DELAY2_TP3, 0x11111111},
242 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
243 {REG_A6XX_RBBM_CLOCK_DELAY3_TP1, 0x11111111},
244 {REG_A6XX_RBBM_CLOCK_DELAY3_TP2, 0x11111111},
245 {REG_A6XX_RBBM_CLOCK_DELAY3_TP3, 0x11111111},
246 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
247 {REG_A6XX_RBBM_CLOCK_DELAY4_TP1, 0x00011111},
248 {REG_A6XX_RBBM_CLOCK_DELAY4_TP2, 0x00011111},
249 {REG_A6XX_RBBM_CLOCK_DELAY4_TP3, 0x00011111},
250 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
251 {REG_A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222},
252 {REG_A6XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222},
253 {REG_A6XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222},
254 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
255 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
256 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
257 {REG_A6XX_RBBM_CLOCK_CNTL_RB1, 0x22222222},
258 {REG_A6XX_RBBM_CLOCK_CNTL_RB2, 0x22222222},
259 {REG_A6XX_RBBM_CLOCK_CNTL_RB3, 0x22222222},
260 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x00002222},
261 {REG_A6XX_RBBM_CLOCK_CNTL2_RB1, 0x00002222},
262 {REG_A6XX_RBBM_CLOCK_CNTL2_RB2, 0x00002222},
263 {REG_A6XX_RBBM_CLOCK_CNTL2_RB3, 0x00002222},
264 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
265 {REG_A6XX_RBBM_CLOCK_CNTL_CCU1, 0x00002220},
266 {REG_A6XX_RBBM_CLOCK_CNTL_CCU2, 0x00002220},
267 {REG_A6XX_RBBM_CLOCK_CNTL_CCU3, 0x00002220},
268 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00},
269 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1, 0x00040f00},
270 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2, 0x00040f00},
271 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3, 0x00040f00},
272 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05022022},
273 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
274 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
275 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
276 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
277 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
278 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
279 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
280 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
281 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
282 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
283 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
284 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
285 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
286 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
287 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
288 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
289 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
290 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
291 {},
292 };
293
294 static const struct adreno_reglist a640_hwcg[] = {
295 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
296 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
297 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
298 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
299 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
300 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
301 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
302 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
303 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
304 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
305 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
306 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
307 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
308 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
309 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
310 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
311 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
312 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
313 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
314 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
315 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05222022},
316 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
317 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
318 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
319 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
320 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
321 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
322 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
323 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
324 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
325 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
326 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
327 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
328 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
329 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
330 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
331 {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
332 {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
333 {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
334 {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000},
335 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
336 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
337 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
338 {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
339 {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
340 {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
341 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
342 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
343 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
344 {},
345 };
346
347 static const struct adreno_reglist a650_hwcg[] = {
348 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
349 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
350 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
351 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
352 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
353 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
354 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
355 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
356 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
357 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
358 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
359 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
360 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
361 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
362 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
363 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
364 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
365 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
366 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
367 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
368 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022},
369 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
370 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
371 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
372 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
373 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
374 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
375 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
376 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
377 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
378 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
379 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
380 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
381 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
382 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
383 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
384 {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
385 {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
386 {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
387 {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000777},
388 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
389 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
390 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
391 {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
392 {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
393 {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
394 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
395 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
396 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
397 {},
398 };
399
400 static const struct adreno_reglist a660_hwcg[] = {
401 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
402 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
403 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
404 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
405 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},
406 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
407 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
408 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
409 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
410 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
411 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
412 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
413 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
414 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
415 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
416 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
417 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
418 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
419 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
420 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
421 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022},
422 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
423 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
424 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
425 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
426 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
427 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
428 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
429 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
430 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
431 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
432 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
433 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
434 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
435 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
436 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
437 {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
438 {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
439 {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
440 {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000},
441 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
442 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
443 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
444 {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
445 {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
446 {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
447 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
448 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
449 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
450 {},
451 };
452
453 static const struct adreno_reglist a690_hwcg[] = {
454 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
455 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
456 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
457 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
458 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},
459 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
460 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
461 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
462 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
463 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
464 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
465 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
466 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
467 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
468 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
469 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
470 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
471 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
472 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
473 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
474 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022},
475 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
476 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
477 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
478 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
479 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
480 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
481 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
482 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
483 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
484 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
485 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
486 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
487 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
488 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
489 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
490 {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
491 {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
492 {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
493 {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000},
494 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
495 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
496 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
497 {REG_A6XX_RBBM_CLOCK_CNTL, 0x8AA8AA82},
498 {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
499 {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
500 {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
501 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
502 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
503 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
504 {REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL, 0x10111},
505 {REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL, 0x5555},
506 {}
507 };
508
509 /* For a615, a616, a618, a619, a630, a640 and a680 */
510 static const u32 a630_protect_regs[] = {
511 A6XX_PROTECT_RDONLY(0x00000, 0x04ff),
512 A6XX_PROTECT_RDONLY(0x00501, 0x0005),
513 A6XX_PROTECT_RDONLY(0x0050b, 0x02f4),
514 A6XX_PROTECT_NORDWR(0x0050e, 0x0000),
515 A6XX_PROTECT_NORDWR(0x00510, 0x0000),
516 A6XX_PROTECT_NORDWR(0x00534, 0x0000),
517 A6XX_PROTECT_NORDWR(0x00800, 0x0082),
518 A6XX_PROTECT_NORDWR(0x008a0, 0x0008),
519 A6XX_PROTECT_NORDWR(0x008ab, 0x0024),
520 A6XX_PROTECT_RDONLY(0x008de, 0x00ae),
521 A6XX_PROTECT_NORDWR(0x00900, 0x004d),
522 A6XX_PROTECT_NORDWR(0x0098d, 0x0272),
523 A6XX_PROTECT_NORDWR(0x00e00, 0x0001),
524 A6XX_PROTECT_NORDWR(0x00e03, 0x000c),
525 A6XX_PROTECT_NORDWR(0x03c00, 0x00c3),
526 A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff),
527 A6XX_PROTECT_NORDWR(0x08630, 0x01cf),
528 A6XX_PROTECT_NORDWR(0x08e00, 0x0000),
529 A6XX_PROTECT_NORDWR(0x08e08, 0x0000),
530 A6XX_PROTECT_NORDWR(0x08e50, 0x001f),
531 A6XX_PROTECT_NORDWR(0x09624, 0x01db),
532 A6XX_PROTECT_NORDWR(0x09e70, 0x0001),
533 A6XX_PROTECT_NORDWR(0x09e78, 0x0187),
534 A6XX_PROTECT_NORDWR(0x0a630, 0x01cf),
535 A6XX_PROTECT_NORDWR(0x0ae02, 0x0000),
536 A6XX_PROTECT_NORDWR(0x0ae50, 0x032f),
537 A6XX_PROTECT_NORDWR(0x0b604, 0x0000),
538 A6XX_PROTECT_NORDWR(0x0be02, 0x0001),
539 A6XX_PROTECT_NORDWR(0x0be20, 0x17df),
540 A6XX_PROTECT_NORDWR(0x0f000, 0x0bff),
541 A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
542 A6XX_PROTECT_NORDWR(0x11c00, 0x0000), /* note: infinite range */
543 };
544 DECLARE_ADRENO_PROTECT(a630_protect, 32);
545
546 static const u32 a650_protect_regs[] = {
547 A6XX_PROTECT_RDONLY(0x00000, 0x04ff),
548 A6XX_PROTECT_RDONLY(0x00501, 0x0005),
549 A6XX_PROTECT_RDONLY(0x0050b, 0x02f4),
550 A6XX_PROTECT_NORDWR(0x0050e, 0x0000),
551 A6XX_PROTECT_NORDWR(0x00510, 0x0000),
552 A6XX_PROTECT_NORDWR(0x00534, 0x0000),
553 A6XX_PROTECT_NORDWR(0x00800, 0x0082),
554 A6XX_PROTECT_NORDWR(0x008a0, 0x0008),
555 A6XX_PROTECT_NORDWR(0x008ab, 0x0024),
556 A6XX_PROTECT_RDONLY(0x008de, 0x00ae),
557 A6XX_PROTECT_NORDWR(0x00900, 0x004d),
558 A6XX_PROTECT_NORDWR(0x0098d, 0x0272),
559 A6XX_PROTECT_NORDWR(0x00e00, 0x0001),
560 A6XX_PROTECT_NORDWR(0x00e03, 0x000c),
561 A6XX_PROTECT_NORDWR(0x03c00, 0x00c3),
562 A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff),
563 A6XX_PROTECT_NORDWR(0x08630, 0x01cf),
564 A6XX_PROTECT_NORDWR(0x08e00, 0x0000),
565 A6XX_PROTECT_NORDWR(0x08e08, 0x0000),
566 A6XX_PROTECT_NORDWR(0x08e50, 0x001f),
567 A6XX_PROTECT_NORDWR(0x08e80, 0x027f),
568 A6XX_PROTECT_NORDWR(0x09624, 0x01db),
569 A6XX_PROTECT_NORDWR(0x09e60, 0x0011),
570 A6XX_PROTECT_NORDWR(0x09e78, 0x0187),
571 A6XX_PROTECT_NORDWR(0x0a630, 0x01cf),
572 A6XX_PROTECT_NORDWR(0x0ae02, 0x0000),
573 A6XX_PROTECT_NORDWR(0x0ae50, 0x032f),
574 A6XX_PROTECT_NORDWR(0x0b604, 0x0000),
575 A6XX_PROTECT_NORDWR(0x0b608, 0x0007),
576 A6XX_PROTECT_NORDWR(0x0be02, 0x0001),
577 A6XX_PROTECT_NORDWR(0x0be20, 0x17df),
578 A6XX_PROTECT_NORDWR(0x0f000, 0x0bff),
579 A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
580 A6XX_PROTECT_NORDWR(0x18400, 0x1fff),
581 A6XX_PROTECT_NORDWR(0x1a800, 0x1fff),
582 A6XX_PROTECT_NORDWR(0x1f400, 0x0443),
583 A6XX_PROTECT_RDONLY(0x1f844, 0x007b),
584 A6XX_PROTECT_NORDWR(0x1f887, 0x001b),
585 A6XX_PROTECT_NORDWR(0x1f8c0, 0x0000), /* note: infinite range */
586 };
587 DECLARE_ADRENO_PROTECT(a650_protect, 48);
588
589 /* These are for a635 and a660 */
590 static const u32 a660_protect_regs[] = {
591 A6XX_PROTECT_RDONLY(0x00000, 0x04ff),
592 A6XX_PROTECT_RDONLY(0x00501, 0x0005),
593 A6XX_PROTECT_RDONLY(0x0050b, 0x02f4),
594 A6XX_PROTECT_NORDWR(0x0050e, 0x0000),
595 A6XX_PROTECT_NORDWR(0x00510, 0x0000),
596 A6XX_PROTECT_NORDWR(0x00534, 0x0000),
597 A6XX_PROTECT_NORDWR(0x00800, 0x0082),
598 A6XX_PROTECT_NORDWR(0x008a0, 0x0008),
599 A6XX_PROTECT_NORDWR(0x008ab, 0x0024),
600 A6XX_PROTECT_RDONLY(0x008de, 0x00ae),
601 A6XX_PROTECT_NORDWR(0x00900, 0x004d),
602 A6XX_PROTECT_NORDWR(0x0098d, 0x0272),
603 A6XX_PROTECT_NORDWR(0x00e00, 0x0001),
604 A6XX_PROTECT_NORDWR(0x00e03, 0x000c),
605 A6XX_PROTECT_NORDWR(0x03c00, 0x00c3),
606 A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff),
607 A6XX_PROTECT_NORDWR(0x08630, 0x01cf),
608 A6XX_PROTECT_NORDWR(0x08e00, 0x0000),
609 A6XX_PROTECT_NORDWR(0x08e08, 0x0000),
610 A6XX_PROTECT_NORDWR(0x08e50, 0x001f),
611 A6XX_PROTECT_NORDWR(0x08e80, 0x027f),
612 A6XX_PROTECT_NORDWR(0x09624, 0x01db),
613 A6XX_PROTECT_NORDWR(0x09e60, 0x0011),
614 A6XX_PROTECT_NORDWR(0x09e78, 0x0187),
615 A6XX_PROTECT_NORDWR(0x0a630, 0x01cf),
616 A6XX_PROTECT_NORDWR(0x0ae02, 0x0000),
617 A6XX_PROTECT_NORDWR(0x0ae50, 0x012f),
618 A6XX_PROTECT_NORDWR(0x0b604, 0x0000),
619 A6XX_PROTECT_NORDWR(0x0b608, 0x0006),
620 A6XX_PROTECT_NORDWR(0x0be02, 0x0001),
621 A6XX_PROTECT_NORDWR(0x0be20, 0x015f),
622 A6XX_PROTECT_NORDWR(0x0d000, 0x05ff),
623 A6XX_PROTECT_NORDWR(0x0f000, 0x0bff),
624 A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
625 A6XX_PROTECT_NORDWR(0x18400, 0x1fff),
626 A6XX_PROTECT_NORDWR(0x1a400, 0x1fff),
627 A6XX_PROTECT_NORDWR(0x1f400, 0x0443),
628 A6XX_PROTECT_RDONLY(0x1f844, 0x007b),
629 A6XX_PROTECT_NORDWR(0x1f860, 0x0000),
630 A6XX_PROTECT_NORDWR(0x1f887, 0x001b),
631 A6XX_PROTECT_NORDWR(0x1f8c0, 0x0000), /* note: infinite range */
632 };
633 DECLARE_ADRENO_PROTECT(a660_protect, 48);
634
635 /* These are for a690 */
636 static const u32 a690_protect_regs[] = {
637 A6XX_PROTECT_RDONLY(0x00000, 0x004ff),
638 A6XX_PROTECT_RDONLY(0x00501, 0x00001),
639 A6XX_PROTECT_RDONLY(0x0050b, 0x002f4),
640 A6XX_PROTECT_NORDWR(0x0050e, 0x00000),
641 A6XX_PROTECT_NORDWR(0x00510, 0x00000),
642 A6XX_PROTECT_NORDWR(0x00534, 0x00000),
643 A6XX_PROTECT_NORDWR(0x00800, 0x00082),
644 A6XX_PROTECT_NORDWR(0x008a0, 0x00008),
645 A6XX_PROTECT_NORDWR(0x008ab, 0x00024),
646 A6XX_PROTECT_RDONLY(0x008de, 0x000ae),
647 A6XX_PROTECT_NORDWR(0x00900, 0x0004d),
648 A6XX_PROTECT_NORDWR(0x0098d, 0x00272),
649 A6XX_PROTECT_NORDWR(0x00e00, 0x00001),
650 A6XX_PROTECT_NORDWR(0x00e03, 0x0000c),
651 A6XX_PROTECT_NORDWR(0x03c00, 0x000c3),
652 A6XX_PROTECT_RDONLY(0x03cc4, 0x01fff),
653 A6XX_PROTECT_NORDWR(0x08630, 0x001cf),
654 A6XX_PROTECT_NORDWR(0x08e00, 0x00000),
655 A6XX_PROTECT_NORDWR(0x08e08, 0x00007),
656 A6XX_PROTECT_NORDWR(0x08e50, 0x0001f),
657 A6XX_PROTECT_NORDWR(0x08e80, 0x0027f),
658 A6XX_PROTECT_NORDWR(0x09624, 0x001db),
659 A6XX_PROTECT_NORDWR(0x09e60, 0x00011),
660 A6XX_PROTECT_NORDWR(0x09e78, 0x00187),
661 A6XX_PROTECT_NORDWR(0x0a630, 0x001cf),
662 A6XX_PROTECT_NORDWR(0x0ae02, 0x00000),
663 A6XX_PROTECT_NORDWR(0x0ae50, 0x0012f),
664 A6XX_PROTECT_NORDWR(0x0b604, 0x00000),
665 A6XX_PROTECT_NORDWR(0x0b608, 0x00006),
666 A6XX_PROTECT_NORDWR(0x0be02, 0x00001),
667 A6XX_PROTECT_NORDWR(0x0be20, 0x0015f),
668 A6XX_PROTECT_NORDWR(0x0d000, 0x005ff),
669 A6XX_PROTECT_NORDWR(0x0f000, 0x00bff),
670 A6XX_PROTECT_RDONLY(0x0fc00, 0x01fff),
671 A6XX_PROTECT_NORDWR(0x11c00, 0x00000), /*note: infiite range */
672 };
673 DECLARE_ADRENO_PROTECT(a690_protect, 48);
674
675 static const struct adreno_reglist a640_gbif[] = {
676 { REG_A6XX_GBIF_QSB_SIDE0, 0x00071620 },
677 { REG_A6XX_GBIF_QSB_SIDE1, 0x00071620 },
678 { REG_A6XX_GBIF_QSB_SIDE2, 0x00071620 },
679 { REG_A6XX_GBIF_QSB_SIDE3, 0x00071620 },
680 { },
681 };
682
683 static const struct adreno_info a6xx_gpus[] = {
684 {
685 .chip_ids = ADRENO_CHIP_IDS(0x06010000),
686 .family = ADRENO_6XX_GEN1,
687 .revn = 610,
688 .fw = {
689 [ADRENO_FW_SQE] = "a630_sqe.fw",
690 },
691 .gmem = (SZ_128K + SZ_4K),
692 .quirks = ADRENO_QUIRK_4GB_VA,
693 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
694 .funcs = &a6xx_gmuwrapper_funcs,
695 .zapfw = "a610_zap.mdt",
696 .a6xx = &(const struct a6xx_info) {
697 .hwcg = a612_hwcg,
698 .protect = &a630_protect,
699 .gbif_cx = a640_gbif,
700 .gmu_cgc_mode = 0x00020202,
701 .prim_fifo_threshold = 0x00080000,
702 },
703 /*
704 * There are (at least) three SoCs implementing A610: SM6125
705 * (trinket), SM6115 (bengal) and SM6225 (khaje). Trinket does
706 * not have speedbinning, as only a single SKU exists and we
707 * don't support khaje upstream yet. Hence, this matching
708 * table is only valid for bengal.
709 */
710 .speedbins = ADRENO_SPEEDBINS(
711 { 0, 0 },
712 { 206, 1 },
713 { 200, 2 },
714 { 157, 3 },
715 { 127, 4 },
716 ),
717 }, {
718 .chip_ids = ADRENO_CHIP_IDS(0x06010200),
719 .family = ADRENO_6XX_GEN1,
720 .fw = {
721 [ADRENO_FW_SQE] = "a630_sqe.fw",
722 [ADRENO_FW_GMU] = "a612_rgmu.bin",
723 },
724 .gmem = (SZ_128K + SZ_4K),
725 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
726 .funcs = &a6xx_gmuwrapper_funcs,
727 .a6xx = &(const struct a6xx_info) {
728 .hwcg = a612_hwcg,
729 .protect = &a630_protect,
730 .gmu_cgc_mode = 0x00000022,
731 .prim_fifo_threshold = 0x00080000,
732 },
733 }, {
734 .chip_ids = ADRENO_CHIP_IDS(0x06010500),
735 .family = ADRENO_6XX_GEN1,
736 .revn = 615,
737 .fw = {
738 [ADRENO_FW_SQE] = "a630_sqe.fw",
739 [ADRENO_FW_GMU] = "a630_gmu.bin",
740 },
741 .gmem = SZ_512K,
742 .quirks = ADRENO_QUIRK_4GB_VA,
743 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
744 .funcs = &a6xx_gpu_funcs,
745 .zapfw = "a615_zap.mdt",
746 .a6xx = &(const struct a6xx_info) {
747 .hwcg = a615_hwcg,
748 .protect = &a630_protect,
749 .gmu_cgc_mode = 0x00000222,
750 .prim_fifo_threshold = 0x0018000,
751 },
752 .speedbins = ADRENO_SPEEDBINS(
753 /*
754 * The default speed bin (0) has the same values as
755 * speed bin 90 which goes up to 432 MHz.
756 */
757 { 0, 0 },
758 { 90, 0 },
759 { 105, 1 },
760 { 146, 2 },
761 { 163, 3 },
762 ),
763 }, {
764 .machine = "qcom,sm7150",
765 .chip_ids = ADRENO_CHIP_IDS(0x06010800),
766 .family = ADRENO_6XX_GEN1,
767 .fw = {
768 [ADRENO_FW_SQE] = "a630_sqe.fw",
769 [ADRENO_FW_GMU] = "a630_gmu.bin",
770 },
771 .gmem = SZ_512K,
772 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
773 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
774 ADRENO_QUIRK_4GB_VA,
775 .funcs = &a6xx_gpu_funcs,
776 .zapfw = "a615_zap.mbn",
777 .a6xx = &(const struct a6xx_info) {
778 .hwcg = a615_hwcg,
779 .protect = &a630_protect,
780 .gmu_cgc_mode = 0x00000222,
781 .prim_fifo_threshold = 0x00180000,
782 },
783 .speedbins = ADRENO_SPEEDBINS(
784 { 0, 0 },
785 { 128, 1 },
786 { 146, 2 },
787 { 167, 3 },
788 { 172, 4 },
789 ),
790 }, {
791 .chip_ids = ADRENO_CHIP_IDS(0x06010800),
792 .family = ADRENO_6XX_GEN1,
793 .revn = 618,
794 .fw = {
795 [ADRENO_FW_SQE] = "a630_sqe.fw",
796 [ADRENO_FW_GMU] = "a630_gmu.bin",
797 },
798 .gmem = SZ_512K,
799 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
800 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
801 ADRENO_QUIRK_4GB_VA,
802 .funcs = &a6xx_gpu_funcs,
803 .a6xx = &(const struct a6xx_info) {
804 .protect = &a630_protect,
805 .gmu_cgc_mode = 0x00000222,
806 .prim_fifo_threshold = 0x00180000,
807 },
808 .speedbins = ADRENO_SPEEDBINS(
809 { 0, 0 },
810 { 169, 1 },
811 { 174, 2 },
812 ),
813 }, {
814 .machine = "qcom,sm4350",
815 .chip_ids = ADRENO_CHIP_IDS(0x06010900),
816 .family = ADRENO_6XX_GEN1,
817 .revn = 619,
818 .fw = {
819 [ADRENO_FW_SQE] = "a630_sqe.fw",
820 [ADRENO_FW_GMU] = "a619_gmu.bin",
821 },
822 .gmem = SZ_512K,
823 .quirks = ADRENO_QUIRK_4GB_VA,
824 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
825 .funcs = &a6xx_gpu_funcs,
826 .zapfw = "a615_zap.mdt",
827 .a6xx = &(const struct a6xx_info) {
828 .hwcg = a615_hwcg,
829 .protect = &a630_protect,
830 .gmu_cgc_mode = 0x00000222,
831 .prim_fifo_threshold = 0x00018000,
832 },
833 .speedbins = ADRENO_SPEEDBINS(
834 { 0, 0 },
835 { 138, 1 },
836 { 92, 2 },
837 ),
838 }, {
839 .machine = "qcom,sm6375",
840 .chip_ids = ADRENO_CHIP_IDS(0x06010901),
841 .family = ADRENO_6XX_GEN1,
842 .revn = 619,
843 .fw = {
844 [ADRENO_FW_SQE] = "a630_sqe.fw",
845 [ADRENO_FW_GMU] = "a619_gmu.bin",
846 },
847 .gmem = SZ_512K,
848 .quirks = ADRENO_QUIRK_4GB_VA,
849 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
850 .funcs = &a6xx_gpu_funcs,
851 .zapfw = "a615_zap.mdt",
852 .a6xx = &(const struct a6xx_info) {
853 .hwcg = a615_hwcg,
854 .protect = &a630_protect,
855 .gmu_cgc_mode = 0x00000222,
856 .prim_fifo_threshold = 0x00018000,
857 },
858 .speedbins = ADRENO_SPEEDBINS(
859 { 0, 0 },
860 { 190, 1 },
861 { 177, 2 },
862 ),
863 }, {
864 .chip_ids = ADRENO_CHIP_IDS(0x06010900),
865 .family = ADRENO_6XX_GEN1,
866 .revn = 619,
867 .fw = {
868 [ADRENO_FW_SQE] = "a630_sqe.fw",
869 [ADRENO_FW_GMU] = "a619_gmu.bin",
870 },
871 .gmem = SZ_512K,
872 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
873 ADRENO_QUIRK_4GB_VA,
874 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
875 .funcs = &a6xx_gpu_funcs,
876 .zapfw = "a615_zap.mdt",
877 .a6xx = &(const struct a6xx_info) {
878 .hwcg = a615_hwcg,
879 .protect = &a630_protect,
880 .gmu_cgc_mode = 0x00000222,
881 .prim_fifo_threshold = 0x00018000,
882 },
883 .speedbins = ADRENO_SPEEDBINS(
884 { 0, 0 },
885 { 120, 4 },
886 { 138, 3 },
887 { 169, 2 },
888 { 180, 1 },
889 ),
890 }, {
891 .chip_ids = ADRENO_CHIP_IDS(0x06020100),
892 .family = ADRENO_6XX_GEN3,
893 .fw = {
894 [ADRENO_FW_SQE] = "a650_sqe.fw",
895 [ADRENO_FW_GMU] = "a621_gmu.bin",
896 },
897 .gmem = SZ_512K,
898 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
899 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
900 ADRENO_QUIRK_HAS_HW_APRIV,
901 .funcs = &a6xx_gpu_funcs,
902 .zapfw = "a620_zap.mbn",
903 .a6xx = &(const struct a6xx_info) {
904 .hwcg = a620_hwcg,
905 .protect = &a650_protect,
906 .gbif_cx = a640_gbif,
907 .gmu_cgc_mode = 0x00020200,
908 .prim_fifo_threshold = 0x00010000,
909 },
910 .speedbins = ADRENO_SPEEDBINS(
911 { 0, 0 },
912 { 137, 1 },
913 ),
914 }, {
915 .chip_ids = ADRENO_CHIP_IDS(0x06020300),
916 .family = ADRENO_6XX_GEN3,
917 .fw = {
918 [ADRENO_FW_SQE] = "a650_sqe.fw",
919 [ADRENO_FW_GMU] = "a623_gmu.bin",
920 },
921 .gmem = SZ_512K,
922 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
923 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
924 ADRENO_QUIRK_HAS_HW_APRIV,
925 .funcs = &a6xx_gpu_funcs,
926 .a6xx = &(const struct a6xx_info) {
927 .hwcg = a690_hwcg,
928 .protect = &a650_protect,
929 .gbif_cx = a640_gbif,
930 .gmu_cgc_mode = 0x00020200,
931 .prim_fifo_threshold = 0x00010000,
932 .bcms = (const struct a6xx_bcm[]) {
933 { .name = "SH0", .buswidth = 16 },
934 { .name = "MC0", .buswidth = 4 },
935 {
936 .name = "ACV",
937 .fixed = true,
938 .perfmode = BIT(3),
939 },
940 { /* sentinel */ },
941 },
942 },
943 .speedbins = ADRENO_SPEEDBINS(
944 { 0, 0 },
945 { 185, 0 },
946 { 127, 1 },
947 ),
948 }, {
949 .chip_ids = ADRENO_CHIP_IDS(
950 0x06030001,
951 0x06030002
952 ),
953 .family = ADRENO_6XX_GEN1,
954 .revn = 630,
955 .fw = {
956 [ADRENO_FW_SQE] = "a630_sqe.fw",
957 [ADRENO_FW_GMU] = "a630_gmu.bin",
958 },
959 .gmem = SZ_1M,
960 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
961 ADRENO_QUIRK_4GB_VA,
962 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
963 .funcs = &a6xx_gpu_funcs,
964 .zapfw = "a630_zap.mdt",
965 .a6xx = &(const struct a6xx_info) {
966 .hwcg = a630_hwcg,
967 .protect = &a630_protect,
968 .gmu_cgc_mode = 0x00020202,
969 .prim_fifo_threshold = 0x00180000,
970 },
971 }, {
972 .chip_ids = ADRENO_CHIP_IDS(0x06040001),
973 .family = ADRENO_6XX_GEN2,
974 .revn = 640,
975 .fw = {
976 [ADRENO_FW_SQE] = "a630_sqe.fw",
977 [ADRENO_FW_GMU] = "a640_gmu.bin",
978 },
979 .gmem = SZ_1M,
980 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
981 ADRENO_QUIRK_4GB_VA,
982 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
983 .funcs = &a6xx_gpu_funcs,
984 .zapfw = "a640_zap.mdt",
985 .a6xx = &(const struct a6xx_info) {
986 .hwcg = a640_hwcg,
987 .protect = &a630_protect,
988 .gmu_cgc_mode = 0x00020202,
989 .prim_fifo_threshold = 0x00180000,
990 },
991 .speedbins = ADRENO_SPEEDBINS(
992 { 0, 0 },
993 { 1, 1 },
994 ),
995 }, {
996 .chip_ids = ADRENO_CHIP_IDS(0x06050002),
997 .family = ADRENO_6XX_GEN3,
998 .revn = 650,
999 .fw = {
1000 [ADRENO_FW_SQE] = "a650_sqe.fw",
1001 [ADRENO_FW_GMU] = "a650_gmu.bin",
1002 },
1003 .gmem = SZ_1M + SZ_128K,
1004 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
1005 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
1006 ADRENO_QUIRK_HAS_HW_APRIV,
1007 .funcs = &a6xx_gpu_funcs,
1008 .zapfw = "a650_zap.mdt",
1009 .a6xx = &(const struct a6xx_info) {
1010 .hwcg = a650_hwcg,
1011 .protect = &a650_protect,
1012 .gbif_cx = a640_gbif,
1013 .gmu_cgc_mode = 0x00020202,
1014 .prim_fifo_threshold = 0x00300200,
1015 },
1016 .speedbins = ADRENO_SPEEDBINS(
1017 { 0, 0 },
1018 { 1, 1 },
1019 { 2, 3 }, /* Yep, 2 and 3 are swapped! :/ */
1020 { 3, 2 },
1021 ),
1022 }, {
1023 .chip_ids = ADRENO_CHIP_IDS(0x06060001),
1024 .family = ADRENO_6XX_GEN4,
1025 .revn = 660,
1026 .fw = {
1027 [ADRENO_FW_SQE] = "a660_sqe.fw",
1028 [ADRENO_FW_GMU] = "a660_gmu.bin",
1029 },
1030 .gmem = SZ_1M + SZ_512K,
1031 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
1032 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
1033 ADRENO_QUIRK_HAS_HW_APRIV,
1034 .funcs = &a6xx_gpu_funcs,
1035 .zapfw = "a660_zap.mdt",
1036 .a6xx = &(const struct a6xx_info) {
1037 .hwcg = a660_hwcg,
1038 .protect = &a660_protect,
1039 .gbif_cx = a640_gbif,
1040 .gmu_cgc_mode = 0x00020000,
1041 .prim_fifo_threshold = 0x00300200,
1042 },
1043 }, {
1044 .chip_ids = ADRENO_CHIP_IDS(0x06060300),
1045 .family = ADRENO_6XX_GEN4,
1046 .fw = {
1047 [ADRENO_FW_SQE] = "a660_sqe.fw",
1048 [ADRENO_FW_GMU] = "a663_gmu.bin",
1049 },
1050 .gmem = SZ_1M + SZ_512K,
1051 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
1052 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
1053 ADRENO_QUIRK_HAS_HW_APRIV,
1054 .funcs = &a6xx_gpu_funcs,
1055 .a6xx = &(const struct a6xx_info) {
1056 .hwcg = a690_hwcg,
1057 .protect = &a660_protect,
1058 .gbif_cx = a640_gbif,
1059 .gmu_cgc_mode = 0x00020200,
1060 .prim_fifo_threshold = 0x00300200,
1061 },
1062 .speedbins = ADRENO_SPEEDBINS(
1063 { 0, 0 },
1064 { 169, 0 },
1065 { 113, 1 },
1066 ),
1067 }, {
1068 .chip_ids = ADRENO_CHIP_IDS(0x06030500),
1069 .family = ADRENO_6XX_GEN4,
1070 .fw = {
1071 [ADRENO_FW_SQE] = "a660_sqe.fw",
1072 [ADRENO_FW_GMU] = "a660_gmu.bin",
1073 },
1074 .gmem = SZ_512K,
1075 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
1076 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
1077 ADRENO_QUIRK_HAS_HW_APRIV,
1078 .funcs = &a6xx_gpu_funcs,
1079 .zapfw = "a660_zap.mbn",
1080 .a6xx = &(const struct a6xx_info) {
1081 .hwcg = a660_hwcg,
1082 .protect = &a660_protect,
1083 .gbif_cx = a640_gbif,
1084 .gmu_cgc_mode = 0x00020202,
1085 .prim_fifo_threshold = 0x00200200,
1086 },
1087 .speedbins = ADRENO_SPEEDBINS(
1088 { 0, 0 },
1089 { 117, 0 },
1090 { 129, 4 },
1091 { 172, 2 }, /* Called speedbin 1 downstream, but let's not break things! */
1092 { 190, 1 },
1093 ),
1094 }, {
1095 .chip_ids = ADRENO_CHIP_IDS(0x06080001),
1096 .family = ADRENO_6XX_GEN2,
1097 .revn = 680,
1098 .fw = {
1099 [ADRENO_FW_SQE] = "a630_sqe.fw",
1100 [ADRENO_FW_GMU] = "a640_gmu.bin",
1101 },
1102 .gmem = SZ_2M,
1103 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
1104 ADRENO_QUIRK_4GB_VA,
1105 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
1106 .funcs = &a6xx_gpu_funcs,
1107 .zapfw = "a640_zap.mdt",
1108 .a6xx = &(const struct a6xx_info) {
1109 .hwcg = a640_hwcg,
1110 .protect = &a630_protect,
1111 .gmu_cgc_mode = 0x00020202,
1112 .prim_fifo_threshold = 0x00200200,
1113 },
1114 }, {
1115 .chip_ids = ADRENO_CHIP_IDS(0x06090000),
1116 .family = ADRENO_6XX_GEN4,
1117 .fw = {
1118 [ADRENO_FW_SQE] = "a660_sqe.fw",
1119 [ADRENO_FW_GMU] = "a660_gmu.bin",
1120 },
1121 .gmem = SZ_4M,
1122 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
1123 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
1124 ADRENO_QUIRK_HAS_HW_APRIV,
1125 .funcs = &a6xx_gpu_funcs,
1126 .zapfw = "a690_zap.mdt",
1127 .a6xx = &(const struct a6xx_info) {
1128 .hwcg = a690_hwcg,
1129 .protect = &a690_protect,
1130 .gbif_cx = a640_gbif,
1131 .gmu_cgc_mode = 0x00020200,
1132 .prim_fifo_threshold = 0x00800200,
1133 },
1134 }
1135 };
1136 DECLARE_ADRENO_GPULIST(a6xx);
1137
1138 static const struct adreno_reglist a702_hwcg[] = {
1139 { REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222 },
1140 { REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220 },
1141 { REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000081 },
1142 { REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf },
1143 { REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222 },
1144 { REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222 },
1145 { REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222 },
1146 { REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222 },
1147 { REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111 },
1148 { REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111 },
1149 { REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111 },
1150 { REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111 },
1151 { REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777 },
1152 { REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777 },
1153 { REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777 },
1154 { REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777 },
1155 { REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222 },
1156 { REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01202222 },
1157 { REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220 },
1158 { REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00 },
1159 { REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05522022 },
1160 { REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555 },
1161 { REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011 },
1162 { REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044 },
1163 { REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222 },
1164 { REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222 },
1165 { REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x02222222 },
1166 { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002 },
1167 { REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222 },
1168 { REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000 },
1169 { REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222 },
1170 { REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200 },
1171 { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000 },
1172 { REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000 },
1173 { REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000 },
1174 { REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004 },
1175 { REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000 },
1176 { REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222 },
1177 { REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004 },
1178 { REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002 },
1179 { REG_A6XX_RBBM_ISDB_CNT, 0x00000182 },
1180 { REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000 },
1181 { REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000 },
1182 { REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222 },
1183 { REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111 },
1184 { REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555 },
1185 { REG_A6XX_RBBM_CLOCK_CNTL_FCHE, 0x00000222 },
1186 { REG_A6XX_RBBM_CLOCK_DELAY_FCHE, 0x00000000 },
1187 { REG_A6XX_RBBM_CLOCK_HYST_FCHE, 0x00000000 },
1188 { REG_A6XX_RBBM_CLOCK_CNTL_GLC, 0x00222222 },
1189 { REG_A6XX_RBBM_CLOCK_DELAY_GLC, 0x00000000 },
1190 { REG_A6XX_RBBM_CLOCK_HYST_GLC, 0x00000000 },
1191 { REG_A6XX_RBBM_CLOCK_CNTL_MHUB, 0x00000002 },
1192 { REG_A6XX_RBBM_CLOCK_DELAY_MHUB, 0x00000000 },
1193 { REG_A6XX_RBBM_CLOCK_HYST_MHUB, 0x00000000 },
1194 {}
1195 };
1196
1197 static const struct adreno_reglist a730_hwcg[] = {
1198 { REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222 },
1199 { REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02022222 },
1200 { REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf },
1201 { REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080 },
1202 { REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222220 },
1203 { REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222 },
1204 { REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222 },
1205 { REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00222222 },
1206 { REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777 },
1207 { REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777 },
1208 { REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777 },
1209 { REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777 },
1210 { REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111 },
1211 { REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111 },
1212 { REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111 },
1213 { REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111 },
1214 { REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222 },
1215 { REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004 },
1216 { REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002 },
1217 { REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222 },
1218 { REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222 },
1219 { REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220 },
1220 { REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x44000f00 },
1221 { REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022 },
1222 { REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00555555 },
1223 { REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011 },
1224 { REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00440044 },
1225 { REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222 },
1226 { REG_A7XX_RBBM_CLOCK_MODE2_GRAS, 0x00000222 },
1227 { REG_A7XX_RBBM_CLOCK_MODE_BV_GRAS, 0x00222222 },
1228 { REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x02222223 },
1229 { REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222 },
1230 { REG_A7XX_RBBM_CLOCK_MODE_BV_GPC, 0x00222222 },
1231 { REG_A7XX_RBBM_CLOCK_MODE_BV_VFD, 0x00002222 },
1232 { REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000 },
1233 { REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004 },
1234 { REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000 },
1235 { REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000 },
1236 { REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200 },
1237 { REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222 },
1238 { REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222 },
1239 { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000 },
1240 { REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000 },
1241 { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002 },
1242 { REG_A7XX_RBBM_CLOCK_MODE_BV_LRZ, 0x55555552 },
1243 { REG_A7XX_RBBM_CLOCK_MODE_CP, 0x00000223 },
1244 { REG_A6XX_RBBM_CLOCK_CNTL, 0x8aa8aa82 },
1245 { REG_A6XX_RBBM_ISDB_CNT, 0x00000182 },
1246 { REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000 },
1247 { REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000 },
1248 { REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222 },
1249 { REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111 },
1250 { REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555 },
1251 {},
1252 };
1253
1254 static const struct adreno_reglist a740_hwcg[] = {
1255 { REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222 },
1256 { REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x22022222 },
1257 { REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x003cf3cf },
1258 { REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080 },
1259 { REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222220 },
1260 { REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222 },
1261 { REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222 },
1262 { REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00222222 },
1263 { REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777 },
1264 { REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777 },
1265 { REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777 },
1266 { REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777 },
1267 { REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111 },
1268 { REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111 },
1269 { REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111 },
1270 { REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111 },
1271 { REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222 },
1272 { REG_A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x00222222 },
1273 { REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000444 },
1274 { REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000222 },
1275 { REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222 },
1276 { REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222 },
1277 { REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220 },
1278 { REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x44000f00 },
1279 { REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022 },
1280 { REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00555555 },
1281 { REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011 },
1282 { REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00440044 },
1283 { REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222 },
1284 { REG_A7XX_RBBM_CLOCK_MODE2_GRAS, 0x00000222 },
1285 { REG_A7XX_RBBM_CLOCK_MODE_BV_GRAS, 0x00222222 },
1286 { REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x02222223 },
1287 { REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00222222 },
1288 { REG_A7XX_RBBM_CLOCK_MODE_BV_GPC, 0x00222222 },
1289 { REG_A7XX_RBBM_CLOCK_MODE_BV_VFD, 0x00002222 },
1290 { REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000 },
1291 { REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004 },
1292 { REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000 },
1293 { REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00000000 },
1294 { REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200 },
1295 { REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00000000 },
1296 { REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222 },
1297 { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000 },
1298 { REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000 },
1299 { REG_A7XX_RBBM_CLOCK_MODE_BV_LRZ, 0x55555552 },
1300 { REG_A7XX_RBBM_CLOCK_HYST2_VFD, 0x00000000 },
1301 { REG_A7XX_RBBM_CLOCK_MODE_CP, 0x00000222 },
1302 { REG_A6XX_RBBM_CLOCK_CNTL, 0x8aa8aa82 },
1303 { REG_A6XX_RBBM_ISDB_CNT, 0x00000182 },
1304 { REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000 },
1305 { REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000 },
1306 { REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222 },
1307 { REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111 },
1308 { REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555 },
1309 {},
1310 };
1311
1312 static const u32 a730_protect_regs[] = {
1313 A6XX_PROTECT_RDONLY(0x00000, 0x04ff),
1314 A6XX_PROTECT_RDONLY(0x0050b, 0x0058),
1315 A6XX_PROTECT_NORDWR(0x0050e, 0x0000),
1316 A6XX_PROTECT_NORDWR(0x00510, 0x0000),
1317 A6XX_PROTECT_NORDWR(0x00534, 0x0000),
1318 A6XX_PROTECT_RDONLY(0x005fb, 0x009d),
1319 A6XX_PROTECT_NORDWR(0x00699, 0x01e9),
1320 A6XX_PROTECT_NORDWR(0x008a0, 0x0008),
1321 A6XX_PROTECT_NORDWR(0x008ab, 0x0024),
1322 /* 0x008d0-0x008dd and 0x008e0-0x008e6 are unprotected on purpose for tools like perfetto */
1323 A6XX_PROTECT_NORDWR(0x008de, 0x0001),
1324 A6XX_PROTECT_RDONLY(0x008e7, 0x014b),
1325 A6XX_PROTECT_NORDWR(0x00900, 0x004d),
1326 A6XX_PROTECT_NORDWR(0x0098d, 0x00b2),
1327 A6XX_PROTECT_NORDWR(0x00a41, 0x01be),
1328 A6XX_PROTECT_NORDWR(0x00df0, 0x0001),
1329 A6XX_PROTECT_NORDWR(0x00e01, 0x0000),
1330 A6XX_PROTECT_NORDWR(0x00e07, 0x0008),
1331 A6XX_PROTECT_NORDWR(0x03c00, 0x00c3),
1332 A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff),
1333 A6XX_PROTECT_NORDWR(0x08630, 0x01cf),
1334 A6XX_PROTECT_NORDWR(0x08e00, 0x0000),
1335 A6XX_PROTECT_NORDWR(0x08e08, 0x0000),
1336 A6XX_PROTECT_NORDWR(0x08e50, 0x001f),
1337 A6XX_PROTECT_NORDWR(0x08e80, 0x0280),
1338 A6XX_PROTECT_NORDWR(0x09624, 0x01db),
1339 A6XX_PROTECT_NORDWR(0x09e40, 0x0000),
1340 A6XX_PROTECT_NORDWR(0x09e64, 0x000d),
1341 A6XX_PROTECT_NORDWR(0x09e78, 0x0187),
1342 A6XX_PROTECT_NORDWR(0x0a630, 0x01cf),
1343 A6XX_PROTECT_NORDWR(0x0ae02, 0x0000),
1344 A6XX_PROTECT_NORDWR(0x0ae50, 0x000f),
1345 A6XX_PROTECT_NORDWR(0x0ae66, 0x0003),
1346 A6XX_PROTECT_NORDWR(0x0ae6f, 0x0003),
1347 A6XX_PROTECT_NORDWR(0x0b604, 0x0003),
1348 A6XX_PROTECT_NORDWR(0x0ec00, 0x0fff),
1349 A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
1350 A6XX_PROTECT_NORDWR(0x18400, 0x0053),
1351 A6XX_PROTECT_RDONLY(0x18454, 0x0004),
1352 A6XX_PROTECT_NORDWR(0x18459, 0x1fff),
1353 A6XX_PROTECT_NORDWR(0x1a459, 0x1fff),
1354 A6XX_PROTECT_NORDWR(0x1c459, 0x1fff),
1355 A6XX_PROTECT_NORDWR(0x1f400, 0x0443),
1356 A6XX_PROTECT_RDONLY(0x1f844, 0x007b),
1357 A6XX_PROTECT_NORDWR(0x1f860, 0x0000),
1358 A6XX_PROTECT_NORDWR(0x1f878, 0x002a),
1359 /* CP_PROTECT_REG[45, 46] are left untouched! */
1360 0,
1361 0,
1362 A6XX_PROTECT_NORDWR(0x1f8c0, 0x00000),
1363 };
1364 DECLARE_ADRENO_PROTECT(a730_protect, 48);
1365
1366 static const uint32_t a7xx_pwrup_reglist_regs[] = {
1367 REG_A6XX_UCHE_TRAP_BASE,
1368 REG_A6XX_UCHE_TRAP_BASE + 1,
1369 REG_A6XX_UCHE_WRITE_THRU_BASE,
1370 REG_A6XX_UCHE_WRITE_THRU_BASE + 1,
1371 REG_A6XX_UCHE_GMEM_RANGE_MIN,
1372 REG_A6XX_UCHE_GMEM_RANGE_MIN + 1,
1373 REG_A6XX_UCHE_GMEM_RANGE_MAX,
1374 REG_A6XX_UCHE_GMEM_RANGE_MAX + 1,
1375 REG_A6XX_UCHE_CACHE_WAYS,
1376 REG_A6XX_UCHE_MODE_CNTL,
1377 REG_A6XX_RB_NC_MODE_CNTL,
1378 REG_A6XX_RB_CMP_DBG_ECO_CNTL,
1379 REG_A7XX_GRAS_NC_MODE_CNTL,
1380 REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ENABLE,
1381 REG_A6XX_UCHE_GBIF_GX_CONFIG,
1382 REG_A6XX_UCHE_CLIENT_PF,
1383 REG_A6XX_TPL1_DBG_ECO_CNTL1,
1384 };
1385
1386 DECLARE_ADRENO_REGLIST_LIST(a7xx_pwrup_reglist);
1387
1388 /* Applicable for X185, A750 */
1389 static const u32 a750_ifpc_reglist_regs[] = {
1390 REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(0),
1391 REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(1),
1392 REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(2),
1393 REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(3),
1394 REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(4),
1395 REG_A6XX_TPL1_NC_MODE_CNTL,
1396 REG_A6XX_SP_NC_MODE_CNTL,
1397 REG_A6XX_CP_DBG_ECO_CNTL,
1398 REG_A6XX_CP_PROTECT_CNTL,
1399 REG_A6XX_CP_PROTECT(0),
1400 REG_A6XX_CP_PROTECT(1),
1401 REG_A6XX_CP_PROTECT(2),
1402 REG_A6XX_CP_PROTECT(3),
1403 REG_A6XX_CP_PROTECT(4),
1404 REG_A6XX_CP_PROTECT(5),
1405 REG_A6XX_CP_PROTECT(6),
1406 REG_A6XX_CP_PROTECT(7),
1407 REG_A6XX_CP_PROTECT(8),
1408 REG_A6XX_CP_PROTECT(9),
1409 REG_A6XX_CP_PROTECT(10),
1410 REG_A6XX_CP_PROTECT(11),
1411 REG_A6XX_CP_PROTECT(12),
1412 REG_A6XX_CP_PROTECT(13),
1413 REG_A6XX_CP_PROTECT(14),
1414 REG_A6XX_CP_PROTECT(15),
1415 REG_A6XX_CP_PROTECT(16),
1416 REG_A6XX_CP_PROTECT(17),
1417 REG_A6XX_CP_PROTECT(18),
1418 REG_A6XX_CP_PROTECT(19),
1419 REG_A6XX_CP_PROTECT(20),
1420 REG_A6XX_CP_PROTECT(21),
1421 REG_A6XX_CP_PROTECT(22),
1422 REG_A6XX_CP_PROTECT(23),
1423 REG_A6XX_CP_PROTECT(24),
1424 REG_A6XX_CP_PROTECT(25),
1425 REG_A6XX_CP_PROTECT(26),
1426 REG_A6XX_CP_PROTECT(27),
1427 REG_A6XX_CP_PROTECT(28),
1428 REG_A6XX_CP_PROTECT(29),
1429 REG_A6XX_CP_PROTECT(30),
1430 REG_A6XX_CP_PROTECT(31),
1431 REG_A6XX_CP_PROTECT(32),
1432 REG_A6XX_CP_PROTECT(33),
1433 REG_A6XX_CP_PROTECT(34),
1434 REG_A6XX_CP_PROTECT(35),
1435 REG_A6XX_CP_PROTECT(36),
1436 REG_A6XX_CP_PROTECT(37),
1437 REG_A6XX_CP_PROTECT(38),
1438 REG_A6XX_CP_PROTECT(39),
1439 REG_A6XX_CP_PROTECT(40),
1440 REG_A6XX_CP_PROTECT(41),
1441 REG_A6XX_CP_PROTECT(42),
1442 REG_A6XX_CP_PROTECT(43),
1443 REG_A6XX_CP_PROTECT(44),
1444 REG_A6XX_CP_PROTECT(45),
1445 REG_A6XX_CP_PROTECT(46),
1446 REG_A6XX_CP_PROTECT(47),
1447 };
1448
1449 DECLARE_ADRENO_REGLIST_LIST(a750_ifpc_reglist);
1450
1451 static const struct adreno_info a7xx_gpus[] = {
1452 {
1453 .chip_ids = ADRENO_CHIP_IDS(0x07000200),
1454 .family = ADRENO_6XX_GEN1, /* NOT a mistake! */
1455 .fw = {
1456 [ADRENO_FW_SQE] = "a702_sqe.fw",
1457 },
1458 .gmem = SZ_128K,
1459 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
1460 .quirks = ADRENO_QUIRK_HAS_HW_APRIV,
1461 .funcs = &a6xx_gmuwrapper_funcs,
1462 .zapfw = "a702_zap.mbn",
1463 .a6xx = &(const struct a6xx_info) {
1464 .hwcg = a702_hwcg,
1465 .protect = &a650_protect,
1466 .gbif_cx = a640_gbif,
1467 .gmu_cgc_mode = 0x00020202,
1468 .prim_fifo_threshold = 0x0000c000,
1469 },
1470 .speedbins = ADRENO_SPEEDBINS(
1471 { 0, 0 },
1472 { 236, 1 },
1473 { 178, 2 },
1474 { 142, 3 },
1475 ),
1476 }, {
1477 .chip_ids = ADRENO_CHIP_IDS(0x07030001),
1478 .family = ADRENO_7XX_GEN1,
1479 .fw = {
1480 [ADRENO_FW_SQE] = "a730_sqe.fw",
1481 [ADRENO_FW_GMU] = "gmu_gen70000.bin",
1482 },
1483 .gmem = SZ_2M,
1484 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
1485 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
1486 ADRENO_QUIRK_HAS_HW_APRIV |
1487 ADRENO_QUIRK_PREEMPTION,
1488 .funcs = &a7xx_gpu_funcs,
1489 .zapfw = "a730_zap.mdt",
1490 .a6xx = &(const struct a6xx_info) {
1491 .hwcg = a730_hwcg,
1492 .protect = &a730_protect,
1493 .pwrup_reglist = &a7xx_pwrup_reglist,
1494 .gbif_cx = a640_gbif,
1495 .gmu_cgc_mode = 0x00020000,
1496 },
1497 .preempt_record_size = 2860 * SZ_1K,
1498 }, {
1499 .chip_ids = ADRENO_CHIP_IDS(0x43050a01), /* "C510v2" */
1500 .family = ADRENO_7XX_GEN2,
1501 .fw = {
1502 [ADRENO_FW_SQE] = "a740_sqe.fw",
1503 [ADRENO_FW_GMU] = "gmu_gen70200.bin",
1504 },
1505 .gmem = 3 * SZ_1M,
1506 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
1507 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
1508 ADRENO_QUIRK_HAS_HW_APRIV |
1509 ADRENO_QUIRK_PREEMPTION,
1510 .funcs = &a7xx_gpu_funcs,
1511 .zapfw = "a740_zap.mdt",
1512 .a6xx = &(const struct a6xx_info) {
1513 .hwcg = a740_hwcg,
1514 .protect = &a730_protect,
1515 .pwrup_reglist = &a7xx_pwrup_reglist,
1516 .gbif_cx = a640_gbif,
1517 .gmu_chipid = 0x7020100,
1518 .gmu_cgc_mode = 0x00020202,
1519 .bcms = (const struct a6xx_bcm[]) {
1520 { .name = "SH0", .buswidth = 16 },
1521 { .name = "MC0", .buswidth = 4 },
1522 {
1523 .name = "ACV",
1524 .fixed = true,
1525 .perfmode = BIT(3),
1526 .perfmode_bw = 16500000,
1527 },
1528 { /* sentinel */ },
1529 },
1530 },
1531 .preempt_record_size = 4192 * SZ_1K,
1532 }, {
1533 .chip_ids = ADRENO_CHIP_IDS(0x43050c01), /* "C512v2" */
1534 .family = ADRENO_7XX_GEN2,
1535 .fw = {
1536 [ADRENO_FW_SQE] = "gen70500_sqe.fw",
1537 [ADRENO_FW_GMU] = "gen70500_gmu.bin",
1538 },
1539 .gmem = 3 * SZ_1M,
1540 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
1541 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
1542 ADRENO_QUIRK_HAS_HW_APRIV |
1543 ADRENO_QUIRK_PREEMPTION |
1544 ADRENO_QUIRK_IFPC,
1545 .funcs = &a7xx_gpu_funcs,
1546 .a6xx = &(const struct a6xx_info) {
1547 .hwcg = a740_hwcg,
1548 .protect = &a730_protect,
1549 .pwrup_reglist = &a7xx_pwrup_reglist,
1550 .ifpc_reglist = &a750_ifpc_reglist,
1551 .gbif_cx = a640_gbif,
1552 .gmu_chipid = 0x7050001,
1553 .gmu_cgc_mode = 0x00020202,
1554 .bcms = (const struct a6xx_bcm[]) {
1555 { .name = "SH0", .buswidth = 16 },
1556 { .name = "MC0", .buswidth = 4 },
1557 {
1558 .name = "ACV",
1559 .fixed = true,
1560 .perfmode = BIT(3),
1561 .perfmode_bw = 16500000,
1562 },
1563 { /* sentinel */ },
1564 },
1565 },
1566 .preempt_record_size = 4192 * SZ_1K,
1567 .speedbins = ADRENO_SPEEDBINS(
1568 { 0, 0 },
1569 { 59, 1 },
1570 { 7, 2 },
1571 { 232, 3 },
1572 { 146, 4 },
1573 ),
1574 }, {
1575 .chip_ids = ADRENO_CHIP_IDS(0x43051401), /* "C520v2" */
1576 .family = ADRENO_7XX_GEN3,
1577 .fw = {
1578 [ADRENO_FW_SQE] = "gen70900_sqe.fw",
1579 [ADRENO_FW_GMU] = "gmu_gen70900.bin",
1580 },
1581 .gmem = 3 * SZ_1M,
1582 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
1583 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
1584 ADRENO_QUIRK_HAS_HW_APRIV |
1585 ADRENO_QUIRK_PREEMPTION |
1586 ADRENO_QUIRK_IFPC,
1587 .funcs = &a7xx_gpu_funcs,
1588 .zapfw = "gen70900_zap.mbn",
1589 .a6xx = &(const struct a6xx_info) {
1590 .protect = &a730_protect,
1591 .pwrup_reglist = &a7xx_pwrup_reglist,
1592 .ifpc_reglist = &a750_ifpc_reglist,
1593 .gbif_cx = a640_gbif,
1594 .gmu_chipid = 0x7090100,
1595 .gmu_cgc_mode = 0x00020202,
1596 .bcms = (const struct a6xx_bcm[]) {
1597 { .name = "SH0", .buswidth = 16 },
1598 { .name = "MC0", .buswidth = 4 },
1599 {
1600 .name = "ACV",
1601 .fixed = true,
1602 .perfmode = BIT(2),
1603 .perfmode_bw = 10687500,
1604 },
1605 { /* sentinel */ },
1606 },
1607 },
1608 .preempt_record_size = 3572 * SZ_1K,
1609 }, {
1610 .chip_ids = ADRENO_CHIP_IDS(0x43030c00),
1611 .family = ADRENO_7XX_GEN2,
1612 .fw = {
1613 [ADRENO_FW_SQE] = "gen71500_sqe.fw",
1614 [ADRENO_FW_GMU] = "gen71500_gmu.bin",
1615 },
1616 .gmem = SZ_1M + SZ_512K,
1617 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
1618 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
1619 ADRENO_QUIRK_HAS_HW_APRIV |
1620 ADRENO_QUIRK_PREEMPTION,
1621 .funcs = &a7xx_gpu_funcs,
1622 .a6xx = &(const struct a6xx_info) {
1623 .hwcg = a740_hwcg,
1624 .protect = &a730_protect,
1625 .pwrup_reglist = &a7xx_pwrup_reglist,
1626 .gbif_cx = a640_gbif,
1627 .gmu_chipid = 0x70f0000,
1628 .gmu_cgc_mode = 0x00020222,
1629 .bcms = (const struct a6xx_bcm[]) {
1630 { .name = "SH0", .buswidth = 16 },
1631 { .name = "MC0", .buswidth = 4 },
1632 {
1633 .name = "ACV",
1634 .fixed = true,
1635 .perfmode = BIT(3),
1636 .perfmode_bw = 16500000,
1637 },
1638 { /* sentinel */ },
1639 },
1640 },
1641 .preempt_record_size = 4192 * SZ_1K,
1642 .speedbins = ADRENO_SPEEDBINS(
1643 { 0, 0 },
1644 { 294, 1 },
1645 { 263, 2 },
1646 { 233, 3 },
1647 { 141, 4 },
1648 ),
1649 }
1650 };
1651 DECLARE_ADRENO_GPULIST(a7xx);
1652
1653 static const struct adreno_reglist_pipe x285_nonctxt_regs[] = {
1654 { REG_A8XX_CP_SMMU_STREAM_ID_LPAC, 0x00000101, BIT(PIPE_NONE) },
1655 { REG_A8XX_GRAS_DBG_ECO_CNTL, 0x00000800, BIT(PIPE_BV) | BIT(PIPE_BR) },
1656 { REG_A8XX_GRAS_TSEFE_DBG_ECO_CNTL, 0x00200000, BIT(PIPE_BV) | BIT(PIPE_BR) },
1657 { REG_A6XX_PC_AUTO_VERTEX_STRIDE, 0x00000001, BIT(PIPE_BV) | BIT(PIPE_BR) },
1658 { REG_A8XX_PC_VIS_STREAM_CNTL, 0x10010000, BIT(PIPE_BV) | BIT(PIPE_BR) },
1659 { REG_A8XX_PC_CONTEXT_SWITCH_STABILIZE_CNTL_1, 0x00000002, BIT(PIPE_BV) | BIT(PIPE_BR) },
1660 { REG_A8XX_PC_CHICKEN_BITS_1, 0x00000003, BIT(PIPE_BV) | BIT(PIPE_BR) },
1661 { REG_A8XX_PC_CHICKEN_BITS_2, 0x00000200, BIT(PIPE_BV) | BIT(PIPE_BR) },
1662 { REG_A8XX_PC_CHICKEN_BITS_3, 0x00500000, BIT(PIPE_BV) | BIT(PIPE_BR) },
1663 { REG_A8XX_PC_CHICKEN_BITS_4, 0x00500050, BIT(PIPE_BV) | BIT(PIPE_BR) },
1664 { REG_A8XX_RB_GC_GMEM_PROTECT, 0x15000000, BIT(PIPE_BR) },
1665 { REG_A8XX_RB_RESOLVE_PREFETCH_CNTL, 0x00000007, BIT(PIPE_BR) },
1666 { REG_A8XX_RB_CMP_DBG_ECO_CNTL, 0x00004000, BIT(PIPE_BR) },
1667 { REG_A8XX_RBBM_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) },
1668 { REG_A8XX_RBBM_SLICE_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) },
1669 { REG_A8XX_RBBM_WAIT_IDLE_CLOCKS_CNTL, 0x00000030, BIT(PIPE_NONE) },
1670 { REG_A8XX_RBBM_WAIT_IDLE_CLOCKS_CNTL2, 0x00000030, BIT(PIPE_NONE) },
1671 { REG_A8XX_RBBM_INTERFACE_HANG_INT_CNTL, 0x0fffffff, BIT(PIPE_NONE) },
1672 { REG_A8XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x22122212, BIT(PIPE_NONE) },
1673 { REG_A8XX_RBBM_CGC_P2S_CNTL, 0x00000040, BIT(PIPE_NONE) },
1674 { REG_A7XX_SP_CHICKEN_BITS_2, 0x00820800, BIT(PIPE_NONE) },
1675 { REG_A7XX_SP_CHICKEN_BITS_3, 0x00300000, BIT(PIPE_NONE) },
1676 { REG_A6XX_SP_PERFCTR_SHADER_MASK, 0x0000003f, BIT(PIPE_NONE) },
1677 /* Disable CS dead batch merge */
1678 { REG_A7XX_SP_HLSQ_DBG_ECO_CNTL_2, BIT(31), BIT(PIPE_NONE) },
1679 { REG_A7XX_SP_HLSQ_TIMEOUT_THRESHOLD_DP, 0x00000080, BIT(PIPE_NONE) },
1680 { REG_A7XX_SP_READ_SEL, 0x0001ff00, BIT(PIPE_NONE) },
1681 { REG_A6XX_TPL1_DBG_ECO_CNTL, 0x10000000, BIT(PIPE_NONE) },
1682 /* BIT(26): Disable final clamp for bicubic filtering */
1683 { REG_A6XX_TPL1_DBG_ECO_CNTL1, 0x00000720, BIT(PIPE_NONE) },
1684 { REG_A6XX_UCHE_MODE_CNTL, 0x80080000, BIT(PIPE_NONE) },
1685 { REG_A8XX_UCHE_CCHE_MODE_CNTL, 0x00001000, BIT(PIPE_NONE) },
1686 { REG_A8XX_UCHE_CCHE_CACHE_WAYS, 0x00000800, BIT(PIPE_NONE) },
1687 { REG_A8XX_UCHE_GBIF_GX_CONFIG, 0x010240e0, BIT(PIPE_NONE) },
1688 { REG_A8XX_UCHE_VARB_IDLE_TIMEOUT, 0x00000020, BIT(PIPE_NONE) },
1689 { REG_A7XX_VFD_DBG_ECO_CNTL, 0x00008000, BIT(PIPE_BV) | BIT(PIPE_BR) },
1690 { REG_A8XX_VFD_CB_BV_THRESHOLD, 0x00500050, BIT(PIPE_BV) | BIT(PIPE_BR) },
1691 { REG_A8XX_VFD_CB_BR_THRESHOLD, 0x00600060, BIT(PIPE_BV) | BIT(PIPE_BR) },
1692 { REG_A8XX_VFD_CB_BUSY_REQ_CNT, 0x00200020, BIT(PIPE_BV) | BIT(PIPE_BR) },
1693 { REG_A8XX_VFD_CB_LP_REQ_CNT, 0x00000020, BIT(PIPE_BV) | BIT(PIPE_BR) },
1694 { REG_A8XX_VPC_FLATSHADE_MODE_CNTL, 0x00000001, BIT(PIPE_BV) | BIT(PIPE_BR) },
1695 { },
1696 };
1697
1698 static const u32 x285_protect_regs[] = {
1699 A6XX_PROTECT_RDONLY(0x00008, 0x039b),
1700 A6XX_PROTECT_RDONLY(0x003b4, 0x008b),
1701 A6XX_PROTECT_NORDWR(0x00440, 0x001f),
1702 A6XX_PROTECT_RDONLY(0x00580, 0x005f),
1703 A6XX_PROTECT_NORDWR(0x005e0, 0x011f),
1704 A6XX_PROTECT_RDONLY(0x0074a, 0x0005),
1705 A6XX_PROTECT_RDONLY(0x00759, 0x0026),
1706 A6XX_PROTECT_RDONLY(0x00789, 0x0000),
1707 A6XX_PROTECT_RDONLY(0x0078c, 0x0013),
1708 A6XX_PROTECT_NORDWR(0x00800, 0x0029),
1709 A6XX_PROTECT_NORDWR(0x0082c, 0x0000),
1710 A6XX_PROTECT_NORDWR(0x00837, 0x00af),
1711 A6XX_PROTECT_RDONLY(0x008e7, 0x00c9),
1712 A6XX_PROTECT_NORDWR(0x008ec, 0x00c3),
1713 A6XX_PROTECT_NORDWR(0x009b1, 0x0250),
1714 A6XX_PROTECT_RDONLY(0x00ce0, 0x0001),
1715 A6XX_PROTECT_RDONLY(0x00df0, 0x0000),
1716 A6XX_PROTECT_NORDWR(0x00df1, 0x0000),
1717 A6XX_PROTECT_NORDWR(0x00e01, 0x0000),
1718 A6XX_PROTECT_NORDWR(0x00e03, 0x1fff),
1719 A6XX_PROTECT_NORDWR(0x03c00, 0x00c5),
1720 A6XX_PROTECT_RDONLY(0x03cc6, 0x0039),
1721 A6XX_PROTECT_NORDWR(0x03d00, 0x1fff),
1722 A6XX_PROTECT_NORDWR(0x08600, 0x01ff),
1723 A6XX_PROTECT_NORDWR(0x08e00, 0x00ff),
1724 A6XX_PROTECT_RDONLY(0x08f00, 0x0000),
1725 A6XX_PROTECT_NORDWR(0x08f01, 0x01be),
1726 A6XX_PROTECT_NORDWR(0x09600, 0x01ff),
1727 A6XX_PROTECT_RDONLY(0x0981a, 0x02e5),
1728 A6XX_PROTECT_NORDWR(0x09e00, 0x01ff),
1729 A6XX_PROTECT_NORDWR(0x0a600, 0x01ff),
1730 A6XX_PROTECT_NORDWR(0x0a82e, 0x0000),
1731 A6XX_PROTECT_NORDWR(0x0ae00, 0x0006),
1732 A6XX_PROTECT_NORDWR(0x0ae08, 0x0006),
1733 A6XX_PROTECT_NORDWR(0x0ae10, 0x00bf),
1734 A6XX_PROTECT_RDONLY(0x0aed0, 0x002f),
1735 A6XX_PROTECT_NORDWR(0x0af00, 0x027f),
1736 A6XX_PROTECT_NORDWR(0x0b600, 0x1fff),
1737 A6XX_PROTECT_NORDWR(0x0dc00, 0x1fff),
1738 A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
1739 A6XX_PROTECT_NORDWR(0x18400, 0x003f),
1740 A6XX_PROTECT_RDONLY(0x18440, 0x013f),
1741 A6XX_PROTECT_NORDWR(0x18580, 0x1fff),
1742 A6XX_PROTECT_NORDWR(0x1b400, 0x1fff),
1743 A6XX_PROTECT_NORDWR(0x1f400, 0x0477),
1744 A6XX_PROTECT_RDONLY(0x1f878, 0x0507),
1745 A6XX_PROTECT_NORDWR(0x1f930, 0x0329),
1746 A6XX_PROTECT_NORDWR(0x1fd80, 0x1fff),
1747 A6XX_PROTECT_NORDWR(0x27800, 0x007f),
1748 A6XX_PROTECT_RDONLY(0x27880, 0x0385),
1749 A6XX_PROTECT_NORDWR(0x27882, 0x000a),
1750 A6XX_PROTECT_NORDWR(0x27c06, 0x0000),
1751 };
1752
1753 DECLARE_ADRENO_PROTECT(x285_protect, 64);
1754
1755 static const struct adreno_reglist_pipe a840_nonctxt_regs[] = {
1756 { REG_A8XX_CP_SMMU_STREAM_ID_LPAC, 0x00000101, BIT(PIPE_NONE) },
1757 { REG_A8XX_GRAS_DBG_ECO_CNTL, 0x00000800, BIT(PIPE_BV) | BIT(PIPE_BR) },
1758 { REG_A8XX_GRAS_TSEFE_DBG_ECO_CNTL, 0x00200000, BIT(PIPE_BV) | BIT(PIPE_BR) },
1759 { REG_A6XX_PC_AUTO_VERTEX_STRIDE, 0x00000001, BIT(PIPE_BV) | BIT(PIPE_BR) },
1760 { REG_A8XX_PC_VIS_STREAM_CNTL, 0x10010000, BIT(PIPE_BV) | BIT(PIPE_BR) },
1761 { REG_A8XX_PC_CONTEXT_SWITCH_STABILIZE_CNTL_1, 0x00000002, BIT(PIPE_BV) | BIT(PIPE_BR) },
1762 { REG_A8XX_PC_CHICKEN_BITS_1, 0x00000003, BIT(PIPE_BV) | BIT(PIPE_BR) },
1763 { REG_A8XX_PC_CHICKEN_BITS_2, 0x00000200, BIT(PIPE_BV) | BIT(PIPE_BR) },
1764 { REG_A8XX_PC_CHICKEN_BITS_3, 0x00500000, BIT(PIPE_BV) | BIT(PIPE_BR) },
1765 { REG_A8XX_PC_CHICKEN_BITS_4, 0x00500050, BIT(PIPE_BV) | BIT(PIPE_BR) },
1766 /* Disable Dead Draw Merge scheme on RB-HLSQ */
1767 { REG_A6XX_RB_RBP_CNTL, BIT(5), BIT(PIPE_BV) | BIT(PIPE_BR) },
1768 { REG_A7XX_RB_CCU_CNTL, 0x00000068, BIT(PIPE_BR) },
1769 /* Partially enable perf clear, Disable DINT to c/z be data forwarding */
1770 { REG_A7XX_RB_CCU_DBG_ECO_CNTL, 0x00002200, BIT(PIPE_BR) },
1771 { REG_A8XX_RB_GC_GMEM_PROTECT, 0x12000000, BIT(PIPE_BR) },
1772 { REG_A8XX_RB_RESOLVE_PREFETCH_CNTL, 0x00000007, BIT(PIPE_BR) },
1773 { REG_A8XX_RB_CMP_DBG_ECO_CNTL, 0x00004000, BIT(PIPE_BR) },
1774 { REG_A8XX_RBBM_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) },
1775 { REG_A8XX_RBBM_SLICE_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) },
1776 { REG_A8XX_RBBM_POWER_UP_RESET_SW_OVERRIDE, 0x70809060, BIT(PIPE_NONE) },
1777 { REG_A8XX_RBBM_POWER_UP_RESET_SW_BV_OVERRIDE, 0x30000000, BIT(PIPE_NONE) },
1778 { REG_A8XX_RBBM_WAIT_IDLE_CLOCKS_CNTL, 0x00000030, BIT(PIPE_NONE) },
1779 { REG_A8XX_RBBM_WAIT_IDLE_CLOCKS_CNTL2, 0x00000030, BIT(PIPE_NONE) },
1780 { REG_A8XX_RBBM_INTERFACE_HANG_INT_CNTL, 0x0fffffff, BIT(PIPE_NONE) },
1781 { REG_A8XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x22122212, BIT(PIPE_NONE) },
1782 { REG_A8XX_RBBM_CGC_P2S_CNTL, 0x00000040, BIT(PIPE_NONE) },
1783 /* Disable mode_switch optimization in UMAS */
1784 { REG_A6XX_SP_CHICKEN_BITS, BIT(24) | BIT(26), BIT(PIPE_NONE) },
1785 /* Disable LPAC large-LM mode */
1786 { REG_A8XX_SP_SS_CHICKEN_BITS_0, BIT(3), BIT(PIPE_NONE) },
1787 /* Disable PS out of order retire */
1788 { REG_A7XX_SP_CHICKEN_BITS_2, 0x00c21800, BIT(PIPE_NONE) },
1789 { REG_A7XX_SP_CHICKEN_BITS_3, 0x00300000, BIT(PIPE_NONE) },
1790 /* Disable SP2TP info attribute */
1791 { REG_A8XX_SP_CHICKEN_BITS_4, 0x00000002, BIT(PIPE_NONE) },
1792 { REG_A6XX_SP_PERFCTR_SHADER_MASK, 0x0000003f, BIT(PIPE_NONE) },
1793 { REG_A7XX_SP_HLSQ_DBG_ECO_CNTL, BIT(14), BIT(PIPE_NONE) },
1794 /* Ignore HLSQ shared constant feedback from SP */
1795 { REG_A7XX_SP_HLSQ_DBG_ECO_CNTL_1, BIT(17), BIT(PIPE_NONE) },
1796 /* Disable CS dead batch merge */
1797 { REG_A7XX_SP_HLSQ_DBG_ECO_CNTL_2, BIT(24), BIT(PIPE_NONE) },
1798 { REG_A8XX_SP_HLSQ_DBG_ECO_CNTL_3, BIT(7), BIT(PIPE_NONE) },
1799 { REG_A7XX_SP_HLSQ_TIMEOUT_THRESHOLD_DP, 0x00000080, BIT(PIPE_NONE) },
1800 { REG_A7XX_SP_READ_SEL, 0x0001ff00, BIT(PIPE_NONE) },
1801 { REG_A6XX_TPL1_DBG_ECO_CNTL, 0x10100000, BIT(PIPE_NONE) },
1802 /* BIT(26): Disable final clamp for bicubic filtering */
1803 { REG_A6XX_TPL1_DBG_ECO_CNTL1, 0x04000720, BIT(PIPE_NONE) },
1804 { REG_A6XX_UCHE_MODE_CNTL, 0x80080000, BIT(PIPE_NONE) },
1805 { REG_A8XX_UCHE_CCHE_MODE_CNTL, 0x00001000, BIT(PIPE_NONE) },
1806 { REG_A8XX_UCHE_CCHE_CACHE_WAYS, 0x00000800, BIT(PIPE_NONE) },
1807 { REG_A8XX_UCHE_GBIF_GX_CONFIG, 0x010240e0, BIT(PIPE_NONE) },
1808 { REG_A8XX_UCHE_VARB_IDLE_TIMEOUT, 0x00000020, BIT(PIPE_NONE) },
1809 { REG_A7XX_VFD_DBG_ECO_CNTL, 0x00008000, BIT(PIPE_BV) | BIT(PIPE_BR) },
1810 { REG_A8XX_VFD_CB_BV_THRESHOLD, 0x00500050, BIT(PIPE_BV) | BIT(PIPE_BR) },
1811 { REG_A8XX_VFD_CB_BR_THRESHOLD, 0x00600060, BIT(PIPE_BV) | BIT(PIPE_BR) },
1812 { REG_A8XX_VFD_CB_BUSY_REQ_CNT, 0x00200020, BIT(PIPE_BV) | BIT(PIPE_BR) },
1813 { REG_A8XX_VFD_CB_LP_REQ_CNT, 0x00000020, BIT(PIPE_BV) | BIT(PIPE_BR) },
1814 { REG_A8XX_VPC_FLATSHADE_MODE_CNTL, 0x00000001, BIT(PIPE_BV) | BIT(PIPE_BR) },
1815 { },
1816 };
1817
1818 static const u32 a840_protect_regs[] = {
1819 A6XX_PROTECT_RDONLY(0x00008, 0x039b),
1820 A6XX_PROTECT_RDONLY(0x003b4, 0x008b),
1821 A6XX_PROTECT_NORDWR(0x00440, 0x001f),
1822 A6XX_PROTECT_RDONLY(0x00580, 0x005f),
1823 A6XX_PROTECT_NORDWR(0x005e0, 0x011f),
1824 A6XX_PROTECT_RDONLY(0x0074a, 0x0005),
1825 A6XX_PROTECT_RDONLY(0x00759, 0x001b),
1826 A6XX_PROTECT_NORDWR(0x00775, 0x000a),
1827 A6XX_PROTECT_RDONLY(0x00789, 0x0000),
1828 A6XX_PROTECT_RDONLY(0x0078c, 0x0013),
1829 A6XX_PROTECT_NORDWR(0x00800, 0x0029),
1830 A6XX_PROTECT_NORDWR(0x00837, 0x00af),
1831 A6XX_PROTECT_RDONLY(0x008e7, 0x00c9),
1832 A6XX_PROTECT_NORDWR(0x008ec, 0x00c3),
1833 A6XX_PROTECT_NORDWR(0x009b1, 0x0250),
1834 A6XX_PROTECT_NORDWR(0x00c07, 0x0008),
1835 A6XX_PROTECT_RDONLY(0x00ce0, 0x0001),
1836 A6XX_PROTECT_RDONLY(0x00df0, 0x0000),
1837 A6XX_PROTECT_NORDWR(0x00df1, 0x0000),
1838 A6XX_PROTECT_NORDWR(0x00e01, 0x0000),
1839 A6XX_PROTECT_NORDWR(0x00e03, 0x1fff),
1840 A6XX_PROTECT_NORDWR(0x03c00, 0x00c5),
1841 A6XX_PROTECT_RDONLY(0x03cc6, 0x0039),
1842 A6XX_PROTECT_NORDWR(0x03d00, 0x1fff),
1843 A6XX_PROTECT_NORDWR(0x08600, 0x01ff),
1844 A6XX_PROTECT_NORDWR(0x08e00, 0x00ff),
1845 A6XX_PROTECT_RDONLY(0x08f00, 0x0000),
1846 A6XX_PROTECT_NORDWR(0x08f01, 0x01be),
1847 A6XX_PROTECT_NORDWR(0x09600, 0x01ff),
1848 A6XX_PROTECT_RDONLY(0x0981a, 0x02e5),
1849 A6XX_PROTECT_NORDWR(0x09e00, 0x01ff),
1850 A6XX_PROTECT_NORDWR(0x0a600, 0x01ff),
1851 A6XX_PROTECT_NORDWR(0x0a82e, 0x0000),
1852 A6XX_PROTECT_NORDWR(0x0ae00, 0x0000),
1853 A6XX_PROTECT_NORDWR(0x0ae02, 0x0004),
1854 A6XX_PROTECT_NORDWR(0x0ae08, 0x0006),
1855 A6XX_PROTECT_NORDWR(0x0ae10, 0x00bf),
1856 A6XX_PROTECT_RDONLY(0x0aed0, 0x002f),
1857 A6XX_PROTECT_NORDWR(0x0af00, 0x027f),
1858 A6XX_PROTECT_NORDWR(0x0b600, 0x1fff),
1859 A6XX_PROTECT_NORDWR(0x0dc00, 0x1fff),
1860 A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
1861 A6XX_PROTECT_NORDWR(0x18400, 0x003f),
1862 A6XX_PROTECT_RDONLY(0x18440, 0x013f),
1863 A6XX_PROTECT_NORDWR(0x18580, 0x1fff),
1864 A6XX_PROTECT_NORDWR(0x1b400, 0x1fff),
1865 A6XX_PROTECT_NORDWR(0x1f400, 0x0477),
1866 A6XX_PROTECT_RDONLY(0x1f878, 0x0507),
1867 A6XX_PROTECT_NORDWR(0x1f930, 0x0329),
1868 A6XX_PROTECT_NORDWR(0x1fd80, 0x1fff),
1869 A6XX_PROTECT_NORDWR(0x27800, 0x007f),
1870 A6XX_PROTECT_RDONLY(0x27880, 0x0385),
1871 A6XX_PROTECT_NORDWR(0x27882, 0x0009),
1872 A6XX_PROTECT_NORDWR(0x27c06, 0x0000),
1873 };
1874 DECLARE_ADRENO_PROTECT(a840_protect, 15);
1875
1876 static const struct adreno_reglist a840_gbif[] = {
1877 { REG_A6XX_GBIF_QSB_SIDE0, 0x00071e20 },
1878 { REG_A6XX_GBIF_QSB_SIDE1, 0x00071e20 },
1879 { REG_A6XX_GBIF_QSB_SIDE2, 0x00071e20 },
1880 { REG_A6XX_GBIF_QSB_SIDE3, 0x00071e20 },
1881 { REG_A8XX_GBIF_CX_CONFIG, 0x20023000 },
1882 { },
1883 };
1884
1885 static const struct adreno_info a8xx_gpus[] = {
1886 {
1887 .chip_ids = ADRENO_CHIP_IDS(0x44070001),
1888 .family = ADRENO_8XX_GEN2,
1889 .fw = {
1890 [ADRENO_FW_SQE] = "gen80100_sqe.fw",
1891 [ADRENO_FW_GMU] = "gen80100_gmu.bin",
1892 },
1893 .gmem = 21 * SZ_1M,
1894 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
1895 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
1896 ADRENO_QUIRK_HAS_HW_APRIV,
1897 .funcs = &a8xx_gpu_funcs,
1898 .a6xx = &(const struct a6xx_info) {
1899 .protect = &x285_protect,
1900 .nonctxt_reglist = x285_nonctxt_regs,
1901 .gbif_cx = a840_gbif,
1902 .max_slices = 4,
1903 .gmu_chipid = 0x8010100,
1904 .bcms = (const struct a6xx_bcm[]) {
1905 { .name = "SH0", .buswidth = 16 },
1906 { .name = "MC0", .buswidth = 4 },
1907 {
1908 .name = "ACV",
1909 .fixed = true,
1910 .perfmode = BIT(2),
1911 .perfmode_bw = 16500000,
1912 },
1913 { /* sentinel */ },
1914 },
1915 },
1916 }, {
1917 .chip_ids = ADRENO_CHIP_IDS(0x44050a01),
1918 .family = ADRENO_8XX_GEN2,
1919 .fw = {
1920 [ADRENO_FW_SQE] = "gen80200_sqe.fw",
1921 [ADRENO_FW_GMU] = "gen80200_gmu.bin",
1922 [ADRENO_FW_AQE] = "gen80200_aqe.fw",
1923 },
1924 .gmem = 18 * SZ_1M,
1925 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
1926 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
1927 ADRENO_QUIRK_HAS_HW_APRIV,
1928 .funcs = &a8xx_gpu_funcs,
1929 .a6xx = &(const struct a6xx_info) {
1930 .protect = &a840_protect,
1931 .nonctxt_reglist = a840_nonctxt_regs,
1932 .gbif_cx = a840_gbif,
1933 .max_slices = 3,
1934 .gmu_chipid = 0x8020100,
1935 .bcms = (const struct a6xx_bcm[]) {
1936 { .name = "SH0", .buswidth = 16 },
1937 { .name = "MC0", .buswidth = 4 },
1938 {
1939 .name = "ACV",
1940 .fixed = true,
1941 .perfmode = BIT(2),
1942 .perfmode_bw = 10687500,
1943 },
1944 { /* sentinel */ },
1945 },
1946 },
1947 .preempt_record_size = 19708 * SZ_1K,
1948 }
1949 };
1950
1951 DECLARE_ADRENO_GPULIST(a8xx);
1952
__build_asserts(void)1953 static inline __always_unused void __build_asserts(void)
1954 {
1955 BUILD_BUG_ON(a630_protect.count > a630_protect.count_max);
1956 BUILD_BUG_ON(a650_protect.count > a650_protect.count_max);
1957 BUILD_BUG_ON(a660_protect.count > a660_protect.count_max);
1958 BUILD_BUG_ON(a690_protect.count > a690_protect.count_max);
1959 BUILD_BUG_ON(a730_protect.count > a730_protect.count_max);
1960 BUILD_BUG_ON(a840_protect.count > a840_protect.count_max);
1961 }
1962