1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015 Endless Mobile, Inc. 4 * Author: Carlo Caione <carlo@endlessm.com> 5 * Copyright (c) 2016 BayLibre, SAS. 6 * Author: Jerome Brunet <jbrunet@baylibre.com> 7 */ 8 9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 10 11 #include <linux/io.h> 12 #include <linux/module.h> 13 #include <linux/irq.h> 14 #include <linux/irqdomain.h> 15 #include <linux/irqchip.h> 16 #include <linux/of.h> 17 #include <linux/of_address.h> 18 19 #define MAX_NUM_CHANNEL 64 20 #define MAX_INPUT_MUX 256 21 22 #define REG_EDGE_POL 0x00 23 #define REG_PIN_03_SEL 0x04 24 #define REG_PIN_47_SEL 0x08 25 #define REG_FILTER_SEL 0x0c 26 27 /* use for A1 like chips */ 28 #define REG_PIN_A1_SEL 0x04 29 30 /* use for A9 like chips */ 31 #define REG_A9_AO_POL 0x00 32 #define REG_A9_AO_EDGE 0x30 33 34 /* 35 * Note: The S905X3 datasheet reports that BOTH_EDGE is controlled by 36 * bits 24 to 31. Tests on the actual HW show that these bits are 37 * stuck at 0. Bits 8 to 15 are responsive and have the expected 38 * effect. 39 */ 40 #define REG_EDGE_POL_EDGE(params, x) BIT((params)->edge_single_offset + (x)) 41 #define REG_EDGE_POL_LOW(params, x) BIT((params)->pol_low_offset + (x)) 42 #define REG_BOTH_EDGE(params, x) BIT((params)->edge_both_offset + (x)) 43 #define REG_EDGE_POL_MASK(params, x) ( \ 44 REG_EDGE_POL_EDGE(params, x) | \ 45 REG_EDGE_POL_LOW(params, x) | \ 46 REG_BOTH_EDGE(params, x)) 47 #define REG_PIN_SEL_SHIFT(x) (((x) % 4) * 8) 48 #define REG_FILTER_SEL_SHIFT(x) ((x) * 4) 49 50 struct meson_gpio_irq_controller; 51 static void meson8_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl, 52 unsigned int channel, unsigned long hwirq); 53 static void meson_gpio_irq_init_dummy(struct meson_gpio_irq_controller *ctl); 54 static void meson_a1_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl, 55 unsigned int channel, 56 unsigned long hwirq); 57 static void meson_a1_gpio_irq_init(struct meson_gpio_irq_controller *ctl); 58 static int meson8_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl, 59 unsigned int type, u32 *channel_hwirq); 60 static int meson_a9_ao_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl, 61 unsigned int type, u32 *channel_hwirq); 62 static int meson_s4_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl, 63 unsigned int type, u32 *channel_hwirq); 64 65 struct irq_ctl_ops { 66 void (*gpio_irq_sel_pin)(struct meson_gpio_irq_controller *ctl, 67 unsigned int channel, unsigned long hwirq); 68 void (*gpio_irq_init)(struct meson_gpio_irq_controller *ctl); 69 int (*gpio_irq_set_type)(struct meson_gpio_irq_controller *ctl, 70 unsigned int type, u32 *channel_hwirq); 71 }; 72 73 struct meson_gpio_irq_params { 74 unsigned int nr_hwirq; 75 unsigned int nr_channels; 76 bool support_edge_both; 77 unsigned int edge_both_offset; 78 unsigned int edge_single_offset; 79 unsigned int edge_pol_reg; 80 unsigned int pol_low_offset; 81 unsigned int pin_sel_mask; 82 struct irq_ctl_ops ops; 83 }; 84 85 #define INIT_MESON_COMMON(irqs, init, sel, type) \ 86 .nr_hwirq = irqs, \ 87 .ops = { \ 88 .gpio_irq_init = init, \ 89 .gpio_irq_sel_pin = sel, \ 90 .gpio_irq_set_type = type, \ 91 }, 92 93 #define INIT_MESON8_COMMON_DATA(irqs) \ 94 INIT_MESON_COMMON(irqs, meson_gpio_irq_init_dummy, \ 95 meson8_gpio_irq_sel_pin, \ 96 meson8_gpio_irq_set_type) \ 97 .edge_single_offset = 0, \ 98 .pol_low_offset = 16, \ 99 .pin_sel_mask = 0xff, \ 100 .nr_channels = 8, \ 101 102 #define INIT_MESON_A1_COMMON_DATA(irqs) \ 103 INIT_MESON_COMMON(irqs, meson_a1_gpio_irq_init, \ 104 meson_a1_gpio_irq_sel_pin, \ 105 meson8_gpio_irq_set_type) \ 106 .support_edge_both = true, \ 107 .edge_both_offset = 16, \ 108 .edge_single_offset = 8, \ 109 .pol_low_offset = 0, \ 110 .pin_sel_mask = 0x7f, \ 111 .nr_channels = 8, \ 112 113 #define INIT_MESON_A4_AO_COMMON_DATA(irqs) \ 114 INIT_MESON_COMMON(irqs, meson_a1_gpio_irq_init, \ 115 meson_a1_gpio_irq_sel_pin, \ 116 meson_s4_gpio_irq_set_type) \ 117 .support_edge_both = true, \ 118 .edge_both_offset = 0, \ 119 .edge_single_offset = 12, \ 120 .edge_pol_reg = 0x8, \ 121 .pol_low_offset = 0, \ 122 .pin_sel_mask = 0xff, \ 123 .nr_channels = 2, \ 124 125 #define INIT_MESON_A9_AO_COMMON_DATA(irqs) \ 126 INIT_MESON_COMMON(irqs, meson_a1_gpio_irq_init, \ 127 meson_a1_gpio_irq_sel_pin, \ 128 meson_a9_ao_gpio_irq_set_type) \ 129 .support_edge_both = true, \ 130 .edge_both_offset = 0, \ 131 .edge_single_offset = 0, \ 132 .edge_pol_reg = 0x2c, \ 133 .pol_low_offset = 0, \ 134 .pin_sel_mask = 0xff, \ 135 .nr_channels = 20, \ 136 137 #define INIT_MESON_S4_COMMON_DATA(irqs) \ 138 INIT_MESON_COMMON(irqs, meson_a1_gpio_irq_init, \ 139 meson_a1_gpio_irq_sel_pin, \ 140 meson_s4_gpio_irq_set_type) \ 141 .support_edge_both = true, \ 142 .edge_both_offset = 0, \ 143 .edge_single_offset = 12, \ 144 .edge_pol_reg = 0x1c, \ 145 .pol_low_offset = 0, \ 146 .pin_sel_mask = 0xff, \ 147 .nr_channels = 12, \ 148 149 static const struct meson_gpio_irq_params meson8_params = { 150 INIT_MESON8_COMMON_DATA(134) 151 }; 152 153 static const struct meson_gpio_irq_params meson8b_params = { 154 INIT_MESON8_COMMON_DATA(119) 155 }; 156 157 static const struct meson_gpio_irq_params gxbb_params = { 158 INIT_MESON8_COMMON_DATA(133) 159 }; 160 161 static const struct meson_gpio_irq_params gxl_params = { 162 INIT_MESON8_COMMON_DATA(110) 163 }; 164 165 static const struct meson_gpio_irq_params axg_params = { 166 INIT_MESON8_COMMON_DATA(100) 167 }; 168 169 static const struct meson_gpio_irq_params sm1_params = { 170 INIT_MESON8_COMMON_DATA(100) 171 .support_edge_both = true, 172 .edge_both_offset = 8, 173 }; 174 175 static const struct meson_gpio_irq_params a1_params = { 176 INIT_MESON_A1_COMMON_DATA(62) 177 }; 178 179 static const struct meson_gpio_irq_params a4_params = { 180 INIT_MESON_S4_COMMON_DATA(81) 181 }; 182 183 static const struct meson_gpio_irq_params a4_ao_params = { 184 INIT_MESON_A4_AO_COMMON_DATA(8) 185 }; 186 187 static const struct meson_gpio_irq_params a5_params = { 188 INIT_MESON_S4_COMMON_DATA(99) 189 }; 190 191 static const struct meson_gpio_irq_params a9_params = { 192 INIT_MESON_S4_COMMON_DATA(96) 193 }; 194 195 static const struct meson_gpio_irq_params a9_ao_params = { 196 INIT_MESON_A9_AO_COMMON_DATA(39) 197 }; 198 199 static const struct meson_gpio_irq_params s4_params = { 200 INIT_MESON_S4_COMMON_DATA(82) 201 }; 202 203 static const struct meson_gpio_irq_params s6_params = { 204 INIT_MESON_S4_COMMON_DATA(100) 205 }; 206 207 static const struct meson_gpio_irq_params s7_params = { 208 INIT_MESON_S4_COMMON_DATA(84) 209 }; 210 211 static const struct meson_gpio_irq_params c3_params = { 212 INIT_MESON_S4_COMMON_DATA(55) 213 }; 214 215 static const struct meson_gpio_irq_params t7_params = { 216 INIT_MESON_S4_COMMON_DATA(157) 217 }; 218 219 static const struct of_device_id meson_irq_gpio_matches[] __maybe_unused = { 220 { .compatible = "amlogic,meson8-gpio-intc", .data = &meson8_params }, 221 { .compatible = "amlogic,meson8b-gpio-intc", .data = &meson8b_params }, 222 { .compatible = "amlogic,meson-gxbb-gpio-intc", .data = &gxbb_params }, 223 { .compatible = "amlogic,meson-gxl-gpio-intc", .data = &gxl_params }, 224 { .compatible = "amlogic,meson-axg-gpio-intc", .data = &axg_params }, 225 { .compatible = "amlogic,meson-g12a-gpio-intc", .data = &axg_params }, 226 { .compatible = "amlogic,meson-sm1-gpio-intc", .data = &sm1_params }, 227 { .compatible = "amlogic,meson-a1-gpio-intc", .data = &a1_params }, 228 { .compatible = "amlogic,meson-s4-gpio-intc", .data = &s4_params }, 229 { .compatible = "amlogic,a4-gpio-ao-intc", .data = &a4_ao_params }, 230 { .compatible = "amlogic,a4-gpio-intc", .data = &a4_params }, 231 { .compatible = "amlogic,a5-gpio-intc", .data = &a5_params }, 232 { .compatible = "amlogic,a9-gpio-ao-intc", .data = &a9_ao_params }, 233 { .compatible = "amlogic,a9-gpio-intc", .data = &a9_params }, 234 { .compatible = "amlogic,s6-gpio-intc", .data = &s6_params }, 235 { .compatible = "amlogic,s7-gpio-intc", .data = &s7_params }, 236 { .compatible = "amlogic,s7d-gpio-intc", .data = &s7_params }, 237 { .compatible = "amlogic,c3-gpio-intc", .data = &c3_params }, 238 { .compatible = "amlogic,t7-gpio-intc", .data = &t7_params }, 239 { } 240 }; 241 242 struct meson_gpio_irq_controller { 243 const struct meson_gpio_irq_params *params; 244 void __iomem *base; 245 u32 channel_irqs[MAX_NUM_CHANNEL]; 246 DECLARE_BITMAP(channel_map, MAX_NUM_CHANNEL); 247 raw_spinlock_t lock; 248 }; 249 250 static void meson_gpio_irq_update_bits(struct meson_gpio_irq_controller *ctl, 251 unsigned int reg, u32 mask, u32 val) 252 { 253 unsigned long flags; 254 u32 tmp; 255 256 raw_spin_lock_irqsave(&ctl->lock, flags); 257 258 tmp = readl_relaxed(ctl->base + reg); 259 tmp &= ~mask; 260 tmp |= val; 261 writel_relaxed(tmp, ctl->base + reg); 262 263 raw_spin_unlock_irqrestore(&ctl->lock, flags); 264 } 265 266 static void meson_gpio_irq_init_dummy(struct meson_gpio_irq_controller *ctl) 267 { 268 } 269 270 static void meson8_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl, 271 unsigned int channel, unsigned long hwirq) 272 { 273 unsigned int reg_offset; 274 unsigned int bit_offset; 275 276 reg_offset = (channel < 4) ? REG_PIN_03_SEL : REG_PIN_47_SEL; 277 bit_offset = REG_PIN_SEL_SHIFT(channel); 278 279 meson_gpio_irq_update_bits(ctl, reg_offset, 280 ctl->params->pin_sel_mask << bit_offset, 281 hwirq << bit_offset); 282 } 283 284 static void meson_a1_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl, 285 unsigned int channel, 286 unsigned long hwirq) 287 { 288 unsigned int reg_offset; 289 unsigned int bit_offset; 290 291 bit_offset = ((channel % 2) == 0) ? 0 : 16; 292 reg_offset = REG_PIN_A1_SEL + ((channel / 2) << 2); 293 294 meson_gpio_irq_update_bits(ctl, reg_offset, 295 ctl->params->pin_sel_mask << bit_offset, 296 hwirq << bit_offset); 297 } 298 299 /* For a1 or later chips like a1 there is a switch to enable/disable irq */ 300 static void meson_a1_gpio_irq_init(struct meson_gpio_irq_controller *ctl) 301 { 302 meson_gpio_irq_update_bits(ctl, REG_EDGE_POL, BIT(31), BIT(31)); 303 } 304 305 static int 306 meson_gpio_irq_request_channel(struct meson_gpio_irq_controller *ctl, 307 unsigned long hwirq, 308 u32 **channel_hwirq) 309 { 310 unsigned long flags; 311 unsigned int idx; 312 313 raw_spin_lock_irqsave(&ctl->lock, flags); 314 315 /* Find a free channel */ 316 idx = find_first_zero_bit(ctl->channel_map, ctl->params->nr_channels); 317 if (idx >= ctl->params->nr_channels) { 318 raw_spin_unlock_irqrestore(&ctl->lock, flags); 319 pr_err("No channel available\n"); 320 return -ENOSPC; 321 } 322 323 /* Mark the channel as used */ 324 set_bit(idx, ctl->channel_map); 325 326 raw_spin_unlock_irqrestore(&ctl->lock, flags); 327 328 /* 329 * Setup the mux of the channel to route the signal of the pad 330 * to the appropriate input of the GIC 331 */ 332 ctl->params->ops.gpio_irq_sel_pin(ctl, idx, hwirq); 333 334 /* 335 * Get the hwirq number assigned to this channel through 336 * a pointer the channel_irq table. The added benefit of this 337 * method is that we can also retrieve the channel index with 338 * it, using the table base. 339 */ 340 *channel_hwirq = &(ctl->channel_irqs[idx]); 341 342 pr_debug("hwirq %lu assigned to channel %d - irq %u\n", 343 hwirq, idx, **channel_hwirq); 344 345 return 0; 346 } 347 348 static unsigned int 349 meson_gpio_irq_get_channel_idx(struct meson_gpio_irq_controller *ctl, 350 u32 *channel_hwirq) 351 { 352 return channel_hwirq - ctl->channel_irqs; 353 } 354 355 static void 356 meson_gpio_irq_release_channel(struct meson_gpio_irq_controller *ctl, 357 u32 *channel_hwirq) 358 { 359 unsigned int idx; 360 361 idx = meson_gpio_irq_get_channel_idx(ctl, channel_hwirq); 362 clear_bit(idx, ctl->channel_map); 363 } 364 365 static int meson8_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl, 366 unsigned int type, u32 *channel_hwirq) 367 { 368 const struct meson_gpio_irq_params *params = ctl->params; 369 unsigned int idx; 370 u32 val = 0; 371 372 idx = meson_gpio_irq_get_channel_idx(ctl, channel_hwirq); 373 374 /* 375 * The controller has a filter block to operate in either LEVEL or 376 * EDGE mode, then signal is sent to the GIC. To enable LEVEL_LOW and 377 * EDGE_FALLING support (which the GIC does not support), the filter 378 * block is also able to invert the input signal it gets before 379 * providing it to the GIC. 380 */ 381 type &= IRQ_TYPE_SENSE_MASK; 382 383 /* 384 * New controller support EDGE_BOTH trigger. This setting takes 385 * precedence over the other edge/polarity settings 386 */ 387 if (type == IRQ_TYPE_EDGE_BOTH) { 388 if (!params->support_edge_both) 389 return -EINVAL; 390 391 val |= REG_BOTH_EDGE(params, idx); 392 } else { 393 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) 394 val |= REG_EDGE_POL_EDGE(params, idx); 395 396 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)) 397 val |= REG_EDGE_POL_LOW(params, idx); 398 } 399 400 meson_gpio_irq_update_bits(ctl, REG_EDGE_POL, 401 REG_EDGE_POL_MASK(params, idx), val); 402 403 return 0; 404 } 405 406 /* 407 * gpio irq relative registers for a9_ao 408 * -PADCTRL_GPIO_IRQ_CTRL0 409 * bit[31]: enable/disable all the irq lines 410 * bit[0-19]: polarity trigger 411 * 412 * -PADCTRL_GPIO_IRQ_CTRL[X] 413 * bit[0-5]: 6 bits to choose gpio source for irq line 2*[X] - 2 414 * bit[16-21]:6 bits to choose gpio source for irq line 2*[X] - 1 415 * where X = 1-10 416 * 417 * -PADCTRL_GPIO_IRQ_CTRL[11] 418 * bit[0-19]: both edge trigger 419 * 420 * -PADCTRL_GPIO_IRQ_CTRL[12] 421 * bit[0-19]: single edge trigger 422 */ 423 static int meson_a9_ao_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl, 424 unsigned int type, u32 *channel_hwirq) 425 { 426 const struct meson_gpio_irq_params *params = ctl->params; 427 unsigned int idx; 428 u32 val; 429 430 idx = meson_gpio_irq_get_channel_idx(ctl, channel_hwirq); 431 432 type &= IRQ_TYPE_SENSE_MASK; 433 434 meson_gpio_irq_update_bits(ctl, params->edge_pol_reg, BIT(idx), 0); 435 436 if (type == IRQ_TYPE_EDGE_BOTH) { 437 val = BIT(ctl->params->edge_both_offset + idx); 438 meson_gpio_irq_update_bits(ctl, params->edge_pol_reg, val, val); 439 return 0; 440 } 441 442 val = 0; 443 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)) 444 val = BIT(idx); 445 meson_gpio_irq_update_bits(ctl, REG_A9_AO_POL, BIT(idx), val); 446 447 val = 0; 448 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) 449 val = BIT(idx); 450 meson_gpio_irq_update_bits(ctl, REG_A9_AO_EDGE, BIT(idx), val); 451 452 return 0; 453 }; 454 455 /* 456 * gpio irq relative registers for s4 457 * -PADCTRL_GPIO_IRQ_CTRL0 458 * bit[31]: enable/disable all the irq lines 459 * bit[12-23]: single edge trigger 460 * bit[0-11]: polarity trigger 461 * 462 * -PADCTRL_GPIO_IRQ_CTRL[X] 463 * bit[0-16]: 7 bits to choose gpio source for irq line 2*[X] - 2 464 * bit[16-22]:7 bits to choose gpio source for irq line 2*[X] - 1 465 * where X = 1-6 466 * 467 * -PADCTRL_GPIO_IRQ_CTRL[7] 468 * bit[0-11]: both edge trigger 469 */ 470 static int meson_s4_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl, 471 unsigned int type, u32 *channel_hwirq) 472 { 473 const struct meson_gpio_irq_params *params = ctl->params; 474 unsigned int idx; 475 u32 val = 0; 476 477 idx = meson_gpio_irq_get_channel_idx(ctl, channel_hwirq); 478 479 type &= IRQ_TYPE_SENSE_MASK; 480 481 meson_gpio_irq_update_bits(ctl, params->edge_pol_reg, BIT(idx), 0); 482 483 if (type == IRQ_TYPE_EDGE_BOTH) { 484 val = BIT(ctl->params->edge_both_offset + idx); 485 meson_gpio_irq_update_bits(ctl, params->edge_pol_reg, val, val); 486 return 0; 487 } 488 489 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)) 490 val |= BIT(ctl->params->pol_low_offset + idx); 491 492 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) 493 val |= BIT(ctl->params->edge_single_offset + idx); 494 495 meson_gpio_irq_update_bits(ctl, REG_EDGE_POL, BIT(idx) | BIT(12 + idx), val); 496 return 0; 497 }; 498 499 static unsigned int meson_gpio_irq_type_output(unsigned int type) 500 { 501 unsigned int sense = type & IRQ_TYPE_SENSE_MASK; 502 503 type &= ~IRQ_TYPE_SENSE_MASK; 504 505 /* 506 * The polarity of the signal provided to the GIC should always 507 * be high. 508 */ 509 if (sense & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) 510 type |= IRQ_TYPE_LEVEL_HIGH; 511 else 512 type |= IRQ_TYPE_EDGE_RISING; 513 514 return type; 515 } 516 517 static int meson_gpio_irq_set_type(struct irq_data *data, unsigned int type) 518 { 519 struct meson_gpio_irq_controller *ctl = data->domain->host_data; 520 u32 *channel_hwirq = irq_data_get_irq_chip_data(data); 521 int ret; 522 523 ret = ctl->params->ops.gpio_irq_set_type(ctl, type, channel_hwirq); 524 if (ret) 525 return ret; 526 527 return irq_chip_set_type_parent(data, 528 meson_gpio_irq_type_output(type)); 529 } 530 531 static struct irq_chip meson_gpio_irq_chip = { 532 .name = "meson-gpio-irqchip", 533 .irq_mask = irq_chip_mask_parent, 534 .irq_unmask = irq_chip_unmask_parent, 535 .irq_eoi = irq_chip_eoi_parent, 536 .irq_set_type = meson_gpio_irq_set_type, 537 .irq_retrigger = irq_chip_retrigger_hierarchy, 538 #ifdef CONFIG_SMP 539 .irq_set_affinity = irq_chip_set_affinity_parent, 540 #endif 541 .flags = IRQCHIP_SET_TYPE_MASKED, 542 }; 543 544 static int meson_gpio_irq_domain_translate(struct irq_domain *domain, 545 struct irq_fwspec *fwspec, 546 unsigned long *hwirq, 547 unsigned int *type) 548 { 549 if (is_of_node(fwspec->fwnode) && fwspec->param_count == 2) { 550 *hwirq = fwspec->param[0]; 551 *type = fwspec->param[1]; 552 return 0; 553 } 554 555 return -EINVAL; 556 } 557 558 static int meson_gpio_irq_allocate_gic_irq(struct irq_domain *domain, 559 unsigned int virq, 560 u32 hwirq, 561 unsigned int type) 562 { 563 struct irq_fwspec fwspec; 564 565 fwspec.fwnode = domain->parent->fwnode; 566 fwspec.param_count = 3; 567 fwspec.param[0] = 0; /* SPI */ 568 fwspec.param[1] = hwirq; 569 fwspec.param[2] = meson_gpio_irq_type_output(type); 570 571 return irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec); 572 } 573 574 static int meson_gpio_irq_domain_alloc(struct irq_domain *domain, 575 unsigned int virq, 576 unsigned int nr_irqs, 577 void *data) 578 { 579 struct irq_fwspec *fwspec = data; 580 struct meson_gpio_irq_controller *ctl = domain->host_data; 581 unsigned long hwirq; 582 u32 *channel_hwirq; 583 unsigned int type; 584 int ret; 585 586 if (WARN_ON(nr_irqs != 1)) 587 return -EINVAL; 588 589 ret = meson_gpio_irq_domain_translate(domain, fwspec, &hwirq, &type); 590 if (ret) 591 return ret; 592 593 ret = meson_gpio_irq_request_channel(ctl, hwirq, &channel_hwirq); 594 if (ret) 595 return ret; 596 597 ret = meson_gpio_irq_allocate_gic_irq(domain, virq, 598 *channel_hwirq, type); 599 if (ret < 0) { 600 pr_err("failed to allocate gic irq %u\n", *channel_hwirq); 601 meson_gpio_irq_release_channel(ctl, channel_hwirq); 602 return ret; 603 } 604 605 irq_domain_set_hwirq_and_chip(domain, virq, hwirq, 606 &meson_gpio_irq_chip, channel_hwirq); 607 608 return 0; 609 } 610 611 static void meson_gpio_irq_domain_free(struct irq_domain *domain, 612 unsigned int virq, 613 unsigned int nr_irqs) 614 { 615 struct meson_gpio_irq_controller *ctl = domain->host_data; 616 struct irq_data *irq_data; 617 u32 *channel_hwirq; 618 619 if (WARN_ON(nr_irqs != 1)) 620 return; 621 622 irq_domain_free_irqs_parent(domain, virq, 1); 623 624 irq_data = irq_domain_get_irq_data(domain, virq); 625 channel_hwirq = irq_data_get_irq_chip_data(irq_data); 626 627 meson_gpio_irq_release_channel(ctl, channel_hwirq); 628 } 629 630 static const struct irq_domain_ops meson_gpio_irq_domain_ops = { 631 .alloc = meson_gpio_irq_domain_alloc, 632 .free = meson_gpio_irq_domain_free, 633 .translate = meson_gpio_irq_domain_translate, 634 }; 635 636 static int meson_gpio_irq_parse_dt(struct device_node *node, struct meson_gpio_irq_controller *ctl) 637 { 638 const struct of_device_id *match; 639 int ret; 640 641 match = of_match_node(meson_irq_gpio_matches, node); 642 if (!match) 643 return -ENODEV; 644 645 ctl->params = match->data; 646 647 ret = of_property_read_variable_u32_array(node, 648 "amlogic,channel-interrupts", 649 ctl->channel_irqs, 650 ctl->params->nr_channels, 651 ctl->params->nr_channels); 652 if (ret < 0) { 653 pr_err("can't get %d channel interrupts\n", ctl->params->nr_channels); 654 return ret; 655 } 656 657 ctl->params->ops.gpio_irq_init(ctl); 658 659 return 0; 660 } 661 662 static int meson_gpio_irq_probe(struct platform_device *pdev, struct device_node *parent) 663 { 664 struct device_node *node = pdev->dev.of_node; 665 struct irq_domain *domain, *parent_domain; 666 struct meson_gpio_irq_controller *ctl; 667 int ret; 668 669 if (!parent) { 670 pr_err("missing parent interrupt node\n"); 671 return -ENODEV; 672 } 673 674 parent_domain = irq_find_host(parent); 675 if (!parent_domain) { 676 pr_err("unable to obtain parent domain\n"); 677 return -ENXIO; 678 } 679 680 ctl = kzalloc_obj(*ctl); 681 if (!ctl) 682 return -ENOMEM; 683 684 raw_spin_lock_init(&ctl->lock); 685 686 ctl->base = of_iomap(node, 0); 687 if (!ctl->base) { 688 ret = -ENOMEM; 689 goto free_ctl; 690 } 691 692 ret = meson_gpio_irq_parse_dt(node, ctl); 693 if (ret) 694 goto free_channel_irqs; 695 696 domain = irq_domain_create_hierarchy(parent_domain, 0, 697 ctl->params->nr_hwirq, 698 of_fwnode_handle(node), 699 &meson_gpio_irq_domain_ops, 700 ctl); 701 if (!domain) { 702 pr_err("failed to add domain\n"); 703 ret = -ENODEV; 704 goto free_channel_irqs; 705 } 706 707 pr_info("%d to %d gpio interrupt mux initialized\n", 708 ctl->params->nr_hwirq, ctl->params->nr_channels); 709 710 return 0; 711 712 free_channel_irqs: 713 iounmap(ctl->base); 714 free_ctl: 715 kfree(ctl); 716 717 return ret; 718 } 719 720 IRQCHIP_PLATFORM_DRIVER_BEGIN(meson_gpio_intc) 721 IRQCHIP_MATCH("amlogic,meson-gpio-intc", meson_gpio_irq_probe) 722 IRQCHIP_PLATFORM_DRIVER_END(meson_gpio_intc) 723 724 MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>"); 725 MODULE_DESCRIPTION("Meson GPIO Interrupt Multiplexer driver"); 726 MODULE_LICENSE("GPL v2"); 727