1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2017-2018, Intel Corporation. All rights reserved
4 * Copyright Altera Corporation (C) 2014-2016. All rights reserved.
5 * Copyright 2011-2012 Calxeda, Inc.
6 */
7
8 #include <asm/cacheflush.h>
9 #include <linux/ctype.h>
10 #include <linux/delay.h>
11 #include <linux/edac.h>
12 #include <linux/firmware/intel/stratix10-smc.h>
13 #include <linux/genalloc.h>
14 #include <linux/interrupt.h>
15 #include <linux/irqchip/chained_irq.h>
16 #include <linux/kernel.h>
17 #include <linux/mfd/altera-sysmgr.h>
18 #include <linux/mfd/syscon.h>
19 #include <linux/notifier.h>
20 #include <linux/of_address.h>
21 #include <linux/of_irq.h>
22 #include <linux/of_platform.h>
23 #include <linux/panic_notifier.h>
24 #include <linux/platform_device.h>
25 #include <linux/property.h>
26 #include <linux/regmap.h>
27 #include <linux/types.h>
28 #include <linux/uaccess.h>
29
30 #include "altera_edac.h"
31 #include "edac_module.h"
32
33 #define EDAC_MOD_STR "altera_edac"
34 #define EDAC_DEVICE "Altera"
35
36 #ifdef CONFIG_EDAC_ALTERA_SDRAM
37 static const struct altr_sdram_prv_data c5_data = {
38 .ecc_ctrl_offset = CV_CTLCFG_OFST,
39 .ecc_ctl_en_mask = CV_CTLCFG_ECC_AUTO_EN,
40 .ecc_stat_offset = CV_DRAMSTS_OFST,
41 .ecc_stat_ce_mask = CV_DRAMSTS_SBEERR,
42 .ecc_stat_ue_mask = CV_DRAMSTS_DBEERR,
43 .ecc_saddr_offset = CV_ERRADDR_OFST,
44 .ecc_daddr_offset = CV_ERRADDR_OFST,
45 .ecc_cecnt_offset = CV_SBECOUNT_OFST,
46 .ecc_uecnt_offset = CV_DBECOUNT_OFST,
47 .ecc_irq_en_offset = CV_DRAMINTR_OFST,
48 .ecc_irq_en_mask = CV_DRAMINTR_INTREN,
49 .ecc_irq_clr_offset = CV_DRAMINTR_OFST,
50 .ecc_irq_clr_mask = (CV_DRAMINTR_INTRCLR | CV_DRAMINTR_INTREN),
51 .ecc_cnt_rst_offset = CV_DRAMINTR_OFST,
52 .ecc_cnt_rst_mask = CV_DRAMINTR_INTRCLR,
53 .ce_ue_trgr_offset = CV_CTLCFG_OFST,
54 .ce_set_mask = CV_CTLCFG_GEN_SB_ERR,
55 .ue_set_mask = CV_CTLCFG_GEN_DB_ERR,
56 };
57
58 static const struct altr_sdram_prv_data a10_data = {
59 .ecc_ctrl_offset = A10_ECCCTRL1_OFST,
60 .ecc_ctl_en_mask = A10_ECCCTRL1_ECC_EN,
61 .ecc_stat_offset = A10_INTSTAT_OFST,
62 .ecc_stat_ce_mask = A10_INTSTAT_SBEERR,
63 .ecc_stat_ue_mask = A10_INTSTAT_DBEERR,
64 .ecc_saddr_offset = A10_SERRADDR_OFST,
65 .ecc_daddr_offset = A10_DERRADDR_OFST,
66 .ecc_irq_en_offset = A10_ERRINTEN_OFST,
67 .ecc_irq_en_mask = A10_ECC_IRQ_EN_MASK,
68 .ecc_irq_clr_offset = A10_INTSTAT_OFST,
69 .ecc_irq_clr_mask = (A10_INTSTAT_SBEERR | A10_INTSTAT_DBEERR),
70 .ecc_cnt_rst_offset = A10_ECCCTRL1_OFST,
71 .ecc_cnt_rst_mask = A10_ECC_CNT_RESET_MASK,
72 .ce_ue_trgr_offset = A10_DIAGINTTEST_OFST,
73 .ce_set_mask = A10_DIAGINT_TSERRA_MASK,
74 .ue_set_mask = A10_DIAGINT_TDERRA_MASK,
75 };
76
77 /*********************** EDAC Memory Controller Functions ****************/
78
79 /* The SDRAM controller uses the EDAC Memory Controller framework. */
80
altr_sdram_mc_err_handler(int irq,void * dev_id)81 static irqreturn_t altr_sdram_mc_err_handler(int irq, void *dev_id)
82 {
83 struct mem_ctl_info *mci = dev_id;
84 struct altr_sdram_mc_data *drvdata = mci->pvt_info;
85 const struct altr_sdram_prv_data *priv = drvdata->data;
86 u32 status, err_count = 1, err_addr;
87
88 regmap_read(drvdata->mc_vbase, priv->ecc_stat_offset, &status);
89
90 if (status & priv->ecc_stat_ue_mask) {
91 regmap_read(drvdata->mc_vbase, priv->ecc_daddr_offset,
92 &err_addr);
93 if (priv->ecc_uecnt_offset)
94 regmap_read(drvdata->mc_vbase, priv->ecc_uecnt_offset,
95 &err_count);
96 panic("\nEDAC: [%d Uncorrectable errors @ 0x%08X]\n",
97 err_count, err_addr);
98 }
99 if (status & priv->ecc_stat_ce_mask) {
100 regmap_read(drvdata->mc_vbase, priv->ecc_saddr_offset,
101 &err_addr);
102 if (priv->ecc_cecnt_offset)
103 regmap_read(drvdata->mc_vbase, priv->ecc_cecnt_offset,
104 &err_count);
105 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, err_count,
106 err_addr >> PAGE_SHIFT,
107 err_addr & ~PAGE_MASK, 0,
108 0, 0, -1, mci->ctl_name, "");
109 /* Clear IRQ to resume */
110 regmap_write(drvdata->mc_vbase, priv->ecc_irq_clr_offset,
111 priv->ecc_irq_clr_mask);
112
113 return IRQ_HANDLED;
114 }
115 return IRQ_NONE;
116 }
117
altr_sdr_mc_err_inject_write(struct file * file,const char __user * data,size_t count,loff_t * ppos)118 static ssize_t altr_sdr_mc_err_inject_write(struct file *file,
119 const char __user *data,
120 size_t count, loff_t *ppos)
121 {
122 struct mem_ctl_info *mci = file->private_data;
123 struct altr_sdram_mc_data *drvdata = mci->pvt_info;
124 const struct altr_sdram_prv_data *priv = drvdata->data;
125 u32 *ptemp;
126 dma_addr_t dma_handle;
127 u32 reg, read_reg;
128
129 ptemp = dma_alloc_coherent(mci->pdev, 16, &dma_handle, GFP_KERNEL);
130 if (!ptemp) {
131 edac_printk(KERN_ERR, EDAC_MC,
132 "Inject: Buffer Allocation error\n");
133 return -ENOMEM;
134 }
135
136 regmap_read(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
137 &read_reg);
138 read_reg &= ~(priv->ce_set_mask | priv->ue_set_mask);
139
140 /* Error are injected by writing a word while the SBE or DBE
141 * bit in the CTLCFG register is set. Reading the word will
142 * trigger the SBE or DBE error and the corresponding IRQ.
143 */
144 if (count == 3) {
145 edac_printk(KERN_ALERT, EDAC_MC,
146 "Inject Double bit error\n");
147 local_irq_disable();
148 regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
149 (read_reg | priv->ue_set_mask));
150 local_irq_enable();
151 } else {
152 edac_printk(KERN_ALERT, EDAC_MC,
153 "Inject Single bit error\n");
154 local_irq_disable();
155 regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
156 (read_reg | priv->ce_set_mask));
157 local_irq_enable();
158 }
159
160 ptemp[0] = 0x5A5A5A5A;
161 ptemp[1] = 0xA5A5A5A5;
162
163 /* Clear the error injection bits */
164 regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset, read_reg);
165 /* Ensure it has been written out */
166 wmb();
167
168 /*
169 * To trigger the error, we need to read the data back
170 * (the data was written with errors above).
171 * The READ_ONCE macros and printk are used to prevent the
172 * the compiler optimizing these reads out.
173 */
174 reg = READ_ONCE(ptemp[0]);
175 read_reg = READ_ONCE(ptemp[1]);
176 /* Force Read */
177 rmb();
178
179 edac_printk(KERN_ALERT, EDAC_MC, "Read Data [0x%X, 0x%X]\n",
180 reg, read_reg);
181
182 dma_free_coherent(mci->pdev, 16, ptemp, dma_handle);
183
184 return count;
185 }
186
187 static const struct file_operations altr_sdr_mc_debug_inject_fops = {
188 .open = simple_open,
189 .write = altr_sdr_mc_err_inject_write,
190 .llseek = generic_file_llseek,
191 };
192
altr_sdr_mc_create_debugfs_nodes(struct mem_ctl_info * mci)193 static void altr_sdr_mc_create_debugfs_nodes(struct mem_ctl_info *mci)
194 {
195 if (!IS_ENABLED(CONFIG_EDAC_DEBUG))
196 return;
197
198 if (!mci->debugfs)
199 return;
200
201 edac_debugfs_create_file("altr_trigger", S_IWUSR, mci->debugfs, mci,
202 &altr_sdr_mc_debug_inject_fops);
203 }
204
205 /* Get total memory size from Open Firmware DTB */
get_total_mem(void)206 static unsigned long get_total_mem(void)
207 {
208 struct device_node *np = NULL;
209 struct resource res;
210 int ret;
211 unsigned long total_mem = 0;
212
213 for_each_node_by_type(np, "memory") {
214 ret = of_address_to_resource(np, 0, &res);
215 if (ret)
216 continue;
217
218 total_mem += resource_size(&res);
219 }
220 edac_dbg(0, "total_mem 0x%lx\n", total_mem);
221 return total_mem;
222 }
223
224 static const struct of_device_id altr_sdram_ctrl_of_match[] = {
225 { .compatible = "altr,sdram-edac", .data = &c5_data},
226 { .compatible = "altr,sdram-edac-a10", .data = &a10_data},
227 {},
228 };
229 MODULE_DEVICE_TABLE(of, altr_sdram_ctrl_of_match);
230
a10_init(struct regmap * mc_vbase)231 static int a10_init(struct regmap *mc_vbase)
232 {
233 if (regmap_update_bits(mc_vbase, A10_INTMODE_OFST,
234 A10_INTMODE_SB_INT, A10_INTMODE_SB_INT)) {
235 edac_printk(KERN_ERR, EDAC_MC,
236 "Error setting SB IRQ mode\n");
237 return -ENODEV;
238 }
239
240 if (regmap_write(mc_vbase, A10_SERRCNTREG_OFST, 1)) {
241 edac_printk(KERN_ERR, EDAC_MC,
242 "Error setting trigger count\n");
243 return -ENODEV;
244 }
245
246 return 0;
247 }
248
a10_unmask_irq(struct platform_device * pdev,u32 mask)249 static int a10_unmask_irq(struct platform_device *pdev, u32 mask)
250 {
251 void __iomem *sm_base;
252 int ret = 0;
253
254 if (!request_mem_region(A10_SYMAN_INTMASK_CLR, sizeof(u32),
255 dev_name(&pdev->dev))) {
256 edac_printk(KERN_ERR, EDAC_MC,
257 "Unable to request mem region\n");
258 return -EBUSY;
259 }
260
261 sm_base = ioremap(A10_SYMAN_INTMASK_CLR, sizeof(u32));
262 if (!sm_base) {
263 edac_printk(KERN_ERR, EDAC_MC,
264 "Unable to ioremap device\n");
265
266 ret = -ENOMEM;
267 goto release;
268 }
269
270 iowrite32(mask, sm_base);
271
272 iounmap(sm_base);
273
274 release:
275 release_mem_region(A10_SYMAN_INTMASK_CLR, sizeof(u32));
276
277 return ret;
278 }
279
altr_sdram_probe(struct platform_device * pdev)280 static int altr_sdram_probe(struct platform_device *pdev)
281 {
282 struct edac_mc_layer layers[2];
283 struct mem_ctl_info *mci;
284 struct altr_sdram_mc_data *drvdata;
285 const struct altr_sdram_prv_data *priv;
286 struct regmap *mc_vbase;
287 struct dimm_info *dimm;
288 u32 read_reg;
289 int irq, irq2, res = 0;
290 unsigned long mem_size, irqflags = 0;
291
292 /* Grab the register range from the sdr controller in device tree */
293 mc_vbase = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
294 "altr,sdr-syscon");
295 if (IS_ERR(mc_vbase)) {
296 edac_printk(KERN_ERR, EDAC_MC,
297 "regmap for altr,sdr-syscon lookup failed.\n");
298 return -ENODEV;
299 }
300
301 /* Check specific dependencies for the module */
302 priv = device_get_match_data(&pdev->dev);
303
304 /* Validate the SDRAM controller has ECC enabled */
305 if (regmap_read(mc_vbase, priv->ecc_ctrl_offset, &read_reg) ||
306 ((read_reg & priv->ecc_ctl_en_mask) != priv->ecc_ctl_en_mask)) {
307 edac_printk(KERN_ERR, EDAC_MC,
308 "No ECC/ECC disabled [0x%08X]\n", read_reg);
309 return -ENODEV;
310 }
311
312 /* Grab memory size from device tree. */
313 mem_size = get_total_mem();
314 if (!mem_size) {
315 edac_printk(KERN_ERR, EDAC_MC, "Unable to calculate memory size\n");
316 return -ENODEV;
317 }
318
319 /* Ensure the SDRAM Interrupt is disabled */
320 if (regmap_update_bits(mc_vbase, priv->ecc_irq_en_offset,
321 priv->ecc_irq_en_mask, 0)) {
322 edac_printk(KERN_ERR, EDAC_MC,
323 "Error disabling SDRAM ECC IRQ\n");
324 return -ENODEV;
325 }
326
327 /* Toggle to clear the SDRAM Error count */
328 if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset,
329 priv->ecc_cnt_rst_mask,
330 priv->ecc_cnt_rst_mask)) {
331 edac_printk(KERN_ERR, EDAC_MC,
332 "Error clearing SDRAM ECC count\n");
333 return -ENODEV;
334 }
335
336 if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset,
337 priv->ecc_cnt_rst_mask, 0)) {
338 edac_printk(KERN_ERR, EDAC_MC,
339 "Error clearing SDRAM ECC count\n");
340 return -ENODEV;
341 }
342
343 irq = platform_get_irq(pdev, 0);
344 if (irq < 0) {
345 edac_printk(KERN_ERR, EDAC_MC,
346 "No irq %d in DT\n", irq);
347 return irq;
348 }
349
350 /* Arria10 has a 2nd IRQ */
351 irq2 = platform_get_irq(pdev, 1);
352
353 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
354 layers[0].size = 1;
355 layers[0].is_virt_csrow = true;
356 layers[1].type = EDAC_MC_LAYER_CHANNEL;
357 layers[1].size = 1;
358 layers[1].is_virt_csrow = false;
359 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
360 sizeof(struct altr_sdram_mc_data));
361 if (!mci)
362 return -ENOMEM;
363
364 mci->pdev = &pdev->dev;
365 drvdata = mci->pvt_info;
366 drvdata->mc_vbase = mc_vbase;
367 drvdata->data = priv;
368 platform_set_drvdata(pdev, mci);
369
370 if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) {
371 edac_printk(KERN_ERR, EDAC_MC,
372 "Unable to get managed device resource\n");
373 res = -ENOMEM;
374 goto free;
375 }
376
377 mci->mtype_cap = MEM_FLAG_DDR3;
378 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
379 mci->edac_cap = EDAC_FLAG_SECDED;
380 mci->mod_name = EDAC_MOD_STR;
381 mci->ctl_name = dev_name(&pdev->dev);
382 mci->scrub_mode = SCRUB_SW_SRC;
383 mci->dev_name = dev_name(&pdev->dev);
384
385 dimm = *mci->dimms;
386 dimm->nr_pages = ((mem_size - 1) >> PAGE_SHIFT) + 1;
387 dimm->grain = 8;
388 dimm->dtype = DEV_X8;
389 dimm->mtype = MEM_DDR3;
390 dimm->edac_mode = EDAC_SECDED;
391
392 res = edac_mc_add_mc(mci);
393 if (res < 0)
394 goto err;
395
396 /* Only the Arria10 has separate IRQs */
397 if (of_machine_is_compatible("altr,socfpga-arria10")) {
398 /* Arria10 specific initialization */
399 res = a10_init(mc_vbase);
400 if (res < 0)
401 goto err2;
402
403 res = devm_request_irq(&pdev->dev, irq2,
404 altr_sdram_mc_err_handler,
405 IRQF_SHARED, dev_name(&pdev->dev), mci);
406 if (res < 0) {
407 edac_mc_printk(mci, KERN_ERR,
408 "Unable to request irq %d\n", irq2);
409 res = -ENODEV;
410 goto err2;
411 }
412
413 res = a10_unmask_irq(pdev, A10_DDR0_IRQ_MASK);
414 if (res < 0)
415 goto err2;
416
417 irqflags = IRQF_SHARED;
418 }
419
420 res = devm_request_irq(&pdev->dev, irq, altr_sdram_mc_err_handler,
421 irqflags, dev_name(&pdev->dev), mci);
422 if (res < 0) {
423 edac_mc_printk(mci, KERN_ERR,
424 "Unable to request irq %d\n", irq);
425 res = -ENODEV;
426 goto err2;
427 }
428
429 /* Infrastructure ready - enable the IRQ */
430 if (regmap_update_bits(drvdata->mc_vbase, priv->ecc_irq_en_offset,
431 priv->ecc_irq_en_mask, priv->ecc_irq_en_mask)) {
432 edac_mc_printk(mci, KERN_ERR,
433 "Error enabling SDRAM ECC IRQ\n");
434 res = -ENODEV;
435 goto err2;
436 }
437
438 altr_sdr_mc_create_debugfs_nodes(mci);
439
440 devres_close_group(&pdev->dev, NULL);
441
442 return 0;
443
444 err2:
445 edac_mc_del_mc(&pdev->dev);
446 err:
447 devres_release_group(&pdev->dev, NULL);
448 free:
449 edac_mc_free(mci);
450 edac_printk(KERN_ERR, EDAC_MC,
451 "EDAC Probe Failed; Error %d\n", res);
452
453 return res;
454 }
455
altr_sdram_remove(struct platform_device * pdev)456 static void altr_sdram_remove(struct platform_device *pdev)
457 {
458 struct mem_ctl_info *mci = platform_get_drvdata(pdev);
459
460 edac_mc_del_mc(&pdev->dev);
461 edac_mc_free(mci);
462 platform_set_drvdata(pdev, NULL);
463 }
464
465 /*
466 * If you want to suspend, need to disable EDAC by removing it
467 * from the device tree or defconfig.
468 */
469 #ifdef CONFIG_PM
altr_sdram_prepare(struct device * dev)470 static int altr_sdram_prepare(struct device *dev)
471 {
472 pr_err("Suspend not allowed when EDAC is enabled.\n");
473
474 return -EPERM;
475 }
476
477 static const struct dev_pm_ops altr_sdram_pm_ops = {
478 .prepare = altr_sdram_prepare,
479 };
480 #endif
481
482 static struct platform_driver altr_sdram_edac_driver = {
483 .probe = altr_sdram_probe,
484 .remove = altr_sdram_remove,
485 .driver = {
486 .name = "altr_sdram_edac",
487 #ifdef CONFIG_PM
488 .pm = &altr_sdram_pm_ops,
489 #endif
490 .of_match_table = altr_sdram_ctrl_of_match,
491 },
492 };
493
494 module_platform_driver(altr_sdram_edac_driver);
495
496 #endif /* CONFIG_EDAC_ALTERA_SDRAM */
497
498 /************************* EDAC Parent Probe *************************/
499
500 static const struct of_device_id altr_edac_device_of_match[];
501
502 static const struct of_device_id altr_edac_of_match[] = {
503 { .compatible = "altr,socfpga-ecc-manager" },
504 {},
505 };
506 MODULE_DEVICE_TABLE(of, altr_edac_of_match);
507
altr_edac_probe(struct platform_device * pdev)508 static int altr_edac_probe(struct platform_device *pdev)
509 {
510 of_platform_populate(pdev->dev.of_node, altr_edac_device_of_match,
511 NULL, &pdev->dev);
512 return 0;
513 }
514
515 static struct platform_driver altr_edac_driver = {
516 .probe = altr_edac_probe,
517 .driver = {
518 .name = "socfpga_ecc_manager",
519 .of_match_table = altr_edac_of_match,
520 },
521 };
522 module_platform_driver(altr_edac_driver);
523
524 /************************* EDAC Device Functions *************************/
525
526 /*
527 * EDAC Device Functions (shared between various IPs).
528 * The discrete memories use the EDAC Device framework. The probe
529 * and error handling functions are very similar between memories
530 * so they are shared. The memory allocation and freeing for EDAC
531 * trigger testing are different for each memory.
532 */
533
534 #ifdef CONFIG_EDAC_ALTERA_OCRAM
535 static const struct edac_device_prv_data ocramecc_data;
536 #endif
537 #ifdef CONFIG_EDAC_ALTERA_L2C
538 static const struct edac_device_prv_data l2ecc_data;
539 #endif
540 #ifdef CONFIG_EDAC_ALTERA_OCRAM
541 static const struct edac_device_prv_data a10_ocramecc_data;
542 #endif
543 #ifdef CONFIG_EDAC_ALTERA_L2C
544 static const struct edac_device_prv_data a10_l2ecc_data;
545 #endif
546
altr_edac_device_handler(int irq,void * dev_id)547 static irqreturn_t altr_edac_device_handler(int irq, void *dev_id)
548 {
549 irqreturn_t ret_value = IRQ_NONE;
550 struct edac_device_ctl_info *dci = dev_id;
551 struct altr_edac_device_dev *drvdata = dci->pvt_info;
552 const struct edac_device_prv_data *priv = drvdata->data;
553
554 if (irq == drvdata->sb_irq) {
555 if (priv->ce_clear_mask)
556 writel(priv->ce_clear_mask, drvdata->base);
557 edac_device_handle_ce(dci, 0, 0, drvdata->edac_dev_name);
558 ret_value = IRQ_HANDLED;
559 } else if (irq == drvdata->db_irq) {
560 if (priv->ue_clear_mask)
561 writel(priv->ue_clear_mask, drvdata->base);
562 edac_device_handle_ue(dci, 0, 0, drvdata->edac_dev_name);
563 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
564 ret_value = IRQ_HANDLED;
565 } else {
566 WARN_ON(1);
567 }
568
569 return ret_value;
570 }
571
572 static ssize_t __maybe_unused
altr_edac_device_trig(struct file * file,const char __user * user_buf,size_t count,loff_t * ppos)573 altr_edac_device_trig(struct file *file, const char __user *user_buf,
574 size_t count, loff_t *ppos)
575
576 {
577 u32 *ptemp, i, error_mask;
578 int result = 0;
579 u8 trig_type;
580 unsigned long flags;
581 struct edac_device_ctl_info *edac_dci = file->private_data;
582 struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
583 const struct edac_device_prv_data *priv = drvdata->data;
584 void *generic_ptr = edac_dci->dev;
585
586 if (!user_buf || get_user(trig_type, user_buf))
587 return -EFAULT;
588
589 if (!priv->alloc_mem)
590 return -ENOMEM;
591
592 /*
593 * Note that generic_ptr is initialized to the device * but in
594 * some alloc_functions, this is overridden and returns data.
595 */
596 ptemp = priv->alloc_mem(priv->trig_alloc_sz, &generic_ptr);
597 if (!ptemp) {
598 edac_printk(KERN_ERR, EDAC_DEVICE,
599 "Inject: Buffer Allocation error\n");
600 return -ENOMEM;
601 }
602
603 if (trig_type == ALTR_UE_TRIGGER_CHAR)
604 error_mask = priv->ue_set_mask;
605 else
606 error_mask = priv->ce_set_mask;
607
608 edac_printk(KERN_ALERT, EDAC_DEVICE,
609 "Trigger Error Mask (0x%X)\n", error_mask);
610
611 local_irq_save(flags);
612 /* write ECC corrupted data out. */
613 for (i = 0; i < (priv->trig_alloc_sz / sizeof(*ptemp)); i++) {
614 /* Read data so we're in the correct state */
615 rmb();
616 if (READ_ONCE(ptemp[i]))
617 result = -1;
618 /* Toggle Error bit (it is latched), leave ECC enabled */
619 writel(error_mask, (drvdata->base + priv->set_err_ofst));
620 writel(priv->ecc_enable_mask, (drvdata->base +
621 priv->set_err_ofst));
622 ptemp[i] = i;
623 }
624 /* Ensure it has been written out */
625 wmb();
626 local_irq_restore(flags);
627
628 if (result)
629 edac_printk(KERN_ERR, EDAC_DEVICE, "Mem Not Cleared\n");
630
631 /* Read out written data. ECC error caused here */
632 for (i = 0; i < ALTR_TRIGGER_READ_WRD_CNT; i++)
633 if (READ_ONCE(ptemp[i]) != i)
634 edac_printk(KERN_ERR, EDAC_DEVICE,
635 "Read doesn't match written data\n");
636
637 if (priv->free_mem)
638 priv->free_mem(ptemp, priv->trig_alloc_sz, generic_ptr);
639
640 return count;
641 }
642
643 static const struct file_operations altr_edac_device_inject_fops __maybe_unused = {
644 .open = simple_open,
645 .write = altr_edac_device_trig,
646 .llseek = generic_file_llseek,
647 };
648
649 static ssize_t __maybe_unused
650 altr_edac_a10_device_trig(struct file *file, const char __user *user_buf,
651 size_t count, loff_t *ppos);
652
653 static const struct file_operations altr_edac_a10_device_inject_fops __maybe_unused = {
654 .open = simple_open,
655 .write = altr_edac_a10_device_trig,
656 .llseek = generic_file_llseek,
657 };
658
659 static ssize_t __maybe_unused
660 altr_edac_a10_device_trig2(struct file *file, const char __user *user_buf,
661 size_t count, loff_t *ppos);
662
663 static const struct file_operations altr_edac_a10_device_inject2_fops __maybe_unused = {
664 .open = simple_open,
665 .write = altr_edac_a10_device_trig2,
666 .llseek = generic_file_llseek,
667 };
668
altr_create_edacdev_dbgfs(struct edac_device_ctl_info * edac_dci,const struct edac_device_prv_data * priv)669 static void altr_create_edacdev_dbgfs(struct edac_device_ctl_info *edac_dci,
670 const struct edac_device_prv_data *priv)
671 {
672 struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
673
674 if (!IS_ENABLED(CONFIG_EDAC_DEBUG))
675 return;
676
677 drvdata->debugfs_dir = edac_debugfs_create_dir(drvdata->edac_dev_name);
678 if (!drvdata->debugfs_dir)
679 return;
680
681 if (!edac_debugfs_create_file("altr_trigger", S_IWUSR,
682 drvdata->debugfs_dir, edac_dci,
683 priv->inject_fops))
684 debugfs_remove_recursive(drvdata->debugfs_dir);
685 }
686
687 static const struct of_device_id altr_edac_device_of_match[] = {
688 #ifdef CONFIG_EDAC_ALTERA_L2C
689 { .compatible = "altr,socfpga-l2-ecc", .data = &l2ecc_data },
690 #endif
691 #ifdef CONFIG_EDAC_ALTERA_OCRAM
692 { .compatible = "altr,socfpga-ocram-ecc", .data = &ocramecc_data },
693 #endif
694 {},
695 };
696 MODULE_DEVICE_TABLE(of, altr_edac_device_of_match);
697
698 /*
699 * altr_edac_device_probe()
700 * This is a generic EDAC device driver that will support
701 * various Altera memory devices such as the L2 cache ECC and
702 * OCRAM ECC as well as the memories for other peripherals.
703 * Module specific initialization is done by passing the
704 * function index in the device tree.
705 */
altr_edac_device_probe(struct platform_device * pdev)706 static int altr_edac_device_probe(struct platform_device *pdev)
707 {
708 struct edac_device_ctl_info *dci;
709 struct altr_edac_device_dev *drvdata;
710 struct resource *r;
711 int res = 0;
712 struct device_node *np = pdev->dev.of_node;
713 char *ecc_name = (char *)np->name;
714 static int dev_instance;
715
716 if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) {
717 edac_printk(KERN_ERR, EDAC_DEVICE,
718 "Unable to open devm\n");
719 return -ENOMEM;
720 }
721
722 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
723 if (!r) {
724 edac_printk(KERN_ERR, EDAC_DEVICE,
725 "Unable to get mem resource\n");
726 res = -ENODEV;
727 goto fail;
728 }
729
730 if (!devm_request_mem_region(&pdev->dev, r->start, resource_size(r),
731 dev_name(&pdev->dev))) {
732 edac_printk(KERN_ERR, EDAC_DEVICE,
733 "%s:Error requesting mem region\n", ecc_name);
734 res = -EBUSY;
735 goto fail;
736 }
737
738 dci = edac_device_alloc_ctl_info(sizeof(*drvdata), ecc_name,
739 1, ecc_name, 1, 0, dev_instance++);
740
741 if (!dci) {
742 edac_printk(KERN_ERR, EDAC_DEVICE,
743 "%s: Unable to allocate EDAC device\n", ecc_name);
744 res = -ENOMEM;
745 goto fail;
746 }
747
748 drvdata = dci->pvt_info;
749 dci->dev = &pdev->dev;
750 platform_set_drvdata(pdev, dci);
751 drvdata->edac_dev_name = ecc_name;
752
753 drvdata->base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
754 if (!drvdata->base) {
755 res = -ENOMEM;
756 goto fail1;
757 }
758
759 /* Get driver specific data for this EDAC device */
760 drvdata->data = of_match_node(altr_edac_device_of_match, np)->data;
761
762 /* Check specific dependencies for the module */
763 if (drvdata->data->setup) {
764 res = drvdata->data->setup(drvdata);
765 if (res)
766 goto fail1;
767 }
768
769 drvdata->sb_irq = platform_get_irq(pdev, 0);
770 res = devm_request_irq(&pdev->dev, drvdata->sb_irq,
771 altr_edac_device_handler,
772 0, dev_name(&pdev->dev), dci);
773 if (res)
774 goto fail1;
775
776 drvdata->db_irq = platform_get_irq(pdev, 1);
777 res = devm_request_irq(&pdev->dev, drvdata->db_irq,
778 altr_edac_device_handler,
779 0, dev_name(&pdev->dev), dci);
780 if (res)
781 goto fail1;
782
783 dci->mod_name = "Altera ECC Manager";
784 dci->dev_name = drvdata->edac_dev_name;
785
786 res = edac_device_add_device(dci);
787 if (res)
788 goto fail1;
789
790 altr_create_edacdev_dbgfs(dci, drvdata->data);
791
792 devres_close_group(&pdev->dev, NULL);
793
794 return 0;
795
796 fail1:
797 edac_device_free_ctl_info(dci);
798 fail:
799 devres_release_group(&pdev->dev, NULL);
800 edac_printk(KERN_ERR, EDAC_DEVICE,
801 "%s:Error setting up EDAC device: %d\n", ecc_name, res);
802
803 return res;
804 }
805
altr_edac_device_remove(struct platform_device * pdev)806 static void altr_edac_device_remove(struct platform_device *pdev)
807 {
808 struct edac_device_ctl_info *dci = platform_get_drvdata(pdev);
809 struct altr_edac_device_dev *drvdata = dci->pvt_info;
810
811 debugfs_remove_recursive(drvdata->debugfs_dir);
812 edac_device_del_device(&pdev->dev);
813 edac_device_free_ctl_info(dci);
814 }
815
816 static struct platform_driver altr_edac_device_driver = {
817 .probe = altr_edac_device_probe,
818 .remove = altr_edac_device_remove,
819 .driver = {
820 .name = "altr_edac_device",
821 .of_match_table = altr_edac_device_of_match,
822 },
823 };
824 module_platform_driver(altr_edac_device_driver);
825
826 /******************* Arria10 Device ECC Shared Functions *****************/
827
828 /*
829 * Test for memory's ECC dependencies upon entry because platform specific
830 * startup should have initialized the memory and enabled the ECC.
831 * Can't turn on ECC here because accessing un-initialized memory will
832 * cause CE/UE errors possibly causing an ABORT.
833 */
834 static int __maybe_unused
altr_check_ecc_deps(struct altr_edac_device_dev * device)835 altr_check_ecc_deps(struct altr_edac_device_dev *device)
836 {
837 void __iomem *base = device->base;
838 const struct edac_device_prv_data *prv = device->data;
839
840 if (readl(base + prv->ecc_en_ofst) & prv->ecc_enable_mask)
841 return 0;
842
843 edac_printk(KERN_ERR, EDAC_DEVICE,
844 "%s: No ECC present or ECC disabled.\n",
845 device->edac_dev_name);
846 return -ENODEV;
847 }
848
altr_edac_a10_ecc_irq(int irq,void * dev_id)849 static irqreturn_t __maybe_unused altr_edac_a10_ecc_irq(int irq, void *dev_id)
850 {
851 struct altr_edac_device_dev *dci = dev_id;
852 void __iomem *base = dci->base;
853
854 if (irq == dci->sb_irq) {
855 writel(ALTR_A10_ECC_SERRPENA,
856 base + ALTR_A10_ECC_INTSTAT_OFST);
857 edac_device_handle_ce(dci->edac_dev, 0, 0, dci->edac_dev_name);
858
859 return IRQ_HANDLED;
860 } else if (irq == dci->db_irq) {
861 writel(ALTR_A10_ECC_DERRPENA,
862 base + ALTR_A10_ECC_INTSTAT_OFST);
863 edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name);
864 if (dci->data->panic)
865 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
866
867 return IRQ_HANDLED;
868 }
869
870 WARN_ON(1);
871
872 return IRQ_NONE;
873 }
874
875 /******************* Arria10 Memory Buffer Functions *********************/
876
a10_get_irq_mask(struct device_node * np)877 static inline int a10_get_irq_mask(struct device_node *np)
878 {
879 int irq;
880 const u32 *handle = of_get_property(np, "interrupts", NULL);
881
882 if (!handle)
883 return -ENODEV;
884 irq = be32_to_cpup(handle);
885 return irq;
886 }
887
ecc_set_bits(u32 bit_mask,void __iomem * ioaddr)888 static inline void ecc_set_bits(u32 bit_mask, void __iomem *ioaddr)
889 {
890 u32 value = readl(ioaddr);
891
892 value |= bit_mask;
893 writel(value, ioaddr);
894 }
895
ecc_clear_bits(u32 bit_mask,void __iomem * ioaddr)896 static inline void ecc_clear_bits(u32 bit_mask, void __iomem *ioaddr)
897 {
898 u32 value = readl(ioaddr);
899
900 value &= ~bit_mask;
901 writel(value, ioaddr);
902 }
903
ecc_test_bits(u32 bit_mask,void __iomem * ioaddr)904 static inline int ecc_test_bits(u32 bit_mask, void __iomem *ioaddr)
905 {
906 u32 value = readl(ioaddr);
907
908 return (value & bit_mask) ? 1 : 0;
909 }
910
911 /*
912 * This function uses the memory initialization block in the Arria10 ECC
913 * controller to initialize/clear the entire memory data and ECC data.
914 */
altr_init_memory_port(void __iomem * ioaddr,int port)915 static int __maybe_unused altr_init_memory_port(void __iomem *ioaddr, int port)
916 {
917 int limit = ALTR_A10_ECC_INIT_WATCHDOG_10US;
918 u32 init_mask, stat_mask, clear_mask;
919 int ret = 0;
920
921 if (port) {
922 init_mask = ALTR_A10_ECC_INITB;
923 stat_mask = ALTR_A10_ECC_INITCOMPLETEB;
924 clear_mask = ALTR_A10_ECC_ERRPENB_MASK;
925 } else {
926 init_mask = ALTR_A10_ECC_INITA;
927 stat_mask = ALTR_A10_ECC_INITCOMPLETEA;
928 clear_mask = ALTR_A10_ECC_ERRPENA_MASK;
929 }
930
931 ecc_set_bits(init_mask, (ioaddr + ALTR_A10_ECC_CTRL_OFST));
932 while (limit--) {
933 if (ecc_test_bits(stat_mask,
934 (ioaddr + ALTR_A10_ECC_INITSTAT_OFST)))
935 break;
936 udelay(1);
937 }
938 if (limit < 0)
939 ret = -EBUSY;
940
941 /* Clear any pending ECC interrupts */
942 writel(clear_mask, (ioaddr + ALTR_A10_ECC_INTSTAT_OFST));
943
944 return ret;
945 }
946
947 static __init int __maybe_unused
altr_init_a10_ecc_block(struct device_node * np,u32 irq_mask,u32 ecc_ctrl_en_mask,bool dual_port)948 altr_init_a10_ecc_block(struct device_node *np, u32 irq_mask,
949 u32 ecc_ctrl_en_mask, bool dual_port)
950 {
951 int ret = 0;
952 void __iomem *ecc_block_base;
953 struct regmap *ecc_mgr_map;
954 char *ecc_name;
955 struct device_node *np_eccmgr;
956
957 ecc_name = (char *)np->name;
958
959 /* Get the ECC Manager - parent of the device EDACs */
960 np_eccmgr = of_get_parent(np);
961
962 ecc_mgr_map =
963 altr_sysmgr_regmap_lookup_by_phandle(np_eccmgr,
964 "altr,sysmgr-syscon");
965
966 of_node_put(np_eccmgr);
967 if (IS_ERR(ecc_mgr_map)) {
968 edac_printk(KERN_ERR, EDAC_DEVICE,
969 "Unable to get syscon altr,sysmgr-syscon\n");
970 return -ENODEV;
971 }
972
973 /* Map the ECC Block */
974 ecc_block_base = of_iomap(np, 0);
975 if (!ecc_block_base) {
976 edac_printk(KERN_ERR, EDAC_DEVICE,
977 "Unable to map %s ECC block\n", ecc_name);
978 return -ENODEV;
979 }
980
981 /* Disable ECC */
982 regmap_write(ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_SET_OFST, irq_mask);
983 writel(ALTR_A10_ECC_SERRINTEN,
984 (ecc_block_base + ALTR_A10_ECC_ERRINTENR_OFST));
985 ecc_clear_bits(ecc_ctrl_en_mask,
986 (ecc_block_base + ALTR_A10_ECC_CTRL_OFST));
987 /* Ensure all writes complete */
988 wmb();
989 /* Use HW initialization block to initialize memory for ECC */
990 ret = altr_init_memory_port(ecc_block_base, 0);
991 if (ret) {
992 edac_printk(KERN_ERR, EDAC_DEVICE,
993 "ECC: cannot init %s PORTA memory\n", ecc_name);
994 goto out;
995 }
996
997 if (dual_port) {
998 ret = altr_init_memory_port(ecc_block_base, 1);
999 if (ret) {
1000 edac_printk(KERN_ERR, EDAC_DEVICE,
1001 "ECC: cannot init %s PORTB memory\n",
1002 ecc_name);
1003 goto out;
1004 }
1005 }
1006
1007 /* Enable ECC */
1008 ecc_set_bits(ecc_ctrl_en_mask, (ecc_block_base +
1009 ALTR_A10_ECC_CTRL_OFST));
1010 writel(ALTR_A10_ECC_SERRINTEN,
1011 (ecc_block_base + ALTR_A10_ECC_ERRINTENS_OFST));
1012 regmap_write(ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_CLR_OFST, irq_mask);
1013 /* Ensure all writes complete */
1014 wmb();
1015 out:
1016 iounmap(ecc_block_base);
1017 return ret;
1018 }
1019
1020 static int validate_parent_available(struct device_node *np);
1021 static const struct of_device_id altr_edac_a10_device_of_match[];
altr_init_a10_ecc_device_type(char * compat)1022 static int __init __maybe_unused altr_init_a10_ecc_device_type(char *compat)
1023 {
1024 int irq;
1025 struct device_node *child, *np;
1026
1027 np = of_find_compatible_node(NULL, NULL,
1028 "altr,socfpga-a10-ecc-manager");
1029 if (!np) {
1030 edac_printk(KERN_ERR, EDAC_DEVICE, "ECC Manager not found\n");
1031 return -ENODEV;
1032 }
1033
1034 for_each_child_of_node(np, child) {
1035 const struct of_device_id *pdev_id;
1036 const struct edac_device_prv_data *prv;
1037
1038 if (!of_device_is_available(child))
1039 continue;
1040 if (!of_device_is_compatible(child, compat))
1041 continue;
1042
1043 if (validate_parent_available(child))
1044 continue;
1045
1046 irq = a10_get_irq_mask(child);
1047 if (irq < 0)
1048 continue;
1049
1050 /* Get matching node and check for valid result */
1051 pdev_id = of_match_node(altr_edac_a10_device_of_match, child);
1052 if (IS_ERR_OR_NULL(pdev_id))
1053 continue;
1054
1055 /* Validate private data pointer before dereferencing */
1056 prv = pdev_id->data;
1057 if (!prv)
1058 continue;
1059
1060 altr_init_a10_ecc_block(child, BIT(irq),
1061 prv->ecc_enable_mask, 0);
1062 }
1063
1064 of_node_put(np);
1065 return 0;
1066 }
1067
1068 /*********************** SDRAM EDAC Device Functions *********************/
1069
1070 #ifdef CONFIG_EDAC_ALTERA_SDRAM
1071
1072 /*
1073 * A legacy U-Boot bug only enabled memory mapped access to the ECC Enable
1074 * register if ECC is enabled. Linux checks the ECC Enable register to
1075 * determine ECC status.
1076 * Use an SMC call (which always works) to determine ECC enablement.
1077 */
altr_s10_sdram_check_ecc_deps(struct altr_edac_device_dev * device)1078 static int altr_s10_sdram_check_ecc_deps(struct altr_edac_device_dev *device)
1079 {
1080 const struct edac_device_prv_data *prv = device->data;
1081 unsigned long sdram_ecc_addr;
1082 struct arm_smccc_res result;
1083 struct device_node *np;
1084 phys_addr_t sdram_addr;
1085 u32 read_reg;
1086 int ret;
1087
1088 np = of_find_compatible_node(NULL, NULL, "altr,sdr-ctl");
1089 if (!np)
1090 goto sdram_err;
1091
1092 sdram_addr = of_translate_address(np, of_get_address(np, 0,
1093 NULL, NULL));
1094 of_node_put(np);
1095 sdram_ecc_addr = (unsigned long)sdram_addr + prv->ecc_en_ofst;
1096 arm_smccc_smc(INTEL_SIP_SMC_REG_READ, sdram_ecc_addr,
1097 0, 0, 0, 0, 0, 0, &result);
1098 read_reg = (unsigned int)result.a1;
1099 ret = (int)result.a0;
1100 if (!ret && (read_reg & prv->ecc_enable_mask))
1101 return 0;
1102
1103 sdram_err:
1104 edac_printk(KERN_ERR, EDAC_DEVICE,
1105 "%s: No ECC present or ECC disabled.\n",
1106 device->edac_dev_name);
1107 return -ENODEV;
1108 }
1109
1110 static const struct edac_device_prv_data s10_sdramecc_data = {
1111 .setup = altr_s10_sdram_check_ecc_deps,
1112 .ce_clear_mask = ALTR_S10_ECC_SERRPENA,
1113 .ue_clear_mask = ALTR_S10_ECC_DERRPENA,
1114 .ecc_enable_mask = ALTR_S10_ECC_EN,
1115 .ecc_en_ofst = ALTR_S10_ECC_CTRL_SDRAM_OFST,
1116 .ce_set_mask = ALTR_S10_ECC_TSERRA,
1117 .ue_set_mask = ALTR_S10_ECC_TDERRA,
1118 .set_err_ofst = ALTR_S10_ECC_INTTEST_OFST,
1119 .ecc_irq_handler = altr_edac_a10_ecc_irq,
1120 .inject_fops = &altr_edac_a10_device_inject_fops,
1121 };
1122 #endif /* CONFIG_EDAC_ALTERA_SDRAM */
1123
1124 /*********************** OCRAM EDAC Device Functions *********************/
1125
1126 #ifdef CONFIG_EDAC_ALTERA_OCRAM
1127
ocram_alloc_mem(size_t size,void ** other)1128 static void *ocram_alloc_mem(size_t size, void **other)
1129 {
1130 struct device_node *np;
1131 struct gen_pool *gp;
1132 void *sram_addr;
1133
1134 np = of_find_compatible_node(NULL, NULL, "altr,socfpga-ocram-ecc");
1135 if (!np)
1136 return NULL;
1137
1138 gp = of_gen_pool_get(np, "iram", 0);
1139 of_node_put(np);
1140 if (!gp)
1141 return NULL;
1142
1143 sram_addr = (void *)gen_pool_alloc(gp, size);
1144 if (!sram_addr)
1145 return NULL;
1146
1147 memset(sram_addr, 0, size);
1148 /* Ensure data is written out */
1149 wmb();
1150
1151 /* Remember this handle for freeing later */
1152 *other = gp;
1153
1154 return sram_addr;
1155 }
1156
ocram_free_mem(void * p,size_t size,void * other)1157 static void ocram_free_mem(void *p, size_t size, void *other)
1158 {
1159 gen_pool_free((struct gen_pool *)other, (unsigned long)p, size);
1160 }
1161
1162 static const struct edac_device_prv_data ocramecc_data = {
1163 .setup = altr_check_ecc_deps,
1164 .ce_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_SERR),
1165 .ue_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_DERR),
1166 .alloc_mem = ocram_alloc_mem,
1167 .free_mem = ocram_free_mem,
1168 .ecc_enable_mask = ALTR_OCR_ECC_EN,
1169 .ecc_en_ofst = ALTR_OCR_ECC_REG_OFFSET,
1170 .ce_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJS),
1171 .ue_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJD),
1172 .set_err_ofst = ALTR_OCR_ECC_REG_OFFSET,
1173 .trig_alloc_sz = ALTR_TRIG_OCRAM_BYTE_SIZE,
1174 .inject_fops = &altr_edac_device_inject_fops,
1175 };
1176
1177 static int __maybe_unused
altr_check_ocram_deps_init(struct altr_edac_device_dev * device)1178 altr_check_ocram_deps_init(struct altr_edac_device_dev *device)
1179 {
1180 void __iomem *base = device->base;
1181 int ret;
1182
1183 ret = altr_check_ecc_deps(device);
1184 if (ret)
1185 return ret;
1186
1187 /* Verify OCRAM has been initialized */
1188 if (!ecc_test_bits(ALTR_A10_ECC_INITCOMPLETEA,
1189 (base + ALTR_A10_ECC_INITSTAT_OFST)))
1190 return -ENODEV;
1191
1192 /* Enable IRQ on Single Bit Error */
1193 writel(ALTR_A10_ECC_SERRINTEN, (base + ALTR_A10_ECC_ERRINTENS_OFST));
1194 /* Ensure all writes complete */
1195 wmb();
1196
1197 return 0;
1198 }
1199
1200 static const struct edac_device_prv_data a10_ocramecc_data = {
1201 .setup = altr_check_ocram_deps_init,
1202 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1203 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1204 .irq_status_mask = A10_SYSMGR_ECC_INTSTAT_OCRAM,
1205 .ecc_enable_mask = ALTR_A10_OCRAM_ECC_EN_CTL,
1206 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1207 .ce_set_mask = ALTR_A10_ECC_TSERRA,
1208 .ue_set_mask = ALTR_A10_ECC_TDERRA,
1209 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1210 .ecc_irq_handler = altr_edac_a10_ecc_irq,
1211 .inject_fops = &altr_edac_a10_device_inject2_fops,
1212 /*
1213 * OCRAM panic on uncorrectable error because sleep/resume
1214 * functions and FPGA contents are stored in OCRAM. Prefer
1215 * a kernel panic over executing/loading corrupted data.
1216 */
1217 .panic = true,
1218 };
1219
1220 #endif /* CONFIG_EDAC_ALTERA_OCRAM */
1221
1222 /********************* L2 Cache EDAC Device Functions ********************/
1223
1224 #ifdef CONFIG_EDAC_ALTERA_L2C
1225
l2_alloc_mem(size_t size,void ** other)1226 static void *l2_alloc_mem(size_t size, void **other)
1227 {
1228 struct device *dev = *other;
1229 void *ptemp = devm_kzalloc(dev, size, GFP_KERNEL);
1230
1231 if (!ptemp)
1232 return NULL;
1233
1234 /* Make sure everything is written out */
1235 wmb();
1236
1237 /*
1238 * Clean all cache levels up to LoC (includes L2)
1239 * This ensures the corrupted data is written into
1240 * L2 cache for readback test (which causes ECC error).
1241 */
1242 flush_cache_all();
1243
1244 return ptemp;
1245 }
1246
l2_free_mem(void * p,size_t size,void * other)1247 static void l2_free_mem(void *p, size_t size, void *other)
1248 {
1249 struct device *dev = other;
1250
1251 if (dev && p)
1252 devm_kfree(dev, p);
1253 }
1254
1255 /*
1256 * altr_l2_check_deps()
1257 * Test for L2 cache ECC dependencies upon entry because
1258 * platform specific startup should have initialized the L2
1259 * memory and enabled the ECC.
1260 * Bail if ECC is not enabled.
1261 * Note that L2 Cache Enable is forced at build time.
1262 */
altr_l2_check_deps(struct altr_edac_device_dev * device)1263 static int altr_l2_check_deps(struct altr_edac_device_dev *device)
1264 {
1265 void __iomem *base = device->base;
1266 const struct edac_device_prv_data *prv = device->data;
1267
1268 if ((readl(base) & prv->ecc_enable_mask) ==
1269 prv->ecc_enable_mask)
1270 return 0;
1271
1272 edac_printk(KERN_ERR, EDAC_DEVICE,
1273 "L2: No ECC present, or ECC disabled\n");
1274 return -ENODEV;
1275 }
1276
altr_edac_a10_l2_irq(int irq,void * dev_id)1277 static irqreturn_t altr_edac_a10_l2_irq(int irq, void *dev_id)
1278 {
1279 struct altr_edac_device_dev *dci = dev_id;
1280
1281 if (irq == dci->sb_irq) {
1282 regmap_write(dci->edac->ecc_mgr_map,
1283 A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST,
1284 A10_SYSGMR_MPU_CLEAR_L2_ECC_SB);
1285 edac_device_handle_ce(dci->edac_dev, 0, 0, dci->edac_dev_name);
1286
1287 return IRQ_HANDLED;
1288 } else if (irq == dci->db_irq) {
1289 regmap_write(dci->edac->ecc_mgr_map,
1290 A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST,
1291 A10_SYSGMR_MPU_CLEAR_L2_ECC_MB);
1292 edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name);
1293 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
1294
1295 return IRQ_HANDLED;
1296 }
1297
1298 WARN_ON(1);
1299
1300 return IRQ_NONE;
1301 }
1302
1303 static const struct edac_device_prv_data l2ecc_data = {
1304 .setup = altr_l2_check_deps,
1305 .ce_clear_mask = 0,
1306 .ue_clear_mask = 0,
1307 .alloc_mem = l2_alloc_mem,
1308 .free_mem = l2_free_mem,
1309 .ecc_enable_mask = ALTR_L2_ECC_EN,
1310 .ce_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJS),
1311 .ue_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJD),
1312 .set_err_ofst = ALTR_L2_ECC_REG_OFFSET,
1313 .trig_alloc_sz = ALTR_TRIG_L2C_BYTE_SIZE,
1314 .inject_fops = &altr_edac_device_inject_fops,
1315 };
1316
1317 static const struct edac_device_prv_data a10_l2ecc_data = {
1318 .setup = altr_l2_check_deps,
1319 .ce_clear_mask = ALTR_A10_L2_ECC_SERR_CLR,
1320 .ue_clear_mask = ALTR_A10_L2_ECC_MERR_CLR,
1321 .irq_status_mask = A10_SYSMGR_ECC_INTSTAT_L2,
1322 .alloc_mem = l2_alloc_mem,
1323 .free_mem = l2_free_mem,
1324 .ecc_enable_mask = ALTR_A10_L2_ECC_EN_CTL,
1325 .ce_set_mask = ALTR_A10_L2_ECC_CE_INJ_MASK,
1326 .ue_set_mask = ALTR_A10_L2_ECC_UE_INJ_MASK,
1327 .set_err_ofst = ALTR_A10_L2_ECC_INJ_OFST,
1328 .ecc_irq_handler = altr_edac_a10_l2_irq,
1329 .trig_alloc_sz = ALTR_TRIG_L2C_BYTE_SIZE,
1330 .inject_fops = &altr_edac_device_inject_fops,
1331 };
1332
1333 #endif /* CONFIG_EDAC_ALTERA_L2C */
1334
1335 /********************* Ethernet Device Functions ********************/
1336
1337 #ifdef CONFIG_EDAC_ALTERA_ETHERNET
1338
socfpga_init_ethernet_ecc(struct altr_edac_device_dev * dev)1339 static int __init socfpga_init_ethernet_ecc(struct altr_edac_device_dev *dev)
1340 {
1341 int ret;
1342
1343 ret = altr_init_a10_ecc_device_type("altr,socfpga-eth-mac-ecc");
1344 if (ret)
1345 return ret;
1346
1347 return altr_check_ecc_deps(dev);
1348 }
1349
1350 static const struct edac_device_prv_data a10_enetecc_data = {
1351 .setup = socfpga_init_ethernet_ecc,
1352 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1353 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1354 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1355 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1356 .ce_set_mask = ALTR_A10_ECC_TSERRA,
1357 .ue_set_mask = ALTR_A10_ECC_TDERRA,
1358 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1359 .ecc_irq_handler = altr_edac_a10_ecc_irq,
1360 .inject_fops = &altr_edac_a10_device_inject2_fops,
1361 };
1362
1363 #endif /* CONFIG_EDAC_ALTERA_ETHERNET */
1364
1365 /********************** NAND Device Functions **********************/
1366
1367 #ifdef CONFIG_EDAC_ALTERA_NAND
1368
socfpga_init_nand_ecc(struct altr_edac_device_dev * device)1369 static int __init socfpga_init_nand_ecc(struct altr_edac_device_dev *device)
1370 {
1371 int ret;
1372
1373 ret = altr_init_a10_ecc_device_type("altr,socfpga-nand-ecc");
1374 if (ret)
1375 return ret;
1376
1377 return altr_check_ecc_deps(device);
1378 }
1379
1380 static const struct edac_device_prv_data a10_nandecc_data = {
1381 .setup = socfpga_init_nand_ecc,
1382 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1383 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1384 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1385 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1386 .ce_set_mask = ALTR_A10_ECC_TSERRA,
1387 .ue_set_mask = ALTR_A10_ECC_TDERRA,
1388 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1389 .ecc_irq_handler = altr_edac_a10_ecc_irq,
1390 .inject_fops = &altr_edac_a10_device_inject_fops,
1391 };
1392
1393 #endif /* CONFIG_EDAC_ALTERA_NAND */
1394
1395 /********************** DMA Device Functions **********************/
1396
1397 #ifdef CONFIG_EDAC_ALTERA_DMA
1398
socfpga_init_dma_ecc(struct altr_edac_device_dev * device)1399 static int __init socfpga_init_dma_ecc(struct altr_edac_device_dev *device)
1400 {
1401 int ret;
1402
1403 ret = altr_init_a10_ecc_device_type("altr,socfpga-dma-ecc");
1404 if (ret)
1405 return ret;
1406
1407 return altr_check_ecc_deps(device);
1408 }
1409
1410 static const struct edac_device_prv_data a10_dmaecc_data = {
1411 .setup = socfpga_init_dma_ecc,
1412 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1413 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1414 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1415 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1416 .ce_set_mask = ALTR_A10_ECC_TSERRA,
1417 .ue_set_mask = ALTR_A10_ECC_TDERRA,
1418 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1419 .ecc_irq_handler = altr_edac_a10_ecc_irq,
1420 .inject_fops = &altr_edac_a10_device_inject_fops,
1421 };
1422
1423 #endif /* CONFIG_EDAC_ALTERA_DMA */
1424
1425 /********************** USB Device Functions **********************/
1426
1427 #ifdef CONFIG_EDAC_ALTERA_USB
1428
socfpga_init_usb_ecc(struct altr_edac_device_dev * device)1429 static int __init socfpga_init_usb_ecc(struct altr_edac_device_dev *device)
1430 {
1431 int ret;
1432
1433 ret = altr_init_a10_ecc_device_type("altr,socfpga-usb-ecc");
1434 if (ret)
1435 return ret;
1436
1437 return altr_check_ecc_deps(device);
1438 }
1439
1440 static const struct edac_device_prv_data a10_usbecc_data = {
1441 .setup = socfpga_init_usb_ecc,
1442 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1443 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1444 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1445 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1446 .ce_set_mask = ALTR_A10_ECC_TSERRA,
1447 .ue_set_mask = ALTR_A10_ECC_TDERRA,
1448 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1449 .ecc_irq_handler = altr_edac_a10_ecc_irq,
1450 .inject_fops = &altr_edac_a10_device_inject2_fops,
1451 };
1452
1453 #endif /* CONFIG_EDAC_ALTERA_USB */
1454
1455 /********************** QSPI Device Functions **********************/
1456
1457 #ifdef CONFIG_EDAC_ALTERA_QSPI
1458
socfpga_init_qspi_ecc(struct altr_edac_device_dev * device)1459 static int __init socfpga_init_qspi_ecc(struct altr_edac_device_dev *device)
1460 {
1461 int ret;
1462
1463 ret = altr_init_a10_ecc_device_type("altr,socfpga-qspi-ecc");
1464 if (ret)
1465 return ret;
1466
1467 return altr_check_ecc_deps(device);
1468 }
1469
1470 static const struct edac_device_prv_data a10_qspiecc_data = {
1471 .setup = socfpga_init_qspi_ecc,
1472 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1473 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1474 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1475 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1476 .ce_set_mask = ALTR_A10_ECC_TSERRA,
1477 .ue_set_mask = ALTR_A10_ECC_TDERRA,
1478 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1479 .ecc_irq_handler = altr_edac_a10_ecc_irq,
1480 .inject_fops = &altr_edac_a10_device_inject_fops,
1481 };
1482
1483 #endif /* CONFIG_EDAC_ALTERA_QSPI */
1484
1485 /********************* SDMMC Device Functions **********************/
1486
1487 #ifdef CONFIG_EDAC_ALTERA_SDMMC
1488
1489 static const struct edac_device_prv_data a10_sdmmceccb_data;
altr_portb_setup(struct altr_edac_device_dev * device)1490 static int altr_portb_setup(struct altr_edac_device_dev *device)
1491 {
1492 struct edac_device_ctl_info *dci;
1493 struct altr_edac_device_dev *altdev;
1494 char *ecc_name = "sdmmcb-ecc";
1495 int edac_idx, rc;
1496 struct device_node *np;
1497 const struct edac_device_prv_data *prv = &a10_sdmmceccb_data;
1498
1499 rc = altr_check_ecc_deps(device);
1500 if (rc)
1501 return rc;
1502
1503 np = of_find_compatible_node(NULL, NULL, "altr,socfpga-sdmmc-ecc");
1504 if (!np) {
1505 edac_printk(KERN_WARNING, EDAC_DEVICE, "SDMMC node not found\n");
1506 return -ENODEV;
1507 }
1508
1509 /* Create the PortB EDAC device */
1510 edac_idx = edac_device_alloc_index();
1511 dci = edac_device_alloc_ctl_info(sizeof(*altdev), ecc_name, 1,
1512 ecc_name, 1, 0, edac_idx);
1513 if (!dci) {
1514 edac_printk(KERN_ERR, EDAC_DEVICE,
1515 "%s: Unable to allocate PortB EDAC device\n",
1516 ecc_name);
1517 return -ENOMEM;
1518 }
1519
1520 /* Initialize the PortB EDAC device structure from PortA structure */
1521 altdev = dci->pvt_info;
1522 *altdev = *device;
1523
1524 if (!devres_open_group(&altdev->ddev, altr_portb_setup, GFP_KERNEL))
1525 return -ENOMEM;
1526
1527 /* Update PortB specific values */
1528 altdev->edac_dev_name = ecc_name;
1529 altdev->edac_idx = edac_idx;
1530 altdev->edac_dev = dci;
1531 altdev->data = prv;
1532 dci->dev = &altdev->ddev;
1533 dci->ctl_name = "Altera ECC Manager";
1534 dci->mod_name = ecc_name;
1535 dci->dev_name = ecc_name;
1536
1537 /*
1538 * Update the PortB IRQs - A10 has 4, S10 has 2, Index accordingly
1539 *
1540 * FIXME: Instead of ifdefs with different architectures the driver
1541 * should properly use compatibles.
1542 */
1543 #ifdef CONFIG_64BIT
1544 altdev->sb_irq = irq_of_parse_and_map(np, 1);
1545 #else
1546 altdev->sb_irq = irq_of_parse_and_map(np, 2);
1547 #endif
1548 if (!altdev->sb_irq) {
1549 edac_printk(KERN_ERR, EDAC_DEVICE, "Error PortB SBIRQ alloc\n");
1550 rc = -ENODEV;
1551 goto err_release_group_1;
1552 }
1553 rc = devm_request_irq(&altdev->ddev, altdev->sb_irq,
1554 prv->ecc_irq_handler,
1555 IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
1556 ecc_name, altdev);
1557 if (rc) {
1558 edac_printk(KERN_ERR, EDAC_DEVICE, "PortB SBERR IRQ error\n");
1559 goto err_release_group_1;
1560 }
1561
1562 #ifdef CONFIG_64BIT
1563 /* Use IRQ to determine SError origin instead of assigning IRQ */
1564 rc = of_property_read_u32_index(np, "interrupts", 1, &altdev->db_irq);
1565 if (rc) {
1566 edac_printk(KERN_ERR, EDAC_DEVICE,
1567 "Error PortB DBIRQ alloc\n");
1568 goto err_release_group_1;
1569 }
1570 #else
1571 altdev->db_irq = irq_of_parse_and_map(np, 3);
1572 if (!altdev->db_irq) {
1573 edac_printk(KERN_ERR, EDAC_DEVICE, "Error PortB DBIRQ alloc\n");
1574 rc = -ENODEV;
1575 goto err_release_group_1;
1576 }
1577 rc = devm_request_irq(&altdev->ddev, altdev->db_irq,
1578 prv->ecc_irq_handler,
1579 IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
1580 ecc_name, altdev);
1581 if (rc) {
1582 edac_printk(KERN_ERR, EDAC_DEVICE, "PortB DBERR IRQ error\n");
1583 goto err_release_group_1;
1584 }
1585 #endif
1586
1587 rc = edac_device_add_device(dci);
1588 if (rc) {
1589 edac_printk(KERN_ERR, EDAC_DEVICE,
1590 "edac_device_add_device portB failed\n");
1591 rc = -ENOMEM;
1592 goto err_release_group_1;
1593 }
1594 altr_create_edacdev_dbgfs(dci, prv);
1595
1596 list_add(&altdev->next, &altdev->edac->a10_ecc_devices);
1597
1598 devres_remove_group(&altdev->ddev, altr_portb_setup);
1599
1600 return 0;
1601
1602 err_release_group_1:
1603 edac_device_free_ctl_info(dci);
1604 devres_release_group(&altdev->ddev, altr_portb_setup);
1605 edac_printk(KERN_ERR, EDAC_DEVICE,
1606 "%s:Error setting up EDAC device: %d\n", ecc_name, rc);
1607 return rc;
1608 }
1609
socfpga_init_sdmmc_ecc(struct altr_edac_device_dev * device)1610 static int __init socfpga_init_sdmmc_ecc(struct altr_edac_device_dev *device)
1611 {
1612 int rc = -ENODEV;
1613 struct device_node *child;
1614
1615 child = of_find_compatible_node(NULL, NULL, "altr,socfpga-sdmmc-ecc");
1616 if (!child)
1617 return -ENODEV;
1618
1619 if (!of_device_is_available(child))
1620 goto exit;
1621
1622 if (validate_parent_available(child))
1623 goto exit;
1624
1625 /* Init portB */
1626 rc = altr_init_a10_ecc_block(child, ALTR_A10_SDMMC_IRQ_MASK,
1627 a10_sdmmceccb_data.ecc_enable_mask, 1);
1628 if (rc)
1629 goto exit;
1630
1631 /* Setup portB */
1632 return altr_portb_setup(device);
1633
1634 exit:
1635 of_node_put(child);
1636 return rc;
1637 }
1638
altr_edac_a10_ecc_irq_portb(int irq,void * dev_id)1639 static irqreturn_t altr_edac_a10_ecc_irq_portb(int irq, void *dev_id)
1640 {
1641 struct altr_edac_device_dev *ad = dev_id;
1642 void __iomem *base = ad->base;
1643 const struct edac_device_prv_data *priv = ad->data;
1644
1645 if (irq == ad->sb_irq) {
1646 writel(priv->ce_clear_mask,
1647 base + ALTR_A10_ECC_INTSTAT_OFST);
1648 edac_device_handle_ce(ad->edac_dev, 0, 0, ad->edac_dev_name);
1649 return IRQ_HANDLED;
1650 } else if (irq == ad->db_irq) {
1651 writel(priv->ue_clear_mask,
1652 base + ALTR_A10_ECC_INTSTAT_OFST);
1653 edac_device_handle_ue(ad->edac_dev, 0, 0, ad->edac_dev_name);
1654 return IRQ_HANDLED;
1655 }
1656
1657 WARN_ONCE(1, "Unhandled IRQ%d on Port B.", irq);
1658
1659 return IRQ_NONE;
1660 }
1661
1662 static const struct edac_device_prv_data a10_sdmmcecca_data = {
1663 .setup = socfpga_init_sdmmc_ecc,
1664 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1665 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1666 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1667 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1668 .ce_set_mask = ALTR_A10_ECC_SERRPENA,
1669 .ue_set_mask = ALTR_A10_ECC_DERRPENA,
1670 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1671 .ecc_irq_handler = altr_edac_a10_ecc_irq,
1672 .inject_fops = &altr_edac_a10_device_inject_fops,
1673 };
1674
1675 static const struct edac_device_prv_data a10_sdmmceccb_data = {
1676 .setup = socfpga_init_sdmmc_ecc,
1677 .ce_clear_mask = ALTR_A10_ECC_SERRPENB,
1678 .ue_clear_mask = ALTR_A10_ECC_DERRPENB,
1679 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1680 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1681 .ce_set_mask = ALTR_A10_ECC_TSERRB,
1682 .ue_set_mask = ALTR_A10_ECC_TDERRB,
1683 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1684 .ecc_irq_handler = altr_edac_a10_ecc_irq_portb,
1685 .inject_fops = &altr_edac_a10_device_inject_fops,
1686 };
1687
1688 #endif /* CONFIG_EDAC_ALTERA_SDMMC */
1689
1690 /********************* Arria10 EDAC Device Functions *************************/
1691 static const struct of_device_id altr_edac_a10_device_of_match[] = {
1692 #ifdef CONFIG_EDAC_ALTERA_L2C
1693 { .compatible = "altr,socfpga-a10-l2-ecc", .data = &a10_l2ecc_data },
1694 #endif
1695 #ifdef CONFIG_EDAC_ALTERA_OCRAM
1696 { .compatible = "altr,socfpga-a10-ocram-ecc",
1697 .data = &a10_ocramecc_data },
1698 #endif
1699 #ifdef CONFIG_EDAC_ALTERA_ETHERNET
1700 { .compatible = "altr,socfpga-eth-mac-ecc",
1701 .data = &a10_enetecc_data },
1702 #endif
1703 #ifdef CONFIG_EDAC_ALTERA_NAND
1704 { .compatible = "altr,socfpga-nand-ecc", .data = &a10_nandecc_data },
1705 #endif
1706 #ifdef CONFIG_EDAC_ALTERA_DMA
1707 { .compatible = "altr,socfpga-dma-ecc", .data = &a10_dmaecc_data },
1708 #endif
1709 #ifdef CONFIG_EDAC_ALTERA_USB
1710 { .compatible = "altr,socfpga-usb-ecc", .data = &a10_usbecc_data },
1711 #endif
1712 #ifdef CONFIG_EDAC_ALTERA_QSPI
1713 { .compatible = "altr,socfpga-qspi-ecc", .data = &a10_qspiecc_data },
1714 #endif
1715 #ifdef CONFIG_EDAC_ALTERA_SDMMC
1716 { .compatible = "altr,socfpga-sdmmc-ecc", .data = &a10_sdmmcecca_data },
1717 #endif
1718 #ifdef CONFIG_EDAC_ALTERA_SDRAM
1719 { .compatible = "altr,sdram-edac-s10", .data = &s10_sdramecc_data },
1720 #endif
1721 {},
1722 };
1723 MODULE_DEVICE_TABLE(of, altr_edac_a10_device_of_match);
1724
1725 /*
1726 * The Arria10 EDAC Device Functions differ from the Cyclone5/Arria5
1727 * because 2 IRQs are shared among the all ECC peripherals. The ECC
1728 * manager manages the IRQs and the children.
1729 * Based on xgene_edac.c peripheral code.
1730 */
1731
1732 static ssize_t __maybe_unused
altr_edac_a10_device_trig(struct file * file,const char __user * user_buf,size_t count,loff_t * ppos)1733 altr_edac_a10_device_trig(struct file *file, const char __user *user_buf,
1734 size_t count, loff_t *ppos)
1735 {
1736 struct edac_device_ctl_info *edac_dci = file->private_data;
1737 struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
1738 const struct edac_device_prv_data *priv = drvdata->data;
1739 void __iomem *set_addr = (drvdata->base + priv->set_err_ofst);
1740 unsigned long flags;
1741 u8 trig_type;
1742
1743 if (!user_buf || get_user(trig_type, user_buf))
1744 return -EFAULT;
1745
1746 local_irq_save(flags);
1747 if (trig_type == ALTR_UE_TRIGGER_CHAR)
1748 writew(priv->ue_set_mask, set_addr);
1749 else
1750 writew(priv->ce_set_mask, set_addr);
1751
1752 /* Ensure the interrupt test bits are set */
1753 wmb();
1754 local_irq_restore(flags);
1755
1756 return count;
1757 }
1758
1759 /*
1760 * The Stratix10 EDAC Error Injection Functions differ from Arria10
1761 * slightly. A few Arria10 peripherals can use this injection function.
1762 * Inject the error into the memory and then readback to trigger the IRQ.
1763 */
1764 static ssize_t __maybe_unused
altr_edac_a10_device_trig2(struct file * file,const char __user * user_buf,size_t count,loff_t * ppos)1765 altr_edac_a10_device_trig2(struct file *file, const char __user *user_buf,
1766 size_t count, loff_t *ppos)
1767 {
1768 struct edac_device_ctl_info *edac_dci = file->private_data;
1769 struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
1770 const struct edac_device_prv_data *priv = drvdata->data;
1771 void __iomem *set_addr = (drvdata->base + priv->set_err_ofst);
1772 unsigned long flags;
1773 u8 trig_type;
1774
1775 if (!user_buf || get_user(trig_type, user_buf))
1776 return -EFAULT;
1777
1778 local_irq_save(flags);
1779 if (trig_type == ALTR_UE_TRIGGER_CHAR) {
1780 writew(priv->ue_set_mask, set_addr);
1781 } else {
1782 /* Setup read/write of 4 bytes */
1783 writel(ECC_WORD_WRITE, drvdata->base + ECC_BLK_DBYTECTRL_OFST);
1784 /* Setup Address to 0 */
1785 writel(0, drvdata->base + ECC_BLK_ADDRESS_OFST);
1786 /* Setup accctrl to read & ecc & data override */
1787 writel(ECC_READ_EDOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST);
1788 /* Kick it. */
1789 writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST);
1790 /* Setup write for single bit change */
1791 writel(readl(drvdata->base + ECC_BLK_RDATA0_OFST) ^ 0x1,
1792 drvdata->base + ECC_BLK_WDATA0_OFST);
1793 writel(readl(drvdata->base + ECC_BLK_RDATA1_OFST),
1794 drvdata->base + ECC_BLK_WDATA1_OFST);
1795 writel(readl(drvdata->base + ECC_BLK_RDATA2_OFST),
1796 drvdata->base + ECC_BLK_WDATA2_OFST);
1797 writel(readl(drvdata->base + ECC_BLK_RDATA3_OFST),
1798 drvdata->base + ECC_BLK_WDATA3_OFST);
1799
1800 /* Copy Read ECC to Write ECC */
1801 writel(readl(drvdata->base + ECC_BLK_RECC0_OFST),
1802 drvdata->base + ECC_BLK_WECC0_OFST);
1803 writel(readl(drvdata->base + ECC_BLK_RECC1_OFST),
1804 drvdata->base + ECC_BLK_WECC1_OFST);
1805 /* Setup accctrl to write & ecc override & data override */
1806 writel(ECC_WRITE_EDOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST);
1807 /* Kick it. */
1808 writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST);
1809 /* Setup accctrl to read & ecc overwrite & data overwrite */
1810 writel(ECC_READ_EDOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST);
1811 /* Kick it. */
1812 writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST);
1813 }
1814
1815 /* Ensure the interrupt test bits are set */
1816 wmb();
1817 local_irq_restore(flags);
1818
1819 return count;
1820 }
1821
altr_edac_a10_irq_handler(struct irq_desc * desc)1822 static void altr_edac_a10_irq_handler(struct irq_desc *desc)
1823 {
1824 int dberr, bit, sm_offset, irq_status;
1825 struct altr_arria10_edac *edac = irq_desc_get_handler_data(desc);
1826 struct irq_chip *chip = irq_desc_get_chip(desc);
1827 int irq = irq_desc_get_irq(desc);
1828 unsigned long bits;
1829
1830 dberr = (irq == edac->db_irq) ? 1 : 0;
1831 sm_offset = dberr ? A10_SYSMGR_ECC_INTSTAT_DERR_OFST :
1832 A10_SYSMGR_ECC_INTSTAT_SERR_OFST;
1833
1834 chained_irq_enter(chip, desc);
1835
1836 regmap_read(edac->ecc_mgr_map, sm_offset, &irq_status);
1837
1838 bits = irq_status;
1839 for_each_set_bit(bit, &bits, 32)
1840 generic_handle_domain_irq(edac->domain, dberr * 32 + bit);
1841
1842 chained_irq_exit(chip, desc);
1843 }
1844
validate_parent_available(struct device_node * np)1845 static int validate_parent_available(struct device_node *np)
1846 {
1847 struct device_node *parent;
1848 int ret = 0;
1849
1850 /* SDRAM must be present for Linux (implied parent) */
1851 if (of_device_is_compatible(np, "altr,sdram-edac-s10"))
1852 return 0;
1853
1854 /* Ensure parent device is enabled if parent node exists */
1855 parent = of_parse_phandle(np, "altr,ecc-parent", 0);
1856 if (parent && !of_device_is_available(parent))
1857 ret = -ENODEV;
1858
1859 of_node_put(parent);
1860 return ret;
1861 }
1862
get_s10_sdram_edac_resource(struct device_node * np,struct resource * res)1863 static int get_s10_sdram_edac_resource(struct device_node *np,
1864 struct resource *res)
1865 {
1866 struct device_node *parent;
1867 int ret;
1868
1869 parent = of_parse_phandle(np, "altr,sdr-syscon", 0);
1870 if (!parent)
1871 return -ENODEV;
1872
1873 ret = of_address_to_resource(parent, 0, res);
1874 of_node_put(parent);
1875
1876 return ret;
1877 }
1878
altr_edac_a10_device_add(struct altr_arria10_edac * edac,struct device_node * np)1879 static int altr_edac_a10_device_add(struct altr_arria10_edac *edac,
1880 struct device_node *np)
1881 {
1882 struct edac_device_ctl_info *dci;
1883 struct altr_edac_device_dev *altdev;
1884 char *ecc_name = (char *)np->name;
1885 struct resource res;
1886 int edac_idx;
1887 int rc = 0;
1888 const struct edac_device_prv_data *prv;
1889 /* Get matching node and check for valid result */
1890 const struct of_device_id *pdev_id =
1891 of_match_node(altr_edac_a10_device_of_match, np);
1892 if (IS_ERR_OR_NULL(pdev_id))
1893 return -ENODEV;
1894
1895 /* Get driver specific data for this EDAC device */
1896 prv = pdev_id->data;
1897 if (IS_ERR_OR_NULL(prv))
1898 return -ENODEV;
1899
1900 if (validate_parent_available(np))
1901 return -ENODEV;
1902
1903 if (!devres_open_group(edac->dev, altr_edac_a10_device_add, GFP_KERNEL))
1904 return -ENOMEM;
1905
1906 if (of_device_is_compatible(np, "altr,sdram-edac-s10"))
1907 rc = get_s10_sdram_edac_resource(np, &res);
1908 else
1909 rc = of_address_to_resource(np, 0, &res);
1910
1911 if (rc < 0) {
1912 edac_printk(KERN_ERR, EDAC_DEVICE,
1913 "%s: no resource address\n", ecc_name);
1914 goto err_release_group;
1915 }
1916
1917 edac_idx = edac_device_alloc_index();
1918 dci = edac_device_alloc_ctl_info(sizeof(*altdev), ecc_name,
1919 1, ecc_name, 1, 0, edac_idx);
1920
1921 if (!dci) {
1922 edac_printk(KERN_ERR, EDAC_DEVICE,
1923 "%s: Unable to allocate EDAC device\n", ecc_name);
1924 rc = -ENOMEM;
1925 goto err_release_group;
1926 }
1927
1928 altdev = dci->pvt_info;
1929 dci->dev = edac->dev;
1930 altdev->edac_dev_name = ecc_name;
1931 altdev->edac_idx = edac_idx;
1932 altdev->edac = edac;
1933 altdev->edac_dev = dci;
1934 altdev->data = prv;
1935 altdev->ddev = *edac->dev;
1936 dci->dev = &altdev->ddev;
1937 dci->ctl_name = "Altera ECC Manager";
1938 dci->mod_name = ecc_name;
1939 dci->dev_name = ecc_name;
1940
1941 altdev->base = devm_ioremap_resource(edac->dev, &res);
1942 if (IS_ERR(altdev->base)) {
1943 rc = PTR_ERR(altdev->base);
1944 goto err_release_group1;
1945 }
1946
1947 /* Check specific dependencies for the module */
1948 if (altdev->data->setup) {
1949 rc = altdev->data->setup(altdev);
1950 if (rc)
1951 goto err_release_group1;
1952 }
1953
1954 altdev->sb_irq = irq_of_parse_and_map(np, 0);
1955 if (!altdev->sb_irq) {
1956 edac_printk(KERN_ERR, EDAC_DEVICE, "Error allocating SBIRQ\n");
1957 rc = -ENODEV;
1958 goto err_release_group1;
1959 }
1960 rc = devm_request_irq(edac->dev, altdev->sb_irq, prv->ecc_irq_handler,
1961 IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
1962 ecc_name, altdev);
1963 if (rc) {
1964 edac_printk(KERN_ERR, EDAC_DEVICE, "No SBERR IRQ resource\n");
1965 goto err_release_group1;
1966 }
1967
1968 #ifdef CONFIG_64BIT
1969 /* Use IRQ to determine SError origin instead of assigning IRQ */
1970 rc = of_property_read_u32_index(np, "interrupts", 0, &altdev->db_irq);
1971 if (rc) {
1972 edac_printk(KERN_ERR, EDAC_DEVICE,
1973 "Unable to parse DB IRQ index\n");
1974 goto err_release_group1;
1975 }
1976 #else
1977 altdev->db_irq = irq_of_parse_and_map(np, 1);
1978 if (!altdev->db_irq) {
1979 edac_printk(KERN_ERR, EDAC_DEVICE, "Error allocating DBIRQ\n");
1980 rc = -ENODEV;
1981 goto err_release_group1;
1982 }
1983 rc = devm_request_irq(edac->dev, altdev->db_irq, prv->ecc_irq_handler,
1984 IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
1985 ecc_name, altdev);
1986 if (rc) {
1987 edac_printk(KERN_ERR, EDAC_DEVICE, "No DBERR IRQ resource\n");
1988 goto err_release_group1;
1989 }
1990 #endif
1991
1992 rc = edac_device_add_device(dci);
1993 if (rc) {
1994 dev_err(edac->dev, "edac_device_add_device failed\n");
1995 rc = -ENOMEM;
1996 goto err_release_group1;
1997 }
1998
1999 altr_create_edacdev_dbgfs(dci, prv);
2000
2001 list_add(&altdev->next, &edac->a10_ecc_devices);
2002
2003 devres_remove_group(edac->dev, altr_edac_a10_device_add);
2004
2005 return 0;
2006
2007 err_release_group1:
2008 edac_device_free_ctl_info(dci);
2009 err_release_group:
2010 devres_release_group(edac->dev, NULL);
2011 edac_printk(KERN_ERR, EDAC_DEVICE,
2012 "%s:Error setting up EDAC device: %d\n", ecc_name, rc);
2013
2014 return rc;
2015 }
2016
a10_eccmgr_irq_mask(struct irq_data * d)2017 static void a10_eccmgr_irq_mask(struct irq_data *d)
2018 {
2019 struct altr_arria10_edac *edac = irq_data_get_irq_chip_data(d);
2020
2021 regmap_write(edac->ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_SET_OFST,
2022 BIT(d->hwirq));
2023 }
2024
a10_eccmgr_irq_unmask(struct irq_data * d)2025 static void a10_eccmgr_irq_unmask(struct irq_data *d)
2026 {
2027 struct altr_arria10_edac *edac = irq_data_get_irq_chip_data(d);
2028
2029 regmap_write(edac->ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_CLR_OFST,
2030 BIT(d->hwirq));
2031 }
2032
a10_eccmgr_irqdomain_map(struct irq_domain * d,unsigned int irq,irq_hw_number_t hwirq)2033 static int a10_eccmgr_irqdomain_map(struct irq_domain *d, unsigned int irq,
2034 irq_hw_number_t hwirq)
2035 {
2036 struct altr_arria10_edac *edac = d->host_data;
2037
2038 irq_set_chip_and_handler(irq, &edac->irq_chip, handle_simple_irq);
2039 irq_set_chip_data(irq, edac);
2040 irq_set_noprobe(irq);
2041
2042 return 0;
2043 }
2044
2045 static const struct irq_domain_ops a10_eccmgr_ic_ops = {
2046 .map = a10_eccmgr_irqdomain_map,
2047 .xlate = irq_domain_xlate_twocell,
2048 };
2049
2050 /************** Stratix 10 EDAC Double Bit Error Handler ************/
2051 #define to_a10edac(p, m) container_of(p, struct altr_arria10_edac, m)
2052
2053 #ifdef CONFIG_64BIT
2054 /* panic routine issues reboot on non-zero panic_timeout */
2055 extern int panic_timeout;
2056
2057 /*
2058 * The double bit error is handled through SError which is fatal. This is
2059 * called as a panic notifier to printout ECC error info as part of the panic.
2060 */
s10_edac_dberr_handler(struct notifier_block * this,unsigned long event,void * ptr)2061 static int s10_edac_dberr_handler(struct notifier_block *this,
2062 unsigned long event, void *ptr)
2063 {
2064 struct altr_arria10_edac *edac = to_a10edac(this, panic_notifier);
2065 int err_addr, dberror;
2066
2067 regmap_read(edac->ecc_mgr_map, S10_SYSMGR_ECC_INTSTAT_DERR_OFST,
2068 &dberror);
2069 regmap_write(edac->ecc_mgr_map, S10_SYSMGR_UE_VAL_OFST, dberror);
2070 if (dberror & S10_DBE_IRQ_MASK) {
2071 struct list_head *position;
2072 struct altr_edac_device_dev *ed;
2073 struct arm_smccc_res result;
2074
2075 /* Find the matching DBE in the list of devices */
2076 list_for_each(position, &edac->a10_ecc_devices) {
2077 ed = list_entry(position, struct altr_edac_device_dev,
2078 next);
2079 if (!(BIT(ed->db_irq) & dberror))
2080 continue;
2081
2082 writel(ALTR_A10_ECC_DERRPENA,
2083 ed->base + ALTR_A10_ECC_INTSTAT_OFST);
2084 err_addr = readl(ed->base + ALTR_S10_DERR_ADDRA_OFST);
2085 regmap_write(edac->ecc_mgr_map,
2086 S10_SYSMGR_UE_ADDR_OFST, err_addr);
2087 edac_printk(KERN_ERR, EDAC_DEVICE,
2088 "EDAC: [Fatal DBE on %s @ 0x%08X]\n",
2089 ed->edac_dev_name, err_addr);
2090 break;
2091 }
2092 /* Notify the System through SMC. Reboot delay = 1 second */
2093 panic_timeout = 1;
2094 arm_smccc_smc(INTEL_SIP_SMC_ECC_DBE, dberror, 0, 0, 0, 0,
2095 0, 0, &result);
2096 }
2097
2098 return NOTIFY_DONE;
2099 }
2100 #endif
2101
2102 /****************** Arria 10 EDAC Probe Function *********************/
altr_edac_a10_probe(struct platform_device * pdev)2103 static int altr_edac_a10_probe(struct platform_device *pdev)
2104 {
2105 struct altr_arria10_edac *edac;
2106 struct device_node *child;
2107
2108 edac = devm_kzalloc(&pdev->dev, sizeof(*edac), GFP_KERNEL);
2109 if (!edac)
2110 return -ENOMEM;
2111
2112 edac->dev = &pdev->dev;
2113 platform_set_drvdata(pdev, edac);
2114 INIT_LIST_HEAD(&edac->a10_ecc_devices);
2115
2116 edac->ecc_mgr_map =
2117 altr_sysmgr_regmap_lookup_by_phandle(pdev->dev.of_node,
2118 "altr,sysmgr-syscon");
2119
2120 if (IS_ERR(edac->ecc_mgr_map)) {
2121 edac_printk(KERN_ERR, EDAC_DEVICE,
2122 "Unable to get syscon altr,sysmgr-syscon\n");
2123 return PTR_ERR(edac->ecc_mgr_map);
2124 }
2125
2126 /* Set irq mask for DDR SBE to avoid any pending irq before registration */
2127 regmap_write(edac->ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_SET_OFST,
2128 (A10_SYSMGR_ECC_INTMASK_SDMMCB | A10_SYSMGR_ECC_INTMASK_DDR0));
2129
2130 edac->irq_chip.name = pdev->dev.of_node->name;
2131 edac->irq_chip.irq_mask = a10_eccmgr_irq_mask;
2132 edac->irq_chip.irq_unmask = a10_eccmgr_irq_unmask;
2133 edac->domain = irq_domain_create_linear(dev_fwnode(&pdev->dev), 64, &a10_eccmgr_ic_ops,
2134 edac);
2135 if (!edac->domain) {
2136 dev_err(&pdev->dev, "Error adding IRQ domain\n");
2137 return -ENOMEM;
2138 }
2139
2140 edac->sb_irq = platform_get_irq(pdev, 0);
2141 if (edac->sb_irq < 0)
2142 return edac->sb_irq;
2143
2144 irq_set_chained_handler_and_data(edac->sb_irq,
2145 altr_edac_a10_irq_handler,
2146 edac);
2147
2148 #ifdef CONFIG_64BIT
2149 {
2150 int dberror, err_addr;
2151
2152 edac->panic_notifier.notifier_call = s10_edac_dberr_handler;
2153 atomic_notifier_chain_register(&panic_notifier_list,
2154 &edac->panic_notifier);
2155
2156 /* Printout a message if uncorrectable error previously. */
2157 regmap_read(edac->ecc_mgr_map, S10_SYSMGR_UE_VAL_OFST,
2158 &dberror);
2159 if (dberror) {
2160 regmap_read(edac->ecc_mgr_map, S10_SYSMGR_UE_ADDR_OFST,
2161 &err_addr);
2162 edac_printk(KERN_ERR, EDAC_DEVICE,
2163 "Previous Boot UE detected[0x%X] @ 0x%X\n",
2164 dberror, err_addr);
2165 /* Reset the sticky registers */
2166 regmap_write(edac->ecc_mgr_map,
2167 S10_SYSMGR_UE_VAL_OFST, 0);
2168 regmap_write(edac->ecc_mgr_map,
2169 S10_SYSMGR_UE_ADDR_OFST, 0);
2170 }
2171 }
2172 #else
2173 edac->db_irq = platform_get_irq(pdev, 1);
2174 if (edac->db_irq < 0)
2175 return edac->db_irq;
2176
2177 irq_set_chained_handler_and_data(edac->db_irq,
2178 altr_edac_a10_irq_handler, edac);
2179 #endif
2180
2181 for_each_child_of_node(pdev->dev.of_node, child) {
2182 if (!of_device_is_available(child))
2183 continue;
2184
2185 if (of_match_node(altr_edac_a10_device_of_match, child))
2186 altr_edac_a10_device_add(edac, child);
2187
2188 #ifdef CONFIG_EDAC_ALTERA_SDRAM
2189 else if (of_device_is_compatible(child, "altr,sdram-edac-a10"))
2190 of_platform_populate(pdev->dev.of_node,
2191 altr_sdram_ctrl_of_match,
2192 NULL, &pdev->dev);
2193 #endif
2194 }
2195
2196 return 0;
2197 }
2198
2199 static const struct of_device_id altr_edac_a10_of_match[] = {
2200 { .compatible = "altr,socfpga-a10-ecc-manager" },
2201 { .compatible = "altr,socfpga-s10-ecc-manager" },
2202 {},
2203 };
2204 MODULE_DEVICE_TABLE(of, altr_edac_a10_of_match);
2205
2206 static struct platform_driver altr_edac_a10_driver = {
2207 .probe = altr_edac_a10_probe,
2208 .driver = {
2209 .name = "socfpga_a10_ecc_manager",
2210 .of_match_table = altr_edac_a10_of_match,
2211 },
2212 };
2213 module_platform_driver(altr_edac_a10_driver);
2214
2215 MODULE_AUTHOR("Thor Thayer");
2216 MODULE_DESCRIPTION("EDAC Driver for Altera Memories");
2217