xref: /linux/sound/pci/rme96.c (revision 79790b6818e96c58fe2bffee1b418c16e64e7b80)
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  *   ALSA driver for RME Digi96, Digi96/8 and Digi96/8 PRO/PAD/PST audio
4  *   interfaces
5  *
6  *	Copyright (c) 2000, 2001 Anders Torger <torger@ludd.luth.se>
7  *
8  *      Thanks to Henk Hesselink <henk@anda.nl> for the analog volume control
9  *      code.
10  */
11 
12 #include <linux/delay.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
15 #include <linux/pci.h>
16 #include <linux/module.h>
17 #include <linux/vmalloc.h>
18 #include <linux/io.h>
19 
20 #include <sound/core.h>
21 #include <sound/info.h>
22 #include <sound/control.h>
23 #include <sound/pcm.h>
24 #include <sound/pcm_params.h>
25 #include <sound/asoundef.h>
26 #include <sound/initval.h>
27 
28 /* note, two last pcis should be equal, it is not a bug */
29 
30 MODULE_AUTHOR("Anders Torger <torger@ludd.luth.se>");
31 MODULE_DESCRIPTION("RME Digi96, Digi96/8, Digi96/8 PRO, Digi96/8 PST, "
32 		   "Digi96/8 PAD");
33 MODULE_LICENSE("GPL");
34 
35 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;	/* Index 0-MAX */
36 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;	/* ID for this card */
37 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;	/* Enable this card */
38 
39 module_param_array(index, int, NULL, 0444);
40 MODULE_PARM_DESC(index, "Index value for RME Digi96 soundcard.");
41 module_param_array(id, charp, NULL, 0444);
42 MODULE_PARM_DESC(id, "ID string for RME Digi96 soundcard.");
43 module_param_array(enable, bool, NULL, 0444);
44 MODULE_PARM_DESC(enable, "Enable RME Digi96 soundcard.");
45 
46 /*
47  * Defines for RME Digi96 series, from internal RME reference documents
48  * dated 12.01.00
49  */
50 
51 #define RME96_SPDIF_NCHANNELS 2
52 
53 /* Playback and capture buffer size */
54 #define RME96_BUFFER_SIZE 0x10000
55 
56 /* IO area size */
57 #define RME96_IO_SIZE 0x60000
58 
59 /* IO area offsets */
60 #define RME96_IO_PLAY_BUFFER      0x0
61 #define RME96_IO_REC_BUFFER       0x10000
62 #define RME96_IO_CONTROL_REGISTER 0x20000
63 #define RME96_IO_ADDITIONAL_REG   0x20004
64 #define RME96_IO_CONFIRM_PLAY_IRQ 0x20008
65 #define RME96_IO_CONFIRM_REC_IRQ  0x2000C
66 #define RME96_IO_SET_PLAY_POS     0x40000
67 #define RME96_IO_RESET_PLAY_POS   0x4FFFC
68 #define RME96_IO_SET_REC_POS      0x50000
69 #define RME96_IO_RESET_REC_POS    0x5FFFC
70 #define RME96_IO_GET_PLAY_POS     0x20000
71 #define RME96_IO_GET_REC_POS      0x30000
72 
73 /* Write control register bits */
74 #define RME96_WCR_START     (1 << 0)
75 #define RME96_WCR_START_2   (1 << 1)
76 #define RME96_WCR_GAIN_0    (1 << 2)
77 #define RME96_WCR_GAIN_1    (1 << 3)
78 #define RME96_WCR_MODE24    (1 << 4)
79 #define RME96_WCR_MODE24_2  (1 << 5)
80 #define RME96_WCR_BM        (1 << 6)
81 #define RME96_WCR_BM_2      (1 << 7)
82 #define RME96_WCR_ADAT      (1 << 8)
83 #define RME96_WCR_FREQ_0    (1 << 9)
84 #define RME96_WCR_FREQ_1    (1 << 10)
85 #define RME96_WCR_DS        (1 << 11)
86 #define RME96_WCR_PRO       (1 << 12)
87 #define RME96_WCR_EMP       (1 << 13)
88 #define RME96_WCR_SEL       (1 << 14)
89 #define RME96_WCR_MASTER    (1 << 15)
90 #define RME96_WCR_PD        (1 << 16)
91 #define RME96_WCR_INP_0     (1 << 17)
92 #define RME96_WCR_INP_1     (1 << 18)
93 #define RME96_WCR_THRU_0    (1 << 19)
94 #define RME96_WCR_THRU_1    (1 << 20)
95 #define RME96_WCR_THRU_2    (1 << 21)
96 #define RME96_WCR_THRU_3    (1 << 22)
97 #define RME96_WCR_THRU_4    (1 << 23)
98 #define RME96_WCR_THRU_5    (1 << 24)
99 #define RME96_WCR_THRU_6    (1 << 25)
100 #define RME96_WCR_THRU_7    (1 << 26)
101 #define RME96_WCR_DOLBY     (1 << 27)
102 #define RME96_WCR_MONITOR_0 (1 << 28)
103 #define RME96_WCR_MONITOR_1 (1 << 29)
104 #define RME96_WCR_ISEL      (1 << 30)
105 #define RME96_WCR_IDIS      (1 << 31)
106 
107 #define RME96_WCR_BITPOS_GAIN_0 2
108 #define RME96_WCR_BITPOS_GAIN_1 3
109 #define RME96_WCR_BITPOS_FREQ_0 9
110 #define RME96_WCR_BITPOS_FREQ_1 10
111 #define RME96_WCR_BITPOS_INP_0 17
112 #define RME96_WCR_BITPOS_INP_1 18
113 #define RME96_WCR_BITPOS_MONITOR_0 28
114 #define RME96_WCR_BITPOS_MONITOR_1 29
115 
116 /* Read control register bits */
117 #define RME96_RCR_AUDIO_ADDR_MASK 0xFFFF
118 #define RME96_RCR_IRQ_2     (1 << 16)
119 #define RME96_RCR_T_OUT     (1 << 17)
120 #define RME96_RCR_DEV_ID_0  (1 << 21)
121 #define RME96_RCR_DEV_ID_1  (1 << 22)
122 #define RME96_RCR_LOCK      (1 << 23)
123 #define RME96_RCR_VERF      (1 << 26)
124 #define RME96_RCR_F0        (1 << 27)
125 #define RME96_RCR_F1        (1 << 28)
126 #define RME96_RCR_F2        (1 << 29)
127 #define RME96_RCR_AUTOSYNC  (1 << 30)
128 #define RME96_RCR_IRQ       (1 << 31)
129 
130 #define RME96_RCR_BITPOS_F0 27
131 #define RME96_RCR_BITPOS_F1 28
132 #define RME96_RCR_BITPOS_F2 29
133 
134 /* Additional register bits */
135 #define RME96_AR_WSEL       (1 << 0)
136 #define RME96_AR_ANALOG     (1 << 1)
137 #define RME96_AR_FREQPAD_0  (1 << 2)
138 #define RME96_AR_FREQPAD_1  (1 << 3)
139 #define RME96_AR_FREQPAD_2  (1 << 4)
140 #define RME96_AR_PD2        (1 << 5)
141 #define RME96_AR_DAC_EN     (1 << 6)
142 #define RME96_AR_CLATCH     (1 << 7)
143 #define RME96_AR_CCLK       (1 << 8)
144 #define RME96_AR_CDATA      (1 << 9)
145 
146 #define RME96_AR_BITPOS_F0 2
147 #define RME96_AR_BITPOS_F1 3
148 #define RME96_AR_BITPOS_F2 4
149 
150 /* Monitor tracks */
151 #define RME96_MONITOR_TRACKS_1_2 0
152 #define RME96_MONITOR_TRACKS_3_4 1
153 #define RME96_MONITOR_TRACKS_5_6 2
154 #define RME96_MONITOR_TRACKS_7_8 3
155 
156 /* Attenuation */
157 #define RME96_ATTENUATION_0 0
158 #define RME96_ATTENUATION_6 1
159 #define RME96_ATTENUATION_12 2
160 #define RME96_ATTENUATION_18 3
161 
162 /* Input types */
163 #define RME96_INPUT_OPTICAL 0
164 #define RME96_INPUT_COAXIAL 1
165 #define RME96_INPUT_INTERNAL 2
166 #define RME96_INPUT_XLR 3
167 #define RME96_INPUT_ANALOG 4
168 
169 /* Clock modes */
170 #define RME96_CLOCKMODE_SLAVE 0
171 #define RME96_CLOCKMODE_MASTER 1
172 #define RME96_CLOCKMODE_WORDCLOCK 2
173 
174 /* Block sizes in bytes */
175 #define RME96_SMALL_BLOCK_SIZE 2048
176 #define RME96_LARGE_BLOCK_SIZE 8192
177 
178 /* Volume control */
179 #define RME96_AD1852_VOL_BITS 14
180 #define RME96_AD1855_VOL_BITS 10
181 
182 /* Defines for snd_rme96_trigger */
183 #define RME96_TB_START_PLAYBACK 1
184 #define RME96_TB_START_CAPTURE 2
185 #define RME96_TB_STOP_PLAYBACK 4
186 #define RME96_TB_STOP_CAPTURE 8
187 #define RME96_TB_RESET_PLAYPOS 16
188 #define RME96_TB_RESET_CAPTUREPOS 32
189 #define RME96_TB_CLEAR_PLAYBACK_IRQ 64
190 #define RME96_TB_CLEAR_CAPTURE_IRQ 128
191 #define RME96_RESUME_PLAYBACK	(RME96_TB_START_PLAYBACK)
192 #define RME96_RESUME_CAPTURE	(RME96_TB_START_CAPTURE)
193 #define RME96_RESUME_BOTH	(RME96_RESUME_PLAYBACK \
194 				| RME96_RESUME_CAPTURE)
195 #define RME96_START_PLAYBACK	(RME96_TB_START_PLAYBACK \
196 				| RME96_TB_RESET_PLAYPOS)
197 #define RME96_START_CAPTURE	(RME96_TB_START_CAPTURE \
198 				| RME96_TB_RESET_CAPTUREPOS)
199 #define RME96_START_BOTH	(RME96_START_PLAYBACK \
200 				| RME96_START_CAPTURE)
201 #define RME96_STOP_PLAYBACK	(RME96_TB_STOP_PLAYBACK \
202 				| RME96_TB_CLEAR_PLAYBACK_IRQ)
203 #define RME96_STOP_CAPTURE	(RME96_TB_STOP_CAPTURE \
204 				| RME96_TB_CLEAR_CAPTURE_IRQ)
205 #define RME96_STOP_BOTH		(RME96_STOP_PLAYBACK \
206 				| RME96_STOP_CAPTURE)
207 
208 struct rme96 {
209 	spinlock_t    lock;
210 	int irq;
211 	unsigned long port;
212 	void __iomem *iobase;
213 
214 	u32 wcreg;    /* cached write control register value */
215 	u32 wcreg_spdif;		/* S/PDIF setup */
216 	u32 wcreg_spdif_stream;		/* S/PDIF setup (temporary) */
217 	u32 rcreg;    /* cached read control register value */
218 	u32 areg;     /* cached additional register value */
219 	u16 vol[2]; /* cached volume of analog output */
220 
221 	u8 rev; /* card revision number */
222 
223 	u32 playback_pointer;
224 	u32 capture_pointer;
225 	void *playback_suspend_buffer;
226 	void *capture_suspend_buffer;
227 
228 	struct snd_pcm_substream *playback_substream;
229 	struct snd_pcm_substream *capture_substream;
230 
231 	int playback_frlog; /* log2 of framesize */
232 	int capture_frlog;
233 
234         size_t playback_periodsize; /* in bytes, zero if not used */
235 	size_t capture_periodsize; /* in bytes, zero if not used */
236 
237 	struct snd_card *card;
238 	struct snd_pcm *spdif_pcm;
239 	struct snd_pcm *adat_pcm;
240 	struct pci_dev     *pci;
241 	struct snd_kcontrol   *spdif_ctl;
242 };
243 
244 static const struct pci_device_id snd_rme96_ids[] = {
245 	{ PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96), 0, },
246 	{ PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8), 0, },
247 	{ PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8_PRO), 0, },
248 	{ PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST), 0, },
249 	{ 0, }
250 };
251 
252 MODULE_DEVICE_TABLE(pci, snd_rme96_ids);
253 
254 #define RME96_ISPLAYING(rme96) ((rme96)->wcreg & RME96_WCR_START)
255 #define RME96_ISRECORDING(rme96) ((rme96)->wcreg & RME96_WCR_START_2)
256 #define	RME96_HAS_ANALOG_IN(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST)
257 #define	RME96_HAS_ANALOG_OUT(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO || \
258 				     (rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST)
259 #define	RME96_DAC_IS_1852(rme96) (RME96_HAS_ANALOG_OUT(rme96) && (rme96)->rev >= 4)
260 #define	RME96_DAC_IS_1855(rme96) (((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && (rme96)->rev < 4) || \
261 			          ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO && (rme96)->rev == 2))
262 #define	RME96_185X_MAX_OUT(rme96) ((1 << (RME96_DAC_IS_1852(rme96) ? RME96_AD1852_VOL_BITS : RME96_AD1855_VOL_BITS)) - 1)
263 
264 static int
265 snd_rme96_playback_prepare(struct snd_pcm_substream *substream);
266 
267 static int
268 snd_rme96_capture_prepare(struct snd_pcm_substream *substream);
269 
270 static int
271 snd_rme96_playback_trigger(struct snd_pcm_substream *substream,
272 			   int cmd);
273 
274 static int
275 snd_rme96_capture_trigger(struct snd_pcm_substream *substream,
276 			  int cmd);
277 
278 static snd_pcm_uframes_t
279 snd_rme96_playback_pointer(struct snd_pcm_substream *substream);
280 
281 static snd_pcm_uframes_t
282 snd_rme96_capture_pointer(struct snd_pcm_substream *substream);
283 
284 static void snd_rme96_proc_init(struct rme96 *rme96);
285 
286 static int
287 snd_rme96_create_switches(struct snd_card *card,
288 			  struct rme96 *rme96);
289 
290 static int
291 snd_rme96_getinputtype(struct rme96 *rme96);
292 
293 static inline unsigned int
snd_rme96_playback_ptr(struct rme96 * rme96)294 snd_rme96_playback_ptr(struct rme96 *rme96)
295 {
296 	return (readl(rme96->iobase + RME96_IO_GET_PLAY_POS)
297 		& RME96_RCR_AUDIO_ADDR_MASK) >> rme96->playback_frlog;
298 }
299 
300 static inline unsigned int
snd_rme96_capture_ptr(struct rme96 * rme96)301 snd_rme96_capture_ptr(struct rme96 *rme96)
302 {
303 	return (readl(rme96->iobase + RME96_IO_GET_REC_POS)
304 		& RME96_RCR_AUDIO_ADDR_MASK) >> rme96->capture_frlog;
305 }
306 
307 static int
snd_rme96_playback_silence(struct snd_pcm_substream * substream,int channel,unsigned long pos,unsigned long count)308 snd_rme96_playback_silence(struct snd_pcm_substream *substream,
309 			   int channel, unsigned long pos, unsigned long count)
310 {
311 	struct rme96 *rme96 = snd_pcm_substream_chip(substream);
312 
313 	memset_io(rme96->iobase + RME96_IO_PLAY_BUFFER + pos,
314 		  0, count);
315 	return 0;
316 }
317 
318 static int
snd_rme96_playback_copy(struct snd_pcm_substream * substream,int channel,unsigned long pos,struct iov_iter * src,unsigned long count)319 snd_rme96_playback_copy(struct snd_pcm_substream *substream,
320 			int channel, unsigned long pos,
321 			struct iov_iter *src, unsigned long count)
322 {
323 	struct rme96 *rme96 = snd_pcm_substream_chip(substream);
324 
325 	return copy_from_iter_toio(rme96->iobase + RME96_IO_PLAY_BUFFER + pos,
326 				   src, count);
327 }
328 
329 static int
snd_rme96_capture_copy(struct snd_pcm_substream * substream,int channel,unsigned long pos,struct iov_iter * dst,unsigned long count)330 snd_rme96_capture_copy(struct snd_pcm_substream *substream,
331 		       int channel, unsigned long pos,
332 		       struct iov_iter *dst, unsigned long count)
333 {
334 	struct rme96 *rme96 = snd_pcm_substream_chip(substream);
335 
336 	return copy_to_iter_fromio(dst,
337 				   rme96->iobase + RME96_IO_REC_BUFFER + pos,
338 				   count);
339 }
340 
341 /*
342  * Digital output capabilities (S/PDIF)
343  */
344 static const struct snd_pcm_hardware snd_rme96_playback_spdif_info =
345 {
346 	.info =		     (SNDRV_PCM_INFO_MMAP_IOMEM |
347 			      SNDRV_PCM_INFO_MMAP_VALID |
348 			      SNDRV_PCM_INFO_SYNC_START |
349 			      SNDRV_PCM_INFO_RESUME |
350 			      SNDRV_PCM_INFO_INTERLEAVED |
351 			      SNDRV_PCM_INFO_PAUSE),
352 	.formats =	     (SNDRV_PCM_FMTBIT_S16_LE |
353 			      SNDRV_PCM_FMTBIT_S32_LE),
354 	.rates =	     (SNDRV_PCM_RATE_32000 |
355 			      SNDRV_PCM_RATE_44100 |
356 			      SNDRV_PCM_RATE_48000 |
357 			      SNDRV_PCM_RATE_64000 |
358 			      SNDRV_PCM_RATE_88200 |
359 			      SNDRV_PCM_RATE_96000),
360 	.rate_min =	     32000,
361 	.rate_max =	     96000,
362 	.channels_min =	     2,
363 	.channels_max =	     2,
364 	.buffer_bytes_max =  RME96_BUFFER_SIZE,
365 	.period_bytes_min =  RME96_SMALL_BLOCK_SIZE,
366 	.period_bytes_max =  RME96_LARGE_BLOCK_SIZE,
367 	.periods_min =	     RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
368 	.periods_max =	     RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
369 	.fifo_size =	     0,
370 };
371 
372 /*
373  * Digital input capabilities (S/PDIF)
374  */
375 static const struct snd_pcm_hardware snd_rme96_capture_spdif_info =
376 {
377 	.info =		     (SNDRV_PCM_INFO_MMAP_IOMEM |
378 			      SNDRV_PCM_INFO_MMAP_VALID |
379 			      SNDRV_PCM_INFO_SYNC_START |
380 			      SNDRV_PCM_INFO_RESUME |
381 			      SNDRV_PCM_INFO_INTERLEAVED |
382 			      SNDRV_PCM_INFO_PAUSE),
383 	.formats =	     (SNDRV_PCM_FMTBIT_S16_LE |
384 			      SNDRV_PCM_FMTBIT_S32_LE),
385 	.rates =	     (SNDRV_PCM_RATE_32000 |
386 			      SNDRV_PCM_RATE_44100 |
387 			      SNDRV_PCM_RATE_48000 |
388 			      SNDRV_PCM_RATE_64000 |
389 			      SNDRV_PCM_RATE_88200 |
390 			      SNDRV_PCM_RATE_96000),
391 	.rate_min =	     32000,
392 	.rate_max =	     96000,
393 	.channels_min =	     2,
394 	.channels_max =	     2,
395 	.buffer_bytes_max =  RME96_BUFFER_SIZE,
396 	.period_bytes_min =  RME96_SMALL_BLOCK_SIZE,
397 	.period_bytes_max =  RME96_LARGE_BLOCK_SIZE,
398 	.periods_min =	     RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
399 	.periods_max =	     RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
400 	.fifo_size =	     0,
401 };
402 
403 /*
404  * Digital output capabilities (ADAT)
405  */
406 static const struct snd_pcm_hardware snd_rme96_playback_adat_info =
407 {
408 	.info =		     (SNDRV_PCM_INFO_MMAP_IOMEM |
409 			      SNDRV_PCM_INFO_MMAP_VALID |
410 			      SNDRV_PCM_INFO_SYNC_START |
411 			      SNDRV_PCM_INFO_RESUME |
412 			      SNDRV_PCM_INFO_INTERLEAVED |
413 			      SNDRV_PCM_INFO_PAUSE),
414 	.formats =	     (SNDRV_PCM_FMTBIT_S16_LE |
415 			      SNDRV_PCM_FMTBIT_S32_LE),
416 	.rates =             (SNDRV_PCM_RATE_44100 |
417 			      SNDRV_PCM_RATE_48000),
418 	.rate_min =          44100,
419 	.rate_max =          48000,
420 	.channels_min =      8,
421 	.channels_max =	     8,
422 	.buffer_bytes_max =  RME96_BUFFER_SIZE,
423 	.period_bytes_min =  RME96_SMALL_BLOCK_SIZE,
424 	.period_bytes_max =  RME96_LARGE_BLOCK_SIZE,
425 	.periods_min =	     RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
426 	.periods_max =	     RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
427 	.fifo_size =	     0,
428 };
429 
430 /*
431  * Digital input capabilities (ADAT)
432  */
433 static const struct snd_pcm_hardware snd_rme96_capture_adat_info =
434 {
435 	.info =		     (SNDRV_PCM_INFO_MMAP_IOMEM |
436 			      SNDRV_PCM_INFO_MMAP_VALID |
437 			      SNDRV_PCM_INFO_SYNC_START |
438 			      SNDRV_PCM_INFO_RESUME |
439 			      SNDRV_PCM_INFO_INTERLEAVED |
440 			      SNDRV_PCM_INFO_PAUSE),
441 	.formats =	     (SNDRV_PCM_FMTBIT_S16_LE |
442 			      SNDRV_PCM_FMTBIT_S32_LE),
443 	.rates =	     (SNDRV_PCM_RATE_44100 |
444 			      SNDRV_PCM_RATE_48000),
445 	.rate_min =          44100,
446 	.rate_max =          48000,
447 	.channels_min =      8,
448 	.channels_max =	     8,
449 	.buffer_bytes_max =  RME96_BUFFER_SIZE,
450 	.period_bytes_min =  RME96_SMALL_BLOCK_SIZE,
451 	.period_bytes_max =  RME96_LARGE_BLOCK_SIZE,
452 	.periods_min =	     RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
453 	.periods_max =	     RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
454 	.fifo_size =         0,
455 };
456 
457 /*
458  * The CDATA, CCLK and CLATCH bits can be used to write to the SPI interface
459  * of the AD1852 or AD1852 D/A converter on the board.  CDATA must be set up
460  * on the falling edge of CCLK and be stable on the rising edge.  The rising
461  * edge of CLATCH after the last data bit clocks in the whole data word.
462  * A fast processor could probably drive the SPI interface faster than the
463  * DAC can handle (3MHz for the 1855, unknown for the 1852).  The udelay(1)
464  * limits the data rate to 500KHz and only causes a delay of 33 microsecs.
465  *
466  * NOTE: increased delay from 1 to 10, since there where problems setting
467  * the volume.
468  */
469 static void
snd_rme96_write_SPI(struct rme96 * rme96,u16 val)470 snd_rme96_write_SPI(struct rme96 *rme96, u16 val)
471 {
472 	int i;
473 
474 	for (i = 0; i < 16; i++) {
475 		if (val & 0x8000) {
476 			rme96->areg |= RME96_AR_CDATA;
477 		} else {
478 			rme96->areg &= ~RME96_AR_CDATA;
479 		}
480 		rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CLATCH);
481 		writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
482 		udelay(10);
483 		rme96->areg |= RME96_AR_CCLK;
484 		writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
485 		udelay(10);
486 		val <<= 1;
487 	}
488 	rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CDATA);
489 	rme96->areg |= RME96_AR_CLATCH;
490 	writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
491 	udelay(10);
492 	rme96->areg &= ~RME96_AR_CLATCH;
493 	writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
494 }
495 
496 static void
snd_rme96_apply_dac_volume(struct rme96 * rme96)497 snd_rme96_apply_dac_volume(struct rme96 *rme96)
498 {
499 	if (RME96_DAC_IS_1852(rme96)) {
500 		snd_rme96_write_SPI(rme96, (rme96->vol[0] << 2) | 0x0);
501 		snd_rme96_write_SPI(rme96, (rme96->vol[1] << 2) | 0x2);
502 	} else if (RME96_DAC_IS_1855(rme96)) {
503 		snd_rme96_write_SPI(rme96, (rme96->vol[0] & 0x3FF) | 0x000);
504 		snd_rme96_write_SPI(rme96, (rme96->vol[1] & 0x3FF) | 0x400);
505 	}
506 }
507 
508 static void
snd_rme96_reset_dac(struct rme96 * rme96)509 snd_rme96_reset_dac(struct rme96 *rme96)
510 {
511 	writel(rme96->wcreg | RME96_WCR_PD,
512 	       rme96->iobase + RME96_IO_CONTROL_REGISTER);
513 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
514 }
515 
516 static int
snd_rme96_getmontracks(struct rme96 * rme96)517 snd_rme96_getmontracks(struct rme96 *rme96)
518 {
519 	return ((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_0) & 1) +
520 		(((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_1) & 1) << 1);
521 }
522 
523 static int
snd_rme96_setmontracks(struct rme96 * rme96,int montracks)524 snd_rme96_setmontracks(struct rme96 *rme96,
525 		       int montracks)
526 {
527 	if (montracks & 1) {
528 		rme96->wcreg |= RME96_WCR_MONITOR_0;
529 	} else {
530 		rme96->wcreg &= ~RME96_WCR_MONITOR_0;
531 	}
532 	if (montracks & 2) {
533 		rme96->wcreg |= RME96_WCR_MONITOR_1;
534 	} else {
535 		rme96->wcreg &= ~RME96_WCR_MONITOR_1;
536 	}
537 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
538 	return 0;
539 }
540 
541 static int
snd_rme96_getattenuation(struct rme96 * rme96)542 snd_rme96_getattenuation(struct rme96 *rme96)
543 {
544 	return ((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_0) & 1) +
545 		(((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_1) & 1) << 1);
546 }
547 
548 static int
snd_rme96_setattenuation(struct rme96 * rme96,int attenuation)549 snd_rme96_setattenuation(struct rme96 *rme96,
550 			 int attenuation)
551 {
552 	switch (attenuation) {
553 	case 0:
554 		rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) &
555 			~RME96_WCR_GAIN_1;
556 		break;
557 	case 1:
558 		rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) &
559 			~RME96_WCR_GAIN_1;
560 		break;
561 	case 2:
562 		rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) |
563 			RME96_WCR_GAIN_1;
564 		break;
565 	case 3:
566 		rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) |
567 			RME96_WCR_GAIN_1;
568 		break;
569 	default:
570 		return -EINVAL;
571 	}
572 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
573 	return 0;
574 }
575 
576 static int
snd_rme96_capture_getrate(struct rme96 * rme96,int * is_adat)577 snd_rme96_capture_getrate(struct rme96 *rme96,
578 			  int *is_adat)
579 {
580 	int n, rate;
581 
582 	*is_adat = 0;
583 	if (rme96->areg & RME96_AR_ANALOG) {
584 		/* Analog input, overrides S/PDIF setting */
585 		n = ((rme96->areg >> RME96_AR_BITPOS_F0) & 1) +
586 			(((rme96->areg >> RME96_AR_BITPOS_F1) & 1) << 1);
587 		switch (n) {
588 		case 1:
589 			rate = 32000;
590 			break;
591 		case 2:
592 			rate = 44100;
593 			break;
594 		case 3:
595 			rate = 48000;
596 			break;
597 		default:
598 			return -1;
599 		}
600 		return (rme96->areg & RME96_AR_BITPOS_F2) ? rate << 1 : rate;
601 	}
602 
603 	rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
604 	if (rme96->rcreg & RME96_RCR_LOCK) {
605 		/* ADAT rate */
606 		*is_adat = 1;
607 		if (rme96->rcreg & RME96_RCR_T_OUT) {
608 			return 48000;
609 		}
610 		return 44100;
611 	}
612 
613 	if (rme96->rcreg & RME96_RCR_VERF) {
614 		return -1;
615 	}
616 
617 	/* S/PDIF rate */
618 	n = ((rme96->rcreg >> RME96_RCR_BITPOS_F0) & 1) +
619 		(((rme96->rcreg >> RME96_RCR_BITPOS_F1) & 1) << 1) +
620 		(((rme96->rcreg >> RME96_RCR_BITPOS_F2) & 1) << 2);
621 
622 	switch (n) {
623 	case 0:
624 		if (rme96->rcreg & RME96_RCR_T_OUT) {
625 			return 64000;
626 		}
627 		return -1;
628 	case 3: return 96000;
629 	case 4: return 88200;
630 	case 5: return 48000;
631 	case 6: return 44100;
632 	case 7: return 32000;
633 	default:
634 		break;
635 	}
636 	return -1;
637 }
638 
639 static int
snd_rme96_playback_getrate(struct rme96 * rme96)640 snd_rme96_playback_getrate(struct rme96 *rme96)
641 {
642 	int rate, dummy;
643 
644 	if (!(rme96->wcreg & RME96_WCR_MASTER) &&
645 	    snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG) {
646 		rate = snd_rme96_capture_getrate(rme96, &dummy);
647 		if (rate > 0) {
648 			/* slave clock */
649 			return rate;
650 		}
651 	}
652 
653 	rate = ((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_0) & 1) +
654 		(((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_1) & 1) << 1);
655 	switch (rate) {
656 	case 1:
657 		rate = 32000;
658 		break;
659 	case 2:
660 		rate = 44100;
661 		break;
662 	case 3:
663 		rate = 48000;
664 		break;
665 	default:
666 		return -1;
667 	}
668 	return (rme96->wcreg & RME96_WCR_DS) ? rate << 1 : rate;
669 }
670 
671 static int
snd_rme96_playback_setrate(struct rme96 * rme96,int rate)672 snd_rme96_playback_setrate(struct rme96 *rme96,
673 			   int rate)
674 {
675 	int ds;
676 
677 	ds = rme96->wcreg & RME96_WCR_DS;
678 	switch (rate) {
679 	case 32000:
680 		rme96->wcreg &= ~RME96_WCR_DS;
681 		rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &
682 			~RME96_WCR_FREQ_1;
683 		break;
684 	case 44100:
685 		rme96->wcreg &= ~RME96_WCR_DS;
686 		rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &
687 			~RME96_WCR_FREQ_0;
688 		break;
689 	case 48000:
690 		rme96->wcreg &= ~RME96_WCR_DS;
691 		rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |
692 			RME96_WCR_FREQ_1;
693 		break;
694 	case 64000:
695 		rme96->wcreg |= RME96_WCR_DS;
696 		rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &
697 			~RME96_WCR_FREQ_1;
698 		break;
699 	case 88200:
700 		rme96->wcreg |= RME96_WCR_DS;
701 		rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &
702 			~RME96_WCR_FREQ_0;
703 		break;
704 	case 96000:
705 		rme96->wcreg |= RME96_WCR_DS;
706 		rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |
707 			RME96_WCR_FREQ_1;
708 		break;
709 	default:
710 		return -EINVAL;
711 	}
712 	if ((!ds && rme96->wcreg & RME96_WCR_DS) ||
713 	    (ds && !(rme96->wcreg & RME96_WCR_DS)))
714 	{
715 		/* change to/from double-speed: reset the DAC (if available) */
716 		snd_rme96_reset_dac(rme96);
717 		return 1; /* need to restore volume */
718 	} else {
719 		writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
720 		return 0;
721 	}
722 }
723 
724 static int
snd_rme96_capture_analog_setrate(struct rme96 * rme96,int rate)725 snd_rme96_capture_analog_setrate(struct rme96 *rme96,
726 				 int rate)
727 {
728 	switch (rate) {
729 	case 32000:
730 		rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) &
731 			       ~RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
732 		break;
733 	case 44100:
734 		rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) |
735 			       RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
736 		break;
737 	case 48000:
738 		rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) |
739 			       RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
740 		break;
741 	case 64000:
742 		if (rme96->rev < 4) {
743 			return -EINVAL;
744 		}
745 		rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) &
746 			       ~RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
747 		break;
748 	case 88200:
749 		if (rme96->rev < 4) {
750 			return -EINVAL;
751 		}
752 		rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) |
753 			       RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
754 		break;
755 	case 96000:
756 		rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) |
757 			       RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
758 		break;
759 	default:
760 		return -EINVAL;
761 	}
762 	writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
763 	return 0;
764 }
765 
766 static int
snd_rme96_setclockmode(struct rme96 * rme96,int mode)767 snd_rme96_setclockmode(struct rme96 *rme96,
768 		       int mode)
769 {
770 	switch (mode) {
771 	case RME96_CLOCKMODE_SLAVE:
772 	        /* AutoSync */
773 		rme96->wcreg &= ~RME96_WCR_MASTER;
774 		rme96->areg &= ~RME96_AR_WSEL;
775 		break;
776 	case RME96_CLOCKMODE_MASTER:
777 	        /* Internal */
778 		rme96->wcreg |= RME96_WCR_MASTER;
779 		rme96->areg &= ~RME96_AR_WSEL;
780 		break;
781 	case RME96_CLOCKMODE_WORDCLOCK:
782 		/* Word clock is a master mode */
783 		rme96->wcreg |= RME96_WCR_MASTER;
784 		rme96->areg |= RME96_AR_WSEL;
785 		break;
786 	default:
787 		return -EINVAL;
788 	}
789 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
790 	writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
791 	return 0;
792 }
793 
794 static int
snd_rme96_getclockmode(struct rme96 * rme96)795 snd_rme96_getclockmode(struct rme96 *rme96)
796 {
797 	if (rme96->areg & RME96_AR_WSEL) {
798 		return RME96_CLOCKMODE_WORDCLOCK;
799 	}
800 	return (rme96->wcreg & RME96_WCR_MASTER) ? RME96_CLOCKMODE_MASTER :
801 		RME96_CLOCKMODE_SLAVE;
802 }
803 
804 static int
snd_rme96_setinputtype(struct rme96 * rme96,int type)805 snd_rme96_setinputtype(struct rme96 *rme96,
806 		       int type)
807 {
808 	int n;
809 
810 	switch (type) {
811 	case RME96_INPUT_OPTICAL:
812 		rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) &
813 			~RME96_WCR_INP_1;
814 		break;
815 	case RME96_INPUT_COAXIAL:
816 		rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) &
817 			~RME96_WCR_INP_1;
818 		break;
819 	case RME96_INPUT_INTERNAL:
820 		rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) |
821 			RME96_WCR_INP_1;
822 		break;
823 	case RME96_INPUT_XLR:
824 		if ((rme96->pci->device != PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST &&
825 		     rme96->pci->device != PCI_DEVICE_ID_RME_DIGI96_8_PRO) ||
826 		    (rme96->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST &&
827 		     rme96->rev > 4))
828 		{
829 			/* Only Digi96/8 PRO and Digi96/8 PAD supports XLR */
830 			return -EINVAL;
831 		}
832 		rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) |
833 			RME96_WCR_INP_1;
834 		break;
835 	case RME96_INPUT_ANALOG:
836 		if (!RME96_HAS_ANALOG_IN(rme96)) {
837 			return -EINVAL;
838 		}
839 		rme96->areg |= RME96_AR_ANALOG;
840 		writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
841 		if (rme96->rev < 4) {
842 			/*
843 			 * Revision less than 004 does not support 64 and
844 			 * 88.2 kHz
845 			 */
846 			if (snd_rme96_capture_getrate(rme96, &n) == 88200) {
847 				snd_rme96_capture_analog_setrate(rme96, 44100);
848 			}
849 			if (snd_rme96_capture_getrate(rme96, &n) == 64000) {
850 				snd_rme96_capture_analog_setrate(rme96, 32000);
851 			}
852 		}
853 		return 0;
854 	default:
855 		return -EINVAL;
856 	}
857 	if (type != RME96_INPUT_ANALOG && RME96_HAS_ANALOG_IN(rme96)) {
858 		rme96->areg &= ~RME96_AR_ANALOG;
859 		writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
860 	}
861 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
862 	return 0;
863 }
864 
865 static int
snd_rme96_getinputtype(struct rme96 * rme96)866 snd_rme96_getinputtype(struct rme96 *rme96)
867 {
868 	if (rme96->areg & RME96_AR_ANALOG) {
869 		return RME96_INPUT_ANALOG;
870 	}
871 	return ((rme96->wcreg >> RME96_WCR_BITPOS_INP_0) & 1) +
872 		(((rme96->wcreg >> RME96_WCR_BITPOS_INP_1) & 1) << 1);
873 }
874 
875 static void
snd_rme96_setframelog(struct rme96 * rme96,int n_channels,int is_playback)876 snd_rme96_setframelog(struct rme96 *rme96,
877 		      int n_channels,
878 		      int is_playback)
879 {
880 	int frlog;
881 
882 	if (n_channels == 2) {
883 		frlog = 1;
884 	} else {
885 		/* assume 8 channels */
886 		frlog = 3;
887 	}
888 	if (is_playback) {
889 		frlog += (rme96->wcreg & RME96_WCR_MODE24) ? 2 : 1;
890 		rme96->playback_frlog = frlog;
891 	} else {
892 		frlog += (rme96->wcreg & RME96_WCR_MODE24_2) ? 2 : 1;
893 		rme96->capture_frlog = frlog;
894 	}
895 }
896 
897 static int
snd_rme96_playback_setformat(struct rme96 * rme96,snd_pcm_format_t format)898 snd_rme96_playback_setformat(struct rme96 *rme96, snd_pcm_format_t format)
899 {
900 	switch (format) {
901 	case SNDRV_PCM_FORMAT_S16_LE:
902 		rme96->wcreg &= ~RME96_WCR_MODE24;
903 		break;
904 	case SNDRV_PCM_FORMAT_S32_LE:
905 		rme96->wcreg |= RME96_WCR_MODE24;
906 		break;
907 	default:
908 		return -EINVAL;
909 	}
910 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
911 	return 0;
912 }
913 
914 static int
snd_rme96_capture_setformat(struct rme96 * rme96,snd_pcm_format_t format)915 snd_rme96_capture_setformat(struct rme96 *rme96, snd_pcm_format_t format)
916 {
917 	switch (format) {
918 	case SNDRV_PCM_FORMAT_S16_LE:
919 		rme96->wcreg &= ~RME96_WCR_MODE24_2;
920 		break;
921 	case SNDRV_PCM_FORMAT_S32_LE:
922 		rme96->wcreg |= RME96_WCR_MODE24_2;
923 		break;
924 	default:
925 		return -EINVAL;
926 	}
927 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
928 	return 0;
929 }
930 
931 static void
snd_rme96_set_period_properties(struct rme96 * rme96,size_t period_bytes)932 snd_rme96_set_period_properties(struct rme96 *rme96,
933 				size_t period_bytes)
934 {
935 	switch (period_bytes) {
936 	case RME96_LARGE_BLOCK_SIZE:
937 		rme96->wcreg &= ~RME96_WCR_ISEL;
938 		break;
939 	case RME96_SMALL_BLOCK_SIZE:
940 		rme96->wcreg |= RME96_WCR_ISEL;
941 		break;
942 	default:
943 		snd_BUG();
944 		break;
945 	}
946 	rme96->wcreg &= ~RME96_WCR_IDIS;
947 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
948 }
949 
950 static int
snd_rme96_playback_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params)951 snd_rme96_playback_hw_params(struct snd_pcm_substream *substream,
952 			     struct snd_pcm_hw_params *params)
953 {
954 	struct rme96 *rme96 = snd_pcm_substream_chip(substream);
955 	struct snd_pcm_runtime *runtime = substream->runtime;
956 	int err, rate, dummy;
957 	bool apply_dac_volume = false;
958 
959 	runtime->dma_area = (void __force *)(rme96->iobase +
960 					     RME96_IO_PLAY_BUFFER);
961 	runtime->dma_addr = rme96->port + RME96_IO_PLAY_BUFFER;
962 	runtime->dma_bytes = RME96_BUFFER_SIZE;
963 
964 	spin_lock_irq(&rme96->lock);
965 	rate = 0;
966 	if (!(rme96->wcreg & RME96_WCR_MASTER) &&
967 	    snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG)
968 		rate = snd_rme96_capture_getrate(rme96, &dummy);
969 	if (rate > 0) {
970                 /* slave clock */
971                 if ((int)params_rate(params) != rate) {
972 			err = -EIO;
973 			goto error;
974 		}
975 	} else {
976 		err = snd_rme96_playback_setrate(rme96, params_rate(params));
977 		if (err < 0)
978 			goto error;
979 		apply_dac_volume = err > 0; /* need to restore volume later? */
980 	}
981 
982 	err = snd_rme96_playback_setformat(rme96, params_format(params));
983 	if (err < 0)
984 		goto error;
985 	snd_rme96_setframelog(rme96, params_channels(params), 1);
986 	if (rme96->capture_periodsize != 0) {
987 		if (params_period_size(params) << rme96->playback_frlog !=
988 		    rme96->capture_periodsize)
989 		{
990 			err = -EBUSY;
991 			goto error;
992 		}
993 	}
994 	rme96->playback_periodsize =
995 		params_period_size(params) << rme96->playback_frlog;
996 	snd_rme96_set_period_properties(rme96, rme96->playback_periodsize);
997 	/* S/PDIF setup */
998 	if ((rme96->wcreg & RME96_WCR_ADAT) == 0) {
999 		rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);
1000 		writel(rme96->wcreg |= rme96->wcreg_spdif_stream, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1001 	}
1002 
1003 	err = 0;
1004  error:
1005 	spin_unlock_irq(&rme96->lock);
1006 	if (apply_dac_volume) {
1007 		usleep_range(3000, 10000);
1008 		snd_rme96_apply_dac_volume(rme96);
1009 	}
1010 
1011 	return err;
1012 }
1013 
1014 static int
snd_rme96_capture_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params)1015 snd_rme96_capture_hw_params(struct snd_pcm_substream *substream,
1016 			    struct snd_pcm_hw_params *params)
1017 {
1018 	struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1019 	struct snd_pcm_runtime *runtime = substream->runtime;
1020 	int err, isadat, rate;
1021 
1022 	runtime->dma_area = (void __force *)(rme96->iobase +
1023 					     RME96_IO_REC_BUFFER);
1024 	runtime->dma_addr = rme96->port + RME96_IO_REC_BUFFER;
1025 	runtime->dma_bytes = RME96_BUFFER_SIZE;
1026 
1027 	spin_lock_irq(&rme96->lock);
1028 	err = snd_rme96_capture_setformat(rme96, params_format(params));
1029 	if (err < 0) {
1030 		spin_unlock_irq(&rme96->lock);
1031 		return err;
1032 	}
1033 	if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1034 		err = snd_rme96_capture_analog_setrate(rme96, params_rate(params));
1035 		if (err < 0) {
1036 			spin_unlock_irq(&rme96->lock);
1037 			return err;
1038 		}
1039 	} else {
1040 		rate = snd_rme96_capture_getrate(rme96, &isadat);
1041 		if (rate > 0) {
1042 			if ((int)params_rate(params) != rate) {
1043 				spin_unlock_irq(&rme96->lock);
1044 				return -EIO;
1045 			}
1046 			if ((isadat && runtime->hw.channels_min == 2) ||
1047 			    (!isadat && runtime->hw.channels_min == 8)) {
1048 				spin_unlock_irq(&rme96->lock);
1049 				return -EIO;
1050 			}
1051 		}
1052         }
1053 	snd_rme96_setframelog(rme96, params_channels(params), 0);
1054 	if (rme96->playback_periodsize != 0) {
1055 		if (params_period_size(params) << rme96->capture_frlog !=
1056 		    rme96->playback_periodsize)
1057 		{
1058 			spin_unlock_irq(&rme96->lock);
1059 			return -EBUSY;
1060 		}
1061 	}
1062 	rme96->capture_periodsize =
1063 		params_period_size(params) << rme96->capture_frlog;
1064 	snd_rme96_set_period_properties(rme96, rme96->capture_periodsize);
1065 	spin_unlock_irq(&rme96->lock);
1066 
1067 	return 0;
1068 }
1069 
1070 static void
snd_rme96_trigger(struct rme96 * rme96,int op)1071 snd_rme96_trigger(struct rme96 *rme96,
1072 		  int op)
1073 {
1074 	if (op & RME96_TB_RESET_PLAYPOS)
1075 		writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1076 	if (op & RME96_TB_RESET_CAPTUREPOS)
1077 		writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1078 	if (op & RME96_TB_CLEAR_PLAYBACK_IRQ) {
1079 		rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1080 		if (rme96->rcreg & RME96_RCR_IRQ)
1081 			writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ);
1082 	}
1083 	if (op & RME96_TB_CLEAR_CAPTURE_IRQ) {
1084 		rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1085 		if (rme96->rcreg & RME96_RCR_IRQ_2)
1086 			writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ);
1087 	}
1088 	if (op & RME96_TB_START_PLAYBACK)
1089 		rme96->wcreg |= RME96_WCR_START;
1090 	if (op & RME96_TB_STOP_PLAYBACK)
1091 		rme96->wcreg &= ~RME96_WCR_START;
1092 	if (op & RME96_TB_START_CAPTURE)
1093 		rme96->wcreg |= RME96_WCR_START_2;
1094 	if (op & RME96_TB_STOP_CAPTURE)
1095 		rme96->wcreg &= ~RME96_WCR_START_2;
1096 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1097 }
1098 
1099 
1100 
1101 static irqreturn_t
snd_rme96_interrupt(int irq,void * dev_id)1102 snd_rme96_interrupt(int irq,
1103 		    void *dev_id)
1104 {
1105 	struct rme96 *rme96 = (struct rme96 *)dev_id;
1106 
1107 	rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1108 	/* fastpath out, to ease interrupt sharing */
1109 	if (!((rme96->rcreg & RME96_RCR_IRQ) ||
1110 	      (rme96->rcreg & RME96_RCR_IRQ_2)))
1111 	{
1112 		return IRQ_NONE;
1113 	}
1114 
1115 	if (rme96->rcreg & RME96_RCR_IRQ) {
1116 		/* playback */
1117                 snd_pcm_period_elapsed(rme96->playback_substream);
1118 		writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ);
1119 	}
1120 	if (rme96->rcreg & RME96_RCR_IRQ_2) {
1121 		/* capture */
1122 		snd_pcm_period_elapsed(rme96->capture_substream);
1123 		writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ);
1124 	}
1125 	return IRQ_HANDLED;
1126 }
1127 
1128 static const unsigned int period_bytes[] = { RME96_SMALL_BLOCK_SIZE, RME96_LARGE_BLOCK_SIZE };
1129 
1130 static const struct snd_pcm_hw_constraint_list hw_constraints_period_bytes = {
1131 	.count = ARRAY_SIZE(period_bytes),
1132 	.list = period_bytes,
1133 	.mask = 0
1134 };
1135 
1136 static void
rme96_set_buffer_size_constraint(struct rme96 * rme96,struct snd_pcm_runtime * runtime)1137 rme96_set_buffer_size_constraint(struct rme96 *rme96,
1138 				 struct snd_pcm_runtime *runtime)
1139 {
1140 	unsigned int size;
1141 
1142 	snd_pcm_hw_constraint_single(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1143 				     RME96_BUFFER_SIZE);
1144 	size = rme96->playback_periodsize;
1145 	if (!size)
1146 		size = rme96->capture_periodsize;
1147 	if (size)
1148 		snd_pcm_hw_constraint_single(runtime,
1149 					     SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1150 					     size);
1151 	else
1152 		snd_pcm_hw_constraint_list(runtime, 0,
1153 					   SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1154 					   &hw_constraints_period_bytes);
1155 }
1156 
1157 static int
snd_rme96_playback_spdif_open(struct snd_pcm_substream * substream)1158 snd_rme96_playback_spdif_open(struct snd_pcm_substream *substream)
1159 {
1160         int rate, dummy;
1161 	struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1162 	struct snd_pcm_runtime *runtime = substream->runtime;
1163 
1164 	snd_pcm_set_sync(substream);
1165 	spin_lock_irq(&rme96->lock);
1166 	if (rme96->playback_substream) {
1167 		spin_unlock_irq(&rme96->lock);
1168                 return -EBUSY;
1169         }
1170 	rme96->wcreg &= ~RME96_WCR_ADAT;
1171 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1172 	rme96->playback_substream = substream;
1173 	spin_unlock_irq(&rme96->lock);
1174 
1175 	runtime->hw = snd_rme96_playback_spdif_info;
1176 	if (!(rme96->wcreg & RME96_WCR_MASTER) &&
1177 	    snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG) {
1178 		rate = snd_rme96_capture_getrate(rme96, &dummy);
1179 		if (rate > 0) {
1180 			/* slave clock */
1181 			runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1182 			runtime->hw.rate_min = rate;
1183 			runtime->hw.rate_max = rate;
1184 		}
1185 	}
1186 	rme96_set_buffer_size_constraint(rme96, runtime);
1187 
1188 	rme96->wcreg_spdif_stream = rme96->wcreg_spdif;
1189 	rme96->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1190 	snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE |
1191 		       SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id);
1192 	return 0;
1193 }
1194 
1195 static int
snd_rme96_capture_spdif_open(struct snd_pcm_substream * substream)1196 snd_rme96_capture_spdif_open(struct snd_pcm_substream *substream)
1197 {
1198         int isadat, rate;
1199 	struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1200 	struct snd_pcm_runtime *runtime = substream->runtime;
1201 
1202 	snd_pcm_set_sync(substream);
1203 	runtime->hw = snd_rme96_capture_spdif_info;
1204 	if (snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG) {
1205 		rate = snd_rme96_capture_getrate(rme96, &isadat);
1206 		if (rate > 0) {
1207 			if (isadat)
1208 				return -EIO;
1209 			runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1210 			runtime->hw.rate_min = rate;
1211 			runtime->hw.rate_max = rate;
1212 		}
1213 	}
1214 
1215 	spin_lock_irq(&rme96->lock);
1216 	if (rme96->capture_substream) {
1217 		spin_unlock_irq(&rme96->lock);
1218                 return -EBUSY;
1219         }
1220 	rme96->capture_substream = substream;
1221 	spin_unlock_irq(&rme96->lock);
1222 
1223 	rme96_set_buffer_size_constraint(rme96, runtime);
1224 	return 0;
1225 }
1226 
1227 static int
snd_rme96_playback_adat_open(struct snd_pcm_substream * substream)1228 snd_rme96_playback_adat_open(struct snd_pcm_substream *substream)
1229 {
1230         int rate, dummy;
1231 	struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1232 	struct snd_pcm_runtime *runtime = substream->runtime;
1233 
1234 	snd_pcm_set_sync(substream);
1235 	spin_lock_irq(&rme96->lock);
1236 	if (rme96->playback_substream) {
1237 		spin_unlock_irq(&rme96->lock);
1238                 return -EBUSY;
1239         }
1240 	rme96->wcreg |= RME96_WCR_ADAT;
1241 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1242 	rme96->playback_substream = substream;
1243 	spin_unlock_irq(&rme96->lock);
1244 
1245 	runtime->hw = snd_rme96_playback_adat_info;
1246 	if (!(rme96->wcreg & RME96_WCR_MASTER) &&
1247 	    snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG) {
1248 		rate = snd_rme96_capture_getrate(rme96, &dummy);
1249 		if (rate > 0) {
1250 			/* slave clock */
1251 			runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1252 			runtime->hw.rate_min = rate;
1253 			runtime->hw.rate_max = rate;
1254 		}
1255 	}
1256 
1257 	rme96_set_buffer_size_constraint(rme96, runtime);
1258 	return 0;
1259 }
1260 
1261 static int
snd_rme96_capture_adat_open(struct snd_pcm_substream * substream)1262 snd_rme96_capture_adat_open(struct snd_pcm_substream *substream)
1263 {
1264         int isadat, rate;
1265 	struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1266 	struct snd_pcm_runtime *runtime = substream->runtime;
1267 
1268 	snd_pcm_set_sync(substream);
1269 	runtime->hw = snd_rme96_capture_adat_info;
1270         if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1271                 /* makes no sense to use analog input. Note that analog
1272                    expension cards AEB4/8-I are RME96_INPUT_INTERNAL */
1273                 return -EIO;
1274         }
1275 	rate = snd_rme96_capture_getrate(rme96, &isadat);
1276 	if (rate > 0) {
1277                 if (!isadat) {
1278                         return -EIO;
1279                 }
1280                 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1281                 runtime->hw.rate_min = rate;
1282                 runtime->hw.rate_max = rate;
1283         }
1284 
1285 	spin_lock_irq(&rme96->lock);
1286 	if (rme96->capture_substream) {
1287 		spin_unlock_irq(&rme96->lock);
1288                 return -EBUSY;
1289         }
1290 	rme96->capture_substream = substream;
1291 	spin_unlock_irq(&rme96->lock);
1292 
1293 	rme96_set_buffer_size_constraint(rme96, runtime);
1294 	return 0;
1295 }
1296 
1297 static int
snd_rme96_playback_close(struct snd_pcm_substream * substream)1298 snd_rme96_playback_close(struct snd_pcm_substream *substream)
1299 {
1300 	struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1301 	int spdif = 0;
1302 
1303 	spin_lock_irq(&rme96->lock);
1304 	if (RME96_ISPLAYING(rme96)) {
1305 		snd_rme96_trigger(rme96, RME96_STOP_PLAYBACK);
1306 	}
1307 	rme96->playback_substream = NULL;
1308 	rme96->playback_periodsize = 0;
1309 	spdif = (rme96->wcreg & RME96_WCR_ADAT) == 0;
1310 	spin_unlock_irq(&rme96->lock);
1311 	if (spdif) {
1312 		rme96->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1313 		snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE |
1314 			       SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id);
1315 	}
1316 	return 0;
1317 }
1318 
1319 static int
snd_rme96_capture_close(struct snd_pcm_substream * substream)1320 snd_rme96_capture_close(struct snd_pcm_substream *substream)
1321 {
1322 	struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1323 
1324 	spin_lock_irq(&rme96->lock);
1325 	if (RME96_ISRECORDING(rme96)) {
1326 		snd_rme96_trigger(rme96, RME96_STOP_CAPTURE);
1327 	}
1328 	rme96->capture_substream = NULL;
1329 	rme96->capture_periodsize = 0;
1330 	spin_unlock_irq(&rme96->lock);
1331 	return 0;
1332 }
1333 
1334 static int
snd_rme96_playback_prepare(struct snd_pcm_substream * substream)1335 snd_rme96_playback_prepare(struct snd_pcm_substream *substream)
1336 {
1337 	struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1338 
1339 	spin_lock_irq(&rme96->lock);
1340 	if (RME96_ISPLAYING(rme96)) {
1341 		snd_rme96_trigger(rme96, RME96_STOP_PLAYBACK);
1342 	}
1343 	writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1344 	spin_unlock_irq(&rme96->lock);
1345 	return 0;
1346 }
1347 
1348 static int
snd_rme96_capture_prepare(struct snd_pcm_substream * substream)1349 snd_rme96_capture_prepare(struct snd_pcm_substream *substream)
1350 {
1351 	struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1352 
1353 	spin_lock_irq(&rme96->lock);
1354 	if (RME96_ISRECORDING(rme96)) {
1355 		snd_rme96_trigger(rme96, RME96_STOP_CAPTURE);
1356 	}
1357 	writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1358 	spin_unlock_irq(&rme96->lock);
1359 	return 0;
1360 }
1361 
1362 static int
snd_rme96_playback_trigger(struct snd_pcm_substream * substream,int cmd)1363 snd_rme96_playback_trigger(struct snd_pcm_substream *substream,
1364 			   int cmd)
1365 {
1366 	struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1367 	struct snd_pcm_substream *s;
1368 	bool sync;
1369 
1370 	snd_pcm_group_for_each_entry(s, substream) {
1371 		if (snd_pcm_substream_chip(s) == rme96)
1372 			snd_pcm_trigger_done(s, substream);
1373 	}
1374 
1375 	sync = (rme96->playback_substream && rme96->capture_substream) &&
1376 	       (rme96->playback_substream->group ==
1377 		rme96->capture_substream->group);
1378 
1379 	switch (cmd) {
1380 	case SNDRV_PCM_TRIGGER_START:
1381 		if (!RME96_ISPLAYING(rme96)) {
1382 			if (substream != rme96->playback_substream)
1383 				return -EBUSY;
1384 			snd_rme96_trigger(rme96, sync ? RME96_START_BOTH
1385 						 : RME96_START_PLAYBACK);
1386 		}
1387 		break;
1388 
1389 	case SNDRV_PCM_TRIGGER_SUSPEND:
1390 	case SNDRV_PCM_TRIGGER_STOP:
1391 		if (RME96_ISPLAYING(rme96)) {
1392 			if (substream != rme96->playback_substream)
1393 				return -EBUSY;
1394 			snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH
1395 						 :  RME96_STOP_PLAYBACK);
1396 		}
1397 		break;
1398 
1399 	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1400 		if (RME96_ISPLAYING(rme96))
1401 			snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH
1402 						 : RME96_STOP_PLAYBACK);
1403 		break;
1404 
1405 	case SNDRV_PCM_TRIGGER_RESUME:
1406 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1407 		if (!RME96_ISPLAYING(rme96))
1408 			snd_rme96_trigger(rme96, sync ? RME96_RESUME_BOTH
1409 						 : RME96_RESUME_PLAYBACK);
1410 		break;
1411 
1412 	default:
1413 		return -EINVAL;
1414 	}
1415 
1416 	return 0;
1417 }
1418 
1419 static int
snd_rme96_capture_trigger(struct snd_pcm_substream * substream,int cmd)1420 snd_rme96_capture_trigger(struct snd_pcm_substream *substream,
1421 			  int cmd)
1422 {
1423 	struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1424 	struct snd_pcm_substream *s;
1425 	bool sync;
1426 
1427 	snd_pcm_group_for_each_entry(s, substream) {
1428 		if (snd_pcm_substream_chip(s) == rme96)
1429 			snd_pcm_trigger_done(s, substream);
1430 	}
1431 
1432 	sync = (rme96->playback_substream && rme96->capture_substream) &&
1433 	       (rme96->playback_substream->group ==
1434 		rme96->capture_substream->group);
1435 
1436 	switch (cmd) {
1437 	case SNDRV_PCM_TRIGGER_START:
1438 		if (!RME96_ISRECORDING(rme96)) {
1439 			if (substream != rme96->capture_substream)
1440 				return -EBUSY;
1441 			snd_rme96_trigger(rme96, sync ? RME96_START_BOTH
1442 						 : RME96_START_CAPTURE);
1443 		}
1444 		break;
1445 
1446 	case SNDRV_PCM_TRIGGER_SUSPEND:
1447 	case SNDRV_PCM_TRIGGER_STOP:
1448 		if (RME96_ISRECORDING(rme96)) {
1449 			if (substream != rme96->capture_substream)
1450 				return -EBUSY;
1451 			snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH
1452 						 : RME96_STOP_CAPTURE);
1453 		}
1454 		break;
1455 
1456 	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1457 		if (RME96_ISRECORDING(rme96))
1458 			snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH
1459 						 : RME96_STOP_CAPTURE);
1460 		break;
1461 
1462 	case SNDRV_PCM_TRIGGER_RESUME:
1463 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1464 		if (!RME96_ISRECORDING(rme96))
1465 			snd_rme96_trigger(rme96, sync ? RME96_RESUME_BOTH
1466 						 : RME96_RESUME_CAPTURE);
1467 		break;
1468 
1469 	default:
1470 		return -EINVAL;
1471 	}
1472 
1473 	return 0;
1474 }
1475 
1476 static snd_pcm_uframes_t
snd_rme96_playback_pointer(struct snd_pcm_substream * substream)1477 snd_rme96_playback_pointer(struct snd_pcm_substream *substream)
1478 {
1479 	struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1480 	return snd_rme96_playback_ptr(rme96);
1481 }
1482 
1483 static snd_pcm_uframes_t
snd_rme96_capture_pointer(struct snd_pcm_substream * substream)1484 snd_rme96_capture_pointer(struct snd_pcm_substream *substream)
1485 {
1486 	struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1487 	return snd_rme96_capture_ptr(rme96);
1488 }
1489 
1490 static const struct snd_pcm_ops snd_rme96_playback_spdif_ops = {
1491 	.open =		snd_rme96_playback_spdif_open,
1492 	.close =	snd_rme96_playback_close,
1493 	.hw_params =	snd_rme96_playback_hw_params,
1494 	.prepare =	snd_rme96_playback_prepare,
1495 	.trigger =	snd_rme96_playback_trigger,
1496 	.pointer =	snd_rme96_playback_pointer,
1497 	.copy =		snd_rme96_playback_copy,
1498 	.fill_silence =	snd_rme96_playback_silence,
1499 	.mmap =		snd_pcm_lib_mmap_iomem,
1500 };
1501 
1502 static const struct snd_pcm_ops snd_rme96_capture_spdif_ops = {
1503 	.open =		snd_rme96_capture_spdif_open,
1504 	.close =	snd_rme96_capture_close,
1505 	.hw_params =	snd_rme96_capture_hw_params,
1506 	.prepare =	snd_rme96_capture_prepare,
1507 	.trigger =	snd_rme96_capture_trigger,
1508 	.pointer =	snd_rme96_capture_pointer,
1509 	.copy =		snd_rme96_capture_copy,
1510 	.mmap =		snd_pcm_lib_mmap_iomem,
1511 };
1512 
1513 static const struct snd_pcm_ops snd_rme96_playback_adat_ops = {
1514 	.open =		snd_rme96_playback_adat_open,
1515 	.close =	snd_rme96_playback_close,
1516 	.hw_params =	snd_rme96_playback_hw_params,
1517 	.prepare =	snd_rme96_playback_prepare,
1518 	.trigger =	snd_rme96_playback_trigger,
1519 	.pointer =	snd_rme96_playback_pointer,
1520 	.copy =		snd_rme96_playback_copy,
1521 	.fill_silence =	snd_rme96_playback_silence,
1522 	.mmap =		snd_pcm_lib_mmap_iomem,
1523 };
1524 
1525 static const struct snd_pcm_ops snd_rme96_capture_adat_ops = {
1526 	.open =		snd_rme96_capture_adat_open,
1527 	.close =	snd_rme96_capture_close,
1528 	.hw_params =	snd_rme96_capture_hw_params,
1529 	.prepare =	snd_rme96_capture_prepare,
1530 	.trigger =	snd_rme96_capture_trigger,
1531 	.pointer =	snd_rme96_capture_pointer,
1532 	.copy =		snd_rme96_capture_copy,
1533 	.mmap =		snd_pcm_lib_mmap_iomem,
1534 };
1535 
1536 static void
snd_rme96_free(struct rme96 * rme96)1537 snd_rme96_free(struct rme96 *rme96)
1538 {
1539 	if (rme96->irq >= 0) {
1540 		snd_rme96_trigger(rme96, RME96_STOP_BOTH);
1541 		rme96->areg &= ~RME96_AR_DAC_EN;
1542 		writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1543 	}
1544 	vfree(rme96->playback_suspend_buffer);
1545 	vfree(rme96->capture_suspend_buffer);
1546 }
1547 
1548 static void
snd_rme96_free_spdif_pcm(struct snd_pcm * pcm)1549 snd_rme96_free_spdif_pcm(struct snd_pcm *pcm)
1550 {
1551 	struct rme96 *rme96 = pcm->private_data;
1552 	rme96->spdif_pcm = NULL;
1553 }
1554 
1555 static void
snd_rme96_free_adat_pcm(struct snd_pcm * pcm)1556 snd_rme96_free_adat_pcm(struct snd_pcm *pcm)
1557 {
1558 	struct rme96 *rme96 = pcm->private_data;
1559 	rme96->adat_pcm = NULL;
1560 }
1561 
1562 static int
snd_rme96_create(struct rme96 * rme96)1563 snd_rme96_create(struct rme96 *rme96)
1564 {
1565 	struct pci_dev *pci = rme96->pci;
1566 	int err;
1567 
1568 	rme96->irq = -1;
1569 	spin_lock_init(&rme96->lock);
1570 
1571 	err = pcim_enable_device(pci);
1572 	if (err < 0)
1573 		return err;
1574 
1575 	err = pci_request_regions(pci, "RME96");
1576 	if (err < 0)
1577 		return err;
1578 	rme96->port = pci_resource_start(rme96->pci, 0);
1579 
1580 	rme96->iobase = devm_ioremap(&pci->dev, rme96->port, RME96_IO_SIZE);
1581 	if (!rme96->iobase) {
1582 		dev_err(rme96->card->dev,
1583 			"unable to remap memory region 0x%lx-0x%lx\n",
1584 			rme96->port, rme96->port + RME96_IO_SIZE - 1);
1585 		return -EBUSY;
1586 	}
1587 
1588 	if (devm_request_irq(&pci->dev, pci->irq, snd_rme96_interrupt,
1589 			     IRQF_SHARED, KBUILD_MODNAME, rme96)) {
1590 		dev_err(rme96->card->dev, "unable to grab IRQ %d\n", pci->irq);
1591 		return -EBUSY;
1592 	}
1593 	rme96->irq = pci->irq;
1594 	rme96->card->sync_irq = rme96->irq;
1595 
1596 	/* read the card's revision number */
1597 	pci_read_config_byte(pci, 8, &rme96->rev);
1598 
1599 	/* set up ALSA pcm device for S/PDIF */
1600 	err = snd_pcm_new(rme96->card, "Digi96 IEC958", 0,
1601 			  1, 1, &rme96->spdif_pcm);
1602 	if (err < 0)
1603 		return err;
1604 
1605 	rme96->spdif_pcm->private_data = rme96;
1606 	rme96->spdif_pcm->private_free = snd_rme96_free_spdif_pcm;
1607 	strcpy(rme96->spdif_pcm->name, "Digi96 IEC958");
1608 	snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_spdif_ops);
1609 	snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_spdif_ops);
1610 
1611 	rme96->spdif_pcm->info_flags = 0;
1612 
1613 	/* set up ALSA pcm device for ADAT */
1614 	if (pci->device == PCI_DEVICE_ID_RME_DIGI96) {
1615 		/* ADAT is not available on the base model */
1616 		rme96->adat_pcm = NULL;
1617 	} else {
1618 		err = snd_pcm_new(rme96->card, "Digi96 ADAT", 1,
1619 				  1, 1, &rme96->adat_pcm);
1620 		if (err < 0)
1621 			return err;
1622 		rme96->adat_pcm->private_data = rme96;
1623 		rme96->adat_pcm->private_free = snd_rme96_free_adat_pcm;
1624 		strcpy(rme96->adat_pcm->name, "Digi96 ADAT");
1625 		snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_adat_ops);
1626 		snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_adat_ops);
1627 
1628 		rme96->adat_pcm->info_flags = 0;
1629 	}
1630 
1631 	rme96->playback_periodsize = 0;
1632 	rme96->capture_periodsize = 0;
1633 
1634 	/* make sure playback/capture is stopped, if by some reason active */
1635 	snd_rme96_trigger(rme96, RME96_STOP_BOTH);
1636 
1637 	/* set default values in registers */
1638 	rme96->wcreg =
1639 		RME96_WCR_FREQ_1 | /* set 44.1 kHz playback */
1640 		RME96_WCR_SEL |    /* normal playback */
1641 		RME96_WCR_MASTER | /* set to master clock mode */
1642 		RME96_WCR_INP_0;   /* set coaxial input */
1643 
1644 	rme96->areg = RME96_AR_FREQPAD_1; /* set 44.1 kHz analog capture */
1645 
1646 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1647 	writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1648 
1649 	/* reset the ADC */
1650 	writel(rme96->areg | RME96_AR_PD2,
1651 	       rme96->iobase + RME96_IO_ADDITIONAL_REG);
1652 	writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1653 
1654 	/* reset and enable the DAC (order is important). */
1655 	snd_rme96_reset_dac(rme96);
1656 	rme96->areg |= RME96_AR_DAC_EN;
1657 	writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1658 
1659 	/* reset playback and record buffer pointers */
1660 	writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1661 	writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1662 
1663 	/* reset volume */
1664 	rme96->vol[0] = rme96->vol[1] = 0;
1665 	if (RME96_HAS_ANALOG_OUT(rme96)) {
1666 		snd_rme96_apply_dac_volume(rme96);
1667 	}
1668 
1669 	/* init switch interface */
1670 	err = snd_rme96_create_switches(rme96->card, rme96);
1671 	if (err < 0)
1672 		return err;
1673 
1674         /* init proc interface */
1675 	snd_rme96_proc_init(rme96);
1676 
1677 	return 0;
1678 }
1679 
1680 /*
1681  * proc interface
1682  */
1683 
1684 static void
snd_rme96_proc_read(struct snd_info_entry * entry,struct snd_info_buffer * buffer)1685 snd_rme96_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
1686 {
1687 	int n;
1688 	struct rme96 *rme96 = entry->private_data;
1689 
1690 	rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1691 
1692 	snd_iprintf(buffer, rme96->card->longname);
1693 	snd_iprintf(buffer, " (index #%d)\n", rme96->card->number + 1);
1694 
1695 	snd_iprintf(buffer, "\nGeneral settings\n");
1696 	if (rme96->wcreg & RME96_WCR_IDIS) {
1697 		snd_iprintf(buffer, "  period size: N/A (interrupts "
1698 			    "disabled)\n");
1699 	} else if (rme96->wcreg & RME96_WCR_ISEL) {
1700 		snd_iprintf(buffer, "  period size: 2048 bytes\n");
1701 	} else {
1702 		snd_iprintf(buffer, "  period size: 8192 bytes\n");
1703 	}
1704 	snd_iprintf(buffer, "\nInput settings\n");
1705 	switch (snd_rme96_getinputtype(rme96)) {
1706 	case RME96_INPUT_OPTICAL:
1707 		snd_iprintf(buffer, "  input: optical");
1708 		break;
1709 	case RME96_INPUT_COAXIAL:
1710 		snd_iprintf(buffer, "  input: coaxial");
1711 		break;
1712 	case RME96_INPUT_INTERNAL:
1713 		snd_iprintf(buffer, "  input: internal");
1714 		break;
1715 	case RME96_INPUT_XLR:
1716 		snd_iprintf(buffer, "  input: XLR");
1717 		break;
1718 	case RME96_INPUT_ANALOG:
1719 		snd_iprintf(buffer, "  input: analog");
1720 		break;
1721 	}
1722 	if (snd_rme96_capture_getrate(rme96, &n) < 0) {
1723 		snd_iprintf(buffer, "\n  sample rate: no valid signal\n");
1724 	} else {
1725 		if (n) {
1726 			snd_iprintf(buffer, " (8 channels)\n");
1727 		} else {
1728 			snd_iprintf(buffer, " (2 channels)\n");
1729 		}
1730 		snd_iprintf(buffer, "  sample rate: %d Hz\n",
1731 			    snd_rme96_capture_getrate(rme96, &n));
1732 	}
1733 	if (rme96->wcreg & RME96_WCR_MODE24_2) {
1734 		snd_iprintf(buffer, "  sample format: 24 bit\n");
1735 	} else {
1736 		snd_iprintf(buffer, "  sample format: 16 bit\n");
1737 	}
1738 
1739 	snd_iprintf(buffer, "\nOutput settings\n");
1740 	if (rme96->wcreg & RME96_WCR_SEL) {
1741 		snd_iprintf(buffer, "  output signal: normal playback\n");
1742 	} else {
1743 		snd_iprintf(buffer, "  output signal: same as input\n");
1744 	}
1745 	snd_iprintf(buffer, "  sample rate: %d Hz\n",
1746 		    snd_rme96_playback_getrate(rme96));
1747 	if (rme96->wcreg & RME96_WCR_MODE24) {
1748 		snd_iprintf(buffer, "  sample format: 24 bit\n");
1749 	} else {
1750 		snd_iprintf(buffer, "  sample format: 16 bit\n");
1751 	}
1752 	if (rme96->areg & RME96_AR_WSEL) {
1753 		snd_iprintf(buffer, "  sample clock source: word clock\n");
1754 	} else if (rme96->wcreg & RME96_WCR_MASTER) {
1755 		snd_iprintf(buffer, "  sample clock source: internal\n");
1756 	} else if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1757 		snd_iprintf(buffer, "  sample clock source: autosync (internal anyway due to analog input setting)\n");
1758 	} else if (snd_rme96_capture_getrate(rme96, &n) < 0) {
1759 		snd_iprintf(buffer, "  sample clock source: autosync (internal anyway due to no valid signal)\n");
1760 	} else {
1761 		snd_iprintf(buffer, "  sample clock source: autosync\n");
1762 	}
1763 	if (rme96->wcreg & RME96_WCR_PRO) {
1764 		snd_iprintf(buffer, "  format: AES/EBU (professional)\n");
1765 	} else {
1766 		snd_iprintf(buffer, "  format: IEC958 (consumer)\n");
1767 	}
1768 	if (rme96->wcreg & RME96_WCR_EMP) {
1769 		snd_iprintf(buffer, "  emphasis: on\n");
1770 	} else {
1771 		snd_iprintf(buffer, "  emphasis: off\n");
1772 	}
1773 	if (rme96->wcreg & RME96_WCR_DOLBY) {
1774 		snd_iprintf(buffer, "  non-audio (dolby): on\n");
1775 	} else {
1776 		snd_iprintf(buffer, "  non-audio (dolby): off\n");
1777 	}
1778 	if (RME96_HAS_ANALOG_IN(rme96)) {
1779 		snd_iprintf(buffer, "\nAnalog output settings\n");
1780 		switch (snd_rme96_getmontracks(rme96)) {
1781 		case RME96_MONITOR_TRACKS_1_2:
1782 			snd_iprintf(buffer, "  monitored ADAT tracks: 1+2\n");
1783 			break;
1784 		case RME96_MONITOR_TRACKS_3_4:
1785 			snd_iprintf(buffer, "  monitored ADAT tracks: 3+4\n");
1786 			break;
1787 		case RME96_MONITOR_TRACKS_5_6:
1788 			snd_iprintf(buffer, "  monitored ADAT tracks: 5+6\n");
1789 			break;
1790 		case RME96_MONITOR_TRACKS_7_8:
1791 			snd_iprintf(buffer, "  monitored ADAT tracks: 7+8\n");
1792 			break;
1793 		}
1794 		switch (snd_rme96_getattenuation(rme96)) {
1795 		case RME96_ATTENUATION_0:
1796 			snd_iprintf(buffer, "  attenuation: 0 dB\n");
1797 			break;
1798 		case RME96_ATTENUATION_6:
1799 			snd_iprintf(buffer, "  attenuation: -6 dB\n");
1800 			break;
1801 		case RME96_ATTENUATION_12:
1802 			snd_iprintf(buffer, "  attenuation: -12 dB\n");
1803 			break;
1804 		case RME96_ATTENUATION_18:
1805 			snd_iprintf(buffer, "  attenuation: -18 dB\n");
1806 			break;
1807 		}
1808 		snd_iprintf(buffer, "  volume left: %u\n", rme96->vol[0]);
1809 		snd_iprintf(buffer, "  volume right: %u\n", rme96->vol[1]);
1810 	}
1811 }
1812 
snd_rme96_proc_init(struct rme96 * rme96)1813 static void snd_rme96_proc_init(struct rme96 *rme96)
1814 {
1815 	snd_card_ro_proc_new(rme96->card, "rme96", rme96, snd_rme96_proc_read);
1816 }
1817 
1818 /*
1819  * control interface
1820  */
1821 
1822 #define snd_rme96_info_loopback_control		snd_ctl_boolean_mono_info
1823 
1824 static int
snd_rme96_get_loopback_control(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1825 snd_rme96_get_loopback_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1826 {
1827 	struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1828 
1829 	spin_lock_irq(&rme96->lock);
1830 	ucontrol->value.integer.value[0] = rme96->wcreg & RME96_WCR_SEL ? 0 : 1;
1831 	spin_unlock_irq(&rme96->lock);
1832 	return 0;
1833 }
1834 static int
snd_rme96_put_loopback_control(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1835 snd_rme96_put_loopback_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1836 {
1837 	struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1838 	unsigned int val;
1839 	int change;
1840 
1841 	val = ucontrol->value.integer.value[0] ? 0 : RME96_WCR_SEL;
1842 	spin_lock_irq(&rme96->lock);
1843 	val = (rme96->wcreg & ~RME96_WCR_SEL) | val;
1844 	change = val != rme96->wcreg;
1845 	rme96->wcreg = val;
1846 	writel(val, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1847 	spin_unlock_irq(&rme96->lock);
1848 	return change;
1849 }
1850 
1851 static int
snd_rme96_info_inputtype_control(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)1852 snd_rme96_info_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1853 {
1854 	static const char * const _texts[5] = {
1855 		"Optical", "Coaxial", "Internal", "XLR", "Analog"
1856 	};
1857 	struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1858 	const char *texts[5] = {
1859 		_texts[0], _texts[1], _texts[2], _texts[3], _texts[4]
1860 	};
1861 	int num_items;
1862 
1863 	switch (rme96->pci->device) {
1864 	case PCI_DEVICE_ID_RME_DIGI96:
1865 	case PCI_DEVICE_ID_RME_DIGI96_8:
1866 		num_items = 3;
1867 		break;
1868 	case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
1869 		num_items = 4;
1870 		break;
1871 	case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
1872 		if (rme96->rev > 4) {
1873 			/* PST */
1874 			num_items = 4;
1875 			texts[3] = _texts[4]; /* Analog instead of XLR */
1876 		} else {
1877 			/* PAD */
1878 			num_items = 5;
1879 		}
1880 		break;
1881 	default:
1882 		snd_BUG();
1883 		return -EINVAL;
1884 	}
1885 	return snd_ctl_enum_info(uinfo, 1, num_items, texts);
1886 }
1887 static int
snd_rme96_get_inputtype_control(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1888 snd_rme96_get_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1889 {
1890 	struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1891 	unsigned int items = 3;
1892 
1893 	spin_lock_irq(&rme96->lock);
1894 	ucontrol->value.enumerated.item[0] = snd_rme96_getinputtype(rme96);
1895 
1896 	switch (rme96->pci->device) {
1897 	case PCI_DEVICE_ID_RME_DIGI96:
1898 	case PCI_DEVICE_ID_RME_DIGI96_8:
1899 		items = 3;
1900 		break;
1901 	case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
1902 		items = 4;
1903 		break;
1904 	case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
1905 		if (rme96->rev > 4) {
1906 			/* for handling PST case, (INPUT_ANALOG is moved to INPUT_XLR */
1907 			if (ucontrol->value.enumerated.item[0] == RME96_INPUT_ANALOG) {
1908 				ucontrol->value.enumerated.item[0] = RME96_INPUT_XLR;
1909 			}
1910 			items = 4;
1911 		} else {
1912 			items = 5;
1913 		}
1914 		break;
1915 	default:
1916 		snd_BUG();
1917 		break;
1918 	}
1919 	if (ucontrol->value.enumerated.item[0] >= items) {
1920 		ucontrol->value.enumerated.item[0] = items - 1;
1921 	}
1922 
1923 	spin_unlock_irq(&rme96->lock);
1924 	return 0;
1925 }
1926 static int
snd_rme96_put_inputtype_control(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1927 snd_rme96_put_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1928 {
1929 	struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1930 	unsigned int val;
1931 	int change, items = 3;
1932 
1933 	switch (rme96->pci->device) {
1934 	case PCI_DEVICE_ID_RME_DIGI96:
1935 	case PCI_DEVICE_ID_RME_DIGI96_8:
1936 		items = 3;
1937 		break;
1938 	case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
1939 		items = 4;
1940 		break;
1941 	case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
1942 		if (rme96->rev > 4) {
1943 			items = 4;
1944 		} else {
1945 			items = 5;
1946 		}
1947 		break;
1948 	default:
1949 		snd_BUG();
1950 		break;
1951 	}
1952 	val = ucontrol->value.enumerated.item[0] % items;
1953 
1954 	/* special case for PST */
1955 	if (rme96->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && rme96->rev > 4) {
1956 		if (val == RME96_INPUT_XLR) {
1957 			val = RME96_INPUT_ANALOG;
1958 		}
1959 	}
1960 
1961 	spin_lock_irq(&rme96->lock);
1962 	change = (int)val != snd_rme96_getinputtype(rme96);
1963 	snd_rme96_setinputtype(rme96, val);
1964 	spin_unlock_irq(&rme96->lock);
1965 	return change;
1966 }
1967 
1968 static int
snd_rme96_info_clockmode_control(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)1969 snd_rme96_info_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1970 {
1971 	static const char * const texts[3] = { "AutoSync", "Internal", "Word" };
1972 
1973 	return snd_ctl_enum_info(uinfo, 1, 3, texts);
1974 }
1975 static int
snd_rme96_get_clockmode_control(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1976 snd_rme96_get_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1977 {
1978 	struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1979 
1980 	spin_lock_irq(&rme96->lock);
1981 	ucontrol->value.enumerated.item[0] = snd_rme96_getclockmode(rme96);
1982 	spin_unlock_irq(&rme96->lock);
1983 	return 0;
1984 }
1985 static int
snd_rme96_put_clockmode_control(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1986 snd_rme96_put_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1987 {
1988 	struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1989 	unsigned int val;
1990 	int change;
1991 
1992 	val = ucontrol->value.enumerated.item[0] % 3;
1993 	spin_lock_irq(&rme96->lock);
1994 	change = (int)val != snd_rme96_getclockmode(rme96);
1995 	snd_rme96_setclockmode(rme96, val);
1996 	spin_unlock_irq(&rme96->lock);
1997 	return change;
1998 }
1999 
2000 static int
snd_rme96_info_attenuation_control(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)2001 snd_rme96_info_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2002 {
2003 	static const char * const texts[4] = {
2004 		"0 dB", "-6 dB", "-12 dB", "-18 dB"
2005 	};
2006 
2007 	return snd_ctl_enum_info(uinfo, 1, 4, texts);
2008 }
2009 static int
snd_rme96_get_attenuation_control(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2010 snd_rme96_get_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2011 {
2012 	struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2013 
2014 	spin_lock_irq(&rme96->lock);
2015 	ucontrol->value.enumerated.item[0] = snd_rme96_getattenuation(rme96);
2016 	spin_unlock_irq(&rme96->lock);
2017 	return 0;
2018 }
2019 static int
snd_rme96_put_attenuation_control(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2020 snd_rme96_put_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2021 {
2022 	struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2023 	unsigned int val;
2024 	int change;
2025 
2026 	val = ucontrol->value.enumerated.item[0] % 4;
2027 	spin_lock_irq(&rme96->lock);
2028 
2029 	change = (int)val != snd_rme96_getattenuation(rme96);
2030 	snd_rme96_setattenuation(rme96, val);
2031 	spin_unlock_irq(&rme96->lock);
2032 	return change;
2033 }
2034 
2035 static int
snd_rme96_info_montracks_control(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)2036 snd_rme96_info_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2037 {
2038 	static const char * const texts[4] = { "1+2", "3+4", "5+6", "7+8" };
2039 
2040 	return snd_ctl_enum_info(uinfo, 1, 4, texts);
2041 }
2042 static int
snd_rme96_get_montracks_control(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2043 snd_rme96_get_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2044 {
2045 	struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2046 
2047 	spin_lock_irq(&rme96->lock);
2048 	ucontrol->value.enumerated.item[0] = snd_rme96_getmontracks(rme96);
2049 	spin_unlock_irq(&rme96->lock);
2050 	return 0;
2051 }
2052 static int
snd_rme96_put_montracks_control(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2053 snd_rme96_put_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2054 {
2055 	struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2056 	unsigned int val;
2057 	int change;
2058 
2059 	val = ucontrol->value.enumerated.item[0] % 4;
2060 	spin_lock_irq(&rme96->lock);
2061 	change = (int)val != snd_rme96_getmontracks(rme96);
2062 	snd_rme96_setmontracks(rme96, val);
2063 	spin_unlock_irq(&rme96->lock);
2064 	return change;
2065 }
2066 
snd_rme96_convert_from_aes(struct snd_aes_iec958 * aes)2067 static u32 snd_rme96_convert_from_aes(struct snd_aes_iec958 *aes)
2068 {
2069 	u32 val = 0;
2070 	val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME96_WCR_PRO : 0;
2071 	val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? RME96_WCR_DOLBY : 0;
2072 	if (val & RME96_WCR_PRO)
2073 		val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME96_WCR_EMP : 0;
2074 	else
2075 		val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME96_WCR_EMP : 0;
2076 	return val;
2077 }
2078 
snd_rme96_convert_to_aes(struct snd_aes_iec958 * aes,u32 val)2079 static void snd_rme96_convert_to_aes(struct snd_aes_iec958 *aes, u32 val)
2080 {
2081 	aes->status[0] = ((val & RME96_WCR_PRO) ? IEC958_AES0_PROFESSIONAL : 0) |
2082 			 ((val & RME96_WCR_DOLBY) ? IEC958_AES0_NONAUDIO : 0);
2083 	if (val & RME96_WCR_PRO)
2084 		aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
2085 	else
2086 		aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
2087 }
2088 
snd_rme96_control_spdif_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)2089 static int snd_rme96_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2090 {
2091 	uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2092 	uinfo->count = 1;
2093 	return 0;
2094 }
2095 
snd_rme96_control_spdif_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2096 static int snd_rme96_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2097 {
2098 	struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2099 
2100 	snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif);
2101 	return 0;
2102 }
2103 
snd_rme96_control_spdif_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2104 static int snd_rme96_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2105 {
2106 	struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2107 	int change;
2108 	u32 val;
2109 
2110 	val = snd_rme96_convert_from_aes(&ucontrol->value.iec958);
2111 	spin_lock_irq(&rme96->lock);
2112 	change = val != rme96->wcreg_spdif;
2113 	rme96->wcreg_spdif = val;
2114 	spin_unlock_irq(&rme96->lock);
2115 	return change;
2116 }
2117 
snd_rme96_control_spdif_stream_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)2118 static int snd_rme96_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2119 {
2120 	uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2121 	uinfo->count = 1;
2122 	return 0;
2123 }
2124 
snd_rme96_control_spdif_stream_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2125 static int snd_rme96_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2126 {
2127 	struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2128 
2129 	snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif_stream);
2130 	return 0;
2131 }
2132 
snd_rme96_control_spdif_stream_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2133 static int snd_rme96_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2134 {
2135 	struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2136 	int change;
2137 	u32 val;
2138 
2139 	val = snd_rme96_convert_from_aes(&ucontrol->value.iec958);
2140 	spin_lock_irq(&rme96->lock);
2141 	change = val != rme96->wcreg_spdif_stream;
2142 	rme96->wcreg_spdif_stream = val;
2143 	rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);
2144 	rme96->wcreg |= val;
2145 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
2146 	spin_unlock_irq(&rme96->lock);
2147 	return change;
2148 }
2149 
snd_rme96_control_spdif_mask_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)2150 static int snd_rme96_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2151 {
2152 	uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2153 	uinfo->count = 1;
2154 	return 0;
2155 }
2156 
snd_rme96_control_spdif_mask_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2157 static int snd_rme96_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2158 {
2159 	ucontrol->value.iec958.status[0] = kcontrol->private_value;
2160 	return 0;
2161 }
2162 
2163 static int
snd_rme96_dac_volume_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)2164 snd_rme96_dac_volume_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2165 {
2166 	struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2167 
2168         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2169         uinfo->count = 2;
2170         uinfo->value.integer.min = 0;
2171 	uinfo->value.integer.max = RME96_185X_MAX_OUT(rme96);
2172         return 0;
2173 }
2174 
2175 static int
snd_rme96_dac_volume_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * u)2176 snd_rme96_dac_volume_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *u)
2177 {
2178 	struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2179 
2180 	spin_lock_irq(&rme96->lock);
2181         u->value.integer.value[0] = rme96->vol[0];
2182         u->value.integer.value[1] = rme96->vol[1];
2183 	spin_unlock_irq(&rme96->lock);
2184 
2185         return 0;
2186 }
2187 
2188 static int
snd_rme96_dac_volume_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * u)2189 snd_rme96_dac_volume_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *u)
2190 {
2191 	struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2192         int change = 0;
2193 	unsigned int vol, maxvol;
2194 
2195 
2196 	if (!RME96_HAS_ANALOG_OUT(rme96))
2197 		return -EINVAL;
2198 	maxvol = RME96_185X_MAX_OUT(rme96);
2199 	spin_lock_irq(&rme96->lock);
2200 	vol = u->value.integer.value[0];
2201 	if (vol != rme96->vol[0] && vol <= maxvol) {
2202 		rme96->vol[0] = vol;
2203 		change = 1;
2204 	}
2205 	vol = u->value.integer.value[1];
2206 	if (vol != rme96->vol[1] && vol <= maxvol) {
2207 		rme96->vol[1] = vol;
2208 		change = 1;
2209 	}
2210 	if (change)
2211 		snd_rme96_apply_dac_volume(rme96);
2212 	spin_unlock_irq(&rme96->lock);
2213 
2214         return change;
2215 }
2216 
2217 static const struct snd_kcontrol_new snd_rme96_controls[] = {
2218 {
2219 	.iface =	SNDRV_CTL_ELEM_IFACE_PCM,
2220 	.name =		SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2221 	.info =		snd_rme96_control_spdif_info,
2222 	.get =		snd_rme96_control_spdif_get,
2223 	.put =		snd_rme96_control_spdif_put
2224 },
2225 {
2226 	.access =	SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
2227 	.iface =	SNDRV_CTL_ELEM_IFACE_PCM,
2228 	.name =		SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2229 	.info =		snd_rme96_control_spdif_stream_info,
2230 	.get =		snd_rme96_control_spdif_stream_get,
2231 	.put =		snd_rme96_control_spdif_stream_put
2232 },
2233 {
2234 	.access =	SNDRV_CTL_ELEM_ACCESS_READ,
2235 	.iface =	SNDRV_CTL_ELEM_IFACE_PCM,
2236 	.name =		SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
2237 	.info =		snd_rme96_control_spdif_mask_info,
2238 	.get =		snd_rme96_control_spdif_mask_get,
2239 	.private_value = IEC958_AES0_NONAUDIO |
2240 			IEC958_AES0_PROFESSIONAL |
2241 			IEC958_AES0_CON_EMPHASIS
2242 },
2243 {
2244 	.access =	SNDRV_CTL_ELEM_ACCESS_READ,
2245 	.iface =	SNDRV_CTL_ELEM_IFACE_PCM,
2246 	.name =		SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
2247 	.info =		snd_rme96_control_spdif_mask_info,
2248 	.get =		snd_rme96_control_spdif_mask_get,
2249 	.private_value = IEC958_AES0_NONAUDIO |
2250 			IEC958_AES0_PROFESSIONAL |
2251 			IEC958_AES0_PRO_EMPHASIS
2252 },
2253 {
2254         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
2255 	.name =         "Input Connector",
2256 	.info =         snd_rme96_info_inputtype_control,
2257 	.get =          snd_rme96_get_inputtype_control,
2258 	.put =          snd_rme96_put_inputtype_control
2259 },
2260 {
2261         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
2262 	.name =         "Loopback Input",
2263 	.info =         snd_rme96_info_loopback_control,
2264 	.get =          snd_rme96_get_loopback_control,
2265 	.put =          snd_rme96_put_loopback_control
2266 },
2267 {
2268         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
2269 	.name =         "Sample Clock Source",
2270 	.info =         snd_rme96_info_clockmode_control,
2271 	.get =          snd_rme96_get_clockmode_control,
2272 	.put =          snd_rme96_put_clockmode_control
2273 },
2274 {
2275         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
2276 	.name =         "Monitor Tracks",
2277 	.info =         snd_rme96_info_montracks_control,
2278 	.get =          snd_rme96_get_montracks_control,
2279 	.put =          snd_rme96_put_montracks_control
2280 },
2281 {
2282         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
2283 	.name =         "Attenuation",
2284 	.info =         snd_rme96_info_attenuation_control,
2285 	.get =          snd_rme96_get_attenuation_control,
2286 	.put =          snd_rme96_put_attenuation_control
2287 },
2288 {
2289         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
2290 	.name =         "DAC Playback Volume",
2291 	.info =         snd_rme96_dac_volume_info,
2292 	.get =          snd_rme96_dac_volume_get,
2293 	.put =          snd_rme96_dac_volume_put
2294 }
2295 };
2296 
2297 static int
snd_rme96_create_switches(struct snd_card * card,struct rme96 * rme96)2298 snd_rme96_create_switches(struct snd_card *card,
2299 			  struct rme96 *rme96)
2300 {
2301 	int idx, err;
2302 	struct snd_kcontrol *kctl;
2303 
2304 	for (idx = 0; idx < 7; idx++) {
2305 		kctl = snd_ctl_new1(&snd_rme96_controls[idx], rme96);
2306 		err = snd_ctl_add(card, kctl);
2307 		if (err < 0)
2308 			return err;
2309 		if (idx == 1)	/* IEC958 (S/PDIF) Stream */
2310 			rme96->spdif_ctl = kctl;
2311 	}
2312 
2313 	if (RME96_HAS_ANALOG_OUT(rme96)) {
2314 		for (idx = 7; idx < 10; idx++) {
2315 			err = snd_ctl_add(card, snd_ctl_new1(&snd_rme96_controls[idx], rme96));
2316 			if (err < 0)
2317 				return err;
2318 		}
2319 	}
2320 
2321 	return 0;
2322 }
2323 
2324 /*
2325  * Card initialisation
2326  */
2327 
rme96_suspend(struct device * dev)2328 static int rme96_suspend(struct device *dev)
2329 {
2330 	struct snd_card *card = dev_get_drvdata(dev);
2331 	struct rme96 *rme96 = card->private_data;
2332 
2333 	snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2334 
2335 	/* save capture & playback pointers */
2336 	rme96->playback_pointer = readl(rme96->iobase + RME96_IO_GET_PLAY_POS)
2337 				  & RME96_RCR_AUDIO_ADDR_MASK;
2338 	rme96->capture_pointer = readl(rme96->iobase + RME96_IO_GET_REC_POS)
2339 				 & RME96_RCR_AUDIO_ADDR_MASK;
2340 
2341 	/* save playback and capture buffers */
2342 	memcpy_fromio(rme96->playback_suspend_buffer,
2343 		      rme96->iobase + RME96_IO_PLAY_BUFFER, RME96_BUFFER_SIZE);
2344 	memcpy_fromio(rme96->capture_suspend_buffer,
2345 		      rme96->iobase + RME96_IO_REC_BUFFER, RME96_BUFFER_SIZE);
2346 
2347 	/* disable the DAC  */
2348 	rme96->areg &= ~RME96_AR_DAC_EN;
2349 	writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
2350 	return 0;
2351 }
2352 
rme96_resume(struct device * dev)2353 static int rme96_resume(struct device *dev)
2354 {
2355 	struct snd_card *card = dev_get_drvdata(dev);
2356 	struct rme96 *rme96 = card->private_data;
2357 
2358 	/* reset playback and record buffer pointers */
2359 	writel(0, rme96->iobase + RME96_IO_SET_PLAY_POS
2360 		  + rme96->playback_pointer);
2361 	writel(0, rme96->iobase + RME96_IO_SET_REC_POS
2362 		  + rme96->capture_pointer);
2363 
2364 	/* restore playback and capture buffers */
2365 	memcpy_toio(rme96->iobase + RME96_IO_PLAY_BUFFER,
2366 		    rme96->playback_suspend_buffer, RME96_BUFFER_SIZE);
2367 	memcpy_toio(rme96->iobase + RME96_IO_REC_BUFFER,
2368 		    rme96->capture_suspend_buffer, RME96_BUFFER_SIZE);
2369 
2370 	/* reset the ADC */
2371 	writel(rme96->areg | RME96_AR_PD2,
2372 	       rme96->iobase + RME96_IO_ADDITIONAL_REG);
2373 	writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
2374 
2375 	/* reset and enable DAC, restore analog volume */
2376 	snd_rme96_reset_dac(rme96);
2377 	rme96->areg |= RME96_AR_DAC_EN;
2378 	writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
2379 	if (RME96_HAS_ANALOG_OUT(rme96)) {
2380 		usleep_range(3000, 10000);
2381 		snd_rme96_apply_dac_volume(rme96);
2382 	}
2383 
2384 	snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2385 
2386 	return 0;
2387 }
2388 
2389 static DEFINE_SIMPLE_DEV_PM_OPS(rme96_pm, rme96_suspend, rme96_resume);
2390 
snd_rme96_card_free(struct snd_card * card)2391 static void snd_rme96_card_free(struct snd_card *card)
2392 {
2393 	snd_rme96_free(card->private_data);
2394 }
2395 
2396 static int
__snd_rme96_probe(struct pci_dev * pci,const struct pci_device_id * pci_id)2397 __snd_rme96_probe(struct pci_dev *pci,
2398 		  const struct pci_device_id *pci_id)
2399 {
2400 	static int dev;
2401 	struct rme96 *rme96;
2402 	struct snd_card *card;
2403 	int err;
2404 	u8 val;
2405 
2406 	if (dev >= SNDRV_CARDS) {
2407 		return -ENODEV;
2408 	}
2409 	if (!enable[dev]) {
2410 		dev++;
2411 		return -ENOENT;
2412 	}
2413 	err = snd_devm_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2414 				sizeof(*rme96), &card);
2415 	if (err < 0)
2416 		return err;
2417 	card->private_free = snd_rme96_card_free;
2418 	rme96 = card->private_data;
2419 	rme96->card = card;
2420 	rme96->pci = pci;
2421 	err = snd_rme96_create(rme96);
2422 	if (err)
2423 		return err;
2424 
2425 	if (IS_ENABLED(CONFIG_PM_SLEEP)) {
2426 		rme96->playback_suspend_buffer = vmalloc(RME96_BUFFER_SIZE);
2427 		if (!rme96->playback_suspend_buffer)
2428 			return -ENOMEM;
2429 		rme96->capture_suspend_buffer = vmalloc(RME96_BUFFER_SIZE);
2430 		if (!rme96->capture_suspend_buffer)
2431 			return -ENOMEM;
2432 	}
2433 
2434 	strcpy(card->driver, "Digi96");
2435 	switch (rme96->pci->device) {
2436 	case PCI_DEVICE_ID_RME_DIGI96:
2437 		strcpy(card->shortname, "RME Digi96");
2438 		break;
2439 	case PCI_DEVICE_ID_RME_DIGI96_8:
2440 		strcpy(card->shortname, "RME Digi96/8");
2441 		break;
2442 	case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
2443 		strcpy(card->shortname, "RME Digi96/8 PRO");
2444 		break;
2445 	case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
2446 		pci_read_config_byte(rme96->pci, 8, &val);
2447 		if (val < 5) {
2448 			strcpy(card->shortname, "RME Digi96/8 PAD");
2449 		} else {
2450 			strcpy(card->shortname, "RME Digi96/8 PST");
2451 		}
2452 		break;
2453 	}
2454 	sprintf(card->longname, "%s at 0x%lx, irq %d", card->shortname,
2455 		rme96->port, rme96->irq);
2456 	err = snd_card_register(card);
2457 	if (err)
2458 		return err;
2459 
2460 	pci_set_drvdata(pci, card);
2461 	dev++;
2462 	return 0;
2463 }
2464 
snd_rme96_probe(struct pci_dev * pci,const struct pci_device_id * pci_id)2465 static int snd_rme96_probe(struct pci_dev *pci,
2466 			   const struct pci_device_id *pci_id)
2467 {
2468 	return snd_card_free_on_error(&pci->dev, __snd_rme96_probe(pci, pci_id));
2469 }
2470 
2471 static struct pci_driver rme96_driver = {
2472 	.name = KBUILD_MODNAME,
2473 	.id_table = snd_rme96_ids,
2474 	.probe = snd_rme96_probe,
2475 	.driver = {
2476 		.pm = &rme96_pm,
2477 	},
2478 };
2479 
2480 module_pci_driver(rme96_driver);
2481