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/linux/drivers/clk/sunxi-ng/
H A Dccu_mp.h34 #define SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(_struct, _name, _parents, _reg, \ argument
55 #define SUNXI_CCU_MP_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ argument
74 #define SUNXI_CCU_MP_WITH_MUX(_struct, _name, _parents, _reg, \ argument
85 #define SUNXI_CCU_MP_DATA_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ argument
104 #define SUNXI_CCU_MP_DATA_WITH_MUX(_struct, _name, _parents, _reg, \ argument
115 #define SUNXI_CCU_MP_HW_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ argument
152 #define SUNXI_CCU_MP_MMC_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ argument
H A Dccu_mux.h49 #define SUNXI_CCU_MUX_TABLE_WITH_GATE_FEAT(_struct, _name, _parents, _table, \ argument
65 #define SUNXI_CCU_MUX_TABLE_WITH_GATE_CLOSEST(_struct, _name, _parents, \ argument
73 #define SUNXI_CCU_MUX_TABLE_WITH_GATE(_struct, _name, _parents, _table, \ argument
80 #define SUNXI_CCU_MUX_WITH_GATE(_struct, _name, _parents, _reg, \ argument
86 #define SUNXI_CCU_MUX(_struct, _name, _parents, _reg, _shift, _width, \ argument
91 #define SUNXI_CCU_MUX_DATA_WITH_GATE(_struct, _name, _parents, _reg, \ argument
105 #define SUNXI_CCU_MUX_DATA(_struct, _name, _parents, _reg, \ argument
110 #define SUNXI_CCU_MUX_HW_WITH_GATE(_struct, _name, _parents, _reg, \ argument
H A Dccu_div.h128 _parents, _table, \ argument
147 _parents, _table, \ argument
166 #define SUNXI_CCU_M_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ argument
175 #define SUNXI_CCU_M_WITH_MUX_GATE_CLOSEST(_struct, _name, _parents, \ argument
185 #define SUNXI_CCU_M_WITH_MUX(_struct, _name, _parents, _reg, \ argument
215 #define SUNXI_CCU_M_DATA_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ argument
232 #define SUNXI_CCU_M_DATA_WITH_MUX(_struct, _name, _parents, _reg, \ argument
241 #define SUNXI_CCU_M_HW_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ argument
H A Dccu_nkm.h36 #define SUNXI_CCU_NKM_WITH_MUX_GATE_LOCK(_struct, _name, _parents, _reg, \ argument
/linux/drivers/clk/sprd/
H A Dmux.h39 #define SPRD_MUX_CLK_HW_INIT_FN(_struct, _name, _parents, _table, \ argument
51 #define SPRD_MUX_CLK_TABLE(_struct, _name, _parents, _table, \ argument
57 #define SPRD_MUX_CLK(_struct, _name, _parents, _reg, \ argument
62 #define SPRD_MUX_CLK_DATA_TABLE(_struct, _name, _parents, _table, \ argument
68 #define SPRD_MUX_CLK_DATA(_struct, _name, _parents, _reg, \ argument
/linux/drivers/clk/mediatek/
H A Dclk-mux.h41 #define __GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _paridx, \ argument
62 #define GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \ argument
70 #define GATE_CLR_SET_UPD_FLAGS_INDEXED(_id, _name, _parents, _paridx, \ argument
81 #define MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \ argument
89 #define MUX_GATE_CLR_SET_UPD_FLAGS_INDEXED(_id, _name, _parents, \ argument
97 #define MUX_GATE_CLR_SET_UPD(_id, _name, _parents, _mux_ofs, \ argument
105 #define MUX_GATE_CLR_SET_UPD_INDEXED(_id, _name, _parents, _paridx, \ argument
113 #define MUX_CLR_SET_UPD(_id, _name, _parents, _mux_ofs, \ argument
H A Dclk-mtk.h112 #define MUX_GATE_FLAGS_2(_id, _name, _parents, _reg, _shift, \ argument
132 #define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \ argument
141 #define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) \ argument
145 #define MUX(_id, _name, _parents, _reg, _shift, _width) \ argument
149 #define MUX_FLAGS(_id, _name, _parents, _reg, _shift, _width, _flags) { \ argument
H A Dclk-mt6795-topckgen.c21 #define TOP_MUX_GATE_NOSR(_id, _name, _parents, _reg, _shift, _width, _gate, _flags) \ argument
26 #define TOP_MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate, _flags) \ argument
H A Dclk-mt8173-topckgen.c22 #define TOP_MUX_GATE_NOSR(_id, _name, _parents, _reg, _shift, _width, _gate, _flags) \ argument
27 #define TOP_MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate, _flags) \ argument
/linux/drivers/clk/tegra/
H A Dclk-tegra-periph.c132 #define MUX(_name, _parents, _offset, \ argument
139 #define MUX_FLAGS(_name, _parents, _offset,\ argument
146 #define MUX8(_name, _parents, _offset, \ argument
153 #define MUX8_NOGATE_LOCK(_name, _parents, _offset, _clk_id, _lock) \ argument
159 #define MUX8_NOGATE(_name, _parents, _offset, _clk_id) \ argument
165 #define INT(_name, _parents, _offset, \ argument
172 #define INT_FLAGS(_name, _parents, _offset,\ argument
179 #define INT8(_name, _parents, _offset,\ argument
186 #define UART(_name, _parents, _offset,\ argument
193 #define UART8(_name, _parents, _offset,\ argument
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H A Dclk-tegra30.c157 #define TEGRA_INIT_DATA_MUX(_name, _parents, _offset, \ argument
163 #define TEGRA_INIT_DATA_MUX8(_name, _parents, _offset, \ argument
169 #define TEGRA_INIT_DATA_INT(_name, _parents, _offset, \ argument
176 #define TEGRA_INIT_DATA_NODIV(_name, _parents, _offset, \ argument
H A Dclk-tegra20.c135 #define TEGRA_INIT_DATA_MUX(_name, _parents, _offset, \ argument
142 #define TEGRA_INIT_DATA_DIV16(_name, _parents, _offset, \ argument
149 #define TEGRA_INIT_DATA_NODIV(_name, _parents, _offset, \ argument
H A Dclk-tegra124.c97 #define MUX8_NOGATE_LOCK(_name, _parents, _offset, _clk_id, _lock) \ argument
103 #define NODIV(_name, _parents, _offset, \ argument
H A Dclk-tegra114.c115 #define MUX8(_name, _parents, _offset, \ argument
/linux/drivers/clk/actions/
H A Dowl-mux.h34 #define OWL_MUX(_struct, _name, _parents, _reg, \ argument
/linux/drivers/clk/microchip/
H A Dclk-mpfs-ccc.c101 #define CLK_CCC_PLL(_id, _parents, _shift, _width, _flags, _offset) { \ argument
187 #define CLK_HW_INIT_PARENTS_DATA_FIXED_SIZE(_name, _parents, _ops, _flags) \ argument
/linux/drivers/clk/sophgo/
H A Dclk-cv18xx-common.h20 #define CV1800_CLK_COMMON(_name, _parents, _op, _flags) \ argument
H A Dclk-sg2042-clkgen.c409 #define SG2042_MUX(_id, _name, _parents, _flags, _r_select, _shift, _width) { \ argument
/linux/drivers/clk/
H A Dclk-stm32h7.c567 #define M_MCLOCF(_name, _parents, _mux_offset, _mux_shift, _mux_width, _flags)\ argument
578 #define M_MCLOC(_name, _parents, _mux_offset, _mux_shift, _mux_width)\ argument
1177 #define M_MCO_F(_name, _parents, _mux_offset, _mux_shift, _mux_width,\ argument
H A Dclk-bm1880.c160 #define GATE_MUX(_id, _name, _parents, _gate_reg, _gate_shift, \ argument
/linux/include/linux/
H A Dsh_clk.h175 #define SH_CLK_DIV6_EXT(_reg, _flags, _parents, \ argument
H A Dclk-provider.h1512 #define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags) \ argument
1521 #define CLK_HW_INIT_PARENTS_HW(_name, _parents, _ops, _flags) \ argument
1530 #define CLK_HW_INIT_PARENTS_DATA(_name, _parents, _ops, _flags) \ argument
/linux/drivers/clk/stm32/
H A Dclk-stm32mp1.c1218 #define MUX(_id, _name, _parents, _flags, _offset, _shift, _width, _mux_flags)\ argument
1234 #define PLL(_id, _name, _parents, _flags, _offset_p, _offset_mux)\ argument
1368 #define COMPOSITE(_id, _name, _parents, _flags, _gate, _mux, _div)\ argument
1389 #define KCLK(_id, _name, _parents, _flags, _mgate, _mmux)\ argument
/linux/drivers/clk/meson/
H A Daxg-audio.c322 #define AUD_TDM_PAD_CTRL(_name, _reg, _shift, _parents) \ argument