| /linux/drivers/clk/bcm/ |
| H A D | clk-kona.h | 91 #define POLICY(_offset, _bit) \ argument
151 #define HW_SW_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ argument
163 #define HW_SW_GATE_AUTO(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ argument
174 #define HW_ENABLE_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ argument
185 #define SW_ONLY_GATE(_offset, _status_bit, _en_bit) \ argument
195 #define HW_ONLY_GATE(_offset, _status_bit) \ argument
211 #define HYST(_offset, _en_bit, _val_bit) \ argument
291 #define DIVIDER(_offset, _shift, _width) \ argument
301 #define FRAC_DIVIDER(_offset, _shift, _width, _frac_width) \ argument
342 #define SELECTOR(_offset, _shift, _width) \ argument
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| /linux/drivers/net/ethernet/mellanox/mlxsw/ |
| H A D | item.h | 270 #define MLXSW_ITEM8(_type, _cname, _iname, _offset, _shift, _sizebits) \ argument
288 #define MLXSW_ITEM8_INDEXED(_type, _cname, _iname, _offset, _shift, _sizebits, \ argument
313 #define MLXSW_ITEM16(_type, _cname, _iname, _offset, _shift, _sizebits) \ argument
331 #define MLXSW_ITEM16_INDEXED(_type, _cname, _iname, _offset, _shift, _sizebits, \ argument
356 #define MLXSW_ITEM32(_type, _cname, _iname, _offset, _shift, _sizebits) \ argument
410 #define MLXSW_ITEM32_INDEXED(_type, _cname, _iname, _offset, _shift, _sizebits, \ argument
435 #define MLXSW_ITEM64(_type, _cname, _iname, _offset, _shift, _sizebits) \ argument
453 #define MLXSW_ITEM64_INDEXED(_type, _cname, _iname, _offset, _shift, \ argument
478 #define MLXSW_ITEM_BUF(_type, _cname, _iname, _offset, _sizebytes) \ argument
502 #define MLXSW_ITEM_BUF_INDEXED(_type, _cname, _iname, _offset, _sizebytes, \ argument
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| H A D | spectrum_acl.c | 532 #define MLXSW_SP_ACL_MANGLE_ACTION(_htype, _offset, _mask, _shift, _field) \ argument
541 #define MLXSW_SP_ACL_MANGLE_ACTION_IP4(_offset, _mask, _shift, _field) \ argument
545 #define MLXSW_SP_ACL_MANGLE_ACTION_IP6(_offset, _mask, _shift, _field) \ argument
549 #define MLXSW_SP_ACL_MANGLE_ACTION_TCP(_offset, _mask, _shift, _field) \ argument
552 #define MLXSW_SP_ACL_MANGLE_ACTION_UDP(_offset, _mask, _shift, _field) \ argument
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| /linux/drivers/clk/tegra/ |
| H A D | clk-tegra-periph.c | 132 #define MUX(_name, _parents, _offset, \ argument
139 #define MUX_FLAGS(_name, _parents, _offset,\ argument
146 #define MUX8(_name, _parents, _offset, \ argument
153 #define MUX8_NOGATE_LOCK(_name, _parents, _offset, _clk_id, _lock) \ argument
159 #define MUX8_NOGATE(_name, _parents, _offset, _clk_id) \ argument
165 #define INT(_name, _parents, _offset, \ argument
172 #define INT_FLAGS(_name, _parents, _offset,\ argument
179 #define INT8(_name, _parents, _offset,\ argument
186 #define UART(_name, _parents, _offset,\ argument
193 #define UART8(_name, _parents, _offset,\ argument
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| H A D | clk-tegra-audio.c | 52 #define AUDIO(_name, _offset) \ argument
71 #define AUDIO2X(_name, _num, _offset) \ argument
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| H A D | clk-tegra30.c | 157 #define TEGRA_INIT_DATA_MUX(_name, _parents, _offset, \ argument
163 #define TEGRA_INIT_DATA_MUX8(_name, _parents, _offset, \ argument
169 #define TEGRA_INIT_DATA_INT(_name, _parents, _offset, \ argument
176 #define TEGRA_INIT_DATA_NODIV(_name, _parents, _offset, \ argument
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| H A D | clk-tegra20.c | 135 #define TEGRA_INIT_DATA_MUX(_name, _parents, _offset, \ argument
142 #define TEGRA_INIT_DATA_DIV16(_name, _parents, _offset, \ argument
149 #define TEGRA_INIT_DATA_NODIV(_name, _parents, _offset, \ argument
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| /linux/drivers/clk/mediatek/ |
| H A D | clk-mt6795-apmixedsys.c | 76 #define _FH(_pllid, _fhid, _slope, _offset) { \ argument
99 #define FH(_pllid, _fhid, _offset) _FH(_pllid, _fhid, 0x6003c97, _offset) argument
100 #define FH_M(_pllid, _fhid, _offset) _FH(_pllid, _fhid, 0x6000140, _offset) argument
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| /linux/drivers/clk/ |
| H A D | clk-loongson2.c | 61 #define CLK_DIV(_id, _name, _pname, _offset, _dshift, _dwidth) \ argument
72 #define CLK_PLL(_id, _name, _offset, _mshift, _mwidth, \ argument
86 #define CLK_SCALE(_id, _name, _pname, _offset, \ argument
98 #define CLK_GATE(_id, _name, _pname, _offset, _bidx) \ argument
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| H A D | clk-loongson1.c | 153 #define LS1X_CLK_PLL(_name, _offset, _fixed, _shift, \ argument
177 #define LS1X_CLK_DIV(_name, _pname, _offset, _shift, _width, \ argument
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| /linux/drivers/clk/renesas/ |
| H A D | rcar-gen3-cpg.h | 37 #define DEF_GEN3_SDH(_name, _id, _parent, _offset) \ argument
40 #define DEF_GEN3_SD(_name, _id, _parent, _offset) \ argument
60 #define DEF_GEN3_Z(_name, _id, _type, _parent, _div, _offset) \ argument
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| H A D | rcar-gen4-cpg.h | 35 #define DEF_GEN4_SDH(_name, _id, _parent, _offset) \ argument
38 #define DEF_GEN4_SD(_name, _id, _parent, _offset) \ argument
61 #define DEF_GEN4_Z(_name, _id, _type, _parent, _div, _offset) \ argument
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| H A D | renesas-cpg-mssr.h | 53 #define DEF_DIV6P1(_name, _id, _parent, _offset) \ argument
55 #define DEF_DIV6_RO(_name, _id, _parent, _offset, _div) \ argument
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| /linux/drivers/bcma/ |
| H A D | sprom.c | 185 #define SPEX(_field, _offset, _mask, _shift) \ argument
188 #define SPEX32(_field, _offset, _mask, _shift) \ argument
192 #define SPEX_ARRAY8(_field, _offset, _mask, _shift) \ argument
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| /linux/drivers/clk/sprd/ |
| H A D | div.h | 28 #define _SPRD_DIV_CLK(_offset, _shift, _width) \ argument
40 #define SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _offset, \ argument
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| /linux/drivers/clk/sunxi-ng/ |
| H A D | ccu_mult.h | 17 #define _SUNXI_CCU_MULT_OFFSET_MIN_MAX(_shift, _width, _offset, _min, _max) \ argument
29 #define _SUNXI_CCU_MULT_OFFSET(_shift, _width, _offset) \ argument
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| /linux/drivers/ssb/ |
| H A D | pci.c | 171 #define SPEX16(_outvar, _offset, _mask, _shift) \ argument
173 #define SPEX32(_outvar, _offset, _mask, _shift) \ argument
176 #define SPEX(_outvar, _offset, _mask, _shift) \ argument
179 #define SPEX_ARRAY8(_field, _offset, _mask, _shift) \ argument
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| /linux/drivers/clk/stm32/ |
| H A D | clk-stm32mp13.c | 140 #define _CFG_GATE(_id, _offset, _bit_idx, _offset_clr)\ argument
147 #define CFG_GATE(_id, _offset, _bit_idx)\ argument
150 #define CFG_GATE_SETCLR(_id, _offset, _bit_idx)\ argument
290 #define CFG_DIV(_id, _offset, _shift, _width, _flags, _table, _ready)\ argument
352 #define _CFG_MUX(_id, _offset, _shift, _witdh, _ready, _flags)\ argument
361 #define CFG_MUX(_id, _offset, _shift, _witdh)\ argument
364 #define CFG_MUX_SAFE(_id, _offset, _shift, _witdh)\ argument
471 #define SECF(_sec_id, _offset, _bit_idx)[_sec_id] = {\ argument
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| H A D | clk-stm32mp1.c | 1170 #define GATE(_id, _name, _parent, _flags, _offset, _bit_idx, _gate_flags)\ argument
1197 #define DIV_TABLE(_id, _name, _parent, _flags, _offset, _shift, _width,\ argument
1214 #define DIV(_id, _name, _parent, _flags, _offset, _shift, _width, _div_flags)\ argument
1218 #define MUX(_id, _name, _parents, _flags, _offset, _shift, _width, _mux_flags)\ argument
1311 #define GATE_MP1(_id, _name, _parent, _flags, _offset, _bit_idx, _gate_flags)\ argument
1344 #define _STM32_MUX(_offset, _shift, _width, _mux_flags, _mmux, _ops)\ argument
1357 #define _MUX(_offset, _shift, _width, _mux_flags)\ argument
1698 #define _K_MUX(_id, _offset, _shift, _width, _mux_flags, _mmux, _ops)\ argument
1711 #define K_MUX(_id, _offset, _shift, _width, _mux_flags)\ argument
1715 #define K_MMUX(_id, _offset, _shift, _width, _mux_flags)\ argument
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| /linux/drivers/clk/microchip/ |
| H A D | clk-mpfs.c | 136 #define CLK_PLL(_id, _name, _parent, _shift, _width, _flags, _offset) { \ argument
175 #define CLK_PLL_OUT(_id, _name, _parent, _flags, _shift, _width, _offset) { \ argument
223 #define CLK_CFG(_id, _name, _parent, _shift, _width, _table, _flags, _offset) { \ argument
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| H A D | clk-mpfs-ccc.c | 101 #define CLK_CCC_PLL(_id, _parents, _shift, _width, _flags, _offset) { \ argument
124 #define CLK_CCC_OUT(_id, _shift, _width, _flags, _offset) { \ argument
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| /linux/drivers/clk/st/ |
| H A D | clkgen.h | 38 #define CLKGEN_FIELD(_offset, _mask, _shift) { \ argument
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| /linux/drivers/pinctrl/berlin/ |
| H A D | berlin.h | 31 #define BERLIN_PINCTRL_GROUP(_name, _offset, _width, _lsb, ...) \ argument
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| /linux/drivers/pinctrl/mediatek/ |
| H A D | pinctrl-mt2701.c | 30 #define MTK_PINMUX_SPEC(_pin, _offset, _bit) \ argument
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| H A D | pinctrl-mtk-common.h | 109 #define MTK_PIN_DRV_GRP(_pin, _offset, _bit, _grp) \ argument
134 #define MTK_PIN_PUPD_SPEC_SR(_pin, _offset, _pupd, _r1, _r0) \ argument
157 #define MTK_PIN_IES_SMT_SPEC(_start, _end, _offset, _bit) \ argument
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