1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright 2021~2022 NXP
4 *
5 * The driver exports a standard gpiochip interface
6 * to control the PIN resources on SCU domain.
7 */
8
9 #include <linux/cleanup.h>
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/mutex.h>
13 #include <linux/gpio/driver.h>
14 #include <linux/platform_device.h>
15 #include <linux/firmware/imx/svc/rm.h>
16 #include <dt-bindings/firmware/imx/rsrc.h>
17
18 struct scu_gpio_priv {
19 struct gpio_chip chip;
20 struct mutex lock;
21 struct device *dev;
22 struct imx_sc_ipc *handle;
23 };
24
25 static unsigned int scu_rsrc_arr[] = {
26 IMX_SC_R_BOARD_R0,
27 IMX_SC_R_BOARD_R1,
28 IMX_SC_R_BOARD_R2,
29 IMX_SC_R_BOARD_R3,
30 IMX_SC_R_BOARD_R4,
31 IMX_SC_R_BOARD_R5,
32 IMX_SC_R_BOARD_R6,
33 IMX_SC_R_BOARD_R7,
34 };
35
imx_scu_gpio_get(struct gpio_chip * chip,unsigned int offset)36 static int imx_scu_gpio_get(struct gpio_chip *chip, unsigned int offset)
37 {
38 struct scu_gpio_priv *priv = gpiochip_get_data(chip);
39 int level;
40 int err;
41
42 scoped_guard(mutex, &priv->lock) {
43 /* to read PIN state via scu api */
44 err = imx_sc_misc_get_control(priv->handle,
45 scu_rsrc_arr[offset], 0, &level);
46 }
47 if (err) {
48 dev_err(priv->dev, "SCU get failed: %d\n", err);
49 return err;
50 }
51
52 return level;
53 }
54
imx_scu_gpio_set(struct gpio_chip * chip,unsigned int offset,int value)55 static int imx_scu_gpio_set(struct gpio_chip *chip, unsigned int offset,
56 int value)
57 {
58 struct scu_gpio_priv *priv = gpiochip_get_data(chip);
59 int err;
60
61 scoped_guard(mutex, &priv->lock) {
62 /* to set PIN output level via scu api */
63 err = imx_sc_misc_set_control(priv->handle,
64 scu_rsrc_arr[offset], 0, value);
65 }
66 if (err)
67 dev_err(priv->dev, "SCU set (%d) failed: %d\n",
68 scu_rsrc_arr[offset], err);
69
70 return err;
71 }
72
imx_scu_gpio_get_direction(struct gpio_chip * chip,unsigned int offset)73 static int imx_scu_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
74 {
75 return GPIO_LINE_DIRECTION_OUT;
76 }
77
imx_scu_gpio_probe(struct platform_device * pdev)78 static int imx_scu_gpio_probe(struct platform_device *pdev)
79 {
80 struct device *dev = &pdev->dev;
81 struct scu_gpio_priv *priv;
82 struct gpio_chip *gc;
83 int ret;
84
85 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
86 if (!priv)
87 return -ENOMEM;
88
89 ret = imx_scu_get_handle(&priv->handle);
90 if (ret)
91 return ret;
92
93 priv->dev = dev;
94
95 ret = devm_mutex_init(&pdev->dev, &priv->lock);
96 if (ret)
97 return ret;
98
99 gc = &priv->chip;
100 gc->base = -1;
101 gc->parent = dev;
102 gc->ngpio = ARRAY_SIZE(scu_rsrc_arr);
103 gc->label = dev_name(dev);
104 gc->get = imx_scu_gpio_get;
105 gc->set_rv = imx_scu_gpio_set;
106 gc->get_direction = imx_scu_gpio_get_direction;
107
108 platform_set_drvdata(pdev, priv);
109
110 return devm_gpiochip_add_data(dev, gc, priv);
111 }
112
113 static const struct of_device_id imx_scu_gpio_dt_ids[] = {
114 { .compatible = "fsl,imx8qxp-sc-gpio" },
115 { /* sentinel */ }
116 };
117
118 static struct platform_driver imx_scu_gpio_driver = {
119 .driver = {
120 .name = "gpio-imx-scu",
121 .of_match_table = imx_scu_gpio_dt_ids,
122 },
123 .probe = imx_scu_gpio_probe,
124 };
125
_imx_scu_gpio_init(void)126 static int __init _imx_scu_gpio_init(void)
127 {
128 return platform_driver_register(&imx_scu_gpio_driver);
129 }
130
131 subsys_initcall_sync(_imx_scu_gpio_init);
132
133 MODULE_AUTHOR("Shenwei Wang <shenwei.wang@nxp.com>");
134 MODULE_DESCRIPTION("NXP GPIO over IMX SCU API");
135