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Searched defs:_i (Results 1 – 25 of 57) sorted by relevance

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/linux/drivers/infiniband/hw/irdma/
H A Di40iw_hw.h34 #define I40E_GLHMC_VFPDINV(_i) (0x000C8300 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ argument
38 #define I40E_GLPES_PFIP4RXDISCARD(_i) (0x00010600 + ((_i) * 4)) /* _i=0...15 */ /* Reset… argument
39 #define I40E_GLPES_PFIP4RXTRUNC(_i) (0x00010700 + ((_i) * 4)) /* _i=0...15 */ /* Reset… argument
40 #define I40E_GLPES_PFIP4TXNOROUTE(_i) (0x00012E00 + ((_i) * 4)) /* _i=0...15 */ /* Reset… argument
41 #define I40E_GLPES_PFIP6RXDISCARD(_i) (0x00011200 + ((_i) * 4)) /* _i=0...15 */ /* Reset… argument
42 #define I40E_GLPES_PFIP6RXTRUNC(_i) (0x00011300 + ((_i) * 4)) /* _i=0...15 */ /* Reset… argument
44 #define I40E_GLPES_PFRDMAVBNDLO(_i) (0x00014800 + ((_i) * 8)) /* _i=0...15 */ /* Reset… argument
45 #define I40E_GLPES_PFIP4TXMCOCTSLO(_i) (0x00012000 + ((_i) * 8)) /* _i=0...15 */ /* Reset… argument
46 #define I40E_GLPES_PFIP6RXMCOCTSLO(_i) (0x00011600 + ((_i) * 8)) /* _i=0...15 */ /* Reset… argument
47 #define I40E_GLPES_PFIP6TXMCOCTSLO(_i) (0x00012A00 + ((_i) * 8)) /* _i=0...15 */ /* Reset… argument
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H A Dicrdma_hw.h19 #define VFINT_DYN_CTLN(_i) (0x00003800 + ((_i) * 4)) /* _i=0...63 */ argument
40 #define GLHMC_VFPDINV(_i) (0x00528300 + ((_i) * 4)) /* _i=0...31 */ argument
/linux/drivers/net/ethernet/intel/i40e/
H A Di40e_register.h74 #define I40E_PRTDCB_RETSTCC(_i) (0x00122180 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */ argument
109 #define I40E_PRTDCB_RUPTQ(_i) (0x00122400 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */ argument
116 #define I40E_PRTDCB_TCMSTC(_i) (0x000A0040 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */ argument
127 #define I40E_PRTDCB_TCWSTC(_i) (0x000A2040 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */ argument
167 #define I40E_PRTDCB_TPFCTS(_i) (0x001E4660 + ((_i) * 32)) /* _i=0...7 */ /* Reset: GLOBR */ argument
182 #define I40E_GLGEN_GPIO_CTL(_i) (0x00088100 + ((_i) * 4)) /* _i=0...29 */ /* Reset: POR */ argument
202 #define I40E_GLGEN_MDIO_I2C_SEL(_i) (0x000881C0 + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */ argument
203 #define I40E_GLGEN_MSCA(_i) (0x0008818C + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */ argument
208 #define I40E_GLGEN_MSCA_OPCODE_MASK(_i) I40E_MASK(_i, I40E_GLGEN_MSCA_OPCODE_SHIFT) argument
210 #define I40E_GLGEN_MSCA_STCODE_MASK(_i) I40E_MASK(_i, I40E_GLGEN_MSCA_STCODE_SHIFT) argument
[all …]
/linux/drivers/net/ethernet/intel/ice/
H A Dice_hw_autogen.h9 #define GLCOMM_QUANTA_PROF(_i) (0x002D2D68 + ((_i) * 4)) argument
119 #define GL_PREEXT_L2_PMASK0(_i) (0x0020F0FC + ((_i) * 4)) argument
120 #define GL_PREEXT_L2_PMASK1(_i) (0x0020F108 + ((_i) * 4)) argument
121 #define GLFLXP_RXDID_FLAGS(_i, _j) (0x0045D000 + ((_i) * 4 + (_j) * 256)) argument
124 #define GLFLXP_RXDID_FLX_WRD_0(_i) (0x0045c800 + ((_i) * 4)) argument
129 #define GLFLXP_RXDID_FLX_WRD_1(_i) (0x0045c900 + ((_i) * 4)) argument
134 #define GLFLXP_RXDID_FLX_WRD_2(_i) (0x0045ca00 + ((_i) * 4)) argument
139 #define GLFLXP_RXDID_FLX_WRD_3(_i) (0x0045cb00 + ((_i) * 4)) argument
153 #define GLGEN_GPIO_CTL(_i) (0x000880C8 + ((_i) * 4)) argument
170 #define GLGEN_VFLRSTAT(_i) (0x00093A04 + ((_i) * 4)) argument
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H A Dice_ethtool.c159 #define TCDCB_TLPM_WAIT_DM(_i) (0x000A0080 + ((_i) * 4)) argument
228 #define GLTDPU_TCLAN_COMP_BOB(_i) (0x00049ADC + ((_i) * 4)) argument
237 #define GLTDPU_TCB_CMD_BOB(_i) (0x0004975C + ((_i) * 4)) argument
246 #define GLTDPU_PSM_UPDATE_BOB(_i) (0x00049B5C + ((_i) * 4)) argument
255 #define GLTCB_CMD_IN_BOB(_i) (0x000AE288 + ((_i) * 4)) argument
264 #define GLLAN_TCLAN_FETCH_CTL_FBK_BOB_CTL(_i) (0x000FC148 + ((_i) * 4)) argument
273 #define GLLAN_TCLAN_FETCH_CTL_SCHED_BOB_CTL(_i) (0x000FC248 + ((_i) * 4)) argument
282 #define GLLAN_TCLAN_CACHE_CTL_BOB_CTL(_i) (0x000FC1C8 + ((_i) * 4)) argument
291 #define GLLAN_TCLAN_FETCH_CTL_PROC_BOB_CTL(_i) (0x000FC188 + ((_i) * 4)) argument
300 #define GLLAN_TCLAN_FETCH_CTL_PCIE_RD_BOB_CTL(_i) (0x000FC288 + ((_i) * 4)) argument
[all …]
/linux/drivers/net/wireless/ath/ath9k/
H A Dreg_wow.h127 #define AR_WOW_LEN1_SHIFT(_i) ((0x3 - ((_i) & 0x3)) << 0x3) argument
128 #define AR_WOW_LENGTH1_MASK(_i) (AR_WOW_LENGTH_MAX << AR_WOW_LEN1_SHIFT(_i)) argument
129 #define AR_WOW_LEN2_SHIFT(_i) ((0x7 - ((_i) & 0x7)) << 0x3) argument
130 #define AR_WOW_LENGTH2_MASK(_i) (AR_WOW_LENGTH_MAX << AR_WOW_LEN2_SHIFT(_i)) argument
131 #define AR_WOW_LEN3_SHIFT(_i) ((0xb - ((_i) & 0xb)) << 0x3) argument
132 #define AR_WOW_LENGTH3_MASK(_i) (AR_WOW_LENGTH_MAX << AR_WOW_LEN3_SHIFT(_i)) argument
133 #define AR_WOW_LEN4_SHIFT(_i) ((0xf - ((_i) & 0xf)) << 0x3) argument
134 #define AR_WOW_LENGTH4_MASK(_i) (AR_WOW_LENGTH_MAX << AR_WOW_LEN4_SHIFT(_i)) argument
H A Dar9002_phy.h190 #define AR_PHY_TIMING_CTRL4(_i) (0x9920 + ((_i) << 12)) argument
305 #define AR_PHY_NEW_ADC_DC_GAIN_CORR(_i) (0x99b4 + ((_i) << 12)) argument
385 #define AR_PHY_CAL_MEAS_0(_i) (0x9c10 + ((_i) << 12)) argument
386 #define AR_PHY_CAL_MEAS_1(_i) (0x9c14 + ((_i) << 12)) argument
387 #define AR_PHY_CAL_MEAS_2(_i) (0x9c18 + ((_i) << 12)) argument
388 #define AR_PHY_CAL_MEAS_3(_i) (0x9c1c + ((_i) << 12)) argument
/linux/fs/bcachefs/
H A Dreplicas.h56 #define for_each_cpu_replicas_entry(_r, _i) \ argument
63 #define replicas_entry_next(_i) \ argument
66 #define for_each_replicas_entry(_r, _i) \ argument
71 #define for_each_replicas_entry_v0(_r, _i) \ argument
H A Ddarray.h91 #define darray_find_p(_d, _i, cond) \ argument
107 #define __darray_for_each(_d, _i) \ argument
110 #define darray_for_each(_d, _i) \ argument
113 #define darray_for_each_reverse(_d, _i) \ argument
H A Dvstructs.h50 #define vstruct_for_each(_s, _i) \ argument
55 #define vstruct_for_each_safe(_s, _i) \ argument
H A Deytzinger.h161 #define eytzinger1_for_each(_i, _size) \ argument
232 #define eytzinger0_for_each(_i, _size) \ argument
237 #define eytzinger0_for_each_prev(_i, _size) \ argument
H A Dreplicas_format.h28 #define replicas_entry_bytes(_i) \ argument
/linux/drivers/crypto/cavium/nitrox/
H A Dnitrox_csr.h21 #define EMU_BIST_STATUSX(_i) (0x1402700 + ((_i) * 0x40000)) argument
29 #define EFL_CORE_BIST_REGX(_i) (0x1240100 + ((_i) * 0x400)) argument
33 #define PEM_BIST_STATUSX(_i) (0x1080468 | ((_i) << 18)) argument
36 #define EMU_SE_ENABLEX(_i) (0x1400000 + ((_i) * 0x40000)) argument
37 #define EMU_AE_ENABLEX(_i) (0x1400008 + ((_i) * 0x40000)) argument
38 #define EMU_WD_INT_ENA_W1SX(_i) (0x1402318 + ((_i) * 0x40000)) argument
39 #define EMU_GE_INT_ENA_W1SX(_i) (0x1402518 + ((_i) * 0x40000)) argument
40 #define EMU_FUSE_MAPX(_i) (0x1402708 + ((_i) * 0x40000)) argument
43 #define UCD_SE_EID_UCODE_BLOCK_NUMX(_i) (0x12C0000 + ((_i) * 0x1000)) argument
44 #define UCD_AE_EID_UCODE_BLOCK_NUMX(_i) (0x12C0008 + ((_i) * 0x800)) argument
[all …]
/linux/drivers/net/ethernet/intel/igb/
H A De1000_regs.h286 #define E1000_PSRTYPE(_i) (0x05480 + ((_i) * 4)) argument
287 #define E1000_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \ argument
289 #define E1000_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \ argument
292 #define E1000_IP4AT_REG(_i) (0x05840 + ((_i) * 8)) argument
293 #define E1000_IP6AT_REG(_i) (0x05880 + ((_i) * 4)) argument
294 #define E1000_WUPM_REG(_i) (0x05A00 + ((_i) * 4)) argument
295 #define E1000_FFMT_REG(_i) (0x09000 + ((_i) * 8)) argument
296 #define E1000_FFVT_REG(_i) (0x09800 + ((_i) * 8)) argument
297 #define E1000_FFLT_REG(_i) (0x05F00 + ((_i) * 8)) argument
319 #define E1000_IMIR(_i) (0x05A80 + ((_i) * 4)) /* Immediate Interrupt */ argument
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/linux/drivers/net/ethernet/wangxun/libwx/
H A Dwx_type.h33 #define WX_MIS_RST_LAN_RST(_i) BIT((_i) + 1) argument
84 #define WX_RDM_VF_RE(_i) (0x12004 + ((_i) * 4)) argument
85 #define WX_RDM_PF_QDE(_i) (0x12080 + ((_i) * 4)) argument
86 #define WX_RDM_VFRE_CLR(_i) (0x120A0 + ((_i) * 4)) argument
99 #define WX_CFG_TAG_TPID(_i) (0x14430 + ((_i) * 4)) argument
128 #define WX_TDM_VF_TE(_i) (0x18004 + ((_i) * 4)) argument
129 #define WX_TDM_MAC_AS(_i) (0x18060 + ((_i) * 4)) argument
130 #define WX_TDM_VLAN_AS(_i) (0x18070 + ((_i) * 4)) argument
131 #define WX_TDM_VFTE_CLR(_i) (0x180A0 + ((_i) * 4)) argument
135 #define WX_TDM_PB_THRE(_i) (0x18020 + ((_i) * 4)) argument
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/linux/drivers/net/ethernet/intel/iavf/
H A Diavf_register.h58 #define IAVF_VFINT_ITRN1(_i, _INTVF) (0x00002800 + ((_i) * 64 + (_INTVF) * 4)) /* _i=0...2, _INTVF=… argument
61 #define IAVF_VFQF_HENA(_i) (0x0000C400 + ((_i) * 4)) /* _i=0...1 */ /* Reset: CORER */ argument
62 #define IAVF_VFQF_HKEY(_i) (0x0000CC00 + ((_i) * 4)) /* _i=0...12 */ /* Reset: CORER */ argument
64 #define IAVF_VFQF_HLUT(_i) (0x0000D000 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ argument
/linux/drivers/input/mouse/
H A Dalps.h92 #define SS4_MF_LF_V2(_b, _i) ((_b[1 + (_i) * 3] & 0x0004) == 0x0004) argument
96 #define SS4_STD_MF_X_V2(_b, _i) (((_b[0 + (_i) * 3] << 5) & 0x00E0) | \ argument
100 #define SS4_PLUS_STD_MF_X_V2(_b, _i) (((_b[0 + (_i) * 3] << 4) & 0x0070) | \ argument
104 #define SS4_STD_MF_Y_V2(_b, _i) (((_b[1 + (_i) * 3] << 3) & 0x0010) | \ argument
109 #define SS4_BTL_MF_X_V2(_b, _i) (SS4_STD_MF_X_V2(_b, _i) | \ argument
113 #define SS4_PLUS_BTL_MF_X_V2(_b, _i) (SS4_PLUS_STD_MF_X_V2(_b, _i) | \ argument
117 #define SS4_BTL_MF_Y_V2(_b, _i) (SS4_STD_MF_Y_V2(_b, _i) | \ argument
121 #define SS4_MF_Z_V2(_b, _i) (((_b[1 + (_i) * 3]) & 0x0001) | \ argument
/linux/drivers/net/ethernet/intel/e1000e/
H A Dich8lan.h47 #define E1000_SHRAL_PCH_LPT(_i) (0x05408 + ((_i) * 8)) argument
48 #define E1000_SHRAH_PCH_LPT(_i) (0x0540C + ((_i) * 8)) argument
125 #define BM_RAR_L(_i) (BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2))) argument
126 #define BM_RAR_M(_i) (BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2))) argument
127 #define BM_RAR_H(_i) (BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2))) argument
128 #define BM_RAR_CTRL(_i) (BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2))) argument
129 #define BM_MTA(_i) (BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1))) argument
H A Dregs.h108 #define E1000_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \ argument
110 #define E1000_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \ argument
112 #define E1000_SHRAL(_i) (0x05438 + ((_i) * 8)) argument
113 #define E1000_SHRAH(_i) (0x0543C + ((_i) * 8)) argument
224 #define E1000_RETA(_i) (0x05C00 + ((_i) * 4)) /* Redirection Table - RW */ argument
225 #define E1000_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* RSS Random Key - RW */ argument
/linux/drivers/gpu/drm/armada/
H A Darmada_crtc.h18 #define armada_reg_queue_mod(_r, _i, _v, _m, _o) \ argument
27 #define armada_reg_queue_set(_r, _i, _v, _o) \ argument
30 #define armada_reg_queue_end(_r, _i) \ argument
/linux/drivers/net/ethernet/intel/idpf/
H A Didpf_lan_vf_regs.h122 #define VF_QF_HENA(_i) (0x0000C400 + ((_i) * 4)) argument
124 #define VF_QF_HKEY(_i) (0x0000CC00 + ((_i) * 4)) argument
126 #define VF_QF_HLUT(_i) (0x0000D000 + ((_i) * 4)) argument
/linux/drivers/net/ethernet/intel/igbvf/
H A Dregs.h55 #define E1000_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \ argument
57 #define E1000_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \ argument
/linux/include/xen/interface/io/
H A Dring.h139 #define FRONT_RING_ATTACH(_r, _s, _i, __size) do { \ argument
153 #define BACK_RING_ATTACH(_r, _s, _i, __size) do { \ argument
/linux/drivers/net/wireless/ath/carl9170/
H A Dphy.h185 #define AR9170_PHY_REG_TIMING_CTRL4(_i) (AR9170_PHY_REG_BASE + \ argument
308 #define AR9170_PHY_REG_NEW_ADC_DC_GAIN_CORR(_i) (AR9170_PHY_REG_BASE + \ argument
381 #define AR9170_PHY_REG_CAL_MEAS_0(_i) (AR9170_PHY_REG_BASE + \ argument
383 #define AR9170_PHY_REG_CAL_MEAS_1(_i) (AR9170_PHY_REG_BASE + \ argument
385 #define AR9170_PHY_REG_CAL_MEAS_2(_i) (AR9170_PHY_REG_BASE + \ argument
387 #define AR9170_PHY_REG_CAL_MEAS_3(_i) (AR9170_PHY_REG_BASE + \ argument
/linux/drivers/net/ethernet/wangxun/txgbe/
H A Dtxgbe_type.h56 #define TXGBE_MIS_RST_MAC_RST(_i) BIT(20 - (_i) * 3) argument
58 #define TXGBE_MIS_PRB_CTL_LAN_UP(_i) BIT(1 - (_i)) argument
63 #define TXGBE_SPI_ILDR_STATUS_LAN_SW_RST(_i) BIT((_i) + 9) /* lan soft reset done */ argument
123 #define TXGBE_RDB_FDIR_IP6(_i) (0x1950C + ((_i) * 4)) /* 0-2 */ argument
157 #define TXGBE_RDB_FDIR_FLEX_CFG(_i) (0x19580 + ((_i) * 4)) argument

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