1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5 #include "acpi.h"
6 #include "debug.h"
7 #include "fw.h"
8 #include "phy.h"
9 #include "reg.h"
10 #include "sar.h"
11 #include "util.h"
12
13 #define RTW89_TAS_FACTOR 2 /* unit: 0.25 dBm */
14 #define RTW89_TAS_SAR_GAP (1 << RTW89_TAS_FACTOR)
15 #define RTW89_TAS_DPR_GAP (1 << RTW89_TAS_FACTOR)
16 #define RTW89_TAS_DELTA (2 << RTW89_TAS_FACTOR)
17 #define RTW89_TAS_TX_RATIO_THRESHOLD 70
18 #define RTW89_TAS_DFLT_TX_RATIO 80
19 #define RTW89_TAS_DPR_ON_OFFSET (RTW89_TAS_DELTA + RTW89_TAS_SAR_GAP)
20 #define RTW89_TAS_DPR_OFF_OFFSET (4 << RTW89_TAS_FACTOR)
21
rtw89_sar_get_subband(struct rtw89_dev * rtwdev,u32 center_freq)22 static enum rtw89_sar_subband rtw89_sar_get_subband(struct rtw89_dev *rtwdev,
23 u32 center_freq)
24 {
25 switch (center_freq) {
26 default:
27 rtw89_debug(rtwdev, RTW89_DBG_SAR,
28 "center freq: %u to SAR subband is unhandled\n",
29 center_freq);
30 fallthrough;
31 case 2412 ... 2484:
32 return RTW89_SAR_2GHZ_SUBBAND;
33 case 5180 ... 5320:
34 return RTW89_SAR_5GHZ_SUBBAND_1_2;
35 case 5500 ... 5720:
36 return RTW89_SAR_5GHZ_SUBBAND_2_E;
37 case 5745 ... 5885:
38 return RTW89_SAR_5GHZ_SUBBAND_3_4;
39 case 5955 ... 6155:
40 return RTW89_SAR_6GHZ_SUBBAND_5_L;
41 case 6175 ... 6415:
42 return RTW89_SAR_6GHZ_SUBBAND_5_H;
43 case 6435 ... 6515:
44 return RTW89_SAR_6GHZ_SUBBAND_6;
45 case 6535 ... 6695:
46 return RTW89_SAR_6GHZ_SUBBAND_7_L;
47 case 6715 ... 6855:
48 return RTW89_SAR_6GHZ_SUBBAND_7_H;
49
50 /* freq 6875 (ch 185, 20MHz) spans RTW89_SAR_6GHZ_SUBBAND_7_H
51 * and RTW89_SAR_6GHZ_SUBBAND_8, so directly describe it with
52 * struct rtw89_6ghz_span.
53 */
54
55 case 6895 ... 7115:
56 return RTW89_SAR_6GHZ_SUBBAND_8;
57 }
58 }
59
rtw89_query_sar_config_common(struct rtw89_dev * rtwdev,const struct rtw89_sar_parm * sar_parm,s32 * cfg)60 static int rtw89_query_sar_config_common(struct rtw89_dev *rtwdev,
61 const struct rtw89_sar_parm *sar_parm,
62 s32 *cfg)
63 {
64 struct rtw89_sar_cfg_common *rtwsar = &rtwdev->sar.cfg_common;
65 enum rtw89_sar_subband subband_l, subband_h;
66 u32 center_freq = sar_parm->center_freq;
67 const struct rtw89_6ghz_span *span;
68
69 span = rtw89_get_6ghz_span(rtwdev, center_freq);
70
71 if (span && RTW89_SAR_SPAN_VALID(span)) {
72 subband_l = span->sar_subband_low;
73 subband_h = span->sar_subband_high;
74 } else {
75 subband_l = rtw89_sar_get_subband(rtwdev, center_freq);
76 subband_h = subband_l;
77 }
78
79 rtw89_debug(rtwdev, RTW89_DBG_SAR,
80 "center_freq %u: SAR subband {%u, %u}\n",
81 center_freq, subband_l, subband_h);
82
83 if (!rtwsar->set[subband_l] && !rtwsar->set[subband_h])
84 return -ENODATA;
85
86 if (!rtwsar->set[subband_l])
87 *cfg = rtwsar->cfg[subband_h];
88 else if (!rtwsar->set[subband_h])
89 *cfg = rtwsar->cfg[subband_l];
90 else
91 *cfg = min(rtwsar->cfg[subband_l], rtwsar->cfg[subband_h]);
92
93 return 0;
94 }
95
96 static const struct rtw89_sar_entry_from_acpi *
rtw89_sar_cfg_acpi_get_ent(const struct rtw89_sar_cfg_acpi * rtwsar,enum rtw89_rf_path path,enum rtw89_regulation_type regd)97 rtw89_sar_cfg_acpi_get_ent(const struct rtw89_sar_cfg_acpi *rtwsar,
98 enum rtw89_rf_path path,
99 enum rtw89_regulation_type regd)
100 {
101 const struct rtw89_sar_indicator_from_acpi *ind = &rtwsar->indicator;
102 const struct rtw89_sar_table_from_acpi *tbl;
103 u8 sel;
104
105 sel = ind->tblsel[path];
106 tbl = &rtwsar->tables[sel];
107
108 return &tbl->entries[regd];
109 }
110
111 static
rtw89_sar_cfg_acpi_get_min(const struct rtw89_sar_entry_from_acpi * ent,enum rtw89_rf_path path,enum rtw89_acpi_sar_subband subband_low,enum rtw89_acpi_sar_subband subband_high)112 s32 rtw89_sar_cfg_acpi_get_min(const struct rtw89_sar_entry_from_acpi *ent,
113 enum rtw89_rf_path path,
114 enum rtw89_acpi_sar_subband subband_low,
115 enum rtw89_acpi_sar_subband subband_high)
116 {
117 return min(ent->v[subband_low][path], ent->v[subband_high][path]);
118 }
119
rtw89_query_sar_config_acpi(struct rtw89_dev * rtwdev,const struct rtw89_sar_parm * sar_parm,s32 * cfg)120 static int rtw89_query_sar_config_acpi(struct rtw89_dev *rtwdev,
121 const struct rtw89_sar_parm *sar_parm,
122 s32 *cfg)
123 {
124 const struct rtw89_chip_info *chip = rtwdev->chip;
125 const struct rtw89_sar_cfg_acpi *rtwsar = &rtwdev->sar.cfg_acpi;
126 const struct rtw89_sar_entry_from_acpi *ent_a, *ent_b;
127 enum rtw89_acpi_sar_subband subband_l, subband_h;
128 u32 center_freq = sar_parm->center_freq;
129 const struct rtw89_6ghz_span *span;
130 enum rtw89_regulation_type regd;
131 enum rtw89_band band;
132 s32 cfg_a, cfg_b;
133
134 span = rtw89_get_6ghz_span(rtwdev, center_freq);
135
136 if (span && RTW89_ACPI_SAR_SPAN_VALID(span)) {
137 subband_l = span->acpi_sar_subband_low;
138 subband_h = span->acpi_sar_subband_high;
139 } else {
140 subband_l = rtw89_acpi_sar_get_subband(rtwdev, center_freq);
141 subband_h = subband_l;
142 }
143
144 band = rtw89_acpi_sar_subband_to_band(rtwdev, subband_l);
145 regd = rtw89_regd_get(rtwdev, band);
146
147 ent_a = rtw89_sar_cfg_acpi_get_ent(rtwsar, RF_PATH_A, regd);
148 ent_b = rtw89_sar_cfg_acpi_get_ent(rtwsar, RF_PATH_B, regd);
149
150 cfg_a = rtw89_sar_cfg_acpi_get_min(ent_a, RF_PATH_A, subband_l, subband_h);
151 cfg_b = rtw89_sar_cfg_acpi_get_min(ent_b, RF_PATH_B, subband_l, subband_h);
152
153 if (chip->support_sar_by_ant) {
154 /* With declaration of support_sar_by_ant, relax the general
155 * SAR querying to return the maximum between paths. However,
156 * expect chip has dealt with the corresponding SAR settings
157 * by path. (To get SAR for a given path, chip can then query
158 * with force_path.)
159 */
160 if (sar_parm->force_path) {
161 switch (sar_parm->path) {
162 default:
163 case RF_PATH_A:
164 *cfg = cfg_a;
165 break;
166 case RF_PATH_B:
167 *cfg = cfg_b;
168 break;
169 }
170 } else {
171 *cfg = max(cfg_a, cfg_b);
172 }
173 } else {
174 *cfg = min(cfg_a, cfg_b);
175 }
176
177 if (sar_parm->ntx == RTW89_2TX)
178 *cfg -= rtwsar->downgrade_2tx;
179
180 return 0;
181 }
182
183 static const
184 struct rtw89_sar_handler rtw89_sar_handlers[RTW89_SAR_SOURCE_NR] = {
185 [RTW89_SAR_SOURCE_COMMON] = {
186 .descr_sar_source = "RTW89_SAR_SOURCE_COMMON",
187 .txpwr_factor_sar = 2,
188 .query_sar_config = rtw89_query_sar_config_common,
189 },
190 [RTW89_SAR_SOURCE_ACPI] = {
191 .descr_sar_source = "RTW89_SAR_SOURCE_ACPI",
192 .txpwr_factor_sar = TXPWR_FACTOR_OF_RTW89_ACPI_SAR,
193 .query_sar_config = rtw89_query_sar_config_acpi,
194 },
195 };
196
197 #define rtw89_sar_set_src(_dev, _src, _cfg_name, _cfg_data) \
198 do { \
199 typeof(_src) _s = (_src); \
200 typeof(_dev) _d = (_dev); \
201 BUILD_BUG_ON(!rtw89_sar_handlers[_s].descr_sar_source); \
202 BUILD_BUG_ON(!rtw89_sar_handlers[_s].query_sar_config); \
203 if (test_bit(RTW89_FLAG_PROBE_DONE, _d->flags)) \
204 lockdep_assert_wiphy(_d->hw->wiphy); \
205 _d->sar._cfg_name = *(_cfg_data); \
206 _d->sar.src = _s; \
207 } while (0)
208
rtw89_txpwr_sar_to_mac(struct rtw89_dev * rtwdev,u8 fct,s32 cfg)209 static s8 rtw89_txpwr_sar_to_mac(struct rtw89_dev *rtwdev, u8 fct, s32 cfg)
210 {
211 const u8 fct_mac = rtwdev->chip->txpwr_factor_mac;
212 s32 cfg_mac;
213
214 cfg_mac = fct > fct_mac ?
215 cfg >> (fct - fct_mac) : cfg << (fct_mac - fct);
216
217 return (s8)clamp_t(s32, cfg_mac,
218 RTW89_SAR_TXPWR_MAC_MIN,
219 RTW89_SAR_TXPWR_MAC_MAX);
220 }
221
rtw89_txpwr_tas_to_sar(const struct rtw89_sar_handler * sar_hdl,s32 cfg)222 static s32 rtw89_txpwr_tas_to_sar(const struct rtw89_sar_handler *sar_hdl,
223 s32 cfg)
224 {
225 const u8 fct = sar_hdl->txpwr_factor_sar;
226
227 if (fct > RTW89_TAS_FACTOR)
228 return cfg << (fct - RTW89_TAS_FACTOR);
229 else
230 return cfg >> (RTW89_TAS_FACTOR - fct);
231 }
232
rtw89_txpwr_sar_to_tas(const struct rtw89_sar_handler * sar_hdl,s32 cfg)233 static s32 rtw89_txpwr_sar_to_tas(const struct rtw89_sar_handler *sar_hdl,
234 s32 cfg)
235 {
236 const u8 fct = sar_hdl->txpwr_factor_sar;
237
238 if (fct > RTW89_TAS_FACTOR)
239 return cfg >> (fct - RTW89_TAS_FACTOR);
240 else
241 return cfg << (RTW89_TAS_FACTOR - fct);
242 }
243
rtw89_tas_is_active(struct rtw89_dev * rtwdev)244 static bool rtw89_tas_is_active(struct rtw89_dev *rtwdev)
245 {
246 struct rtw89_tas_info *tas = &rtwdev->tas;
247 struct rtw89_vif *rtwvif;
248
249 if (!tas->enable)
250 return false;
251
252 rtw89_for_each_rtwvif(rtwdev, rtwvif) {
253 if (ieee80211_vif_is_mld(rtwvif_to_vif(rtwvif)))
254 return false;
255 }
256
257 return true;
258 }
259
rtw89_tas_state_str(enum rtw89_tas_state state)260 static const char *rtw89_tas_state_str(enum rtw89_tas_state state)
261 {
262 switch (state) {
263 case RTW89_TAS_STATE_DPR_OFF:
264 return "DPR OFF";
265 case RTW89_TAS_STATE_DPR_ON:
266 return "DPR ON";
267 case RTW89_TAS_STATE_STATIC_SAR:
268 return "STATIC SAR";
269 default:
270 return NULL;
271 }
272 }
273
rtw89_query_sar(struct rtw89_dev * rtwdev,const struct rtw89_sar_parm * sar_parm)274 s8 rtw89_query_sar(struct rtw89_dev *rtwdev, const struct rtw89_sar_parm *sar_parm)
275 {
276 const enum rtw89_sar_sources src = rtwdev->sar.src;
277 /* its members are protected by rtw89_sar_set_src() */
278 const struct rtw89_sar_handler *sar_hdl = &rtw89_sar_handlers[src];
279 struct rtw89_tas_info *tas = &rtwdev->tas;
280 s32 offset;
281 int ret;
282 s32 cfg;
283 u8 fct;
284
285 lockdep_assert_wiphy(rtwdev->hw->wiphy);
286
287 if (src == RTW89_SAR_SOURCE_NONE)
288 return RTW89_SAR_TXPWR_MAC_MAX;
289
290 ret = sar_hdl->query_sar_config(rtwdev, sar_parm, &cfg);
291 if (ret)
292 return RTW89_SAR_TXPWR_MAC_MAX;
293
294 if (rtw89_tas_is_active(rtwdev)) {
295 switch (tas->state) {
296 case RTW89_TAS_STATE_DPR_OFF:
297 offset = rtw89_txpwr_tas_to_sar(sar_hdl, RTW89_TAS_DPR_OFF_OFFSET);
298 cfg += offset;
299 break;
300 case RTW89_TAS_STATE_DPR_ON:
301 offset = rtw89_txpwr_tas_to_sar(sar_hdl, RTW89_TAS_DPR_ON_OFFSET);
302 cfg -= offset;
303 break;
304 case RTW89_TAS_STATE_STATIC_SAR:
305 default:
306 break;
307 }
308 }
309
310 fct = sar_hdl->txpwr_factor_sar;
311
312 return rtw89_txpwr_sar_to_mac(rtwdev, fct, cfg);
313 }
314 EXPORT_SYMBOL(rtw89_query_sar);
315
rtw89_print_sar(struct rtw89_dev * rtwdev,char * buf,size_t bufsz,const struct rtw89_sar_parm * sar_parm)316 int rtw89_print_sar(struct rtw89_dev *rtwdev, char *buf, size_t bufsz,
317 const struct rtw89_sar_parm *sar_parm)
318 {
319 const enum rtw89_sar_sources src = rtwdev->sar.src;
320 /* its members are protected by rtw89_sar_set_src() */
321 const struct rtw89_sar_handler *sar_hdl = &rtw89_sar_handlers[src];
322 const u8 fct_mac = rtwdev->chip->txpwr_factor_mac;
323 char *p = buf, *end = buf + bufsz;
324 int ret;
325 s32 cfg;
326 u8 fct;
327
328 lockdep_assert_wiphy(rtwdev->hw->wiphy);
329
330 if (src == RTW89_SAR_SOURCE_NONE) {
331 p += scnprintf(p, end - p, "no SAR is applied\n");
332 goto out;
333 }
334
335 p += scnprintf(p, end - p, "source: %d (%s)\n", src,
336 sar_hdl->descr_sar_source);
337
338 ret = sar_hdl->query_sar_config(rtwdev, sar_parm, &cfg);
339 if (ret) {
340 p += scnprintf(p, end - p, "config: return code: %d\n", ret);
341 p += scnprintf(p, end - p,
342 "assign: max setting: %d (unit: 1/%lu dBm)\n",
343 RTW89_SAR_TXPWR_MAC_MAX, BIT(fct_mac));
344 goto out;
345 }
346
347 fct = sar_hdl->txpwr_factor_sar;
348
349 p += scnprintf(p, end - p, "config: %d (unit: 1/%lu dBm)\n", cfg,
350 BIT(fct));
351
352 p += scnprintf(p, end - p, "support different configs by antenna: %s\n",
353 str_yes_no(rtwdev->chip->support_sar_by_ant));
354 out:
355 return p - buf;
356 }
357
rtw89_print_tas(struct rtw89_dev * rtwdev,char * buf,size_t bufsz)358 int rtw89_print_tas(struct rtw89_dev *rtwdev, char *buf, size_t bufsz)
359 {
360 struct rtw89_tas_info *tas = &rtwdev->tas;
361 char *p = buf, *end = buf + bufsz;
362
363 if (!rtw89_tas_is_active(rtwdev)) {
364 p += scnprintf(p, end - p, "no TAS is applied\n");
365 goto out;
366 }
367
368 p += scnprintf(p, end - p, "State: %s\n",
369 rtw89_tas_state_str(tas->state));
370 p += scnprintf(p, end - p, "Average time: %d\n",
371 tas->window_size * 2);
372 p += scnprintf(p, end - p, "SAR gap: %d dBm\n",
373 RTW89_TAS_SAR_GAP >> RTW89_TAS_FACTOR);
374 p += scnprintf(p, end - p, "DPR gap: %d dBm\n",
375 RTW89_TAS_DPR_GAP >> RTW89_TAS_FACTOR);
376 p += scnprintf(p, end - p, "DPR ON offset: %d dBm\n",
377 RTW89_TAS_DPR_ON_OFFSET >> RTW89_TAS_FACTOR);
378 p += scnprintf(p, end - p, "DPR OFF offset: %d dBm\n",
379 RTW89_TAS_DPR_OFF_OFFSET >> RTW89_TAS_FACTOR);
380
381 out:
382 return p - buf;
383 }
384
rtw89_apply_sar_common(struct rtw89_dev * rtwdev,const struct rtw89_sar_cfg_common * sar)385 static int rtw89_apply_sar_common(struct rtw89_dev *rtwdev,
386 const struct rtw89_sar_cfg_common *sar)
387 {
388 /* let common SAR have the highest priority; always apply it */
389 rtw89_sar_set_src(rtwdev, RTW89_SAR_SOURCE_COMMON, cfg_common, sar);
390 rtw89_core_set_chip_txpwr(rtwdev);
391 rtw89_tas_reset(rtwdev, false);
392
393 return 0;
394 }
395
396 static const struct cfg80211_sar_freq_ranges rtw89_common_sar_freq_ranges[] = {
397 { .start_freq = 2412, .end_freq = 2484, },
398 { .start_freq = 5180, .end_freq = 5320, },
399 { .start_freq = 5500, .end_freq = 5720, },
400 { .start_freq = 5745, .end_freq = 5885, },
401 { .start_freq = 5955, .end_freq = 6155, },
402 { .start_freq = 6175, .end_freq = 6415, },
403 { .start_freq = 6435, .end_freq = 6515, },
404 { .start_freq = 6535, .end_freq = 6695, },
405 { .start_freq = 6715, .end_freq = 6875, },
406 { .start_freq = 6875, .end_freq = 7115, },
407 };
408
409 static_assert(RTW89_SAR_SUBBAND_NR ==
410 ARRAY_SIZE(rtw89_common_sar_freq_ranges));
411
412 const struct cfg80211_sar_capa rtw89_sar_capa = {
413 .type = NL80211_SAR_TYPE_POWER,
414 .num_freq_ranges = ARRAY_SIZE(rtw89_common_sar_freq_ranges),
415 .freq_ranges = rtw89_common_sar_freq_ranges,
416 };
417
rtw89_ops_set_sar_specs(struct ieee80211_hw * hw,const struct cfg80211_sar_specs * sar)418 int rtw89_ops_set_sar_specs(struct ieee80211_hw *hw,
419 const struct cfg80211_sar_specs *sar)
420 {
421 struct rtw89_dev *rtwdev = hw->priv;
422 struct rtw89_sar_cfg_common sar_common = {0};
423 u8 fct;
424 u32 freq_start;
425 u32 freq_end;
426 s32 power;
427 u32 i, idx;
428
429 lockdep_assert_wiphy(rtwdev->hw->wiphy);
430
431 if (sar->type != NL80211_SAR_TYPE_POWER)
432 return -EINVAL;
433
434 fct = rtw89_sar_handlers[RTW89_SAR_SOURCE_COMMON].txpwr_factor_sar;
435
436 for (i = 0; i < sar->num_sub_specs; i++) {
437 idx = sar->sub_specs[i].freq_range_index;
438 if (idx >= ARRAY_SIZE(rtw89_common_sar_freq_ranges))
439 return -EINVAL;
440
441 freq_start = rtw89_common_sar_freq_ranges[idx].start_freq;
442 freq_end = rtw89_common_sar_freq_ranges[idx].end_freq;
443 power = sar->sub_specs[i].power;
444
445 rtw89_debug(rtwdev, RTW89_DBG_SAR,
446 "On freq %u to %u, set SAR limit %d (unit: 1/%lu dBm)\n",
447 freq_start, freq_end, power, BIT(fct));
448
449 sar_common.set[idx] = true;
450 sar_common.cfg[idx] = power;
451 }
452
453 return rtw89_apply_sar_common(rtwdev, &sar_common);
454 }
455
rtw89_apply_sar_acpi(struct rtw89_dev * rtwdev,const struct rtw89_sar_cfg_acpi * sar)456 static void rtw89_apply_sar_acpi(struct rtw89_dev *rtwdev,
457 const struct rtw89_sar_cfg_acpi *sar)
458 {
459 const struct rtw89_sar_table_from_acpi *tbl;
460 const struct rtw89_sar_entry_from_acpi *ent;
461 enum rtw89_sar_sources src;
462 unsigned int i, j, k;
463
464 src = rtwdev->sar.src;
465 if (src != RTW89_SAR_SOURCE_NONE) {
466 rtw89_warn(rtwdev, "SAR source: %d is in use", src);
467 return;
468 }
469
470 rtw89_debug(rtwdev, RTW89_DBG_SAR,
471 "SAR-ACPI downgrade 2TX: %u (unit: 1/%lu dBm)\n",
472 sar->downgrade_2tx, BIT(TXPWR_FACTOR_OF_RTW89_ACPI_SAR));
473
474 for (i = 0; i < sar->valid_num; i++) {
475 tbl = &sar->tables[i];
476
477 for (j = 0; j < RTW89_REGD_NUM; j++) {
478 ent = &tbl->entries[j];
479
480 rtw89_debug(rtwdev, RTW89_DBG_SAR,
481 "SAR-ACPI-[%u] REGD-%s (unit: 1/%lu dBm)\n",
482 i, rtw89_regd_get_string(j),
483 BIT(TXPWR_FACTOR_OF_RTW89_ACPI_SAR));
484
485 for (k = 0; k < NUM_OF_RTW89_ACPI_SAR_SUBBAND; k++)
486 rtw89_debug(rtwdev, RTW89_DBG_SAR,
487 "On subband %u, { %d, %d }\n", k,
488 ent->v[k][RF_PATH_A], ent->v[k][RF_PATH_B]);
489 }
490 }
491
492 rtw89_sar_set_src(rtwdev, RTW89_SAR_SOURCE_ACPI, cfg_acpi, sar);
493
494 /* SAR via ACPI is only configured in the early initial phase, so
495 * it does not seem necessary to reset txpwr related things here.
496 */
497 }
498
rtw89_set_sar_from_acpi(struct rtw89_dev * rtwdev)499 static void rtw89_set_sar_from_acpi(struct rtw89_dev *rtwdev)
500 {
501 struct rtw89_sar_cfg_acpi *cfg;
502 int ret;
503
504 cfg = kzalloc_obj(*cfg);
505 if (!cfg)
506 return;
507
508 ret = rtw89_acpi_evaluate_sar(rtwdev, cfg);
509 if (ret) {
510 rtw89_debug(rtwdev, RTW89_DBG_SAR,
511 "evaluating ACPI SAR returns %d\n", ret);
512 goto out;
513 }
514
515 if (unlikely(!cfg->valid_num)) {
516 rtw89_debug(rtwdev, RTW89_DBG_SAR, "no valid SAR table from ACPI\n");
517 goto out;
518 }
519
520 rtw89_apply_sar_acpi(rtwdev, cfg);
521
522 out:
523 kfree(cfg);
524 }
525
rtw89_tas_query_sar_config(struct rtw89_dev * rtwdev,s32 * cfg)526 static bool rtw89_tas_query_sar_config(struct rtw89_dev *rtwdev, s32 *cfg)
527 {
528 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_CHANCTX_0);
529 const enum rtw89_sar_sources src = rtwdev->sar.src;
530 /* its members are protected by rtw89_sar_set_src() */
531 const struct rtw89_sar_handler *sar_hdl = &rtw89_sar_handlers[src];
532 struct rtw89_sar_parm sar_parm = {};
533 int ret;
534
535 if (src == RTW89_SAR_SOURCE_NONE)
536 return false;
537
538 sar_parm.center_freq = chan->freq;
539 ret = sar_hdl->query_sar_config(rtwdev, &sar_parm, cfg);
540 if (ret)
541 return false;
542
543 *cfg = rtw89_txpwr_sar_to_tas(sar_hdl, *cfg);
544
545 return true;
546 }
547
__rtw89_tas_state_update(struct rtw89_dev * rtwdev,enum rtw89_tas_state state)548 static bool __rtw89_tas_state_update(struct rtw89_dev *rtwdev,
549 enum rtw89_tas_state state)
550 {
551 struct rtw89_tas_info *tas = &rtwdev->tas;
552
553 if (tas->state == state)
554 return false;
555
556 rtw89_debug(rtwdev, RTW89_DBG_SAR, "tas: switch state: %s -> %s\n",
557 rtw89_tas_state_str(tas->state), rtw89_tas_state_str(state));
558
559 tas->state = state;
560 return true;
561 }
562
rtw89_tas_state_update(struct rtw89_dev * rtwdev,enum rtw89_tas_state state)563 static void rtw89_tas_state_update(struct rtw89_dev *rtwdev,
564 enum rtw89_tas_state state)
565 {
566 if (!__rtw89_tas_state_update(rtwdev, state))
567 return;
568
569 rtw89_core_set_chip_txpwr(rtwdev);
570 }
571
rtw89_tas_get_window_size(struct rtw89_dev * rtwdev)572 static u32 rtw89_tas_get_window_size(struct rtw89_dev *rtwdev)
573 {
574 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_CHANCTX_0);
575 u8 band = chan->band_type;
576 u8 regd = rtw89_regd_get(rtwdev, band);
577
578 switch (regd) {
579 default:
580 rtw89_debug(rtwdev, RTW89_DBG_SAR,
581 "tas: regd: %u is unhandled\n", regd);
582 fallthrough;
583 case RTW89_IC:
584 case RTW89_KCC:
585 return 180;
586 case RTW89_FCC:
587 switch (band) {
588 case RTW89_BAND_2G:
589 return 50;
590 case RTW89_BAND_5G:
591 return 30;
592 case RTW89_BAND_6G:
593 default:
594 return 15;
595 }
596 break;
597 }
598 }
599
rtw89_tas_window_update(struct rtw89_dev * rtwdev)600 static void rtw89_tas_window_update(struct rtw89_dev *rtwdev)
601 {
602 u32 window_size = rtw89_tas_get_window_size(rtwdev);
603 struct rtw89_tas_info *tas = &rtwdev->tas;
604 u64 total_txpwr = 0;
605 u8 head_idx;
606 u32 i, j;
607
608 WARN_ON_ONCE(tas->window_size > RTW89_TAS_TXPWR_WINDOW);
609
610 if (tas->window_size == window_size)
611 return;
612
613 rtw89_debug(rtwdev, RTW89_DBG_SAR, "tas: window update: %u -> %u\n",
614 tas->window_size, window_size);
615
616 head_idx = (tas->txpwr_tail_idx - window_size + 1 + RTW89_TAS_TXPWR_WINDOW) %
617 RTW89_TAS_TXPWR_WINDOW;
618 for (i = 0; i < window_size; i++) {
619 j = (head_idx + i) % RTW89_TAS_TXPWR_WINDOW;
620 total_txpwr += tas->txpwr_history[j];
621 }
622
623 tas->window_size = window_size;
624 tas->total_txpwr = total_txpwr;
625 tas->txpwr_head_idx = head_idx;
626 }
627
rtw89_tas_history_update(struct rtw89_dev * rtwdev)628 static void rtw89_tas_history_update(struct rtw89_dev *rtwdev)
629 {
630 struct rtw89_bb_ctx *bb = rtw89_get_bb_ctx(rtwdev, RTW89_PHY_0);
631 struct rtw89_env_monitor_info *env = &bb->env_monitor;
632 struct rtw89_tas_info *tas = &rtwdev->tas;
633 u8 tx_ratio = env->ifs_clm_tx_ratio;
634 u64 instant_txpwr, txpwr;
635
636 /* txpwr in unit of linear(mW) multiply by percentage */
637 if (tx_ratio == 0) {
638 /* special case: idle tx power
639 * use -40 dBm * 100 tx ratio
640 */
641 instant_txpwr = rtw89_db_to_linear(-40);
642 txpwr = instant_txpwr * 100;
643 } else {
644 instant_txpwr = tas->instant_txpwr;
645 txpwr = instant_txpwr * tx_ratio;
646 }
647
648 tas->total_txpwr += txpwr - tas->txpwr_history[tas->txpwr_head_idx];
649 tas->total_tx_ratio += tx_ratio - tas->tx_ratio_history[tas->tx_ratio_idx];
650 tas->tx_ratio_history[tas->tx_ratio_idx] = tx_ratio;
651
652 tas->txpwr_head_idx = (tas->txpwr_head_idx + 1) % RTW89_TAS_TXPWR_WINDOW;
653 tas->txpwr_tail_idx = (tas->txpwr_tail_idx + 1) % RTW89_TAS_TXPWR_WINDOW;
654 tas->tx_ratio_idx = (tas->tx_ratio_idx + 1) % RTW89_TAS_TX_RATIO_WINDOW;
655 tas->txpwr_history[tas->txpwr_tail_idx] = txpwr;
656
657 rtw89_debug(rtwdev, RTW89_DBG_SAR,
658 "tas: instant_txpwr: %d, tx_ratio: %u, txpwr: %d\n",
659 rtw89_linear_to_db_quarter(instant_txpwr), tx_ratio,
660 rtw89_linear_to_db_quarter(div_u64(txpwr, PERCENT)));
661 }
662
rtw89_tas_rolling_average(struct rtw89_dev * rtwdev)663 static bool rtw89_tas_rolling_average(struct rtw89_dev *rtwdev)
664 {
665 struct rtw89_tas_info *tas = &rtwdev->tas;
666 s32 dpr_on_threshold, dpr_off_threshold;
667 enum rtw89_tas_state state;
668 u16 tx_ratio_avg;
669 s32 txpwr_avg;
670 u64 linear;
671
672 linear = DIV_ROUND_DOWN_ULL(tas->total_txpwr, tas->window_size * PERCENT);
673 txpwr_avg = rtw89_linear_to_db_quarter(linear);
674 tx_ratio_avg = tas->total_tx_ratio / RTW89_TAS_TX_RATIO_WINDOW;
675 dpr_on_threshold = tas->dpr_on_threshold;
676 dpr_off_threshold = tas->dpr_off_threshold;
677
678 rtw89_debug(rtwdev, RTW89_DBG_SAR,
679 "tas: DPR_ON: %d, DPR_OFF: %d, txpwr_avg: %d, tx_ratio_avg: %u\n",
680 dpr_on_threshold, dpr_off_threshold, txpwr_avg, tx_ratio_avg);
681
682 if (tx_ratio_avg >= RTW89_TAS_TX_RATIO_THRESHOLD)
683 state = RTW89_TAS_STATE_STATIC_SAR;
684 else if (txpwr_avg >= dpr_on_threshold)
685 state = RTW89_TAS_STATE_DPR_ON;
686 else if (txpwr_avg < dpr_off_threshold)
687 state = RTW89_TAS_STATE_DPR_OFF;
688 else
689 return false;
690
691 return __rtw89_tas_state_update(rtwdev, state);
692 }
693
rtw89_tas_init(struct rtw89_dev * rtwdev)694 static void rtw89_tas_init(struct rtw89_dev *rtwdev)
695 {
696 const struct rtw89_chip_info *chip = rtwdev->chip;
697 struct rtw89_tas_info *tas = &rtwdev->tas;
698 const struct rtw89_acpi_policy_tas *ptr;
699 struct rtw89_acpi_dsm_result res = {};
700 int ret;
701
702 if (!chip->support_tas)
703 return;
704
705 ret = rtw89_acpi_evaluate_dsm(rtwdev, RTW89_ACPI_DSM_FUNC_TAS_EN, &res);
706 if (ret) {
707 rtw89_debug(rtwdev, RTW89_DBG_SAR,
708 "acpi: cannot get TAS: %d\n", ret);
709 return;
710 }
711
712 ptr = res.u.policy_tas;
713
714 switch (ptr->enable) {
715 case 0:
716 tas->enable = false;
717 break;
718 case 1:
719 tas->enable = true;
720 break;
721 default:
722 break;
723 }
724
725 if (!tas->enable) {
726 rtw89_debug(rtwdev, RTW89_DBG_SAR, "TAS not enable\n");
727 goto out;
728 }
729
730 tas->enabled_countries = ptr->enabled_countries;
731
732 out:
733 kfree(ptr);
734 }
735
rtw89_tas_reset(struct rtw89_dev * rtwdev,bool force)736 void rtw89_tas_reset(struct rtw89_dev *rtwdev, bool force)
737 {
738 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_CHANCTX_0);
739 struct rtw89_tas_info *tas = &rtwdev->tas;
740 u64 linear;
741 s32 cfg;
742 int i;
743
744 if (!rtw89_tas_is_active(rtwdev))
745 return;
746
747 if (!rtw89_tas_query_sar_config(rtwdev, &cfg))
748 return;
749
750 tas->dpr_on_threshold = cfg - RTW89_TAS_SAR_GAP;
751 tas->dpr_off_threshold = cfg - RTW89_TAS_SAR_GAP - RTW89_TAS_DPR_GAP;
752
753 /* avoid history reset after new SAR apply */
754 if (!force && tas->keep_history)
755 return;
756
757 linear = rtw89_db_quarter_to_linear(cfg) * RTW89_TAS_DFLT_TX_RATIO;
758 for (i = 0; i < RTW89_TAS_TXPWR_WINDOW; i++)
759 tas->txpwr_history[i] = linear;
760
761 for (i = 0; i < RTW89_TAS_TX_RATIO_WINDOW; i++)
762 tas->tx_ratio_history[i] = RTW89_TAS_DFLT_TX_RATIO;
763
764 tas->total_tx_ratio = RTW89_TAS_DFLT_TX_RATIO * RTW89_TAS_TX_RATIO_WINDOW;
765 tas->total_txpwr = linear * RTW89_TAS_TXPWR_WINDOW;
766 tas->window_size = RTW89_TAS_TXPWR_WINDOW;
767 tas->txpwr_head_idx = 0;
768 tas->txpwr_tail_idx = RTW89_TAS_TXPWR_WINDOW - 1;
769 tas->tx_ratio_idx = 0;
770 tas->state = RTW89_TAS_STATE_DPR_OFF;
771 tas->backup_state = RTW89_TAS_STATE_DPR_OFF;
772 tas->keep_history = true;
773
774 rtw89_debug(rtwdev, RTW89_DBG_SAR,
775 "tas: band: %u, freq: %u\n", chan->band_type, chan->freq);
776 }
777
rtw89_tas_track(struct rtw89_dev * rtwdev)778 static bool rtw89_tas_track(struct rtw89_dev *rtwdev)
779 {
780 struct rtw89_tas_info *tas = &rtwdev->tas;
781 struct rtw89_hal *hal = &rtwdev->hal;
782 s32 cfg;
783
784 if (hal->disabled_dm_bitmap & BIT(RTW89_DM_TAS))
785 return false;
786
787 if (!rtw89_tas_is_active(rtwdev))
788 return false;
789
790 if (!rtw89_tas_query_sar_config(rtwdev, &cfg) || tas->block_regd)
791 return __rtw89_tas_state_update(rtwdev, RTW89_TAS_STATE_STATIC_SAR);
792
793 if (tas->pause)
794 return false;
795
796 rtw89_tas_window_update(rtwdev);
797 rtw89_tas_history_update(rtwdev);
798
799 return rtw89_tas_rolling_average(rtwdev);
800 }
801
rtw89_tas_scan(struct rtw89_dev * rtwdev,bool start)802 void rtw89_tas_scan(struct rtw89_dev *rtwdev, bool start)
803 {
804 struct rtw89_tas_info *tas = &rtwdev->tas;
805 s32 cfg;
806
807 if (!rtw89_tas_is_active(rtwdev))
808 return;
809
810 if (!rtw89_tas_query_sar_config(rtwdev, &cfg))
811 return;
812
813 if (start) {
814 tas->backup_state = tas->state;
815 rtw89_tas_state_update(rtwdev, RTW89_TAS_STATE_STATIC_SAR);
816 } else {
817 rtw89_tas_state_update(rtwdev, tas->backup_state);
818 }
819 }
820
rtw89_tas_chanctx_cb(struct rtw89_dev * rtwdev,enum rtw89_chanctx_state state)821 void rtw89_tas_chanctx_cb(struct rtw89_dev *rtwdev,
822 enum rtw89_chanctx_state state)
823 {
824 struct rtw89_tas_info *tas = &rtwdev->tas;
825 s32 cfg;
826
827 if (!rtw89_tas_is_active(rtwdev))
828 return;
829
830 if (!rtw89_tas_query_sar_config(rtwdev, &cfg))
831 return;
832
833 switch (state) {
834 case RTW89_CHANCTX_STATE_MCC_START:
835 tas->pause = true;
836 rtw89_tas_state_update(rtwdev, RTW89_TAS_STATE_STATIC_SAR);
837 break;
838 case RTW89_CHANCTX_STATE_MCC_STOP:
839 tas->pause = false;
840 break;
841 default:
842 break;
843 }
844 }
845 EXPORT_SYMBOL(rtw89_tas_chanctx_cb);
846
rtw89_tas_fw_timer_enable(struct rtw89_dev * rtwdev,bool enable)847 void rtw89_tas_fw_timer_enable(struct rtw89_dev *rtwdev, bool enable)
848 {
849 const struct rtw89_chip_info *chip = rtwdev->chip;
850 struct rtw89_tas_info *tas = &rtwdev->tas;
851
852 if (!tas->enable)
853 return;
854
855 if (chip->chip_gen == RTW89_CHIP_AX)
856 return;
857
858 rtw89_fw_h2c_rf_tas_trigger(rtwdev, enable);
859 }
860
rtw89_sar_init(struct rtw89_dev * rtwdev)861 void rtw89_sar_init(struct rtw89_dev *rtwdev)
862 {
863 rtw89_set_sar_from_acpi(rtwdev);
864 rtw89_tas_init(rtwdev);
865 }
866
rtw89_sar_track_acpi(struct rtw89_dev * rtwdev)867 static bool rtw89_sar_track_acpi(struct rtw89_dev *rtwdev)
868 {
869 struct rtw89_sar_cfg_acpi *cfg = &rtwdev->sar.cfg_acpi;
870 struct rtw89_sar_indicator_from_acpi *ind = &cfg->indicator;
871 const enum rtw89_sar_sources src = rtwdev->sar.src;
872 bool changed;
873 int ret;
874
875 lockdep_assert_wiphy(rtwdev->hw->wiphy);
876
877 if (src != RTW89_SAR_SOURCE_ACPI)
878 return false;
879
880 if (!ind->enable_sync)
881 return false;
882
883 ret = rtw89_acpi_evaluate_dynamic_sar_indicator(rtwdev, cfg, &changed);
884 if (likely(!ret))
885 return changed;
886
887 rtw89_debug(rtwdev, RTW89_DBG_SAR,
888 "%s: failed to track indicator: %d; reset and disable\n",
889 __func__, ret);
890
891 memset(ind->tblsel, 0, sizeof(ind->tblsel));
892 ind->enable_sync = false;
893 return true;
894 }
895
rtw89_sar_track(struct rtw89_dev * rtwdev)896 void rtw89_sar_track(struct rtw89_dev *rtwdev)
897 {
898 unsigned int changes = 0;
899
900 changes += rtw89_sar_track_acpi(rtwdev);
901 changes += rtw89_tas_track(rtwdev);
902
903 if (!changes)
904 return;
905
906 rtw89_core_set_chip_txpwr(rtwdev);
907 }
908