| /linux/drivers/clk/actions/ |
| H A D | owl-gate.h | 27 #define OWL_GATE_HW(_reg, _bit_idx, _gate_flags) \ argument
35 _bit_idx, _gate_flags, _flags) \ argument
48 _bit_idx, _gate_flags, _flags) \ argument
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| H A D | owl-pll.h | 41 #define OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \ argument
55 #define OWL_PLL(_struct, _name, _parent, _reg, _bfreq, _bit_idx, \ argument
70 #define OWL_PLL_NO_PARENT(_struct, _name, _reg, _bfreq, _bit_idx, \ argument
84 #define OWL_PLL_NO_PARENT_DELAY(_struct, _name, _reg, _bfreq, _bit_idx, \ argument
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| /linux/drivers/clk/ |
| H A D | clk-stm32h7.c | 598 #define OSC_CLKF(_name, _parent, _gate_offset, _bit_idx, _bit_rdy, _flags)\ argument
608 #define OSC_CLK(_name, _parent, _gate_offset, _bit_idx, _bit_rdy)\ argument
937 #define M_ODF_F(_name, _parent, _gate_offset, _bit_idx, _rate_offset,\ argument
949 #define M_ODF(_name, _parent, _gate_offset, _bit_idx, _rate_offset,\ argument
985 #define PER_CLKF(_gate_offset, _bit_idx, _name, _parent, _flags)\ argument
994 #define PER_CLK(_gate_offset, _bit_idx, _name, _parent)\ argument
1063 #define KER_CLKF(_gate_offset, _bit_idx,\ argument
1076 #define KER_CLK(_gate_offset, _bit_idx, _mux_offset, _mux_shift, _mux_width,\ argument
1081 #define KER_CLKF_NOMUX(_gate_offset, _bit_idx,\ argument
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| /linux/drivers/clk/sophgo/ |
| H A D | clk-sg2042-clkgen.c | 374 _r_enable, _bit_idx) { \ argument
386 _r_enable, _bit_idx) { \ argument
398 _r_enable, _bit_idx) { \ argument
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| H A D | clk-sg2042-rpgate.c | 73 _r_enable, _bit_idx) { \ argument
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| /linux/drivers/clk/keystone/ |
| H A D | syscon-clk.c | 160 #define TI_SYSCON_CLK_GATE(_name, _offset, _bit_idx) \ argument
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| /linux/drivers/clk/stm32/ |
| H A D | clk-stm32mp13.c | 140 #define _CFG_GATE(_id, _offset, _bit_idx, _offset_clr)\ argument
147 #define CFG_GATE(_id, _offset, _bit_idx)\ argument
150 #define CFG_GATE_SETCLR(_id, _offset, _bit_idx)\ argument
471 #define SECF(_sec_id, _offset, _bit_idx)[_sec_id] = {\ argument
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| H A D | clk-stm32mp25.c | 342 #define GATE_CFG(id, _offset, _bit_idx, _offset_clr) \ argument
1829 #define RESET_MP25(id, _offset, _bit_idx, _set_clr) \ argument
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| H A D | clk-stm32mp1.c | 1170 #define GATE(_id, _name, _parent, _flags, _offset, _bit_idx, _gate_flags)\ argument
1261 #define STM32_TIM(_id, _name, _parent, _offset_set, _bit_idx)\ argument
1311 #define GATE_MP1(_id, _name, _parent, _flags, _offset, _bit_idx, _gate_flags)\ argument
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