1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2014-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/printk.h> 26 #include <linux/slab.h> 27 #include <linux/mm_types.h> 28 29 #include "kfd_priv.h" 30 #include "kfd_mqd_manager.h" 31 #include "vi_structs.h" 32 #include "gca/gfx_8_0_sh_mask.h" 33 #include "gca/gfx_8_0_enum.h" 34 #include "oss/oss_3_0_sh_mask.h" 35 36 #define CP_MQD_CONTROL__PRIV_STATE__SHIFT 0x8 37 38 static inline struct vi_mqd *get_mqd(void *mqd) 39 { 40 return (struct vi_mqd *)mqd; 41 } 42 43 static inline struct vi_sdma_mqd *get_sdma_mqd(void *mqd) 44 { 45 return (struct vi_sdma_mqd *)mqd; 46 } 47 48 static void update_cu_mask(struct mqd_manager *mm, void *mqd, 49 struct mqd_update_info *minfo) 50 { 51 struct vi_mqd *m; 52 uint32_t se_mask[4] = {0}; /* 4 is the max # of SEs */ 53 54 if (!minfo || !minfo->cu_mask.ptr) 55 return; 56 57 mqd_symmetrically_map_cu_mask(mm, 58 minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask, 0); 59 60 m = get_mqd(mqd); 61 m->compute_static_thread_mgmt_se0 = se_mask[0]; 62 m->compute_static_thread_mgmt_se1 = se_mask[1]; 63 m->compute_static_thread_mgmt_se2 = se_mask[2]; 64 m->compute_static_thread_mgmt_se3 = se_mask[3]; 65 66 pr_debug("Update cu mask to %#x %#x %#x %#x\n", 67 m->compute_static_thread_mgmt_se0, 68 m->compute_static_thread_mgmt_se1, 69 m->compute_static_thread_mgmt_se2, 70 m->compute_static_thread_mgmt_se3); 71 } 72 73 static void set_priority(struct vi_mqd *m, struct queue_properties *q) 74 { 75 m->cp_hqd_pipe_priority = pipe_priority_map[q->priority]; 76 } 77 78 static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm, 79 struct queue_properties *q) 80 { 81 struct kfd_node *kfd = mm->dev; 82 struct kfd_mem_obj *mqd_mem_obj; 83 84 if (kfd_gtt_sa_allocate(kfd, sizeof(struct vi_mqd), 85 &mqd_mem_obj)) 86 return NULL; 87 88 return mqd_mem_obj; 89 } 90 91 static void init_mqd(struct mqd_manager *mm, void **mqd, 92 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 93 struct queue_properties *q) 94 { 95 uint64_t addr; 96 struct vi_mqd *m; 97 98 m = (struct vi_mqd *) mqd_mem_obj->cpu_ptr; 99 addr = mqd_mem_obj->gpu_addr; 100 101 memset(m, 0, sizeof(struct vi_mqd)); 102 103 m->header = 0xC0310800; 104 m->compute_pipelinestat_enable = 1; 105 m->compute_static_thread_mgmt_se0 = 0xFFFFFFFF; 106 m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF; 107 m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF; 108 m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF; 109 110 m->cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK | 111 0x53 << CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT; 112 113 m->cp_mqd_control = 1 << CP_MQD_CONTROL__PRIV_STATE__SHIFT | 114 MTYPE_UC << CP_MQD_CONTROL__MTYPE__SHIFT; 115 116 m->cp_mqd_base_addr_lo = lower_32_bits(addr); 117 m->cp_mqd_base_addr_hi = upper_32_bits(addr); 118 119 m->cp_hqd_quantum = 1 << CP_HQD_QUANTUM__QUANTUM_EN__SHIFT | 120 1 << CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT | 121 1 << CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT; 122 123 set_priority(m, q); 124 m->cp_hqd_eop_rptr = 1 << CP_HQD_EOP_RPTR__INIT_FETCHER__SHIFT; 125 126 if (q->format == KFD_QUEUE_FORMAT_AQL) 127 m->cp_hqd_iq_rptr = 1; 128 129 if (q->tba_addr) { 130 m->compute_tba_lo = lower_32_bits(q->tba_addr >> 8); 131 m->compute_tba_hi = upper_32_bits(q->tba_addr >> 8); 132 m->compute_tma_lo = lower_32_bits(q->tma_addr >> 8); 133 m->compute_tma_hi = upper_32_bits(q->tma_addr >> 8); 134 m->compute_pgm_rsrc2 |= 135 (1 << COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT); 136 } 137 138 if (mm->dev->kfd->cwsr_enabled && q->ctx_save_restore_area_address) { 139 m->cp_hqd_persistent_state |= 140 (1 << CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT); 141 m->cp_hqd_ctx_save_base_addr_lo = 142 lower_32_bits(q->ctx_save_restore_area_address); 143 m->cp_hqd_ctx_save_base_addr_hi = 144 upper_32_bits(q->ctx_save_restore_area_address); 145 m->cp_hqd_ctx_save_size = q->ctx_save_restore_area_size; 146 m->cp_hqd_cntl_stack_size = q->ctl_stack_size; 147 m->cp_hqd_cntl_stack_offset = q->ctl_stack_size; 148 m->cp_hqd_wg_state_offset = q->ctl_stack_size; 149 } 150 151 mutex_lock(&mm->dev->kfd->profiler_lock); 152 if (mm->dev->kfd->profiler_process != NULL) 153 m->compute_perfcount_enable = 1; 154 mutex_unlock(&mm->dev->kfd->profiler_lock); 155 156 *mqd = m; 157 if (gart_addr) 158 *gart_addr = addr; 159 mm->update_mqd(mm, m, q, NULL); 160 } 161 162 static int load_mqd(struct mqd_manager *mm, void *mqd, 163 uint32_t pipe_id, uint32_t queue_id, 164 struct queue_properties *p, struct mm_struct *mms) 165 { 166 /* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */ 167 uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0); 168 uint32_t wptr_mask = (uint32_t)((p->queue_size / 4) - 1); 169 170 return mm->dev->kfd2kgd->hqd_load(mm->dev->adev, mqd, pipe_id, queue_id, 171 (uint32_t __user *)p->write_ptr, 172 wptr_shift, wptr_mask, mms, 0); 173 } 174 175 static void __update_mqd(struct mqd_manager *mm, void *mqd, 176 struct queue_properties *q, struct mqd_update_info *minfo, 177 unsigned int mtype, unsigned int atc_bit) 178 { 179 struct vi_mqd *m; 180 181 m = get_mqd(mqd); 182 183 m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT | 184 atc_bit << CP_HQD_PQ_CONTROL__PQ_ATC__SHIFT | 185 mtype << CP_HQD_PQ_CONTROL__MTYPE__SHIFT; 186 m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1; 187 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); 188 189 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); 190 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); 191 192 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 193 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 194 m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); 195 m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); 196 197 m->cp_hqd_pq_doorbell_control = 198 q->doorbell_off << 199 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT; 200 pr_debug("cp_hqd_pq_doorbell_control 0x%x\n", 201 m->cp_hqd_pq_doorbell_control); 202 203 m->cp_hqd_eop_control = atc_bit << CP_HQD_EOP_CONTROL__EOP_ATC__SHIFT | 204 mtype << CP_HQD_EOP_CONTROL__MTYPE__SHIFT; 205 206 m->cp_hqd_ib_control = atc_bit << CP_HQD_IB_CONTROL__IB_ATC__SHIFT | 207 3 << CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT | 208 mtype << CP_HQD_IB_CONTROL__MTYPE__SHIFT; 209 210 /* 211 * The lowest 6 bits of eop_control store the EOP ring size. If 212 * their value is X, the ring size is 2^(X + 1) dwords, or 213 * 2^(X + 3) bytes. 214 * HW does not clamp this field correctly. Maximum EOP queue size 215 * is constrained by per-SE EOP done signal count, which is 8-bit. 216 * Limit is 0xFF EOP entries (= 0x7F8 dwords). CP will not submit 217 * more than (EOP entry count - 1) so a queue size of 0x800 dwords 218 * is safe, giving a maximum field value of 0xA. 219 */ 220 m->cp_hqd_eop_control |= q->eop_ring_buffer_size ? min(0xA, 221 order_base_2(q->eop_ring_buffer_size / 8)) : 0; 222 m->cp_hqd_eop_base_addr_lo = 223 lower_32_bits(q->eop_ring_buffer_address >> 8); 224 m->cp_hqd_eop_base_addr_hi = 225 upper_32_bits(q->eop_ring_buffer_address >> 8); 226 227 m->cp_hqd_iq_timer = atc_bit << CP_HQD_IQ_TIMER__IQ_ATC__SHIFT | 228 mtype << CP_HQD_IQ_TIMER__MTYPE__SHIFT; 229 230 m->cp_hqd_vmid = q->vmid; 231 232 if (q->format == KFD_QUEUE_FORMAT_AQL) { 233 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | 234 2 << CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT; 235 } 236 237 if (mm->dev->kfd->cwsr_enabled && q->ctx_save_restore_area_address) 238 m->cp_hqd_ctx_save_control = 239 atc_bit << CP_HQD_CTX_SAVE_CONTROL__ATC__SHIFT | 240 mtype << CP_HQD_CTX_SAVE_CONTROL__MTYPE__SHIFT; 241 if (minfo) { 242 if (minfo->update_flag == UPDATE_FLAG_PERFCOUNT_ENABLE) 243 m->compute_perfcount_enable = 1; 244 else if (minfo->update_flag == UPDATE_FLAG_PERFCOUNT_DISABLE) 245 m->compute_perfcount_enable = 0; 246 } 247 248 update_cu_mask(mm, mqd, minfo); 249 set_priority(m, q); 250 251 q->is_active = QUEUE_IS_ACTIVE(*q); 252 } 253 254 static bool check_preemption_failed(struct mqd_manager *mm, void *mqd) 255 { 256 struct vi_mqd *m = (struct vi_mqd *)mqd; 257 258 return kfd_check_hiq_mqd_doorbell_id(mm->dev, m->queue_doorbell_id0, 0); 259 } 260 261 static void update_mqd(struct mqd_manager *mm, void *mqd, 262 struct queue_properties *q, 263 struct mqd_update_info *minfo) 264 { 265 __update_mqd(mm, mqd, q, minfo, MTYPE_UC, 0); 266 } 267 268 static int get_wave_state(struct mqd_manager *mm, void *mqd, 269 struct queue_properties *q, 270 void __user *ctl_stack, 271 u32 *ctl_stack_used_size, 272 u32 *save_area_used_size) 273 { 274 struct vi_mqd *m; 275 276 m = get_mqd(mqd); 277 278 *ctl_stack_used_size = m->cp_hqd_cntl_stack_size - 279 m->cp_hqd_cntl_stack_offset; 280 *save_area_used_size = m->cp_hqd_wg_state_offset - 281 m->cp_hqd_cntl_stack_size; 282 283 /* Control stack is not copied to user mode for GFXv8 because 284 * it's part of the context save area that is already 285 * accessible to user mode 286 */ 287 288 return 0; 289 } 290 291 static int get_checkpoint_info(struct mqd_manager *mm, void *mqd, u32 *ctl_stack_size) 292 { 293 /* Control stack is stored in user mode */ 294 *ctl_stack_size = 0; 295 return 0; 296 } 297 298 static void checkpoint_mqd(struct mqd_manager *mm, void *mqd, void *mqd_dst, void *ctl_stack_dst) 299 { 300 struct vi_mqd *m; 301 302 m = get_mqd(mqd); 303 304 memcpy(mqd_dst, m, sizeof(struct vi_mqd)); 305 } 306 307 static void restore_mqd(struct mqd_manager *mm, void **mqd, 308 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 309 struct queue_properties *qp, 310 const void *mqd_src, 311 const void *ctl_stack_src, const u32 ctl_stack_size) 312 { 313 uint64_t addr; 314 struct vi_mqd *m; 315 316 m = (struct vi_mqd *) mqd_mem_obj->cpu_ptr; 317 addr = mqd_mem_obj->gpu_addr; 318 319 memcpy(m, mqd_src, sizeof(*m)); 320 321 *mqd = m; 322 if (gart_addr) 323 *gart_addr = addr; 324 325 m->cp_hqd_pq_doorbell_control = 326 qp->doorbell_off << 327 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT; 328 pr_debug("cp_hqd_pq_doorbell_control 0x%x\n", 329 m->cp_hqd_pq_doorbell_control); 330 331 qp->is_active = 0; 332 } 333 334 static void init_mqd_hiq(struct mqd_manager *mm, void **mqd, 335 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 336 struct queue_properties *q) 337 { 338 struct vi_mqd *m; 339 340 init_mqd(mm, mqd, mqd_mem_obj, gart_addr, q); 341 342 m = get_mqd(*mqd); 343 344 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | 345 1 << CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT; 346 } 347 348 static void update_mqd_hiq(struct mqd_manager *mm, void *mqd, 349 struct queue_properties *q, 350 struct mqd_update_info *minfo) 351 { 352 __update_mqd(mm, mqd, q, minfo, MTYPE_UC, 0); 353 } 354 355 static void init_mqd_sdma(struct mqd_manager *mm, void **mqd, 356 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 357 struct queue_properties *q) 358 { 359 struct vi_sdma_mqd *m; 360 361 m = (struct vi_sdma_mqd *) mqd_mem_obj->cpu_ptr; 362 363 memset(m, 0, sizeof(struct vi_sdma_mqd)); 364 365 *mqd = m; 366 if (gart_addr) 367 *gart_addr = mqd_mem_obj->gpu_addr; 368 369 mm->update_mqd(mm, m, q, NULL); 370 } 371 372 static void update_mqd_sdma(struct mqd_manager *mm, void *mqd, 373 struct queue_properties *q, 374 struct mqd_update_info *minfo) 375 { 376 struct vi_sdma_mqd *m; 377 378 m = get_sdma_mqd(mqd); 379 m->sdmax_rlcx_rb_cntl = order_base_2(q->queue_size / 4) 380 << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT | 381 q->vmid << SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT | 382 1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT | 383 6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT; 384 385 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8); 386 m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8); 387 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 388 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 389 m->sdmax_rlcx_doorbell = 390 q->doorbell_off << SDMA0_RLC0_DOORBELL__OFFSET__SHIFT; 391 392 m->sdmax_rlcx_virtual_addr = q->sdma_vm_addr; 393 394 m->sdma_engine_id = q->sdma_engine_id; 395 m->sdma_queue_id = q->sdma_queue_id; 396 397 q->is_active = QUEUE_IS_ACTIVE(*q); 398 } 399 400 static void checkpoint_mqd_sdma(struct mqd_manager *mm, 401 void *mqd, 402 void *mqd_dst, 403 void *ctl_stack_dst) 404 { 405 struct vi_sdma_mqd *m; 406 407 m = get_sdma_mqd(mqd); 408 409 memcpy(mqd_dst, m, sizeof(struct vi_sdma_mqd)); 410 } 411 412 static void restore_mqd_sdma(struct mqd_manager *mm, void **mqd, 413 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 414 struct queue_properties *qp, 415 const void *mqd_src, 416 const void *ctl_stack_src, const u32 ctl_stack_size) 417 { 418 uint64_t addr; 419 struct vi_sdma_mqd *m; 420 421 m = (struct vi_sdma_mqd *) mqd_mem_obj->cpu_ptr; 422 addr = mqd_mem_obj->gpu_addr; 423 424 memcpy(m, mqd_src, sizeof(*m)); 425 426 m->sdmax_rlcx_doorbell = 427 qp->doorbell_off << SDMA0_RLC0_DOORBELL__OFFSET__SHIFT; 428 429 *mqd = m; 430 if (gart_addr) 431 *gart_addr = addr; 432 433 qp->is_active = 0; 434 } 435 436 #if defined(CONFIG_DEBUG_FS) 437 438 439 static int debugfs_show_mqd(struct seq_file *m, void *data) 440 { 441 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, 442 data, sizeof(struct vi_mqd), false); 443 return 0; 444 } 445 446 static int debugfs_show_mqd_sdma(struct seq_file *m, void *data) 447 { 448 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, 449 data, sizeof(struct vi_sdma_mqd), false); 450 return 0; 451 } 452 453 #endif 454 455 struct mqd_manager *mqd_manager_init_vi(enum KFD_MQD_TYPE type, 456 struct kfd_node *dev) 457 { 458 struct mqd_manager *mqd; 459 460 if (WARN_ON(type >= KFD_MQD_TYPE_MAX)) 461 return NULL; 462 463 mqd = kzalloc_obj(*mqd); 464 if (!mqd) 465 return NULL; 466 467 mqd->dev = dev; 468 469 switch (type) { 470 case KFD_MQD_TYPE_CP: 471 mqd->allocate_mqd = allocate_mqd; 472 mqd->init_mqd = init_mqd; 473 mqd->free_mqd = kfd_free_mqd_cp; 474 mqd->load_mqd = load_mqd; 475 mqd->update_mqd = update_mqd; 476 mqd->destroy_mqd = kfd_destroy_mqd_cp; 477 mqd->is_occupied = kfd_is_occupied_cp; 478 mqd->get_wave_state = get_wave_state; 479 mqd->get_checkpoint_info = get_checkpoint_info; 480 mqd->checkpoint_mqd = checkpoint_mqd; 481 mqd->restore_mqd = restore_mqd; 482 mqd->mqd_size = sizeof(struct vi_mqd); 483 #if defined(CONFIG_DEBUG_FS) 484 mqd->debugfs_show_mqd = debugfs_show_mqd; 485 #endif 486 break; 487 case KFD_MQD_TYPE_HIQ: 488 mqd->allocate_mqd = allocate_hiq_mqd; 489 mqd->init_mqd = init_mqd_hiq; 490 mqd->free_mqd = free_mqd_hiq_sdma; 491 mqd->load_mqd = load_mqd; 492 mqd->update_mqd = update_mqd_hiq; 493 mqd->destroy_mqd = kfd_destroy_mqd_cp; 494 mqd->is_occupied = kfd_is_occupied_cp; 495 mqd->mqd_size = sizeof(struct vi_mqd); 496 mqd->mqd_stride = kfd_mqd_stride; 497 #if defined(CONFIG_DEBUG_FS) 498 mqd->debugfs_show_mqd = debugfs_show_mqd; 499 #endif 500 mqd->check_preemption_failed = check_preemption_failed; 501 break; 502 case KFD_MQD_TYPE_DIQ: 503 mqd->allocate_mqd = allocate_mqd; 504 mqd->init_mqd = init_mqd_hiq; 505 mqd->free_mqd = kfd_free_mqd_cp; 506 mqd->load_mqd = load_mqd; 507 mqd->update_mqd = update_mqd_hiq; 508 mqd->destroy_mqd = kfd_destroy_mqd_cp; 509 mqd->is_occupied = kfd_is_occupied_cp; 510 mqd->mqd_size = sizeof(struct vi_mqd); 511 mqd->mqd_stride = kfd_mqd_stride; 512 #if defined(CONFIG_DEBUG_FS) 513 mqd->debugfs_show_mqd = debugfs_show_mqd; 514 #endif 515 break; 516 case KFD_MQD_TYPE_SDMA: 517 mqd->allocate_mqd = allocate_sdma_mqd; 518 mqd->init_mqd = init_mqd_sdma; 519 mqd->free_mqd = free_mqd_hiq_sdma; 520 mqd->load_mqd = kfd_load_mqd_sdma; 521 mqd->update_mqd = update_mqd_sdma; 522 mqd->destroy_mqd = kfd_destroy_mqd_sdma; 523 mqd->is_occupied = kfd_is_occupied_sdma; 524 mqd->checkpoint_mqd = checkpoint_mqd_sdma; 525 mqd->restore_mqd = restore_mqd_sdma; 526 mqd->mqd_size = sizeof(struct vi_sdma_mqd); 527 mqd->mqd_stride = kfd_mqd_stride; 528 #if defined(CONFIG_DEBUG_FS) 529 mqd->debugfs_show_mqd = debugfs_show_mqd_sdma; 530 #endif 531 break; 532 default: 533 kfree(mqd); 534 return NULL; 535 } 536 537 return mqd; 538 } 539