1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2012-2015 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 */
6
7 #ifndef __ARM64_KVM_HYP_SYSREG_SR_H__
8 #define __ARM64_KVM_HYP_SYSREG_SR_H__
9
10 #include <linux/compiler.h>
11 #include <linux/kvm_host.h>
12
13 #include <asm/kprobes.h>
14 #include <asm/kvm_asm.h>
15 #include <asm/kvm_emulate.h>
16 #include <asm/kvm_hyp.h>
17 #include <asm/kvm_mmu.h>
18
19 static inline bool ctxt_has_s1poe(struct kvm_cpu_context *ctxt);
20
ctxt_to_vcpu(struct kvm_cpu_context * ctxt)21 static inline struct kvm_vcpu *ctxt_to_vcpu(struct kvm_cpu_context *ctxt)
22 {
23 struct kvm_vcpu *vcpu = ctxt->__hyp_running_vcpu;
24
25 if (!vcpu)
26 vcpu = container_of(ctxt, struct kvm_vcpu, arch.ctxt);
27
28 return vcpu;
29 }
30
ctxt_is_guest(struct kvm_cpu_context * ctxt)31 static inline bool ctxt_is_guest(struct kvm_cpu_context *ctxt)
32 {
33 return host_data_ptr(host_ctxt) != ctxt;
34 }
35
ctxt_mdscr_el1(struct kvm_cpu_context * ctxt)36 static inline u64 *ctxt_mdscr_el1(struct kvm_cpu_context *ctxt)
37 {
38 struct kvm_vcpu *vcpu = ctxt_to_vcpu(ctxt);
39
40 if (ctxt_is_guest(ctxt) && kvm_host_owns_debug_regs(vcpu))
41 return &vcpu->arch.external_mdscr_el1;
42
43 return &ctxt_sys_reg(ctxt, MDSCR_EL1);
44 }
45
ctxt_midr_el1(struct kvm_cpu_context * ctxt)46 static inline u64 ctxt_midr_el1(struct kvm_cpu_context *ctxt)
47 {
48 struct kvm *kvm = kern_hyp_va(ctxt_to_vcpu(ctxt)->kvm);
49
50 if (!(ctxt_is_guest(ctxt) &&
51 test_bit(KVM_ARCH_FLAG_WRITABLE_IMP_ID_REGS, &kvm->arch.flags)))
52 return read_cpuid_id();
53
54 return kvm_read_vm_id_reg(kvm, SYS_MIDR_EL1);
55 }
56
__sysreg_save_common_state(struct kvm_cpu_context * ctxt)57 static inline void __sysreg_save_common_state(struct kvm_cpu_context *ctxt)
58 {
59 *ctxt_mdscr_el1(ctxt) = read_sysreg(mdscr_el1);
60
61 // POR_EL0 can affect uaccess, so must be saved/restored early.
62 if (ctxt_has_s1poe(ctxt))
63 ctxt_sys_reg(ctxt, POR_EL0) = read_sysreg_s(SYS_POR_EL0);
64 }
65
__sysreg_save_user_state(struct kvm_cpu_context * ctxt)66 static inline void __sysreg_save_user_state(struct kvm_cpu_context *ctxt)
67 {
68 ctxt_sys_reg(ctxt, TPIDR_EL0) = read_sysreg(tpidr_el0);
69 ctxt_sys_reg(ctxt, TPIDRRO_EL0) = read_sysreg(tpidrro_el0);
70 }
71
ctxt_has_mte(struct kvm_cpu_context * ctxt)72 static inline bool ctxt_has_mte(struct kvm_cpu_context *ctxt)
73 {
74 struct kvm_vcpu *vcpu = ctxt_to_vcpu(ctxt);
75
76 return kvm_has_mte(kern_hyp_va(vcpu->kvm));
77 }
78
ctxt_has_s1pie(struct kvm_cpu_context * ctxt)79 static inline bool ctxt_has_s1pie(struct kvm_cpu_context *ctxt)
80 {
81 struct kvm_vcpu *vcpu;
82
83 if (!cpus_have_final_cap(ARM64_HAS_S1PIE))
84 return false;
85
86 vcpu = ctxt_to_vcpu(ctxt);
87 return kvm_has_s1pie(kern_hyp_va(vcpu->kvm));
88 }
89
ctxt_has_tcrx(struct kvm_cpu_context * ctxt)90 static inline bool ctxt_has_tcrx(struct kvm_cpu_context *ctxt)
91 {
92 struct kvm_vcpu *vcpu;
93
94 if (!cpus_have_final_cap(ARM64_HAS_TCR2))
95 return false;
96
97 vcpu = ctxt_to_vcpu(ctxt);
98 return kvm_has_tcr2(kern_hyp_va(vcpu->kvm));
99 }
100
ctxt_has_s1poe(struct kvm_cpu_context * ctxt)101 static inline bool ctxt_has_s1poe(struct kvm_cpu_context *ctxt)
102 {
103 struct kvm_vcpu *vcpu;
104
105 if (!system_supports_poe())
106 return false;
107
108 vcpu = ctxt_to_vcpu(ctxt);
109 return kvm_has_s1poe(kern_hyp_va(vcpu->kvm));
110 }
111
__sysreg_save_el1_state(struct kvm_cpu_context * ctxt)112 static inline void __sysreg_save_el1_state(struct kvm_cpu_context *ctxt)
113 {
114 ctxt_sys_reg(ctxt, SCTLR_EL1) = read_sysreg_el1(SYS_SCTLR);
115 ctxt_sys_reg(ctxt, CPACR_EL1) = read_sysreg_el1(SYS_CPACR);
116 ctxt_sys_reg(ctxt, TTBR0_EL1) = read_sysreg_el1(SYS_TTBR0);
117 ctxt_sys_reg(ctxt, TTBR1_EL1) = read_sysreg_el1(SYS_TTBR1);
118 ctxt_sys_reg(ctxt, TCR_EL1) = read_sysreg_el1(SYS_TCR);
119 if (ctxt_has_tcrx(ctxt)) {
120 ctxt_sys_reg(ctxt, TCR2_EL1) = read_sysreg_el1(SYS_TCR2);
121
122 if (ctxt_has_s1pie(ctxt)) {
123 ctxt_sys_reg(ctxt, PIR_EL1) = read_sysreg_el1(SYS_PIR);
124 ctxt_sys_reg(ctxt, PIRE0_EL1) = read_sysreg_el1(SYS_PIRE0);
125 }
126
127 if (ctxt_has_s1poe(ctxt))
128 ctxt_sys_reg(ctxt, POR_EL1) = read_sysreg_el1(SYS_POR);
129 }
130 ctxt_sys_reg(ctxt, ESR_EL1) = read_sysreg_el1(SYS_ESR);
131 ctxt_sys_reg(ctxt, AFSR0_EL1) = read_sysreg_el1(SYS_AFSR0);
132 ctxt_sys_reg(ctxt, AFSR1_EL1) = read_sysreg_el1(SYS_AFSR1);
133 ctxt_sys_reg(ctxt, FAR_EL1) = read_sysreg_el1(SYS_FAR);
134 ctxt_sys_reg(ctxt, MAIR_EL1) = read_sysreg_el1(SYS_MAIR);
135 ctxt_sys_reg(ctxt, VBAR_EL1) = read_sysreg_el1(SYS_VBAR);
136 ctxt_sys_reg(ctxt, CONTEXTIDR_EL1) = read_sysreg_el1(SYS_CONTEXTIDR);
137 ctxt_sys_reg(ctxt, AMAIR_EL1) = read_sysreg_el1(SYS_AMAIR);
138 ctxt_sys_reg(ctxt, CNTKCTL_EL1) = read_sysreg_el1(SYS_CNTKCTL);
139 ctxt_sys_reg(ctxt, PAR_EL1) = read_sysreg_par();
140 ctxt_sys_reg(ctxt, TPIDR_EL1) = read_sysreg(tpidr_el1);
141
142 if (ctxt_has_mte(ctxt)) {
143 ctxt_sys_reg(ctxt, TFSR_EL1) = read_sysreg_el1(SYS_TFSR);
144 ctxt_sys_reg(ctxt, TFSRE0_EL1) = read_sysreg_s(SYS_TFSRE0_EL1);
145 }
146
147 ctxt_sys_reg(ctxt, SP_EL1) = read_sysreg(sp_el1);
148 ctxt_sys_reg(ctxt, ELR_EL1) = read_sysreg_el1(SYS_ELR);
149 ctxt_sys_reg(ctxt, SPSR_EL1) = read_sysreg_el1(SYS_SPSR);
150 }
151
__sysreg_save_el2_return_state(struct kvm_cpu_context * ctxt)152 static inline void __sysreg_save_el2_return_state(struct kvm_cpu_context *ctxt)
153 {
154 ctxt->regs.pc = read_sysreg_el2(SYS_ELR);
155 /*
156 * Guest PSTATE gets saved at guest fixup time in all
157 * cases. We still need to handle the nVHE host side here.
158 */
159 if (!has_vhe() && ctxt->__hyp_running_vcpu)
160 ctxt->regs.pstate = read_sysreg_el2(SYS_SPSR);
161
162 if (cpus_have_final_cap(ARM64_HAS_RAS_EXTN))
163 ctxt_sys_reg(ctxt, DISR_EL1) = read_sysreg_s(SYS_VDISR_EL2);
164 }
165
__sysreg_restore_common_state(struct kvm_cpu_context * ctxt)166 static inline void __sysreg_restore_common_state(struct kvm_cpu_context *ctxt)
167 {
168 write_sysreg(*ctxt_mdscr_el1(ctxt), mdscr_el1);
169
170 // POR_EL0 can affect uaccess, so must be saved/restored early.
171 if (ctxt_has_s1poe(ctxt))
172 write_sysreg_s(ctxt_sys_reg(ctxt, POR_EL0), SYS_POR_EL0);
173 }
174
__sysreg_restore_user_state(struct kvm_cpu_context * ctxt)175 static inline void __sysreg_restore_user_state(struct kvm_cpu_context *ctxt)
176 {
177 write_sysreg(ctxt_sys_reg(ctxt, TPIDR_EL0), tpidr_el0);
178 write_sysreg(ctxt_sys_reg(ctxt, TPIDRRO_EL0), tpidrro_el0);
179 }
180
__sysreg_restore_el1_state(struct kvm_cpu_context * ctxt,u64 midr,u64 mpidr)181 static inline void __sysreg_restore_el1_state(struct kvm_cpu_context *ctxt,
182 u64 midr, u64 mpidr)
183 {
184 write_sysreg(midr, vpidr_el2);
185 write_sysreg(mpidr, vmpidr_el2);
186
187 if (has_vhe() ||
188 !cpus_have_final_cap(ARM64_WORKAROUND_SPECULATIVE_AT)) {
189 write_sysreg_el1(ctxt_sys_reg(ctxt, SCTLR_EL1), SYS_SCTLR);
190 write_sysreg_el1(ctxt_sys_reg(ctxt, TCR_EL1), SYS_TCR);
191 } else if (!ctxt->__hyp_running_vcpu) {
192 /*
193 * Must only be done for guest registers, hence the context
194 * test. We're coming from the host, so SCTLR.M is already
195 * set. Pairs with nVHE's __activate_traps().
196 */
197 write_sysreg_el1((ctxt_sys_reg(ctxt, TCR_EL1) |
198 TCR_EPD1_MASK | TCR_EPD0_MASK),
199 SYS_TCR);
200 isb();
201 }
202
203 write_sysreg_el1(ctxt_sys_reg(ctxt, CPACR_EL1), SYS_CPACR);
204 write_sysreg_el1(ctxt_sys_reg(ctxt, TTBR0_EL1), SYS_TTBR0);
205 write_sysreg_el1(ctxt_sys_reg(ctxt, TTBR1_EL1), SYS_TTBR1);
206 if (ctxt_has_tcrx(ctxt)) {
207 write_sysreg_el1(ctxt_sys_reg(ctxt, TCR2_EL1), SYS_TCR2);
208
209 if (ctxt_has_s1pie(ctxt)) {
210 write_sysreg_el1(ctxt_sys_reg(ctxt, PIR_EL1), SYS_PIR);
211 write_sysreg_el1(ctxt_sys_reg(ctxt, PIRE0_EL1), SYS_PIRE0);
212 }
213
214 if (ctxt_has_s1poe(ctxt))
215 write_sysreg_el1(ctxt_sys_reg(ctxt, POR_EL1), SYS_POR);
216 }
217 write_sysreg_el1(ctxt_sys_reg(ctxt, ESR_EL1), SYS_ESR);
218 write_sysreg_el1(ctxt_sys_reg(ctxt, AFSR0_EL1), SYS_AFSR0);
219 write_sysreg_el1(ctxt_sys_reg(ctxt, AFSR1_EL1), SYS_AFSR1);
220 write_sysreg_el1(ctxt_sys_reg(ctxt, FAR_EL1), SYS_FAR);
221 write_sysreg_el1(ctxt_sys_reg(ctxt, MAIR_EL1), SYS_MAIR);
222 write_sysreg_el1(ctxt_sys_reg(ctxt, VBAR_EL1), SYS_VBAR);
223 write_sysreg_el1(ctxt_sys_reg(ctxt, CONTEXTIDR_EL1), SYS_CONTEXTIDR);
224 write_sysreg_el1(ctxt_sys_reg(ctxt, AMAIR_EL1), SYS_AMAIR);
225 write_sysreg_el1(ctxt_sys_reg(ctxt, CNTKCTL_EL1), SYS_CNTKCTL);
226 write_sysreg(ctxt_sys_reg(ctxt, PAR_EL1), par_el1);
227 write_sysreg(ctxt_sys_reg(ctxt, TPIDR_EL1), tpidr_el1);
228
229 if (ctxt_has_mte(ctxt)) {
230 write_sysreg_el1(ctxt_sys_reg(ctxt, TFSR_EL1), SYS_TFSR);
231 write_sysreg_s(ctxt_sys_reg(ctxt, TFSRE0_EL1), SYS_TFSRE0_EL1);
232 }
233
234 if (!has_vhe() &&
235 cpus_have_final_cap(ARM64_WORKAROUND_SPECULATIVE_AT) &&
236 ctxt->__hyp_running_vcpu) {
237 /*
238 * Must only be done for host registers, hence the context
239 * test. Pairs with nVHE's __deactivate_traps().
240 */
241 isb();
242 /*
243 * At this stage, and thanks to the above isb(), S2 is
244 * deconfigured and disabled. We can now restore the host's
245 * S1 configuration: SCTLR, and only then TCR.
246 */
247 write_sysreg_el1(ctxt_sys_reg(ctxt, SCTLR_EL1), SYS_SCTLR);
248 isb();
249 write_sysreg_el1(ctxt_sys_reg(ctxt, TCR_EL1), SYS_TCR);
250 }
251
252 write_sysreg(ctxt_sys_reg(ctxt, SP_EL1), sp_el1);
253 write_sysreg_el1(ctxt_sys_reg(ctxt, ELR_EL1), SYS_ELR);
254 write_sysreg_el1(ctxt_sys_reg(ctxt, SPSR_EL1), SYS_SPSR);
255 }
256
257 /* Read the VCPU state's PSTATE, but translate (v)EL2 to EL1. */
to_hw_pstate(const struct kvm_cpu_context * ctxt)258 static inline u64 to_hw_pstate(const struct kvm_cpu_context *ctxt)
259 {
260 u64 mode = ctxt->regs.pstate & (PSR_MODE_MASK | PSR_MODE32_BIT);
261
262 switch (mode) {
263 case PSR_MODE_EL2t:
264 mode = PSR_MODE_EL1t;
265 break;
266 case PSR_MODE_EL2h:
267 mode = PSR_MODE_EL1h;
268 break;
269 }
270
271 return (ctxt->regs.pstate & ~(PSR_MODE_MASK | PSR_MODE32_BIT)) | mode;
272 }
273
__sysreg_restore_el2_return_state(struct kvm_cpu_context * ctxt)274 static inline void __sysreg_restore_el2_return_state(struct kvm_cpu_context *ctxt)
275 {
276 u64 pstate = to_hw_pstate(ctxt);
277 u64 mode = pstate & PSR_AA32_MODE_MASK;
278
279 /*
280 * Safety check to ensure we're setting the CPU up to enter the guest
281 * in a less privileged mode.
282 *
283 * If we are attempting a return to EL2 or higher in AArch64 state,
284 * program SPSR_EL2 with M=EL2h and the IL bit set which ensures that
285 * we'll take an illegal exception state exception immediately after
286 * the ERET to the guest. Attempts to return to AArch32 Hyp will
287 * result in an illegal exception return because EL2's execution state
288 * is determined by SCR_EL3.RW.
289 */
290 if (!(mode & PSR_MODE32_BIT) && mode >= PSR_MODE_EL2t)
291 pstate = PSR_MODE_EL2h | PSR_IL_BIT;
292
293 write_sysreg_el2(ctxt->regs.pc, SYS_ELR);
294 write_sysreg_el2(pstate, SYS_SPSR);
295
296 if (cpus_have_final_cap(ARM64_HAS_RAS_EXTN))
297 write_sysreg_s(ctxt_sys_reg(ctxt, DISR_EL1), SYS_VDISR_EL2);
298 }
299
__sysreg32_save_state(struct kvm_vcpu * vcpu)300 static inline void __sysreg32_save_state(struct kvm_vcpu *vcpu)
301 {
302 if (!vcpu_el1_is_32bit(vcpu))
303 return;
304
305 vcpu->arch.ctxt.spsr_abt = read_sysreg(spsr_abt);
306 vcpu->arch.ctxt.spsr_und = read_sysreg(spsr_und);
307 vcpu->arch.ctxt.spsr_irq = read_sysreg(spsr_irq);
308 vcpu->arch.ctxt.spsr_fiq = read_sysreg(spsr_fiq);
309
310 __vcpu_assign_sys_reg(vcpu, DACR32_EL2, read_sysreg(dacr32_el2));
311 __vcpu_assign_sys_reg(vcpu, IFSR32_EL2, read_sysreg(ifsr32_el2));
312
313 if (has_vhe() || kvm_debug_regs_in_use(vcpu))
314 __vcpu_assign_sys_reg(vcpu, DBGVCR32_EL2, read_sysreg(dbgvcr32_el2));
315 }
316
__sysreg32_restore_state(struct kvm_vcpu * vcpu)317 static inline void __sysreg32_restore_state(struct kvm_vcpu *vcpu)
318 {
319 if (!vcpu_el1_is_32bit(vcpu))
320 return;
321
322 write_sysreg(vcpu->arch.ctxt.spsr_abt, spsr_abt);
323 write_sysreg(vcpu->arch.ctxt.spsr_und, spsr_und);
324 write_sysreg(vcpu->arch.ctxt.spsr_irq, spsr_irq);
325 write_sysreg(vcpu->arch.ctxt.spsr_fiq, spsr_fiq);
326
327 write_sysreg(__vcpu_sys_reg(vcpu, DACR32_EL2), dacr32_el2);
328 write_sysreg(__vcpu_sys_reg(vcpu, IFSR32_EL2), ifsr32_el2);
329
330 if (has_vhe() || kvm_debug_regs_in_use(vcpu))
331 write_sysreg(__vcpu_sys_reg(vcpu, DBGVCR32_EL2), dbgvcr32_el2);
332 }
333
334 #endif /* __ARM64_KVM_HYP_SYSREG_SR_H__ */
335