1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Resource Director Technology(RDT)
4 * - Cache Allocation code.
5 *
6 * Copyright (C) 2016 Intel Corporation
7 *
8 * Authors:
9 * Fenghua Yu <fenghua.yu@intel.com>
10 * Tony Luck <tony.luck@intel.com>
11 * Vikas Shivappa <vikas.shivappa@intel.com>
12 *
13 * More information about RDT be found in the Intel (R) x86 Architecture
14 * Software Developer Manual June 2016, volume 3, section 17.17.
15 */
16
17 #define pr_fmt(fmt) "resctrl: " fmt
18
19 #include <linux/cpu.h>
20 #include <linux/slab.h>
21 #include <linux/err.h>
22 #include <linux/cpuhotplug.h>
23
24 #include <asm/cpu_device_id.h>
25 #include <asm/msr.h>
26 #include <asm/resctrl.h>
27 #include "internal.h"
28
29 /*
30 * rdt_domain structures are kfree()d when their last CPU goes offline,
31 * and allocated when the first CPU in a new domain comes online.
32 * The rdt_resource's domain list is updated when this happens. Readers of
33 * the domain list must either take cpus_read_lock(), or rely on an RCU
34 * read-side critical section, to avoid observing concurrent modification.
35 * All writers take this mutex:
36 */
37 static DEFINE_MUTEX(domain_list_lock);
38
39 /*
40 * The cached resctrl_pqr_state is strictly per CPU and can never be
41 * updated from a remote CPU. Functions which modify the state
42 * are called with interrupts disabled and no preemption, which
43 * is sufficient for the protection.
44 */
45 DEFINE_PER_CPU(struct resctrl_pqr_state, pqr_state);
46
47 /*
48 * Global boolean for rdt_alloc which is true if any
49 * resource allocation is enabled.
50 */
51 bool rdt_alloc_capable;
52
53 static void mba_wrmsr_intel(struct msr_param *m);
54 static void cat_wrmsr(struct msr_param *m);
55 static void mba_wrmsr_amd(struct msr_param *m);
56
57 #define ctrl_domain_init(id) LIST_HEAD_INIT(rdt_resources_all[id].r_resctrl.ctrl_domains)
58 #define mon_domain_init(id) LIST_HEAD_INIT(rdt_resources_all[id].r_resctrl.mon_domains)
59
60 struct rdt_hw_resource rdt_resources_all[RDT_NUM_RESOURCES] = {
61 [RDT_RESOURCE_L3] =
62 {
63 .r_resctrl = {
64 .name = "L3",
65 .ctrl_scope = RESCTRL_L3_CACHE,
66 .mon_scope = RESCTRL_L3_CACHE,
67 .ctrl_domains = ctrl_domain_init(RDT_RESOURCE_L3),
68 .mon_domains = mon_domain_init(RDT_RESOURCE_L3),
69 .schema_fmt = RESCTRL_SCHEMA_BITMAP,
70 },
71 .msr_base = MSR_IA32_L3_CBM_BASE,
72 .msr_update = cat_wrmsr,
73 },
74 [RDT_RESOURCE_L2] =
75 {
76 .r_resctrl = {
77 .name = "L2",
78 .ctrl_scope = RESCTRL_L2_CACHE,
79 .ctrl_domains = ctrl_domain_init(RDT_RESOURCE_L2),
80 .schema_fmt = RESCTRL_SCHEMA_BITMAP,
81 },
82 .msr_base = MSR_IA32_L2_CBM_BASE,
83 .msr_update = cat_wrmsr,
84 },
85 [RDT_RESOURCE_MBA] =
86 {
87 .r_resctrl = {
88 .name = "MB",
89 .ctrl_scope = RESCTRL_L3_CACHE,
90 .ctrl_domains = ctrl_domain_init(RDT_RESOURCE_MBA),
91 .schema_fmt = RESCTRL_SCHEMA_RANGE,
92 },
93 },
94 [RDT_RESOURCE_SMBA] =
95 {
96 .r_resctrl = {
97 .name = "SMBA",
98 .ctrl_scope = RESCTRL_L3_CACHE,
99 .ctrl_domains = ctrl_domain_init(RDT_RESOURCE_SMBA),
100 .schema_fmt = RESCTRL_SCHEMA_RANGE,
101 },
102 },
103 };
104
resctrl_arch_system_num_rmid_idx(void)105 u32 resctrl_arch_system_num_rmid_idx(void)
106 {
107 struct rdt_resource *r = &rdt_resources_all[RDT_RESOURCE_L3].r_resctrl;
108
109 /* RMID are independent numbers for x86. num_rmid_idx == num_rmid */
110 return r->mon.num_rmid;
111 }
112
resctrl_arch_get_resource(enum resctrl_res_level l)113 struct rdt_resource *resctrl_arch_get_resource(enum resctrl_res_level l)
114 {
115 if (l >= RDT_NUM_RESOURCES)
116 return NULL;
117
118 return &rdt_resources_all[l].r_resctrl;
119 }
120
121 /*
122 * cache_alloc_hsw_probe() - Have to probe for Intel haswell server CPUs
123 * as they do not have CPUID enumeration support for Cache allocation.
124 * The check for Vendor/Family/Model is not enough to guarantee that
125 * the MSRs won't #GP fault because only the following SKUs support
126 * CAT:
127 * Intel(R) Xeon(R) CPU E5-2658 v3 @ 2.20GHz
128 * Intel(R) Xeon(R) CPU E5-2648L v3 @ 1.80GHz
129 * Intel(R) Xeon(R) CPU E5-2628L v3 @ 2.00GHz
130 * Intel(R) Xeon(R) CPU E5-2618L v3 @ 2.30GHz
131 * Intel(R) Xeon(R) CPU E5-2608L v3 @ 2.00GHz
132 * Intel(R) Xeon(R) CPU E5-2658A v3 @ 2.20GHz
133 *
134 * Probe by trying to write the first of the L3 cache mask registers
135 * and checking that the bits stick. Max CLOSids is always 4 and max cbm length
136 * is always 20 on hsw server parts. The minimum cache bitmask length
137 * allowed for HSW server is always 2 bits. Hardcode all of them.
138 */
cache_alloc_hsw_probe(void)139 static inline void cache_alloc_hsw_probe(void)
140 {
141 struct rdt_hw_resource *hw_res = &rdt_resources_all[RDT_RESOURCE_L3];
142 struct rdt_resource *r = &hw_res->r_resctrl;
143 u64 max_cbm = BIT_ULL_MASK(20) - 1, l3_cbm_0;
144
145 if (wrmsrq_safe(MSR_IA32_L3_CBM_BASE, max_cbm))
146 return;
147
148 rdmsrq(MSR_IA32_L3_CBM_BASE, l3_cbm_0);
149
150 /* If all the bits were set in MSR, return success */
151 if (l3_cbm_0 != max_cbm)
152 return;
153
154 hw_res->num_closid = 4;
155 r->cache.cbm_len = 20;
156 r->cache.shareable_bits = 0xc0000;
157 r->cache.min_cbm_bits = 2;
158 r->cache.arch_has_sparse_bitmasks = false;
159 r->alloc_capable = true;
160
161 rdt_alloc_capable = true;
162 }
163
164 /*
165 * rdt_get_mb_table() - get a mapping of bandwidth(b/w) percentage values
166 * exposed to user interface and the h/w understandable delay values.
167 *
168 * The non-linear delay values have the granularity of power of two
169 * and also the h/w does not guarantee a curve for configured delay
170 * values vs. actual b/w enforced.
171 * Hence we need a mapping that is pre calibrated so the user can
172 * express the memory b/w as a percentage value.
173 */
rdt_get_mb_table(struct rdt_resource * r)174 static inline bool rdt_get_mb_table(struct rdt_resource *r)
175 {
176 /*
177 * There are no Intel SKUs as of now to support non-linear delay.
178 */
179 pr_info("MBA b/w map not implemented for cpu:%d, model:%d",
180 boot_cpu_data.x86, boot_cpu_data.x86_model);
181
182 return false;
183 }
184
__get_mem_config_intel(struct rdt_resource * r)185 static __init bool __get_mem_config_intel(struct rdt_resource *r)
186 {
187 struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r);
188 union cpuid_0x10_3_eax eax;
189 union cpuid_0x10_x_edx edx;
190 u32 ebx, ecx, max_delay;
191
192 cpuid_count(0x00000010, 3, &eax.full, &ebx, &ecx, &edx.full);
193 hw_res->num_closid = edx.split.cos_max + 1;
194 max_delay = eax.split.max_delay + 1;
195 r->membw.max_bw = MAX_MBA_BW;
196 r->membw.arch_needs_linear = true;
197 if (ecx & MBA_IS_LINEAR) {
198 r->membw.delay_linear = true;
199 r->membw.min_bw = MAX_MBA_BW - max_delay;
200 r->membw.bw_gran = MAX_MBA_BW - max_delay;
201 } else {
202 if (!rdt_get_mb_table(r))
203 return false;
204 r->membw.arch_needs_linear = false;
205 }
206
207 if (boot_cpu_has(X86_FEATURE_PER_THREAD_MBA))
208 r->membw.throttle_mode = THREAD_THROTTLE_PER_THREAD;
209 else
210 r->membw.throttle_mode = THREAD_THROTTLE_MAX;
211
212 r->alloc_capable = true;
213
214 return true;
215 }
216
__rdt_get_mem_config_amd(struct rdt_resource * r)217 static __init bool __rdt_get_mem_config_amd(struct rdt_resource *r)
218 {
219 struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r);
220 u32 eax, ebx, ecx, edx, subleaf;
221
222 /*
223 * Query CPUID_Fn80000020_EDX_x01 for MBA and
224 * CPUID_Fn80000020_EDX_x02 for SMBA
225 */
226 subleaf = (r->rid == RDT_RESOURCE_SMBA) ? 2 : 1;
227
228 cpuid_count(0x80000020, subleaf, &eax, &ebx, &ecx, &edx);
229 hw_res->num_closid = edx + 1;
230 r->membw.max_bw = 1 << eax;
231
232 /* AMD does not use delay */
233 r->membw.delay_linear = false;
234 r->membw.arch_needs_linear = false;
235
236 /*
237 * AMD does not use memory delay throttle model to control
238 * the allocation like Intel does.
239 */
240 r->membw.throttle_mode = THREAD_THROTTLE_UNDEFINED;
241 r->membw.min_bw = 0;
242 r->membw.bw_gran = 1;
243
244 r->alloc_capable = true;
245
246 return true;
247 }
248
rdt_get_cache_alloc_cfg(int idx,struct rdt_resource * r)249 static void rdt_get_cache_alloc_cfg(int idx, struct rdt_resource *r)
250 {
251 struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r);
252 union cpuid_0x10_1_eax eax;
253 union cpuid_0x10_x_ecx ecx;
254 union cpuid_0x10_x_edx edx;
255 u32 ebx, default_ctrl;
256
257 cpuid_count(0x00000010, idx, &eax.full, &ebx, &ecx.full, &edx.full);
258 hw_res->num_closid = edx.split.cos_max + 1;
259 r->cache.cbm_len = eax.split.cbm_len + 1;
260 default_ctrl = BIT_MASK(eax.split.cbm_len + 1) - 1;
261 r->cache.shareable_bits = ebx & default_ctrl;
262 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
263 r->cache.arch_has_sparse_bitmasks = ecx.split.noncont;
264 r->alloc_capable = true;
265 }
266
rdt_get_cdp_config(int level)267 static void rdt_get_cdp_config(int level)
268 {
269 /*
270 * By default, CDP is disabled. CDP can be enabled by mount parameter
271 * "cdp" during resctrl file system mount time.
272 */
273 rdt_resources_all[level].cdp_enabled = false;
274 rdt_resources_all[level].r_resctrl.cdp_capable = true;
275 }
276
rdt_get_cdp_l3_config(void)277 static void rdt_get_cdp_l3_config(void)
278 {
279 rdt_get_cdp_config(RDT_RESOURCE_L3);
280 }
281
rdt_get_cdp_l2_config(void)282 static void rdt_get_cdp_l2_config(void)
283 {
284 rdt_get_cdp_config(RDT_RESOURCE_L2);
285 }
286
mba_wrmsr_amd(struct msr_param * m)287 static void mba_wrmsr_amd(struct msr_param *m)
288 {
289 struct rdt_hw_ctrl_domain *hw_dom = resctrl_to_arch_ctrl_dom(m->dom);
290 struct rdt_hw_resource *hw_res = resctrl_to_arch_res(m->res);
291 unsigned int i;
292
293 for (i = m->low; i < m->high; i++)
294 wrmsrq(hw_res->msr_base + i, hw_dom->ctrl_val[i]);
295 }
296
297 /*
298 * Map the memory b/w percentage value to delay values
299 * that can be written to QOS_MSRs.
300 * There are currently no SKUs which support non linear delay values.
301 */
delay_bw_map(unsigned long bw,struct rdt_resource * r)302 static u32 delay_bw_map(unsigned long bw, struct rdt_resource *r)
303 {
304 if (r->membw.delay_linear)
305 return MAX_MBA_BW - bw;
306
307 pr_warn_once("Non Linear delay-bw map not supported but queried\n");
308 return MAX_MBA_BW;
309 }
310
mba_wrmsr_intel(struct msr_param * m)311 static void mba_wrmsr_intel(struct msr_param *m)
312 {
313 struct rdt_hw_ctrl_domain *hw_dom = resctrl_to_arch_ctrl_dom(m->dom);
314 struct rdt_hw_resource *hw_res = resctrl_to_arch_res(m->res);
315 unsigned int i;
316
317 /* Write the delay values for mba. */
318 for (i = m->low; i < m->high; i++)
319 wrmsrq(hw_res->msr_base + i, delay_bw_map(hw_dom->ctrl_val[i], m->res));
320 }
321
cat_wrmsr(struct msr_param * m)322 static void cat_wrmsr(struct msr_param *m)
323 {
324 struct rdt_hw_ctrl_domain *hw_dom = resctrl_to_arch_ctrl_dom(m->dom);
325 struct rdt_hw_resource *hw_res = resctrl_to_arch_res(m->res);
326 unsigned int i;
327
328 for (i = m->low; i < m->high; i++)
329 wrmsrq(hw_res->msr_base + i, hw_dom->ctrl_val[i]);
330 }
331
resctrl_arch_get_num_closid(struct rdt_resource * r)332 u32 resctrl_arch_get_num_closid(struct rdt_resource *r)
333 {
334 return resctrl_to_arch_res(r)->num_closid;
335 }
336
rdt_ctrl_update(void * arg)337 void rdt_ctrl_update(void *arg)
338 {
339 struct rdt_hw_resource *hw_res;
340 struct msr_param *m = arg;
341
342 hw_res = resctrl_to_arch_res(m->res);
343 hw_res->msr_update(m);
344 }
345
setup_default_ctrlval(struct rdt_resource * r,u32 * dc)346 static void setup_default_ctrlval(struct rdt_resource *r, u32 *dc)
347 {
348 struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r);
349 int i;
350
351 /*
352 * Initialize the Control MSRs to having no control.
353 * For Cache Allocation: Set all bits in cbm
354 * For Memory Allocation: Set b/w requested to 100%
355 */
356 for (i = 0; i < hw_res->num_closid; i++, dc++)
357 *dc = resctrl_get_default_ctrl(r);
358 }
359
ctrl_domain_free(struct rdt_hw_ctrl_domain * hw_dom)360 static void ctrl_domain_free(struct rdt_hw_ctrl_domain *hw_dom)
361 {
362 kfree(hw_dom->ctrl_val);
363 kfree(hw_dom);
364 }
365
mon_domain_free(struct rdt_hw_mon_domain * hw_dom)366 static void mon_domain_free(struct rdt_hw_mon_domain *hw_dom)
367 {
368 int idx;
369
370 for_each_mbm_idx(idx)
371 kfree(hw_dom->arch_mbm_states[idx]);
372 kfree(hw_dom);
373 }
374
domain_setup_ctrlval(struct rdt_resource * r,struct rdt_ctrl_domain * d)375 static int domain_setup_ctrlval(struct rdt_resource *r, struct rdt_ctrl_domain *d)
376 {
377 struct rdt_hw_ctrl_domain *hw_dom = resctrl_to_arch_ctrl_dom(d);
378 struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r);
379 struct msr_param m;
380 u32 *dc;
381
382 dc = kmalloc_array(hw_res->num_closid, sizeof(*hw_dom->ctrl_val),
383 GFP_KERNEL);
384 if (!dc)
385 return -ENOMEM;
386
387 hw_dom->ctrl_val = dc;
388 setup_default_ctrlval(r, dc);
389
390 m.res = r;
391 m.dom = d;
392 m.low = 0;
393 m.high = hw_res->num_closid;
394 hw_res->msr_update(&m);
395 return 0;
396 }
397
398 /**
399 * arch_domain_mbm_alloc() - Allocate arch private storage for the MBM counters
400 * @num_rmid: The size of the MBM counter array
401 * @hw_dom: The domain that owns the allocated arrays
402 */
arch_domain_mbm_alloc(u32 num_rmid,struct rdt_hw_mon_domain * hw_dom)403 static int arch_domain_mbm_alloc(u32 num_rmid, struct rdt_hw_mon_domain *hw_dom)
404 {
405 size_t tsize = sizeof(*hw_dom->arch_mbm_states[0]);
406 enum resctrl_event_id eventid;
407 int idx;
408
409 for_each_mbm_event_id(eventid) {
410 if (!resctrl_is_mon_event_enabled(eventid))
411 continue;
412 idx = MBM_STATE_IDX(eventid);
413 hw_dom->arch_mbm_states[idx] = kcalloc(num_rmid, tsize, GFP_KERNEL);
414 if (!hw_dom->arch_mbm_states[idx])
415 goto cleanup;
416 }
417
418 return 0;
419 cleanup:
420 for_each_mbm_idx(idx) {
421 kfree(hw_dom->arch_mbm_states[idx]);
422 hw_dom->arch_mbm_states[idx] = NULL;
423 }
424
425 return -ENOMEM;
426 }
427
get_domain_id_from_scope(int cpu,enum resctrl_scope scope)428 static int get_domain_id_from_scope(int cpu, enum resctrl_scope scope)
429 {
430 switch (scope) {
431 case RESCTRL_L2_CACHE:
432 case RESCTRL_L3_CACHE:
433 return get_cpu_cacheinfo_id(cpu, scope);
434 case RESCTRL_L3_NODE:
435 return cpu_to_node(cpu);
436 default:
437 break;
438 }
439
440 return -EINVAL;
441 }
442
domain_add_cpu_ctrl(int cpu,struct rdt_resource * r)443 static void domain_add_cpu_ctrl(int cpu, struct rdt_resource *r)
444 {
445 int id = get_domain_id_from_scope(cpu, r->ctrl_scope);
446 struct rdt_hw_ctrl_domain *hw_dom;
447 struct list_head *add_pos = NULL;
448 struct rdt_domain_hdr *hdr;
449 struct rdt_ctrl_domain *d;
450 int err;
451
452 lockdep_assert_held(&domain_list_lock);
453
454 if (id < 0) {
455 pr_warn_once("Can't find control domain id for CPU:%d scope:%d for resource %s\n",
456 cpu, r->ctrl_scope, r->name);
457 return;
458 }
459
460 hdr = resctrl_find_domain(&r->ctrl_domains, id, &add_pos);
461 if (hdr) {
462 if (WARN_ON_ONCE(hdr->type != RESCTRL_CTRL_DOMAIN))
463 return;
464 d = container_of(hdr, struct rdt_ctrl_domain, hdr);
465
466 cpumask_set_cpu(cpu, &d->hdr.cpu_mask);
467 if (r->cache.arch_has_per_cpu_cfg)
468 rdt_domain_reconfigure_cdp(r);
469 return;
470 }
471
472 hw_dom = kzalloc_node(sizeof(*hw_dom), GFP_KERNEL, cpu_to_node(cpu));
473 if (!hw_dom)
474 return;
475
476 d = &hw_dom->d_resctrl;
477 d->hdr.id = id;
478 d->hdr.type = RESCTRL_CTRL_DOMAIN;
479 cpumask_set_cpu(cpu, &d->hdr.cpu_mask);
480
481 rdt_domain_reconfigure_cdp(r);
482
483 if (domain_setup_ctrlval(r, d)) {
484 ctrl_domain_free(hw_dom);
485 return;
486 }
487
488 list_add_tail_rcu(&d->hdr.list, add_pos);
489
490 err = resctrl_online_ctrl_domain(r, d);
491 if (err) {
492 list_del_rcu(&d->hdr.list);
493 synchronize_rcu();
494 ctrl_domain_free(hw_dom);
495 }
496 }
497
domain_add_cpu_mon(int cpu,struct rdt_resource * r)498 static void domain_add_cpu_mon(int cpu, struct rdt_resource *r)
499 {
500 int id = get_domain_id_from_scope(cpu, r->mon_scope);
501 struct list_head *add_pos = NULL;
502 struct rdt_hw_mon_domain *hw_dom;
503 struct rdt_domain_hdr *hdr;
504 struct rdt_mon_domain *d;
505 struct cacheinfo *ci;
506 int err;
507
508 lockdep_assert_held(&domain_list_lock);
509
510 if (id < 0) {
511 pr_warn_once("Can't find monitor domain id for CPU:%d scope:%d for resource %s\n",
512 cpu, r->mon_scope, r->name);
513 return;
514 }
515
516 hdr = resctrl_find_domain(&r->mon_domains, id, &add_pos);
517 if (hdr) {
518 if (WARN_ON_ONCE(hdr->type != RESCTRL_MON_DOMAIN))
519 return;
520 d = container_of(hdr, struct rdt_mon_domain, hdr);
521
522 cpumask_set_cpu(cpu, &d->hdr.cpu_mask);
523 /* Update the mbm_assign_mode state for the CPU if supported */
524 if (r->mon.mbm_cntr_assignable)
525 resctrl_arch_mbm_cntr_assign_set_one(r);
526 return;
527 }
528
529 hw_dom = kzalloc_node(sizeof(*hw_dom), GFP_KERNEL, cpu_to_node(cpu));
530 if (!hw_dom)
531 return;
532
533 d = &hw_dom->d_resctrl;
534 d->hdr.id = id;
535 d->hdr.type = RESCTRL_MON_DOMAIN;
536 ci = get_cpu_cacheinfo_level(cpu, RESCTRL_L3_CACHE);
537 if (!ci) {
538 pr_warn_once("Can't find L3 cache for CPU:%d resource %s\n", cpu, r->name);
539 mon_domain_free(hw_dom);
540 return;
541 }
542 d->ci_id = ci->id;
543 cpumask_set_cpu(cpu, &d->hdr.cpu_mask);
544
545 /* Update the mbm_assign_mode state for the CPU if supported */
546 if (r->mon.mbm_cntr_assignable)
547 resctrl_arch_mbm_cntr_assign_set_one(r);
548
549 arch_mon_domain_online(r, d);
550
551 if (arch_domain_mbm_alloc(r->mon.num_rmid, hw_dom)) {
552 mon_domain_free(hw_dom);
553 return;
554 }
555
556 list_add_tail_rcu(&d->hdr.list, add_pos);
557
558 err = resctrl_online_mon_domain(r, d);
559 if (err) {
560 list_del_rcu(&d->hdr.list);
561 synchronize_rcu();
562 mon_domain_free(hw_dom);
563 }
564 }
565
domain_add_cpu(int cpu,struct rdt_resource * r)566 static void domain_add_cpu(int cpu, struct rdt_resource *r)
567 {
568 if (r->alloc_capable)
569 domain_add_cpu_ctrl(cpu, r);
570 if (r->mon_capable)
571 domain_add_cpu_mon(cpu, r);
572 }
573
domain_remove_cpu_ctrl(int cpu,struct rdt_resource * r)574 static void domain_remove_cpu_ctrl(int cpu, struct rdt_resource *r)
575 {
576 int id = get_domain_id_from_scope(cpu, r->ctrl_scope);
577 struct rdt_hw_ctrl_domain *hw_dom;
578 struct rdt_domain_hdr *hdr;
579 struct rdt_ctrl_domain *d;
580
581 lockdep_assert_held(&domain_list_lock);
582
583 if (id < 0) {
584 pr_warn_once("Can't find control domain id for CPU:%d scope:%d for resource %s\n",
585 cpu, r->ctrl_scope, r->name);
586 return;
587 }
588
589 hdr = resctrl_find_domain(&r->ctrl_domains, id, NULL);
590 if (!hdr) {
591 pr_warn("Can't find control domain for id=%d for CPU %d for resource %s\n",
592 id, cpu, r->name);
593 return;
594 }
595
596 if (WARN_ON_ONCE(hdr->type != RESCTRL_CTRL_DOMAIN))
597 return;
598
599 d = container_of(hdr, struct rdt_ctrl_domain, hdr);
600 hw_dom = resctrl_to_arch_ctrl_dom(d);
601
602 cpumask_clear_cpu(cpu, &d->hdr.cpu_mask);
603 if (cpumask_empty(&d->hdr.cpu_mask)) {
604 resctrl_offline_ctrl_domain(r, d);
605 list_del_rcu(&d->hdr.list);
606 synchronize_rcu();
607
608 /*
609 * rdt_ctrl_domain "d" is going to be freed below, so clear
610 * its pointer from pseudo_lock_region struct.
611 */
612 if (d->plr)
613 d->plr->d = NULL;
614 ctrl_domain_free(hw_dom);
615
616 return;
617 }
618 }
619
domain_remove_cpu_mon(int cpu,struct rdt_resource * r)620 static void domain_remove_cpu_mon(int cpu, struct rdt_resource *r)
621 {
622 int id = get_domain_id_from_scope(cpu, r->mon_scope);
623 struct rdt_hw_mon_domain *hw_dom;
624 struct rdt_domain_hdr *hdr;
625 struct rdt_mon_domain *d;
626
627 lockdep_assert_held(&domain_list_lock);
628
629 if (id < 0) {
630 pr_warn_once("Can't find monitor domain id for CPU:%d scope:%d for resource %s\n",
631 cpu, r->mon_scope, r->name);
632 return;
633 }
634
635 hdr = resctrl_find_domain(&r->mon_domains, id, NULL);
636 if (!hdr) {
637 pr_warn("Can't find monitor domain for id=%d for CPU %d for resource %s\n",
638 id, cpu, r->name);
639 return;
640 }
641
642 if (WARN_ON_ONCE(hdr->type != RESCTRL_MON_DOMAIN))
643 return;
644
645 d = container_of(hdr, struct rdt_mon_domain, hdr);
646 hw_dom = resctrl_to_arch_mon_dom(d);
647
648 cpumask_clear_cpu(cpu, &d->hdr.cpu_mask);
649 if (cpumask_empty(&d->hdr.cpu_mask)) {
650 resctrl_offline_mon_domain(r, d);
651 list_del_rcu(&d->hdr.list);
652 synchronize_rcu();
653 mon_domain_free(hw_dom);
654
655 return;
656 }
657 }
658
domain_remove_cpu(int cpu,struct rdt_resource * r)659 static void domain_remove_cpu(int cpu, struct rdt_resource *r)
660 {
661 if (r->alloc_capable)
662 domain_remove_cpu_ctrl(cpu, r);
663 if (r->mon_capable)
664 domain_remove_cpu_mon(cpu, r);
665 }
666
clear_closid_rmid(int cpu)667 static void clear_closid_rmid(int cpu)
668 {
669 struct resctrl_pqr_state *state = this_cpu_ptr(&pqr_state);
670
671 state->default_closid = RESCTRL_RESERVED_CLOSID;
672 state->default_rmid = RESCTRL_RESERVED_RMID;
673 state->cur_closid = RESCTRL_RESERVED_CLOSID;
674 state->cur_rmid = RESCTRL_RESERVED_RMID;
675 wrmsr(MSR_IA32_PQR_ASSOC, RESCTRL_RESERVED_RMID,
676 RESCTRL_RESERVED_CLOSID);
677 }
678
resctrl_arch_online_cpu(unsigned int cpu)679 static int resctrl_arch_online_cpu(unsigned int cpu)
680 {
681 struct rdt_resource *r;
682
683 mutex_lock(&domain_list_lock);
684 for_each_capable_rdt_resource(r)
685 domain_add_cpu(cpu, r);
686 mutex_unlock(&domain_list_lock);
687
688 clear_closid_rmid(cpu);
689 resctrl_online_cpu(cpu);
690
691 return 0;
692 }
693
resctrl_arch_offline_cpu(unsigned int cpu)694 static int resctrl_arch_offline_cpu(unsigned int cpu)
695 {
696 struct rdt_resource *r;
697
698 resctrl_offline_cpu(cpu);
699
700 mutex_lock(&domain_list_lock);
701 for_each_capable_rdt_resource(r)
702 domain_remove_cpu(cpu, r);
703 mutex_unlock(&domain_list_lock);
704
705 clear_closid_rmid(cpu);
706
707 return 0;
708 }
709
710 enum {
711 RDT_FLAG_CMT,
712 RDT_FLAG_MBM_TOTAL,
713 RDT_FLAG_MBM_LOCAL,
714 RDT_FLAG_L3_CAT,
715 RDT_FLAG_L3_CDP,
716 RDT_FLAG_L2_CAT,
717 RDT_FLAG_L2_CDP,
718 RDT_FLAG_MBA,
719 RDT_FLAG_SMBA,
720 RDT_FLAG_BMEC,
721 RDT_FLAG_ABMC,
722 };
723
724 #define RDT_OPT(idx, n, f) \
725 [idx] = { \
726 .name = n, \
727 .flag = f \
728 }
729
730 struct rdt_options {
731 char *name;
732 int flag;
733 bool force_off, force_on;
734 };
735
736 static struct rdt_options rdt_options[] __ro_after_init = {
737 RDT_OPT(RDT_FLAG_CMT, "cmt", X86_FEATURE_CQM_OCCUP_LLC),
738 RDT_OPT(RDT_FLAG_MBM_TOTAL, "mbmtotal", X86_FEATURE_CQM_MBM_TOTAL),
739 RDT_OPT(RDT_FLAG_MBM_LOCAL, "mbmlocal", X86_FEATURE_CQM_MBM_LOCAL),
740 RDT_OPT(RDT_FLAG_L3_CAT, "l3cat", X86_FEATURE_CAT_L3),
741 RDT_OPT(RDT_FLAG_L3_CDP, "l3cdp", X86_FEATURE_CDP_L3),
742 RDT_OPT(RDT_FLAG_L2_CAT, "l2cat", X86_FEATURE_CAT_L2),
743 RDT_OPT(RDT_FLAG_L2_CDP, "l2cdp", X86_FEATURE_CDP_L2),
744 RDT_OPT(RDT_FLAG_MBA, "mba", X86_FEATURE_MBA),
745 RDT_OPT(RDT_FLAG_SMBA, "smba", X86_FEATURE_SMBA),
746 RDT_OPT(RDT_FLAG_BMEC, "bmec", X86_FEATURE_BMEC),
747 RDT_OPT(RDT_FLAG_ABMC, "abmc", X86_FEATURE_ABMC),
748 };
749 #define NUM_RDT_OPTIONS ARRAY_SIZE(rdt_options)
750
set_rdt_options(char * str)751 static int __init set_rdt_options(char *str)
752 {
753 struct rdt_options *o;
754 bool force_off;
755 char *tok;
756
757 if (*str == '=')
758 str++;
759 while ((tok = strsep(&str, ",")) != NULL) {
760 force_off = *tok == '!';
761 if (force_off)
762 tok++;
763 for (o = rdt_options; o < &rdt_options[NUM_RDT_OPTIONS]; o++) {
764 if (strcmp(tok, o->name) == 0) {
765 if (force_off)
766 o->force_off = true;
767 else
768 o->force_on = true;
769 break;
770 }
771 }
772 }
773 return 1;
774 }
775 __setup("rdt", set_rdt_options);
776
rdt_cpu_has(int flag)777 bool rdt_cpu_has(int flag)
778 {
779 bool ret = boot_cpu_has(flag);
780 struct rdt_options *o;
781
782 if (!ret)
783 return ret;
784
785 for (o = rdt_options; o < &rdt_options[NUM_RDT_OPTIONS]; o++) {
786 if (flag == o->flag) {
787 if (o->force_off)
788 ret = false;
789 if (o->force_on)
790 ret = true;
791 break;
792 }
793 }
794 return ret;
795 }
796
resctrl_arch_is_evt_configurable(enum resctrl_event_id evt)797 bool resctrl_arch_is_evt_configurable(enum resctrl_event_id evt)
798 {
799 if (!rdt_cpu_has(X86_FEATURE_BMEC))
800 return false;
801
802 switch (evt) {
803 case QOS_L3_MBM_TOTAL_EVENT_ID:
804 return rdt_cpu_has(X86_FEATURE_CQM_MBM_TOTAL);
805 case QOS_L3_MBM_LOCAL_EVENT_ID:
806 return rdt_cpu_has(X86_FEATURE_CQM_MBM_LOCAL);
807 default:
808 return false;
809 }
810 }
811
get_mem_config(void)812 static __init bool get_mem_config(void)
813 {
814 struct rdt_hw_resource *hw_res = &rdt_resources_all[RDT_RESOURCE_MBA];
815
816 if (!rdt_cpu_has(X86_FEATURE_MBA))
817 return false;
818
819 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
820 return __get_mem_config_intel(&hw_res->r_resctrl);
821 else if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
822 return __rdt_get_mem_config_amd(&hw_res->r_resctrl);
823
824 return false;
825 }
826
get_slow_mem_config(void)827 static __init bool get_slow_mem_config(void)
828 {
829 struct rdt_hw_resource *hw_res = &rdt_resources_all[RDT_RESOURCE_SMBA];
830
831 if (!rdt_cpu_has(X86_FEATURE_SMBA))
832 return false;
833
834 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
835 return __rdt_get_mem_config_amd(&hw_res->r_resctrl);
836
837 return false;
838 }
839
get_rdt_alloc_resources(void)840 static __init bool get_rdt_alloc_resources(void)
841 {
842 struct rdt_resource *r;
843 bool ret = false;
844
845 if (rdt_alloc_capable)
846 return true;
847
848 if (!boot_cpu_has(X86_FEATURE_RDT_A))
849 return false;
850
851 if (rdt_cpu_has(X86_FEATURE_CAT_L3)) {
852 r = &rdt_resources_all[RDT_RESOURCE_L3].r_resctrl;
853 rdt_get_cache_alloc_cfg(1, r);
854 if (rdt_cpu_has(X86_FEATURE_CDP_L3))
855 rdt_get_cdp_l3_config();
856 ret = true;
857 }
858 if (rdt_cpu_has(X86_FEATURE_CAT_L2)) {
859 /* CPUID 0x10.2 fields are same format at 0x10.1 */
860 r = &rdt_resources_all[RDT_RESOURCE_L2].r_resctrl;
861 rdt_get_cache_alloc_cfg(2, r);
862 if (rdt_cpu_has(X86_FEATURE_CDP_L2))
863 rdt_get_cdp_l2_config();
864 ret = true;
865 }
866
867 if (get_mem_config())
868 ret = true;
869
870 if (get_slow_mem_config())
871 ret = true;
872
873 return ret;
874 }
875
get_rdt_mon_resources(void)876 static __init bool get_rdt_mon_resources(void)
877 {
878 struct rdt_resource *r = &rdt_resources_all[RDT_RESOURCE_L3].r_resctrl;
879 bool ret = false;
880
881 if (rdt_cpu_has(X86_FEATURE_CQM_OCCUP_LLC)) {
882 resctrl_enable_mon_event(QOS_L3_OCCUP_EVENT_ID);
883 ret = true;
884 }
885 if (rdt_cpu_has(X86_FEATURE_CQM_MBM_TOTAL)) {
886 resctrl_enable_mon_event(QOS_L3_MBM_TOTAL_EVENT_ID);
887 ret = true;
888 }
889 if (rdt_cpu_has(X86_FEATURE_CQM_MBM_LOCAL)) {
890 resctrl_enable_mon_event(QOS_L3_MBM_LOCAL_EVENT_ID);
891 ret = true;
892 }
893 if (rdt_cpu_has(X86_FEATURE_ABMC))
894 ret = true;
895
896 if (!ret)
897 return false;
898
899 return !rdt_get_mon_l3_config(r);
900 }
901
__check_quirks_intel(void)902 static __init void __check_quirks_intel(void)
903 {
904 switch (boot_cpu_data.x86_vfm) {
905 case INTEL_HASWELL_X:
906 if (!rdt_options[RDT_FLAG_L3_CAT].force_off)
907 cache_alloc_hsw_probe();
908 break;
909 case INTEL_SKYLAKE_X:
910 if (boot_cpu_data.x86_stepping <= 4)
911 set_rdt_options("!cmt,!mbmtotal,!mbmlocal,!l3cat");
912 else
913 set_rdt_options("!l3cat");
914 fallthrough;
915 case INTEL_BROADWELL_X:
916 intel_rdt_mbm_apply_quirk();
917 break;
918 }
919 }
920
check_quirks(void)921 static __init void check_quirks(void)
922 {
923 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
924 __check_quirks_intel();
925 }
926
get_rdt_resources(void)927 static __init bool get_rdt_resources(void)
928 {
929 rdt_alloc_capable = get_rdt_alloc_resources();
930 rdt_mon_capable = get_rdt_mon_resources();
931
932 return (rdt_mon_capable || rdt_alloc_capable);
933 }
934
rdt_init_res_defs_intel(void)935 static __init void rdt_init_res_defs_intel(void)
936 {
937 struct rdt_hw_resource *hw_res;
938 struct rdt_resource *r;
939
940 for_each_rdt_resource(r) {
941 hw_res = resctrl_to_arch_res(r);
942
943 if (r->rid == RDT_RESOURCE_L3 ||
944 r->rid == RDT_RESOURCE_L2) {
945 r->cache.arch_has_per_cpu_cfg = false;
946 r->cache.min_cbm_bits = 1;
947 } else if (r->rid == RDT_RESOURCE_MBA) {
948 hw_res->msr_base = MSR_IA32_MBA_THRTL_BASE;
949 hw_res->msr_update = mba_wrmsr_intel;
950 }
951 }
952 }
953
rdt_init_res_defs_amd(void)954 static __init void rdt_init_res_defs_amd(void)
955 {
956 struct rdt_hw_resource *hw_res;
957 struct rdt_resource *r;
958
959 for_each_rdt_resource(r) {
960 hw_res = resctrl_to_arch_res(r);
961
962 if (r->rid == RDT_RESOURCE_L3 ||
963 r->rid == RDT_RESOURCE_L2) {
964 r->cache.arch_has_sparse_bitmasks = true;
965 r->cache.arch_has_per_cpu_cfg = true;
966 r->cache.min_cbm_bits = 0;
967 } else if (r->rid == RDT_RESOURCE_MBA) {
968 hw_res->msr_base = MSR_IA32_MBA_BW_BASE;
969 hw_res->msr_update = mba_wrmsr_amd;
970 } else if (r->rid == RDT_RESOURCE_SMBA) {
971 hw_res->msr_base = MSR_IA32_SMBA_BW_BASE;
972 hw_res->msr_update = mba_wrmsr_amd;
973 }
974 }
975 }
976
rdt_init_res_defs(void)977 static __init void rdt_init_res_defs(void)
978 {
979 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
980 rdt_init_res_defs_intel();
981 else if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
982 rdt_init_res_defs_amd();
983 }
984
985 static enum cpuhp_state rdt_online;
986
987 /* Runs once on the BSP during boot. */
resctrl_cpu_detect(struct cpuinfo_x86 * c)988 void resctrl_cpu_detect(struct cpuinfo_x86 *c)
989 {
990 if (!cpu_has(c, X86_FEATURE_CQM_LLC) && !cpu_has(c, X86_FEATURE_ABMC)) {
991 c->x86_cache_max_rmid = -1;
992 c->x86_cache_occ_scale = -1;
993 c->x86_cache_mbm_width_offset = -1;
994 return;
995 }
996
997 /* will be overridden if occupancy monitoring exists */
998 c->x86_cache_max_rmid = cpuid_ebx(0xf);
999
1000 if (cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC) ||
1001 cpu_has(c, X86_FEATURE_CQM_MBM_TOTAL) ||
1002 cpu_has(c, X86_FEATURE_CQM_MBM_LOCAL) ||
1003 cpu_has(c, X86_FEATURE_ABMC)) {
1004 u32 eax, ebx, ecx, edx;
1005
1006 /* QoS sub-leaf, EAX=0Fh, ECX=1 */
1007 cpuid_count(0xf, 1, &eax, &ebx, &ecx, &edx);
1008
1009 c->x86_cache_max_rmid = ecx;
1010 c->x86_cache_occ_scale = ebx;
1011 c->x86_cache_mbm_width_offset = eax & 0xff;
1012
1013 if (c->x86_vendor == X86_VENDOR_AMD && !c->x86_cache_mbm_width_offset)
1014 c->x86_cache_mbm_width_offset = MBM_CNTR_WIDTH_OFFSET_AMD;
1015 }
1016 }
1017
resctrl_arch_late_init(void)1018 static int __init resctrl_arch_late_init(void)
1019 {
1020 struct rdt_resource *r;
1021 int state, ret, i;
1022
1023 /* for_each_rdt_resource() requires all rid to be initialised. */
1024 for (i = 0; i < RDT_NUM_RESOURCES; i++)
1025 rdt_resources_all[i].r_resctrl.rid = i;
1026
1027 /*
1028 * Initialize functions(or definitions) that are different
1029 * between vendors here.
1030 */
1031 rdt_init_res_defs();
1032
1033 check_quirks();
1034
1035 if (!get_rdt_resources())
1036 return -ENODEV;
1037
1038 state = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN,
1039 "x86/resctrl/cat:online:",
1040 resctrl_arch_online_cpu,
1041 resctrl_arch_offline_cpu);
1042 if (state < 0)
1043 return state;
1044
1045 ret = resctrl_init();
1046 if (ret) {
1047 cpuhp_remove_state(state);
1048 return ret;
1049 }
1050 rdt_online = state;
1051
1052 for_each_alloc_capable_rdt_resource(r)
1053 pr_info("%s allocation detected\n", r->name);
1054
1055 for_each_mon_capable_rdt_resource(r)
1056 pr_info("%s monitoring detected\n", r->name);
1057
1058 return 0;
1059 }
1060
1061 late_initcall(resctrl_arch_late_init);
1062
resctrl_arch_exit(void)1063 static void __exit resctrl_arch_exit(void)
1064 {
1065 cpuhp_remove_state(rdt_online);
1066
1067 resctrl_exit();
1068 }
1069
1070 __exitcall(resctrl_arch_exit);
1071