1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2015 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 */
6
7 #ifndef __ARM64_KVM_HYP_SWITCH_H__
8 #define __ARM64_KVM_HYP_SWITCH_H__
9
10 #include <hyp/adjust_pc.h>
11 #include <hyp/fault.h>
12
13 #include <linux/arm-smccc.h>
14 #include <linux/kvm_host.h>
15 #include <linux/types.h>
16 #include <linux/jump_label.h>
17 #include <uapi/linux/psci.h>
18
19 #include <kvm/arm_psci.h>
20
21 #include <asm/barrier.h>
22 #include <asm/cpufeature.h>
23 #include <asm/extable.h>
24 #include <asm/kprobes.h>
25 #include <asm/kvm_asm.h>
26 #include <asm/kvm_emulate.h>
27 #include <asm/kvm_hyp.h>
28 #include <asm/kvm_mmu.h>
29 #include <asm/kvm_nested.h>
30 #include <asm/fpsimd.h>
31 #include <asm/debug-monitors.h>
32 #include <asm/processor.h>
33 #include <asm/traps.h>
34
35 struct kvm_exception_table_entry {
36 int insn, fixup;
37 };
38
39 extern struct kvm_exception_table_entry __start___kvm_ex_table;
40 extern struct kvm_exception_table_entry __stop___kvm_ex_table;
41
42 /* Save the 32-bit only FPSIMD system register state */
__fpsimd_save_fpexc32(struct kvm_vcpu * vcpu)43 static inline void __fpsimd_save_fpexc32(struct kvm_vcpu *vcpu)
44 {
45 if (!vcpu_el1_is_32bit(vcpu))
46 return;
47
48 __vcpu_assign_sys_reg(vcpu, FPEXC32_EL2, read_sysreg(fpexc32_el2));
49 }
50
__activate_traps_fpsimd32(struct kvm_vcpu * vcpu)51 static inline void __activate_traps_fpsimd32(struct kvm_vcpu *vcpu)
52 {
53 /*
54 * We are about to set CPTR_EL2.TFP to trap all floating point
55 * register accesses to EL2, however, the ARM ARM clearly states that
56 * traps are only taken to EL2 if the operation would not otherwise
57 * trap to EL1. Therefore, always make sure that for 32-bit guests,
58 * we set FPEXC.EN to prevent traps to EL1, when setting the TFP bit.
59 * If FP/ASIMD is not implemented, FPEXC is UNDEFINED and any access to
60 * it will cause an exception.
61 */
62 if (vcpu_el1_is_32bit(vcpu) && system_supports_fpsimd()) {
63 write_sysreg(1 << 30, fpexc32_el2);
64 isb();
65 }
66 }
67
__activate_cptr_traps_nvhe(struct kvm_vcpu * vcpu)68 static inline void __activate_cptr_traps_nvhe(struct kvm_vcpu *vcpu)
69 {
70 u64 val = CPTR_NVHE_EL2_RES1 | CPTR_EL2_TAM | CPTR_EL2_TTA;
71
72 /*
73 * Always trap SME since it's not supported in KVM.
74 * TSM is RES1 if SME isn't implemented.
75 */
76 val |= CPTR_EL2_TSM;
77
78 if (!vcpu_has_sve(vcpu) || !guest_owns_fp_regs())
79 val |= CPTR_EL2_TZ;
80
81 if (!guest_owns_fp_regs())
82 val |= CPTR_EL2_TFP;
83
84 write_sysreg(val, cptr_el2);
85 }
86
__activate_cptr_traps_vhe(struct kvm_vcpu * vcpu)87 static inline void __activate_cptr_traps_vhe(struct kvm_vcpu *vcpu)
88 {
89 /*
90 * With VHE (HCR.E2H == 1), accesses to CPACR_EL1 are routed to
91 * CPTR_EL2. In general, CPACR_EL1 has the same layout as CPTR_EL2,
92 * except for some missing controls, such as TAM.
93 * In this case, CPTR_EL2.TAM has the same position with or without
94 * VHE (HCR.E2H == 1) which allows us to use here the CPTR_EL2.TAM
95 * shift value for trapping the AMU accesses.
96 */
97 u64 val = CPTR_EL2_TAM | CPACR_EL1_TTA;
98 u64 cptr;
99
100 if (guest_owns_fp_regs()) {
101 val |= CPACR_EL1_FPEN;
102 if (vcpu_has_sve(vcpu))
103 val |= CPACR_EL1_ZEN;
104 }
105
106 if (!vcpu_has_nv(vcpu))
107 goto write;
108
109 /*
110 * The architecture is a bit crap (what a surprise): an EL2 guest
111 * writing to CPTR_EL2 via CPACR_EL1 can't set any of TCPAC or TTA,
112 * as they are RES0 in the guest's view. To work around it, trap the
113 * sucker using the very same bit it can't set...
114 */
115 if (vcpu_el2_e2h_is_set(vcpu) && is_hyp_ctxt(vcpu))
116 val |= CPTR_EL2_TCPAC;
117
118 /*
119 * Layer the guest hypervisor's trap configuration on top of our own if
120 * we're in a nested context.
121 */
122 if (is_hyp_ctxt(vcpu))
123 goto write;
124
125 cptr = vcpu_sanitised_cptr_el2(vcpu);
126
127 /*
128 * Pay attention, there's some interesting detail here.
129 *
130 * The CPTR_EL2.xEN fields are 2 bits wide, although there are only two
131 * meaningful trap states when HCR_EL2.TGE = 0 (running a nested guest):
132 *
133 * - CPTR_EL2.xEN = x0, traps are enabled
134 * - CPTR_EL2.xEN = x1, traps are disabled
135 *
136 * In other words, bit[0] determines if guest accesses trap or not. In
137 * the interest of simplicity, clear the entire field if the guest
138 * hypervisor has traps enabled to dispel any illusion of something more
139 * complicated taking place.
140 */
141 if (!(SYS_FIELD_GET(CPACR_EL1, FPEN, cptr) & BIT(0)))
142 val &= ~CPACR_EL1_FPEN;
143 if (!(SYS_FIELD_GET(CPACR_EL1, ZEN, cptr) & BIT(0)))
144 val &= ~CPACR_EL1_ZEN;
145
146 if (kvm_has_feat(vcpu->kvm, ID_AA64MMFR3_EL1, S2POE, IMP))
147 val |= cptr & CPACR_EL1_E0POE;
148
149 val |= cptr & CPTR_EL2_TCPAC;
150
151 write:
152 write_sysreg(val, cpacr_el1);
153 }
154
__activate_cptr_traps(struct kvm_vcpu * vcpu)155 static inline void __activate_cptr_traps(struct kvm_vcpu *vcpu)
156 {
157 if (!guest_owns_fp_regs())
158 __activate_traps_fpsimd32(vcpu);
159
160 if (has_vhe() || has_hvhe())
161 __activate_cptr_traps_vhe(vcpu);
162 else
163 __activate_cptr_traps_nvhe(vcpu);
164 }
165
__deactivate_cptr_traps_nvhe(struct kvm_vcpu * vcpu)166 static inline void __deactivate_cptr_traps_nvhe(struct kvm_vcpu *vcpu)
167 {
168 u64 val = CPTR_NVHE_EL2_RES1;
169
170 if (!cpus_have_final_cap(ARM64_SVE))
171 val |= CPTR_EL2_TZ;
172 if (!cpus_have_final_cap(ARM64_SME))
173 val |= CPTR_EL2_TSM;
174
175 write_sysreg(val, cptr_el2);
176 }
177
__deactivate_cptr_traps_vhe(struct kvm_vcpu * vcpu)178 static inline void __deactivate_cptr_traps_vhe(struct kvm_vcpu *vcpu)
179 {
180 u64 val = CPACR_EL1_FPEN;
181
182 if (cpus_have_final_cap(ARM64_SVE))
183 val |= CPACR_EL1_ZEN;
184 if (cpus_have_final_cap(ARM64_SME))
185 val |= CPACR_EL1_SMEN;
186
187 write_sysreg(val, cpacr_el1);
188 }
189
__deactivate_cptr_traps(struct kvm_vcpu * vcpu)190 static inline void __deactivate_cptr_traps(struct kvm_vcpu *vcpu)
191 {
192 if (has_vhe() || has_hvhe())
193 __deactivate_cptr_traps_vhe(vcpu);
194 else
195 __deactivate_cptr_traps_nvhe(vcpu);
196 }
197
198 #define reg_to_fgt_masks(reg) \
199 ({ \
200 struct fgt_masks *m; \
201 switch(reg) { \
202 case HFGRTR_EL2: \
203 m = &hfgrtr_masks; \
204 break; \
205 case HFGWTR_EL2: \
206 m = &hfgwtr_masks; \
207 break; \
208 case HFGITR_EL2: \
209 m = &hfgitr_masks; \
210 break; \
211 case HDFGRTR_EL2: \
212 m = &hdfgrtr_masks; \
213 break; \
214 case HDFGWTR_EL2: \
215 m = &hdfgwtr_masks; \
216 break; \
217 case HAFGRTR_EL2: \
218 m = &hafgrtr_masks; \
219 break; \
220 case HFGRTR2_EL2: \
221 m = &hfgrtr2_masks; \
222 break; \
223 case HFGWTR2_EL2: \
224 m = &hfgwtr2_masks; \
225 break; \
226 case HFGITR2_EL2: \
227 m = &hfgitr2_masks; \
228 break; \
229 case HDFGRTR2_EL2: \
230 m = &hdfgrtr2_masks; \
231 break; \
232 case HDFGWTR2_EL2: \
233 m = &hdfgwtr2_masks; \
234 break; \
235 default: \
236 BUILD_BUG_ON(1); \
237 } \
238 \
239 m; \
240 })
241
242 #define compute_clr_set(vcpu, reg, clr, set) \
243 do { \
244 u64 hfg = __vcpu_sys_reg(vcpu, reg); \
245 struct fgt_masks *m = reg_to_fgt_masks(reg); \
246 set |= hfg & m->mask; \
247 clr |= ~hfg & m->nmask; \
248 } while(0)
249
250 #define reg_to_fgt_group_id(reg) \
251 ({ \
252 enum fgt_group_id id; \
253 switch(reg) { \
254 case HFGRTR_EL2: \
255 case HFGWTR_EL2: \
256 id = HFGRTR_GROUP; \
257 break; \
258 case HFGITR_EL2: \
259 id = HFGITR_GROUP; \
260 break; \
261 case HDFGRTR_EL2: \
262 case HDFGWTR_EL2: \
263 id = HDFGRTR_GROUP; \
264 break; \
265 case HAFGRTR_EL2: \
266 id = HAFGRTR_GROUP; \
267 break; \
268 case HFGRTR2_EL2: \
269 case HFGWTR2_EL2: \
270 id = HFGRTR2_GROUP; \
271 break; \
272 case HFGITR2_EL2: \
273 id = HFGITR2_GROUP; \
274 break; \
275 case HDFGRTR2_EL2: \
276 case HDFGWTR2_EL2: \
277 id = HDFGRTR2_GROUP; \
278 break; \
279 default: \
280 BUILD_BUG_ON(1); \
281 } \
282 \
283 id; \
284 })
285
286 #define compute_undef_clr_set(vcpu, kvm, reg, clr, set) \
287 do { \
288 u64 hfg = kvm->arch.fgu[reg_to_fgt_group_id(reg)]; \
289 struct fgt_masks *m = reg_to_fgt_masks(reg); \
290 set |= hfg & m->mask; \
291 clr |= hfg & m->nmask; \
292 } while(0)
293
294 #define update_fgt_traps_cs(hctxt, vcpu, kvm, reg, clr, set) \
295 do { \
296 struct fgt_masks *m = reg_to_fgt_masks(reg); \
297 u64 c = clr, s = set; \
298 u64 val; \
299 \
300 ctxt_sys_reg(hctxt, reg) = read_sysreg_s(SYS_ ## reg); \
301 if (vcpu_has_nv(vcpu) && !is_hyp_ctxt(vcpu)) \
302 compute_clr_set(vcpu, reg, c, s); \
303 \
304 compute_undef_clr_set(vcpu, kvm, reg, c, s); \
305 \
306 val = m->nmask; \
307 val |= s; \
308 val &= ~c; \
309 write_sysreg_s(val, SYS_ ## reg); \
310 } while(0)
311
312 #define update_fgt_traps(hctxt, vcpu, kvm, reg) \
313 update_fgt_traps_cs(hctxt, vcpu, kvm, reg, 0, 0)
314
cpu_has_amu(void)315 static inline bool cpu_has_amu(void)
316 {
317 u64 pfr0 = read_sysreg_s(SYS_ID_AA64PFR0_EL1);
318
319 return cpuid_feature_extract_unsigned_field(pfr0,
320 ID_AA64PFR0_EL1_AMU_SHIFT);
321 }
322
__activate_traps_hfgxtr(struct kvm_vcpu * vcpu)323 static inline void __activate_traps_hfgxtr(struct kvm_vcpu *vcpu)
324 {
325 struct kvm_cpu_context *hctxt = host_data_ptr(host_ctxt);
326 struct kvm *kvm = kern_hyp_va(vcpu->kvm);
327
328 if (!cpus_have_final_cap(ARM64_HAS_FGT))
329 return;
330
331 update_fgt_traps(hctxt, vcpu, kvm, HFGRTR_EL2);
332 update_fgt_traps_cs(hctxt, vcpu, kvm, HFGWTR_EL2, 0,
333 cpus_have_final_cap(ARM64_WORKAROUND_AMPERE_AC03_CPU_38) ?
334 HFGWTR_EL2_TCR_EL1_MASK : 0);
335 update_fgt_traps(hctxt, vcpu, kvm, HFGITR_EL2);
336 update_fgt_traps(hctxt, vcpu, kvm, HDFGRTR_EL2);
337 update_fgt_traps(hctxt, vcpu, kvm, HDFGWTR_EL2);
338
339 if (cpu_has_amu())
340 update_fgt_traps(hctxt, vcpu, kvm, HAFGRTR_EL2);
341
342 if (!cpus_have_final_cap(ARM64_HAS_FGT2))
343 return;
344
345 update_fgt_traps(hctxt, vcpu, kvm, HFGRTR2_EL2);
346 update_fgt_traps(hctxt, vcpu, kvm, HFGWTR2_EL2);
347 update_fgt_traps(hctxt, vcpu, kvm, HFGITR2_EL2);
348 update_fgt_traps(hctxt, vcpu, kvm, HDFGRTR2_EL2);
349 update_fgt_traps(hctxt, vcpu, kvm, HDFGWTR2_EL2);
350 }
351
352 #define __deactivate_fgt(htcxt, vcpu, reg) \
353 do { \
354 write_sysreg_s(ctxt_sys_reg(hctxt, reg), \
355 SYS_ ## reg); \
356 } while(0)
357
__deactivate_traps_hfgxtr(struct kvm_vcpu * vcpu)358 static inline void __deactivate_traps_hfgxtr(struct kvm_vcpu *vcpu)
359 {
360 struct kvm_cpu_context *hctxt = host_data_ptr(host_ctxt);
361
362 if (!cpus_have_final_cap(ARM64_HAS_FGT))
363 return;
364
365 __deactivate_fgt(hctxt, vcpu, HFGRTR_EL2);
366 __deactivate_fgt(hctxt, vcpu, HFGWTR_EL2);
367 __deactivate_fgt(hctxt, vcpu, HFGITR_EL2);
368 __deactivate_fgt(hctxt, vcpu, HDFGRTR_EL2);
369 __deactivate_fgt(hctxt, vcpu, HDFGWTR_EL2);
370
371 if (cpu_has_amu())
372 __deactivate_fgt(hctxt, vcpu, HAFGRTR_EL2);
373
374 if (!cpus_have_final_cap(ARM64_HAS_FGT2))
375 return;
376
377 __deactivate_fgt(hctxt, vcpu, HFGRTR2_EL2);
378 __deactivate_fgt(hctxt, vcpu, HFGWTR2_EL2);
379 __deactivate_fgt(hctxt, vcpu, HFGITR2_EL2);
380 __deactivate_fgt(hctxt, vcpu, HDFGRTR2_EL2);
381 __deactivate_fgt(hctxt, vcpu, HDFGWTR2_EL2);
382 }
383
__activate_traps_mpam(struct kvm_vcpu * vcpu)384 static inline void __activate_traps_mpam(struct kvm_vcpu *vcpu)
385 {
386 u64 r = MPAM2_EL2_TRAPMPAM0EL1 | MPAM2_EL2_TRAPMPAM1EL1;
387
388 if (!system_supports_mpam())
389 return;
390
391 /* trap guest access to MPAMIDR_EL1 */
392 if (system_supports_mpam_hcr()) {
393 write_sysreg_s(MPAMHCR_EL2_TRAP_MPAMIDR_EL1, SYS_MPAMHCR_EL2);
394 } else {
395 /* From v1.1 TIDR can trap MPAMIDR, set it unconditionally */
396 r |= MPAM2_EL2_TIDR;
397 }
398
399 write_sysreg_s(r, SYS_MPAM2_EL2);
400 }
401
__deactivate_traps_mpam(void)402 static inline void __deactivate_traps_mpam(void)
403 {
404 if (!system_supports_mpam())
405 return;
406
407 write_sysreg_s(0, SYS_MPAM2_EL2);
408
409 if (system_supports_mpam_hcr())
410 write_sysreg_s(MPAMHCR_HOST_FLAGS, SYS_MPAMHCR_EL2);
411 }
412
__activate_traps_common(struct kvm_vcpu * vcpu)413 static inline void __activate_traps_common(struct kvm_vcpu *vcpu)
414 {
415 struct kvm_cpu_context *hctxt = host_data_ptr(host_ctxt);
416
417 /* Trap on AArch32 cp15 c15 (impdef sysregs) accesses (EL1 or EL0) */
418 write_sysreg(1 << 15, hstr_el2);
419
420 /*
421 * Make sure we trap PMU access from EL0 to EL2. Also sanitize
422 * PMSELR_EL0 to make sure it never contains the cycle
423 * counter, which could make a PMXEVCNTR_EL0 access UNDEF at
424 * EL1 instead of being trapped to EL2.
425 */
426 if (system_supports_pmuv3()) {
427 write_sysreg(0, pmselr_el0);
428
429 ctxt_sys_reg(hctxt, PMUSERENR_EL0) = read_sysreg(pmuserenr_el0);
430 write_sysreg(ARMV8_PMU_USERENR_MASK, pmuserenr_el0);
431 vcpu_set_flag(vcpu, PMUSERENR_ON_CPU);
432 }
433
434 *host_data_ptr(host_debug_state.mdcr_el2) = read_sysreg(mdcr_el2);
435 write_sysreg(vcpu->arch.mdcr_el2, mdcr_el2);
436
437 if (cpus_have_final_cap(ARM64_HAS_HCX)) {
438 u64 hcrx = vcpu->arch.hcrx_el2;
439 if (vcpu_has_nv(vcpu) && !is_hyp_ctxt(vcpu)) {
440 u64 val = __vcpu_sys_reg(vcpu, HCRX_EL2);
441 hcrx |= val & __HCRX_EL2_MASK;
442 hcrx &= ~(~val & __HCRX_EL2_nMASK);
443 }
444
445 ctxt_sys_reg(hctxt, HCRX_EL2) = read_sysreg_s(SYS_HCRX_EL2);
446 write_sysreg_s(hcrx, SYS_HCRX_EL2);
447 }
448
449 __activate_traps_hfgxtr(vcpu);
450 __activate_traps_mpam(vcpu);
451 }
452
__deactivate_traps_common(struct kvm_vcpu * vcpu)453 static inline void __deactivate_traps_common(struct kvm_vcpu *vcpu)
454 {
455 struct kvm_cpu_context *hctxt = host_data_ptr(host_ctxt);
456
457 write_sysreg(*host_data_ptr(host_debug_state.mdcr_el2), mdcr_el2);
458
459 write_sysreg(0, hstr_el2);
460 if (system_supports_pmuv3()) {
461 write_sysreg(ctxt_sys_reg(hctxt, PMUSERENR_EL0), pmuserenr_el0);
462 vcpu_clear_flag(vcpu, PMUSERENR_ON_CPU);
463 }
464
465 if (cpus_have_final_cap(ARM64_HAS_HCX))
466 write_sysreg_s(ctxt_sys_reg(hctxt, HCRX_EL2), SYS_HCRX_EL2);
467
468 __deactivate_traps_hfgxtr(vcpu);
469 __deactivate_traps_mpam();
470 }
471
___activate_traps(struct kvm_vcpu * vcpu,u64 hcr)472 static inline void ___activate_traps(struct kvm_vcpu *vcpu, u64 hcr)
473 {
474 if (cpus_have_final_cap(ARM64_WORKAROUND_CAVIUM_TX2_219_TVM))
475 hcr |= HCR_TVM;
476
477 write_sysreg_hcr(hcr);
478
479 if (cpus_have_final_cap(ARM64_HAS_RAS_EXTN) && (hcr & HCR_VSE))
480 write_sysreg_s(vcpu->arch.vsesr_el2, SYS_VSESR_EL2);
481 }
482
___deactivate_traps(struct kvm_vcpu * vcpu)483 static inline void ___deactivate_traps(struct kvm_vcpu *vcpu)
484 {
485 /*
486 * If we pended a virtual abort, preserve it until it gets
487 * cleared. See D1.14.3 (Virtual Interrupts) for details, but
488 * the crucial bit is "On taking a vSError interrupt,
489 * HCR_EL2.VSE is cleared to 0."
490 */
491 if (vcpu->arch.hcr_el2 & HCR_VSE) {
492 vcpu->arch.hcr_el2 &= ~HCR_VSE;
493 vcpu->arch.hcr_el2 |= read_sysreg(hcr_el2) & HCR_VSE;
494 }
495 }
496
__populate_fault_info(struct kvm_vcpu * vcpu)497 static inline bool __populate_fault_info(struct kvm_vcpu *vcpu)
498 {
499 return __get_fault_info(vcpu->arch.fault.esr_el2, &vcpu->arch.fault);
500 }
501
kvm_hyp_handle_mops(struct kvm_vcpu * vcpu,u64 * exit_code)502 static inline bool kvm_hyp_handle_mops(struct kvm_vcpu *vcpu, u64 *exit_code)
503 {
504 *vcpu_pc(vcpu) = read_sysreg_el2(SYS_ELR);
505 arm64_mops_reset_regs(vcpu_gp_regs(vcpu), vcpu->arch.fault.esr_el2);
506 write_sysreg_el2(*vcpu_pc(vcpu), SYS_ELR);
507
508 /*
509 * Finish potential single step before executing the prologue
510 * instruction.
511 */
512 *vcpu_cpsr(vcpu) &= ~DBG_SPSR_SS;
513 write_sysreg_el2(*vcpu_cpsr(vcpu), SYS_SPSR);
514
515 return true;
516 }
517
__hyp_sve_restore_guest(struct kvm_vcpu * vcpu)518 static inline void __hyp_sve_restore_guest(struct kvm_vcpu *vcpu)
519 {
520 /*
521 * The vCPU's saved SVE state layout always matches the max VL of the
522 * vCPU. Start off with the max VL so we can load the SVE state.
523 */
524 sve_cond_update_zcr_vq(vcpu_sve_max_vq(vcpu) - 1, SYS_ZCR_EL2);
525 __sve_restore_state(vcpu_sve_pffr(vcpu),
526 &vcpu->arch.ctxt.fp_regs.fpsr,
527 true);
528
529 /*
530 * The effective VL for a VM could differ from the max VL when running a
531 * nested guest, as the guest hypervisor could select a smaller VL. Slap
532 * that into hardware before wrapping up.
533 */
534 if (vcpu_has_nv(vcpu) && !is_hyp_ctxt(vcpu))
535 sve_cond_update_zcr_vq(__vcpu_sys_reg(vcpu, ZCR_EL2), SYS_ZCR_EL2);
536
537 write_sysreg_el1(__vcpu_sys_reg(vcpu, vcpu_sve_zcr_elx(vcpu)), SYS_ZCR);
538 }
539
__hyp_sve_save_host(void)540 static inline void __hyp_sve_save_host(void)
541 {
542 struct cpu_sve_state *sve_state = *host_data_ptr(sve_state);
543
544 sve_state->zcr_el1 = read_sysreg_el1(SYS_ZCR);
545 write_sysreg_s(sve_vq_from_vl(kvm_host_sve_max_vl) - 1, SYS_ZCR_EL2);
546 __sve_save_state(sve_state->sve_regs + sve_ffr_offset(kvm_host_sve_max_vl),
547 &sve_state->fpsr,
548 true);
549 }
550
fpsimd_lazy_switch_to_guest(struct kvm_vcpu * vcpu)551 static inline void fpsimd_lazy_switch_to_guest(struct kvm_vcpu *vcpu)
552 {
553 u64 zcr_el1, zcr_el2;
554
555 if (!guest_owns_fp_regs())
556 return;
557
558 if (vcpu_has_sve(vcpu)) {
559 /* A guest hypervisor may restrict the effective max VL. */
560 if (vcpu_has_nv(vcpu) && !is_hyp_ctxt(vcpu))
561 zcr_el2 = __vcpu_sys_reg(vcpu, ZCR_EL2);
562 else
563 zcr_el2 = vcpu_sve_max_vq(vcpu) - 1;
564
565 write_sysreg_el2(zcr_el2, SYS_ZCR);
566
567 zcr_el1 = __vcpu_sys_reg(vcpu, vcpu_sve_zcr_elx(vcpu));
568 write_sysreg_el1(zcr_el1, SYS_ZCR);
569 }
570 }
571
fpsimd_lazy_switch_to_host(struct kvm_vcpu * vcpu)572 static inline void fpsimd_lazy_switch_to_host(struct kvm_vcpu *vcpu)
573 {
574 u64 zcr_el1, zcr_el2;
575
576 if (!guest_owns_fp_regs())
577 return;
578
579 /*
580 * When the guest owns the FP regs, we know that guest+hyp traps for
581 * any FPSIMD/SVE/SME features exposed to the guest have been disabled
582 * by either fpsimd_lazy_switch_to_guest() or kvm_hyp_handle_fpsimd()
583 * prior to __guest_entry(). As __guest_entry() guarantees a context
584 * synchronization event, we don't need an ISB here to avoid taking
585 * traps for anything that was exposed to the guest.
586 */
587 if (vcpu_has_sve(vcpu)) {
588 zcr_el1 = read_sysreg_el1(SYS_ZCR);
589 __vcpu_assign_sys_reg(vcpu, vcpu_sve_zcr_elx(vcpu), zcr_el1);
590
591 /*
592 * The guest's state is always saved using the guest's max VL.
593 * Ensure that the host has the guest's max VL active such that
594 * the host can save the guest's state lazily, but don't
595 * artificially restrict the host to the guest's max VL.
596 */
597 if (has_vhe()) {
598 zcr_el2 = vcpu_sve_max_vq(vcpu) - 1;
599 write_sysreg_el2(zcr_el2, SYS_ZCR);
600 } else {
601 zcr_el2 = sve_vq_from_vl(kvm_host_sve_max_vl) - 1;
602 write_sysreg_el2(zcr_el2, SYS_ZCR);
603
604 zcr_el1 = vcpu_sve_max_vq(vcpu) - 1;
605 write_sysreg_el1(zcr_el1, SYS_ZCR);
606 }
607 }
608 }
609
kvm_hyp_save_fpsimd_host(struct kvm_vcpu * vcpu)610 static void kvm_hyp_save_fpsimd_host(struct kvm_vcpu *vcpu)
611 {
612 /*
613 * Non-protected kvm relies on the host restoring its sve state.
614 * Protected kvm restores the host's sve state as not to reveal that
615 * fpsimd was used by a guest nor leak upper sve bits.
616 */
617 if (system_supports_sve()) {
618 __hyp_sve_save_host();
619 } else {
620 __fpsimd_save_state(host_data_ptr(host_ctxt.fp_regs));
621 }
622
623 if (kvm_has_fpmr(kern_hyp_va(vcpu->kvm)))
624 *host_data_ptr(fpmr) = read_sysreg_s(SYS_FPMR);
625 }
626
627
628 /*
629 * We trap the first access to the FP/SIMD to save the host context and
630 * restore the guest context lazily.
631 * If FP/SIMD is not implemented, handle the trap and inject an undefined
632 * instruction exception to the guest. Similarly for trapped SVE accesses.
633 */
kvm_hyp_handle_fpsimd(struct kvm_vcpu * vcpu,u64 * exit_code)634 static inline bool kvm_hyp_handle_fpsimd(struct kvm_vcpu *vcpu, u64 *exit_code)
635 {
636 bool sve_guest;
637 u8 esr_ec;
638
639 if (!system_supports_fpsimd())
640 return false;
641
642 sve_guest = vcpu_has_sve(vcpu);
643 esr_ec = kvm_vcpu_trap_get_class(vcpu);
644
645 /* Only handle traps the vCPU can support here: */
646 switch (esr_ec) {
647 case ESR_ELx_EC_FP_ASIMD:
648 /* Forward traps to the guest hypervisor as required */
649 if (guest_hyp_fpsimd_traps_enabled(vcpu))
650 return false;
651 break;
652 case ESR_ELx_EC_SYS64:
653 if (WARN_ON_ONCE(!is_hyp_ctxt(vcpu)))
654 return false;
655 fallthrough;
656 case ESR_ELx_EC_SVE:
657 if (!sve_guest)
658 return false;
659 if (guest_hyp_sve_traps_enabled(vcpu))
660 return false;
661 break;
662 default:
663 return false;
664 }
665
666 /* Valid trap. Switch the context: */
667
668 /* First disable enough traps to allow us to update the registers */
669 __deactivate_cptr_traps(vcpu);
670 isb();
671
672 /* Write out the host state if it's in the registers */
673 if (is_protected_kvm_enabled() && host_owns_fp_regs())
674 kvm_hyp_save_fpsimd_host(vcpu);
675
676 /* Restore the guest state */
677 if (sve_guest)
678 __hyp_sve_restore_guest(vcpu);
679 else
680 __fpsimd_restore_state(&vcpu->arch.ctxt.fp_regs);
681
682 if (kvm_has_fpmr(kern_hyp_va(vcpu->kvm)))
683 write_sysreg_s(__vcpu_sys_reg(vcpu, FPMR), SYS_FPMR);
684
685 /* Skip restoring fpexc32 for AArch64 guests */
686 if (!(read_sysreg(hcr_el2) & HCR_RW))
687 write_sysreg(__vcpu_sys_reg(vcpu, FPEXC32_EL2), fpexc32_el2);
688
689 *host_data_ptr(fp_owner) = FP_STATE_GUEST_OWNED;
690
691 /*
692 * Re-enable traps necessary for the current state of the guest, e.g.
693 * those enabled by a guest hypervisor. The ERET to the guest will
694 * provide the necessary context synchronization.
695 */
696 __activate_cptr_traps(vcpu);
697
698 return true;
699 }
700
handle_tx2_tvm(struct kvm_vcpu * vcpu)701 static inline bool handle_tx2_tvm(struct kvm_vcpu *vcpu)
702 {
703 u32 sysreg = esr_sys64_to_sysreg(kvm_vcpu_get_esr(vcpu));
704 int rt = kvm_vcpu_sys_get_rt(vcpu);
705 u64 val = vcpu_get_reg(vcpu, rt);
706
707 /*
708 * The normal sysreg handling code expects to see the traps,
709 * let's not do anything here.
710 */
711 if (vcpu->arch.hcr_el2 & HCR_TVM)
712 return false;
713
714 switch (sysreg) {
715 case SYS_SCTLR_EL1:
716 write_sysreg_el1(val, SYS_SCTLR);
717 break;
718 case SYS_TTBR0_EL1:
719 write_sysreg_el1(val, SYS_TTBR0);
720 break;
721 case SYS_TTBR1_EL1:
722 write_sysreg_el1(val, SYS_TTBR1);
723 break;
724 case SYS_TCR_EL1:
725 write_sysreg_el1(val, SYS_TCR);
726 break;
727 case SYS_ESR_EL1:
728 write_sysreg_el1(val, SYS_ESR);
729 break;
730 case SYS_FAR_EL1:
731 write_sysreg_el1(val, SYS_FAR);
732 break;
733 case SYS_AFSR0_EL1:
734 write_sysreg_el1(val, SYS_AFSR0);
735 break;
736 case SYS_AFSR1_EL1:
737 write_sysreg_el1(val, SYS_AFSR1);
738 break;
739 case SYS_MAIR_EL1:
740 write_sysreg_el1(val, SYS_MAIR);
741 break;
742 case SYS_AMAIR_EL1:
743 write_sysreg_el1(val, SYS_AMAIR);
744 break;
745 case SYS_CONTEXTIDR_EL1:
746 write_sysreg_el1(val, SYS_CONTEXTIDR);
747 break;
748 default:
749 return false;
750 }
751
752 __kvm_skip_instr(vcpu);
753 return true;
754 }
755
756 /* Open-coded version of timer_get_offset() to allow for kern_hyp_va() */
hyp_timer_get_offset(struct arch_timer_context * ctxt)757 static inline u64 hyp_timer_get_offset(struct arch_timer_context *ctxt)
758 {
759 u64 offset = 0;
760
761 if (ctxt->offset.vm_offset)
762 offset += *kern_hyp_va(ctxt->offset.vm_offset);
763 if (ctxt->offset.vcpu_offset)
764 offset += *kern_hyp_va(ctxt->offset.vcpu_offset);
765
766 return offset;
767 }
768
compute_counter_value(struct arch_timer_context * ctxt)769 static inline u64 compute_counter_value(struct arch_timer_context *ctxt)
770 {
771 return arch_timer_read_cntpct_el0() - hyp_timer_get_offset(ctxt);
772 }
773
kvm_handle_cntxct(struct kvm_vcpu * vcpu)774 static bool kvm_handle_cntxct(struct kvm_vcpu *vcpu)
775 {
776 struct arch_timer_context *ctxt;
777 u32 sysreg;
778 u64 val;
779
780 /*
781 * We only get here for 64bit guests, 32bit guests will hit
782 * the long and winding road all the way to the standard
783 * handling. Yes, it sucks to be irrelevant.
784 *
785 * Also, we only deal with non-hypervisor context here (either
786 * an EL1 guest, or a non-HYP context of an EL2 guest).
787 */
788 if (is_hyp_ctxt(vcpu))
789 return false;
790
791 sysreg = esr_sys64_to_sysreg(kvm_vcpu_get_esr(vcpu));
792
793 switch (sysreg) {
794 case SYS_CNTPCT_EL0:
795 case SYS_CNTPCTSS_EL0:
796 if (vcpu_has_nv(vcpu)) {
797 /* Check for guest hypervisor trapping */
798 val = __vcpu_sys_reg(vcpu, CNTHCTL_EL2);
799 if (!vcpu_el2_e2h_is_set(vcpu))
800 val = (val & CNTHCTL_EL1PCTEN) << 10;
801
802 if (!(val & (CNTHCTL_EL1PCTEN << 10)))
803 return false;
804 }
805
806 ctxt = vcpu_ptimer(vcpu);
807 break;
808 case SYS_CNTVCT_EL0:
809 case SYS_CNTVCTSS_EL0:
810 if (vcpu_has_nv(vcpu)) {
811 /* Check for guest hypervisor trapping */
812 val = __vcpu_sys_reg(vcpu, CNTHCTL_EL2);
813
814 if (val & CNTHCTL_EL1TVCT)
815 return false;
816 }
817
818 ctxt = vcpu_vtimer(vcpu);
819 break;
820 default:
821 return false;
822 }
823
824 val = compute_counter_value(ctxt);
825
826 vcpu_set_reg(vcpu, kvm_vcpu_sys_get_rt(vcpu), val);
827 __kvm_skip_instr(vcpu);
828 return true;
829 }
830
handle_ampere1_tcr(struct kvm_vcpu * vcpu)831 static bool handle_ampere1_tcr(struct kvm_vcpu *vcpu)
832 {
833 u32 sysreg = esr_sys64_to_sysreg(kvm_vcpu_get_esr(vcpu));
834 int rt = kvm_vcpu_sys_get_rt(vcpu);
835 u64 val = vcpu_get_reg(vcpu, rt);
836
837 if (sysreg != SYS_TCR_EL1)
838 return false;
839
840 /*
841 * Affected parts do not advertise support for hardware Access Flag /
842 * Dirty state management in ID_AA64MMFR1_EL1.HAFDBS, but the underlying
843 * control bits are still functional. The architecture requires these be
844 * RES0 on systems that do not implement FEAT_HAFDBS.
845 *
846 * Uphold the requirements of the architecture by masking guest writes
847 * to TCR_EL1.{HA,HD} here.
848 */
849 val &= ~(TCR_HD | TCR_HA);
850 write_sysreg_el1(val, SYS_TCR);
851 __kvm_skip_instr(vcpu);
852 return true;
853 }
854
kvm_hyp_handle_sysreg(struct kvm_vcpu * vcpu,u64 * exit_code)855 static inline bool kvm_hyp_handle_sysreg(struct kvm_vcpu *vcpu, u64 *exit_code)
856 {
857 if (cpus_have_final_cap(ARM64_WORKAROUND_CAVIUM_TX2_219_TVM) &&
858 handle_tx2_tvm(vcpu))
859 return true;
860
861 if (cpus_have_final_cap(ARM64_WORKAROUND_AMPERE_AC03_CPU_38) &&
862 handle_ampere1_tcr(vcpu))
863 return true;
864
865 if (static_branch_unlikely(&vgic_v3_cpuif_trap) &&
866 __vgic_v3_perform_cpuif_access(vcpu) == 1)
867 return true;
868
869 if (kvm_handle_cntxct(vcpu))
870 return true;
871
872 return false;
873 }
874
kvm_hyp_handle_cp15_32(struct kvm_vcpu * vcpu,u64 * exit_code)875 static inline bool kvm_hyp_handle_cp15_32(struct kvm_vcpu *vcpu, u64 *exit_code)
876 {
877 if (static_branch_unlikely(&vgic_v3_cpuif_trap) &&
878 __vgic_v3_perform_cpuif_access(vcpu) == 1)
879 return true;
880
881 return false;
882 }
883
kvm_hyp_handle_memory_fault(struct kvm_vcpu * vcpu,u64 * exit_code)884 static inline bool kvm_hyp_handle_memory_fault(struct kvm_vcpu *vcpu,
885 u64 *exit_code)
886 {
887 if (!__populate_fault_info(vcpu))
888 return true;
889
890 return false;
891 }
892 #define kvm_hyp_handle_iabt_low kvm_hyp_handle_memory_fault
893 #define kvm_hyp_handle_watchpt_low kvm_hyp_handle_memory_fault
894
kvm_hyp_handle_dabt_low(struct kvm_vcpu * vcpu,u64 * exit_code)895 static inline bool kvm_hyp_handle_dabt_low(struct kvm_vcpu *vcpu, u64 *exit_code)
896 {
897 if (kvm_hyp_handle_memory_fault(vcpu, exit_code))
898 return true;
899
900 if (static_branch_unlikely(&vgic_v2_cpuif_trap)) {
901 bool valid;
902
903 valid = kvm_vcpu_trap_is_translation_fault(vcpu) &&
904 kvm_vcpu_dabt_isvalid(vcpu) &&
905 !kvm_vcpu_abt_issea(vcpu) &&
906 !kvm_vcpu_abt_iss1tw(vcpu);
907
908 if (valid) {
909 int ret = __vgic_v2_perform_cpuif_access(vcpu);
910
911 if (ret == 1)
912 return true;
913
914 /* Promote an illegal access to an SError.*/
915 if (ret == -1)
916 *exit_code = ARM_EXCEPTION_EL1_SERROR;
917 }
918 }
919
920 return false;
921 }
922
923 typedef bool (*exit_handler_fn)(struct kvm_vcpu *, u64 *);
924
925 /*
926 * Allow the hypervisor to handle the exit with an exit handler if it has one.
927 *
928 * Returns true if the hypervisor handled the exit, and control should go back
929 * to the guest, or false if it hasn't.
930 */
kvm_hyp_handle_exit(struct kvm_vcpu * vcpu,u64 * exit_code,const exit_handler_fn * handlers)931 static inline bool kvm_hyp_handle_exit(struct kvm_vcpu *vcpu, u64 *exit_code,
932 const exit_handler_fn *handlers)
933 {
934 exit_handler_fn fn = handlers[kvm_vcpu_trap_get_class(vcpu)];
935 if (fn)
936 return fn(vcpu, exit_code);
937
938 return false;
939 }
940
synchronize_vcpu_pstate(struct kvm_vcpu * vcpu,u64 * exit_code)941 static inline void synchronize_vcpu_pstate(struct kvm_vcpu *vcpu, u64 *exit_code)
942 {
943 /*
944 * Check for the conditions of Cortex-A510's #2077057. When these occur
945 * SPSR_EL2 can't be trusted, but isn't needed either as it is
946 * unchanged from the value in vcpu_gp_regs(vcpu)->pstate.
947 * Are we single-stepping the guest, and took a PAC exception from the
948 * active-not-pending state?
949 */
950 if (cpus_have_final_cap(ARM64_WORKAROUND_2077057) &&
951 vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
952 *vcpu_cpsr(vcpu) & DBG_SPSR_SS &&
953 ESR_ELx_EC(read_sysreg_el2(SYS_ESR)) == ESR_ELx_EC_PAC)
954 write_sysreg_el2(*vcpu_cpsr(vcpu), SYS_SPSR);
955
956 vcpu->arch.ctxt.regs.pstate = read_sysreg_el2(SYS_SPSR);
957 }
958
959 /*
960 * Return true when we were able to fixup the guest exit and should return to
961 * the guest, false when we should restore the host state and return to the
962 * main run loop.
963 */
__fixup_guest_exit(struct kvm_vcpu * vcpu,u64 * exit_code,const exit_handler_fn * handlers)964 static inline bool __fixup_guest_exit(struct kvm_vcpu *vcpu, u64 *exit_code,
965 const exit_handler_fn *handlers)
966 {
967 if (ARM_EXCEPTION_CODE(*exit_code) != ARM_EXCEPTION_IRQ)
968 vcpu->arch.fault.esr_el2 = read_sysreg_el2(SYS_ESR);
969
970 if (ARM_SERROR_PENDING(*exit_code) &&
971 ARM_EXCEPTION_CODE(*exit_code) != ARM_EXCEPTION_IRQ) {
972 u8 esr_ec = kvm_vcpu_trap_get_class(vcpu);
973
974 /*
975 * HVC already have an adjusted PC, which we need to
976 * correct in order to return to after having injected
977 * the SError.
978 *
979 * SMC, on the other hand, is *trapped*, meaning its
980 * preferred return address is the SMC itself.
981 */
982 if (esr_ec == ESR_ELx_EC_HVC32 || esr_ec == ESR_ELx_EC_HVC64)
983 write_sysreg_el2(read_sysreg_el2(SYS_ELR) - 4, SYS_ELR);
984 }
985
986 /*
987 * We're using the raw exception code in order to only process
988 * the trap if no SError is pending. We will come back to the
989 * same PC once the SError has been injected, and replay the
990 * trapping instruction.
991 */
992 if (*exit_code != ARM_EXCEPTION_TRAP)
993 goto exit;
994
995 /* Check if there's an exit handler and allow it to handle the exit. */
996 if (kvm_hyp_handle_exit(vcpu, exit_code, handlers))
997 goto guest;
998 exit:
999 /* Return to the host kernel and handle the exit */
1000 return false;
1001
1002 guest:
1003 /* Re-enter the guest */
1004 asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412));
1005 return true;
1006 }
1007
__kvm_unexpected_el2_exception(void)1008 static inline void __kvm_unexpected_el2_exception(void)
1009 {
1010 extern char __guest_exit_restore_elr_and_panic[];
1011 unsigned long addr, fixup;
1012 struct kvm_exception_table_entry *entry, *end;
1013 unsigned long elr_el2 = read_sysreg(elr_el2);
1014
1015 entry = &__start___kvm_ex_table;
1016 end = &__stop___kvm_ex_table;
1017
1018 while (entry < end) {
1019 addr = (unsigned long)&entry->insn + entry->insn;
1020 fixup = (unsigned long)&entry->fixup + entry->fixup;
1021
1022 if (addr != elr_el2) {
1023 entry++;
1024 continue;
1025 }
1026
1027 write_sysreg(fixup, elr_el2);
1028 return;
1029 }
1030
1031 /* Trigger a panic after restoring the hyp context. */
1032 this_cpu_ptr(&kvm_hyp_ctxt)->sys_regs[ELR_EL2] = elr_el2;
1033 write_sysreg(__guest_exit_restore_elr_and_panic, elr_el2);
1034 }
1035
1036 #endif /* __ARM64_KVM_HYP_SWITCH_H__ */
1037