1 /*
2 * Performance events x86 architecture header
3 *
4 * Copyright (C) 2008 Linutronix GmbH, Thomas Gleixner <tglx@kernel.org>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
11 *
12 * For licencing details see kernel-base/COPYING
13 */
14
15 #include <linux/perf_event.h>
16
17 #include <asm/fpu/xstate.h>
18 #include <asm/intel_ds.h>
19 #include <asm/cpu.h>
20 #include <asm/msr.h>
21
22 /* To enable MSR tracing please use the generic trace points. */
23
24 /*
25 * | NHM/WSM | SNB |
26 * register -------------------------------
27 * | HT | no HT | HT | no HT |
28 *-----------------------------------------
29 * offcore | core | core | cpu | core |
30 * lbr_sel | core | core | cpu | core |
31 * ld_lat | cpu | core | cpu | core |
32 *-----------------------------------------
33 *
34 * Given that there is a small number of shared regs,
35 * we can pre-allocate their slot in the per-cpu
36 * per-core reg tables.
37 */
38 enum extra_reg_type {
39 EXTRA_REG_NONE = -1, /* not used */
40
41 EXTRA_REG_RSP_0 = 0, /* offcore_response_0 */
42 EXTRA_REG_RSP_1 = 1, /* offcore_response_1 */
43 EXTRA_REG_LBR = 2, /* lbr_select */
44 EXTRA_REG_LDLAT = 3, /* ld_lat_threshold */
45 EXTRA_REG_FE = 4, /* fe_* */
46 EXTRA_REG_SNOOP_0 = 5, /* snoop response 0 */
47 EXTRA_REG_SNOOP_1 = 6, /* snoop response 1 */
48 EXTRA_REG_OMR_0 = 7, /* OMR 0 */
49 EXTRA_REG_OMR_1 = 8, /* OMR 1 */
50 EXTRA_REG_OMR_2 = 9, /* OMR 2 */
51 EXTRA_REG_OMR_3 = 10, /* OMR 3 */
52
53 EXTRA_REG_MAX /* number of entries needed */
54 };
55
56 struct event_constraint {
57 union {
58 unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
59 u64 idxmsk64;
60 };
61 u64 code;
62 u64 cmask;
63 int weight;
64 int overlap;
65 int flags;
66 unsigned int size;
67 };
68
constraint_match(struct event_constraint * c,u64 ecode)69 static inline bool constraint_match(struct event_constraint *c, u64 ecode)
70 {
71 return ((ecode & c->cmask) - c->code) <= (u64)c->size;
72 }
73
74 #define PERF_ARCH(name, val) \
75 PERF_X86_EVENT_##name = val,
76
77 /*
78 * struct hw_perf_event.flags flags
79 */
80 enum {
81 #include "perf_event_flags.h"
82 };
83
84 #undef PERF_ARCH
85
86 #define PERF_ARCH(name, val) \
87 static_assert((PERF_X86_EVENT_##name & PERF_EVENT_FLAG_ARCH) == \
88 PERF_X86_EVENT_##name);
89
90 #include "perf_event_flags.h"
91
92 #undef PERF_ARCH
93
is_topdown_count(struct perf_event * event)94 static inline bool is_topdown_count(struct perf_event *event)
95 {
96 return event->hw.flags & PERF_X86_EVENT_TOPDOWN;
97 }
98
is_metric_event(struct perf_event * event)99 static inline bool is_metric_event(struct perf_event *event)
100 {
101 u64 config = event->attr.config;
102
103 return ((config & ARCH_PERFMON_EVENTSEL_EVENT) == 0) &&
104 ((config & INTEL_ARCH_EVENT_MASK) >= INTEL_TD_METRIC_RETIRING) &&
105 ((config & INTEL_ARCH_EVENT_MASK) <= INTEL_TD_METRIC_MAX);
106 }
107
is_slots_event(struct perf_event * event)108 static inline bool is_slots_event(struct perf_event *event)
109 {
110 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == INTEL_TD_SLOTS;
111 }
112
is_topdown_event(struct perf_event * event)113 static inline bool is_topdown_event(struct perf_event *event)
114 {
115 return is_metric_event(event) || is_slots_event(event);
116 }
117
118 int is_x86_event(struct perf_event *event);
119
check_leader_group(struct perf_event * leader,int flags)120 static inline bool check_leader_group(struct perf_event *leader, int flags)
121 {
122 return is_x86_event(leader) ? !!(leader->hw.flags & flags) : false;
123 }
124
is_branch_counters_group(struct perf_event * event)125 static inline bool is_branch_counters_group(struct perf_event *event)
126 {
127 return check_leader_group(event->group_leader, PERF_X86_EVENT_BRANCH_COUNTERS);
128 }
129
is_pebs_counter_event_group(struct perf_event * event)130 static inline bool is_pebs_counter_event_group(struct perf_event *event)
131 {
132 return check_leader_group(event->group_leader, PERF_X86_EVENT_PEBS_CNTR);
133 }
134
is_acr_event_group(struct perf_event * event)135 static inline bool is_acr_event_group(struct perf_event *event)
136 {
137 return check_leader_group(event->group_leader, PERF_X86_EVENT_ACR);
138 }
139
is_acr_self_reload_event(struct perf_event * event)140 static inline bool is_acr_self_reload_event(struct perf_event *event)
141 {
142 struct hw_perf_event *hwc = &event->hw;
143
144 if (hwc->idx < 0 || !is_acr_event_group(event))
145 return false;
146
147 return test_bit(hwc->idx, (unsigned long *)&hwc->config1);
148 }
149
__event_needs_xmm(struct perf_event * event,u64 sample_type)150 static inline bool __event_needs_xmm(struct perf_event *event, u64 sample_type)
151 {
152 if (event->attr.sample_simd_regs_enabled) {
153 if (event->attr.sample_simd_vec_reg_qwords < PERF_X86_XMM_QWORDS)
154 return false;
155
156 if ((sample_type & PERF_SAMPLE_REGS_USER) &&
157 (event->attr.sample_type & PERF_SAMPLE_REGS_USER) &&
158 (event->attr.sample_simd_vec_reg_user > 0))
159 return true;
160
161 if ((sample_type & PERF_SAMPLE_REGS_INTR) &&
162 (event->attr.sample_type & PERF_SAMPLE_REGS_INTR) &&
163 (event->attr.sample_simd_vec_reg_intr > 0))
164 return true;
165 } else {
166 if ((sample_type & PERF_SAMPLE_REGS_USER) &&
167 (event->attr.sample_type & PERF_SAMPLE_REGS_USER) &&
168 (event->attr.sample_regs_user & PERF_REG_EXTENDED_MASK))
169 return true;
170
171 if ((sample_type & PERF_SAMPLE_REGS_INTR) &&
172 (event->attr.sample_type & PERF_SAMPLE_REGS_INTR) &&
173 (event->attr.sample_regs_intr & PERF_REG_EXTENDED_MASK))
174 return true;
175 }
176
177 return false;
178 }
179
event_needs_xmm(struct perf_event * event)180 static inline bool event_needs_xmm(struct perf_event *event)
181 {
182 return __event_needs_xmm(event,
183 PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER);
184 }
185
__event_needs_ymm(struct perf_event * event,u64 sample_type)186 static inline bool __event_needs_ymm(struct perf_event *event, u64 sample_type)
187 {
188 if (!event->attr.sample_simd_regs_enabled)
189 return false;
190 if (event->attr.sample_simd_vec_reg_qwords < PERF_X86_YMM_QWORDS)
191 return false;
192
193 if ((sample_type & PERF_SAMPLE_REGS_USER) &&
194 (event->attr.sample_type & PERF_SAMPLE_REGS_USER) &&
195 (event->attr.sample_simd_vec_reg_user > 0))
196 return true;
197
198 if ((sample_type & PERF_SAMPLE_REGS_INTR) &&
199 (event->attr.sample_type & PERF_SAMPLE_REGS_INTR) &&
200 (event->attr.sample_simd_vec_reg_intr > 0))
201 return true;
202
203 return false;
204 }
205
event_needs_ymm(struct perf_event * event)206 static inline bool event_needs_ymm(struct perf_event *event)
207 {
208 return __event_needs_ymm(event,
209 PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER);
210 }
211
__event_needs_low16_zmm(struct perf_event * event,u64 sample_type)212 static inline bool __event_needs_low16_zmm(struct perf_event *event,
213 u64 sample_type)
214 {
215 if (!event->attr.sample_simd_regs_enabled)
216 return false;
217 if (event->attr.sample_simd_vec_reg_qwords < PERF_X86_ZMM_QWORDS)
218 return false;
219
220 if ((sample_type & PERF_SAMPLE_REGS_USER) &&
221 (event->attr.sample_type & PERF_SAMPLE_REGS_USER) &&
222 (event->attr.sample_simd_vec_reg_user > 0))
223 return true;
224
225 if ((sample_type & PERF_SAMPLE_REGS_INTR) &&
226 (event->attr.sample_type & PERF_SAMPLE_REGS_INTR) &&
227 (event->attr.sample_simd_vec_reg_intr > 0))
228 return true;
229
230 return false;
231 }
232
event_needs_low16_zmm(struct perf_event * event)233 static inline bool event_needs_low16_zmm(struct perf_event *event)
234 {
235 return __event_needs_low16_zmm(event,
236 PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER);
237 }
238
__event_needs_high16_zmm(struct perf_event * event,u64 sample_type)239 static inline bool __event_needs_high16_zmm(struct perf_event *event,
240 u64 sample_type)
241 {
242 if (!event->attr.sample_simd_regs_enabled)
243 return false;
244 if (event->attr.sample_simd_vec_reg_qwords < PERF_X86_ZMM_QWORDS)
245 return false;
246
247 if ((sample_type & PERF_SAMPLE_REGS_USER) &&
248 (event->attr.sample_type & PERF_SAMPLE_REGS_USER) &&
249 (fls64(event->attr.sample_simd_vec_reg_user) > PERF_X86_H16ZMM_BASE))
250 return true;
251
252 if ((sample_type & PERF_SAMPLE_REGS_INTR) &&
253 (event->attr.sample_type & PERF_SAMPLE_REGS_INTR) &&
254 (fls64(event->attr.sample_simd_vec_reg_intr) > PERF_X86_H16ZMM_BASE))
255 return true;
256
257 return false;
258 }
259
event_needs_high16_zmm(struct perf_event * event)260 static inline bool event_needs_high16_zmm(struct perf_event *event)
261 {
262 return __event_needs_high16_zmm(event,
263 PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER);
264 }
265
__event_needs_opmask(struct perf_event * event,u64 sample_type)266 static inline bool __event_needs_opmask(struct perf_event *event,
267 u64 sample_type)
268 {
269 if (!event->attr.sample_simd_regs_enabled)
270 return false;
271 if (event->attr.sample_simd_pred_reg_qwords != PERF_X86_OPMASK_QWORDS)
272 return false;
273
274 if ((sample_type & PERF_SAMPLE_REGS_USER) &&
275 (event->attr.sample_type & PERF_SAMPLE_REGS_USER) &&
276 (event->attr.sample_simd_pred_reg_user > 0))
277 return true;
278
279 if ((sample_type & PERF_SAMPLE_REGS_INTR) &&
280 (event->attr.sample_type & PERF_SAMPLE_REGS_INTR) &&
281 (event->attr.sample_simd_pred_reg_intr > 0))
282 return true;
283
284 return false;
285 }
286
event_needs_opmask(struct perf_event * event)287 static inline bool event_needs_opmask(struct perf_event *event)
288 {
289 return __event_needs_opmask(event,
290 PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER);
291 }
292
__event_needs_egprs(struct perf_event * event,u64 sample_type)293 static inline bool __event_needs_egprs(struct perf_event *event,
294 u64 sample_type)
295 {
296 if (!event->attr.sample_simd_regs_enabled)
297 return false;
298
299 if ((sample_type & PERF_SAMPLE_REGS_USER) &&
300 (event->attr.sample_type & PERF_SAMPLE_REGS_USER) &&
301 (event->attr.sample_regs_user & PERF_X86_EGPRS_MASK))
302 return true;
303
304 if ((sample_type & PERF_SAMPLE_REGS_INTR) &&
305 (event->attr.sample_type & PERF_SAMPLE_REGS_INTR) &&
306 (event->attr.sample_regs_intr & PERF_X86_EGPRS_MASK))
307 return true;
308
309 return false;
310 }
311
event_needs_egprs(struct perf_event * event)312 static inline bool event_needs_egprs(struct perf_event *event)
313 {
314 return __event_needs_egprs(event,
315 PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER);
316 }
317
__event_needs_ssp(struct perf_event * event,u64 sample_type)318 static inline bool __event_needs_ssp(struct perf_event *event,
319 u64 sample_type)
320 {
321 if (!event->attr.sample_simd_regs_enabled)
322 return false;
323
324 if ((sample_type & PERF_SAMPLE_REGS_USER) &&
325 (event->attr.sample_type & PERF_SAMPLE_REGS_USER) &&
326 (event->attr.sample_regs_user & BIT_ULL(PERF_REG_X86_SSP)))
327 return true;
328
329 if ((sample_type & PERF_SAMPLE_REGS_INTR) &&
330 (event->attr.sample_type & PERF_SAMPLE_REGS_INTR) &&
331 (event->attr.sample_regs_intr & BIT_ULL(PERF_REG_X86_SSP)))
332 return true;
333
334 return false;
335 }
336
event_needs_ssp(struct perf_event * event)337 static inline bool event_needs_ssp(struct perf_event *event)
338 {
339 return __event_needs_ssp(event,
340 PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER);
341 }
342
343 struct amd_nb {
344 int nb_id; /* NorthBridge id */
345 int refcnt; /* reference count */
346 struct perf_event *owners[X86_PMC_IDX_MAX];
347 struct event_constraint event_constraints[X86_PMC_IDX_MAX];
348 };
349
350 #define PEBS_COUNTER_MASK ((1ULL << MAX_PEBS_EVENTS) - 1)
351 #define PEBS_PMI_AFTER_EACH_RECORD BIT_ULL(60)
352 #define PEBS_OUTPUT_OFFSET 61
353 #define PEBS_OUTPUT_MASK (3ull << PEBS_OUTPUT_OFFSET)
354 #define PEBS_OUTPUT_PT (1ull << PEBS_OUTPUT_OFFSET)
355 #define PEBS_VIA_PT_MASK (PEBS_OUTPUT_PT | PEBS_PMI_AFTER_EACH_RECORD)
356
357 /*
358 * Flags PEBS can handle without an PMI.
359 *
360 * TID can only be handled by flushing at context switch.
361 * REGS_USER can be handled for events limited to ring 3.
362 *
363 */
364 #define LARGE_PEBS_FLAGS \
365 (PERF_SAMPLE_IP | PERF_SAMPLE_TID | PERF_SAMPLE_ADDR | \
366 PERF_SAMPLE_ID | PERF_SAMPLE_CPU | PERF_SAMPLE_STREAM_ID | \
367 PERF_SAMPLE_DATA_SRC | PERF_SAMPLE_IDENTIFIER | \
368 PERF_SAMPLE_TRANSACTION | PERF_SAMPLE_PHYS_ADDR | \
369 PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER | \
370 PERF_SAMPLE_PERIOD | PERF_SAMPLE_CODE_PAGE_SIZE | \
371 PERF_SAMPLE_WEIGHT_TYPE)
372
373 #define PEBS_GP_REGS \
374 ((1ULL << PERF_REG_X86_AX) | \
375 (1ULL << PERF_REG_X86_BX) | \
376 (1ULL << PERF_REG_X86_CX) | \
377 (1ULL << PERF_REG_X86_DX) | \
378 (1ULL << PERF_REG_X86_DI) | \
379 (1ULL << PERF_REG_X86_SI) | \
380 (1ULL << PERF_REG_X86_SP) | \
381 (1ULL << PERF_REG_X86_BP) | \
382 (1ULL << PERF_REG_X86_IP) | \
383 (1ULL << PERF_REG_X86_FLAGS) | \
384 (1ULL << PERF_REG_X86_R8) | \
385 (1ULL << PERF_REG_X86_R9) | \
386 (1ULL << PERF_REG_X86_R10) | \
387 (1ULL << PERF_REG_X86_R11) | \
388 (1ULL << PERF_REG_X86_R12) | \
389 (1ULL << PERF_REG_X86_R13) | \
390 (1ULL << PERF_REG_X86_R14) | \
391 (1ULL << PERF_REG_X86_R15))
392
393 /* user space rdpmc control values */
394 enum {
395 X86_USER_RDPMC_NEVER_ENABLE = 0,
396 X86_USER_RDPMC_CONDITIONAL_ENABLE = 1,
397 X86_USER_RDPMC_ALWAYS_ENABLE = 2,
398 };
399
400 /*
401 * Per register state.
402 */
403 struct er_account {
404 raw_spinlock_t lock; /* per-core: protect structure */
405 u64 config; /* extra MSR config */
406 u64 reg; /* extra MSR number */
407 atomic_t ref; /* reference count */
408 };
409
410 /*
411 * Per core/cpu state
412 *
413 * Used to coordinate shared registers between HT threads or
414 * among events on a single PMU.
415 */
416 struct intel_shared_regs {
417 struct er_account regs[EXTRA_REG_MAX];
418 int refcnt; /* per-core: #HT threads */
419 unsigned core_id; /* per-core: core id */
420 };
421
422 enum intel_excl_state_type {
423 INTEL_EXCL_UNUSED = 0, /* counter is unused */
424 INTEL_EXCL_SHARED = 1, /* counter can be used by both threads */
425 INTEL_EXCL_EXCLUSIVE = 2, /* counter can be used by one thread only */
426 };
427
428 struct intel_excl_states {
429 enum intel_excl_state_type state[X86_PMC_IDX_MAX];
430 bool sched_started; /* true if scheduling has started */
431 };
432
433 struct intel_excl_cntrs {
434 raw_spinlock_t lock;
435
436 struct intel_excl_states states[2];
437
438 union {
439 u16 has_exclusive[2];
440 u32 exclusive_present;
441 };
442
443 int refcnt; /* per-core: #HT threads */
444 unsigned core_id; /* per-core: core id */
445 };
446
447 struct x86_perf_task_context;
448 #define MAX_LBR_ENTRIES 32
449
450 enum {
451 LBR_FORMAT_32 = 0x00,
452 LBR_FORMAT_LIP = 0x01,
453 LBR_FORMAT_EIP = 0x02,
454 LBR_FORMAT_EIP_FLAGS = 0x03,
455 LBR_FORMAT_EIP_FLAGS2 = 0x04,
456 LBR_FORMAT_INFO = 0x05,
457 LBR_FORMAT_TIME = 0x06,
458 LBR_FORMAT_INFO2 = 0x07,
459 LBR_FORMAT_MAX_KNOWN = LBR_FORMAT_INFO2,
460 };
461
462 enum {
463 X86_PERF_KFREE_SHARED = 0,
464 X86_PERF_KFREE_EXCL = 1,
465 X86_PERF_KFREE_MAX
466 };
467
468 struct cpu_hw_events {
469 /*
470 * Generic x86 PMC bits
471 */
472 struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */
473 unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
474 unsigned long dirty[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
475 int enabled;
476
477 int n_events; /* the # of events in the below arrays */
478 int n_added; /* the # last events in the below arrays;
479 they've never been enabled yet */
480 int n_txn; /* the # last events in the below arrays;
481 added in the current transaction */
482 int n_txn_pair;
483 int n_txn_metric;
484 int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
485 u64 tags[X86_PMC_IDX_MAX];
486
487 struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */
488 struct event_constraint *event_constraint[X86_PMC_IDX_MAX];
489
490 int n_excl; /* the number of exclusive events */
491 int n_late_setup; /* the num of events needs late setup */
492
493 unsigned int txn_flags;
494 int is_fake;
495
496 /*
497 * Intel DebugStore bits
498 */
499 struct debug_store *ds;
500 void *ds_bts_vaddr;
501 /* DS based PEBS or arch-PEBS buffer address */
502 void *pebs_vaddr;
503 u64 pebs_enabled;
504 int n_pebs;
505 int n_large_pebs;
506 int n_pebs_via_pt;
507 int pebs_output;
508
509 /* Current super set of events hardware configuration */
510 u64 pebs_data_cfg;
511 u64 active_pebs_data_cfg;
512 int pebs_record_size;
513
514 /* Intel Fixed counter configuration */
515 u64 fixed_ctrl_val;
516 u64 active_fixed_ctrl_val;
517
518 /* Intel ACR/arch-PEBS configuration */
519 u64 acr_cfg_b[X86_PMC_IDX_MAX];
520 u64 cfg_c_val[X86_PMC_IDX_MAX];
521
522 /*
523 * Intel LBR bits
524 */
525 int lbr_users;
526 int lbr_pebs_users;
527 struct perf_branch_stack lbr_stack;
528 struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES];
529 u64 lbr_counters[MAX_LBR_ENTRIES]; /* branch stack extra */
530 union {
531 struct er_account *lbr_sel;
532 struct er_account *lbr_ctl;
533 };
534 u64 br_sel;
535 void *last_task_ctx;
536 int last_log_id;
537 int lbr_select;
538 void *lbr_xsave;
539
540 /*
541 * Intel host/guest exclude bits
542 */
543 u64 intel_ctrl_exclude_host_mask;
544 u64 intel_ctrl_exclude_guest_mask;
545 struct perf_guest_switch_msr guest_switch_msrs[X86_PMC_IDX_MAX];
546
547 /*
548 * Intel checkpoint mask
549 */
550 u64 intel_cp_status;
551
552 /*
553 * manage shared (per-core, per-cpu) registers
554 * used on Intel NHM/WSM/SNB
555 */
556 struct intel_shared_regs *shared_regs;
557 /*
558 * manage exclusive counter access between hyperthread
559 */
560 struct event_constraint *constraint_list; /* in enable order */
561 struct intel_excl_cntrs *excl_cntrs;
562 int excl_thread_id; /* 0 or 1 */
563
564 /*
565 * SKL TSX_FORCE_ABORT shadow
566 */
567 u64 tfa_shadow;
568
569 /*
570 * Perf Metrics
571 */
572 /* number of accepted metrics events */
573 int n_metric;
574
575 /*
576 * AMD specific bits
577 */
578 struct amd_nb *amd_nb;
579 int brs_active; /* BRS is enabled */
580
581 /* Inverted mask of bits to clear in the perf_ctr ctrl registers */
582 u64 perf_ctr_virt_mask;
583 int n_pair; /* Large increment events */
584
585 void *kfree_on_online[X86_PERF_KFREE_MAX];
586
587 struct pmu *pmu;
588 };
589
590 #define __EVENT_CONSTRAINT_RANGE(c, e, n, m, w, o, f) { \
591 { .idxmsk64 = (n) }, \
592 .code = (c), \
593 .size = (e) - (c), \
594 .cmask = (m), \
595 .weight = (w), \
596 .overlap = (o), \
597 .flags = f, \
598 }
599
600 #define __EVENT_CONSTRAINT(c, n, m, w, o, f) \
601 __EVENT_CONSTRAINT_RANGE(c, c, n, m, w, o, f)
602
603 #define EVENT_CONSTRAINT(c, n, m) \
604 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 0, 0)
605
606 /*
607 * The constraint_match() function only works for 'simple' event codes
608 * and not for extended (AMD64_EVENTSEL_EVENT) events codes.
609 */
610 #define EVENT_CONSTRAINT_RANGE(c, e, n, m) \
611 __EVENT_CONSTRAINT_RANGE(c, e, n, m, HWEIGHT(n), 0, 0)
612
613 #define INTEL_EXCLEVT_CONSTRAINT(c, n) \
614 __EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT, HWEIGHT(n),\
615 0, PERF_X86_EVENT_EXCL)
616
617 /*
618 * The overlap flag marks event constraints with overlapping counter
619 * masks. This is the case if the counter mask of such an event is not
620 * a subset of any other counter mask of a constraint with an equal or
621 * higher weight, e.g.:
622 *
623 * c_overlaps = EVENT_CONSTRAINT_OVERLAP(0, 0x09, 0);
624 * c_another1 = EVENT_CONSTRAINT(0, 0x07, 0);
625 * c_another2 = EVENT_CONSTRAINT(0, 0x38, 0);
626 *
627 * The event scheduler may not select the correct counter in the first
628 * cycle because it needs to know which subsequent events will be
629 * scheduled. It may fail to schedule the events then. So we set the
630 * overlap flag for such constraints to give the scheduler a hint which
631 * events to select for counter rescheduling.
632 *
633 * Care must be taken as the rescheduling algorithm is O(n!) which
634 * will increase scheduling cycles for an over-committed system
635 * dramatically. The number of such EVENT_CONSTRAINT_OVERLAP() macros
636 * and its counter masks must be kept at a minimum.
637 */
638 #define EVENT_CONSTRAINT_OVERLAP(c, n, m) \
639 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 1, 0)
640
641 /*
642 * Constraint on the Event code.
643 */
644 #define INTEL_EVENT_CONSTRAINT(c, n) \
645 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)
646
647 /*
648 * Constraint on a range of Event codes
649 */
650 #define INTEL_EVENT_CONSTRAINT_RANGE(c, e, n) \
651 EVENT_CONSTRAINT_RANGE(c, e, n, ARCH_PERFMON_EVENTSEL_EVENT)
652
653 /*
654 * Constraint on the Event code + UMask + fixed-mask
655 *
656 * filter mask to validate fixed counter events.
657 * the following filters disqualify for fixed counters:
658 * - inv
659 * - edge
660 * - cnt-mask
661 * - in_tx
662 * - in_tx_checkpointed
663 * The other filters are supported by fixed counters.
664 * The any-thread option is supported starting with v3.
665 */
666 #define FIXED_EVENT_FLAGS (X86_RAW_EVENT_MASK|HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)
667 #define FIXED_EVENT_CONSTRAINT(c, n) \
668 EVENT_CONSTRAINT(c, (1ULL << (32+n)), FIXED_EVENT_FLAGS)
669
670 /*
671 * The special metric counters do not actually exist. They are calculated from
672 * the combination of the FxCtr3 + MSR_PERF_METRICS.
673 *
674 * The special metric counters are mapped to a dummy offset for the scheduler.
675 * The sharing between multiple users of the same metric without multiplexing
676 * is not allowed, even though the hardware supports that in principle.
677 */
678
679 #define METRIC_EVENT_CONSTRAINT(c, n) \
680 EVENT_CONSTRAINT(c, (1ULL << (INTEL_PMC_IDX_METRIC_BASE + n)), \
681 INTEL_ARCH_EVENT_MASK)
682
683 /*
684 * Constraint on the Event code + UMask
685 */
686 #define INTEL_UEVENT_CONSTRAINT(c, n) \
687 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
688
689 /* Constraint on specific umask bit only + event */
690 #define INTEL_UBIT_EVENT_CONSTRAINT(c, n) \
691 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT|(c))
692
693 /* Like UEVENT_CONSTRAINT, but match flags too */
694 #define INTEL_FLAGS_UEVENT_CONSTRAINT(c, n) \
695 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS)
696
697 #define INTEL_EXCLUEVT_CONSTRAINT(c, n) \
698 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK, \
699 HWEIGHT(n), 0, PERF_X86_EVENT_EXCL)
700
701 #define INTEL_PLD_CONSTRAINT(c, n) \
702 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
703 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LDLAT)
704
705 #define INTEL_PSD_CONSTRAINT(c, n) \
706 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
707 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_STLAT)
708
709 #define INTEL_PST_CONSTRAINT(c, n) \
710 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
711 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST)
712
713 #define INTEL_HYBRID_LDLAT_CONSTRAINT(c, n) \
714 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
715 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LAT_HYBRID|PERF_X86_EVENT_PEBS_LD_HSW)
716
717 #define INTEL_HYBRID_STLAT_CONSTRAINT(c, n) \
718 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
719 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LAT_HYBRID|PERF_X86_EVENT_PEBS_ST_HSW)
720
721 /* Event constraint, but match on all event flags too. */
722 #define INTEL_FLAGS_EVENT_CONSTRAINT(c, n) \
723 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS)
724
725 #define INTEL_FLAGS_EVENT_CONSTRAINT_RANGE(c, e, n) \
726 EVENT_CONSTRAINT_RANGE(c, e, n, ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS)
727
728 /* Check only flags, but allow all event/umask */
729 #define INTEL_ALL_EVENT_CONSTRAINT(code, n) \
730 EVENT_CONSTRAINT(code, n, X86_ALL_EVENT_FLAGS)
731
732 /* Check flags and event code, and set the HSW store flag */
733 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_ST(code, n) \
734 __EVENT_CONSTRAINT(code, n, \
735 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \
736 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW)
737
738 /* Check flags and event code, and set the HSW load flag */
739 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(code, n) \
740 __EVENT_CONSTRAINT(code, n, \
741 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \
742 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW)
743
744 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD_RANGE(code, end, n) \
745 __EVENT_CONSTRAINT_RANGE(code, end, n, \
746 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \
747 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW)
748
749 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(code, n) \
750 __EVENT_CONSTRAINT(code, n, \
751 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \
752 HWEIGHT(n), 0, \
753 PERF_X86_EVENT_PEBS_LD_HSW|PERF_X86_EVENT_EXCL)
754
755 /* Check flags and event code/umask, and set the HSW store flag */
756 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(code, n) \
757 __EVENT_CONSTRAINT(code, n, \
758 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
759 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW)
760
761 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(code, n) \
762 __EVENT_CONSTRAINT(code, n, \
763 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
764 HWEIGHT(n), 0, \
765 PERF_X86_EVENT_PEBS_ST_HSW|PERF_X86_EVENT_EXCL)
766
767 /* Check flags and event code/umask, and set the HSW load flag */
768 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(code, n) \
769 __EVENT_CONSTRAINT(code, n, \
770 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
771 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW)
772
773 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(code, n) \
774 __EVENT_CONSTRAINT(code, n, \
775 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
776 HWEIGHT(n), 0, \
777 PERF_X86_EVENT_PEBS_LD_HSW|PERF_X86_EVENT_EXCL)
778
779 /* Check flags and event code/umask, and set the HSW N/A flag */
780 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(code, n) \
781 __EVENT_CONSTRAINT(code, n, \
782 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
783 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_NA_HSW)
784
785
786 /*
787 * We define the end marker as having a weight of -1
788 * to enable blacklisting of events using a counter bitmask
789 * of zero and thus a weight of zero.
790 * The end marker has a weight that cannot possibly be
791 * obtained from counting the bits in the bitmask.
792 */
793 #define EVENT_CONSTRAINT_END { .weight = -1 }
794
795 /*
796 * Check for end marker with weight == -1
797 */
798 #define for_each_event_constraint(e, c) \
799 for ((e) = (c); (e)->weight != -1; (e)++)
800
801 /*
802 * Extra registers for specific events.
803 *
804 * Some events need large masks and require external MSRs.
805 * Those extra MSRs end up being shared for all events on
806 * a PMU and sometimes between PMU of sibling HT threads.
807 * In either case, the kernel needs to handle conflicting
808 * accesses to those extra, shared, regs. The data structure
809 * to manage those registers is stored in cpu_hw_event.
810 */
811 struct extra_reg {
812 unsigned int event;
813 unsigned int msr;
814 u64 config_mask;
815 u64 valid_mask;
816 int idx; /* per_xxx->regs[] reg index */
817 bool extra_msr_access;
818 };
819
820 #define EVENT_EXTRA_REG(e, ms, m, vm, i) { \
821 .event = (e), \
822 .msr = (ms), \
823 .config_mask = (m), \
824 .valid_mask = (vm), \
825 .idx = EXTRA_REG_##i, \
826 .extra_msr_access = true, \
827 }
828
829 #define INTEL_EVENT_EXTRA_REG(event, msr, vm, idx) \
830 EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm, idx)
831
832 #define INTEL_UEVENT_EXTRA_REG(event, msr, vm, idx) \
833 EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT | \
834 ARCH_PERFMON_EVENTSEL_UMASK, vm, idx)
835
836 #define INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(c) \
837 INTEL_UEVENT_EXTRA_REG(c, \
838 MSR_PEBS_LD_LAT_THRESHOLD, \
839 0xffff, \
840 LDLAT)
841
842 #define EVENT_EXTRA_END EVENT_EXTRA_REG(0, 0, 0, 0, RSP_0)
843
844 union perf_capabilities {
845 struct {
846 u64 lbr_format:6;
847 u64 pebs_trap:1;
848 u64 pebs_arch_reg:1;
849 u64 pebs_format:4;
850 u64 smm_freeze:1;
851 /*
852 * PMU supports separate counter range for writing
853 * values > 32bit.
854 */
855 u64 full_width_write:1;
856 u64 pebs_baseline:1;
857 u64 perf_metrics:1;
858 u64 pebs_output_pt_available:1;
859 u64 pebs_timing_info:1;
860 u64 __reserved:1;
861 u64 rdpmc_metrics_clear:1;
862 };
863 u64 capabilities;
864 };
865
866 struct x86_pmu_quirk {
867 struct x86_pmu_quirk *next;
868 void (*func)(void);
869 };
870
871 union x86_pmu_config {
872 struct {
873 u64 event:8,
874 umask:8,
875 usr:1,
876 os:1,
877 edge:1,
878 pc:1,
879 interrupt:1,
880 __reserved1:1,
881 en:1,
882 inv:1,
883 cmask:8,
884 event2:4,
885 __reserved2:4,
886 go:1,
887 ho:1;
888 } bits;
889 u64 value;
890 };
891
892 #define X86_CONFIG(args...) ((union x86_pmu_config){.bits = {args}}).value
893
894 enum {
895 x86_lbr_exclusive_lbr,
896 x86_lbr_exclusive_bts,
897 x86_lbr_exclusive_pt,
898 x86_lbr_exclusive_max,
899 };
900
901 #define PERF_PEBS_DATA_SOURCE_MAX 0x100
902 #define PERF_PEBS_DATA_SOURCE_MASK (PERF_PEBS_DATA_SOURCE_MAX - 1)
903 #define PERF_PEBS_DATA_SOURCE_GRT_MAX 0x10
904 #define PERF_PEBS_DATA_SOURCE_GRT_MASK (PERF_PEBS_DATA_SOURCE_GRT_MAX - 1)
905
906 #define X86_HYBRID_PMU_ATOM_IDX 0
907 #define X86_HYBRID_PMU_CORE_IDX 1
908 #define X86_HYBRID_PMU_TINY_IDX 2
909
910 enum hybrid_pmu_type {
911 not_hybrid,
912 hybrid_small = BIT(X86_HYBRID_PMU_ATOM_IDX),
913 hybrid_big = BIT(X86_HYBRID_PMU_CORE_IDX),
914 hybrid_tiny = BIT(X86_HYBRID_PMU_TINY_IDX),
915
916 /* The belows are only used for matching */
917 hybrid_big_small = hybrid_big | hybrid_small,
918 hybrid_small_tiny = hybrid_small | hybrid_tiny,
919 hybrid_big_small_tiny = hybrid_big | hybrid_small_tiny,
920 };
921
922 struct arch_pebs_cap {
923 u64 caps;
924 u64 counters;
925 u64 pdists;
926 };
927
928 struct x86_hybrid_pmu {
929 struct pmu pmu;
930 const char *name;
931 enum hybrid_pmu_type pmu_type;
932 cpumask_t supported_cpus;
933 union perf_capabilities intel_cap;
934 u64 intel_ctrl;
935 u64 pebs_events_mask;
936 u64 config_mask;
937 union {
938 u64 cntr_mask64;
939 unsigned long cntr_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
940 };
941 union {
942 u64 fixed_cntr_mask64;
943 unsigned long fixed_cntr_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
944 };
945
946 union {
947 u64 acr_cntr_mask64;
948 unsigned long acr_cntr_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
949 };
950 union {
951 u64 acr_cause_mask64;
952 unsigned long acr_cause_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
953 };
954 struct event_constraint unconstrained;
955
956 u64 hw_cache_event_ids
957 [PERF_COUNT_HW_CACHE_MAX]
958 [PERF_COUNT_HW_CACHE_OP_MAX]
959 [PERF_COUNT_HW_CACHE_RESULT_MAX];
960 u64 hw_cache_extra_regs
961 [PERF_COUNT_HW_CACHE_MAX]
962 [PERF_COUNT_HW_CACHE_OP_MAX]
963 [PERF_COUNT_HW_CACHE_RESULT_MAX];
964 struct event_constraint *event_constraints;
965 struct event_constraint *pebs_constraints;
966 struct extra_reg *extra_regs;
967
968 unsigned int late_ack :1,
969 mid_ack :1,
970 enabled_ack :1;
971
972 struct arch_pebs_cap arch_pebs_cap;
973
974 u64 pebs_data_source[PERF_PEBS_DATA_SOURCE_MAX];
975 };
976
hybrid_pmu(struct pmu * pmu)977 static __always_inline struct x86_hybrid_pmu *hybrid_pmu(struct pmu *pmu)
978 {
979 return container_of(pmu, struct x86_hybrid_pmu, pmu);
980 }
981
982 extern struct static_key_false perf_is_hybrid;
983 #define is_hybrid() static_branch_unlikely(&perf_is_hybrid)
984
985 #define hybrid(_pmu, _field) \
986 (*({ \
987 typeof(&x86_pmu._field) __Fp = &x86_pmu._field; \
988 \
989 if (is_hybrid() && (_pmu)) \
990 __Fp = &hybrid_pmu(_pmu)->_field; \
991 \
992 __Fp; \
993 }))
994
995 #define hybrid_var(_pmu, _var) \
996 (*({ \
997 typeof(&_var) __Fp = &_var; \
998 \
999 if (is_hybrid() && (_pmu)) \
1000 __Fp = &hybrid_pmu(_pmu)->_var; \
1001 \
1002 __Fp; \
1003 }))
1004
1005 #define hybrid_bit(_pmu, _field) \
1006 ({ \
1007 bool __Fp = x86_pmu._field; \
1008 \
1009 if (is_hybrid() && (_pmu)) \
1010 __Fp = hybrid_pmu(_pmu)->_field; \
1011 \
1012 __Fp; \
1013 })
1014
1015 /*
1016 * struct x86_pmu - generic x86 pmu
1017 */
1018 struct x86_pmu {
1019 /*
1020 * Generic x86 PMC bits
1021 */
1022 const char *name;
1023 int version;
1024 int (*handle_irq)(struct pt_regs *);
1025 void (*disable_all)(void);
1026 void (*enable_all)(int added);
1027 void (*enable)(struct perf_event *);
1028 void (*disable)(struct perf_event *);
1029 void (*assign)(struct perf_event *event, int idx);
1030 void (*add)(struct perf_event *);
1031 void (*del)(struct perf_event *);
1032 void (*read)(struct perf_event *event);
1033 int (*set_period)(struct perf_event *event);
1034 u64 (*update)(struct perf_event *event);
1035 int (*hw_config)(struct perf_event *event);
1036 int (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign);
1037 void (*late_setup)(void);
1038 void (*pebs_enable)(struct perf_event *event);
1039 void (*pebs_disable)(struct perf_event *event);
1040 void (*pebs_enable_all)(void);
1041 void (*pebs_disable_all)(void);
1042 unsigned eventsel;
1043 unsigned perfctr;
1044 unsigned fixedctr;
1045 int (*addr_offset)(int index, bool eventsel);
1046 int (*rdpmc_index)(int index);
1047 u64 (*event_map)(int);
1048 int max_events;
1049 u64 config_mask;
1050 union {
1051 u64 cntr_mask64;
1052 unsigned long cntr_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
1053 };
1054 union {
1055 u64 fixed_cntr_mask64;
1056 unsigned long fixed_cntr_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
1057 };
1058 union {
1059 u64 acr_cntr_mask64;
1060 unsigned long acr_cntr_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
1061 };
1062 union {
1063 u64 acr_cause_mask64;
1064 unsigned long acr_cause_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
1065 };
1066 int cntval_bits;
1067 u64 cntval_mask;
1068 union {
1069 unsigned long events_maskl;
1070 unsigned long events_mask[BITS_TO_LONGS(ARCH_PERFMON_EVENTS_COUNT)];
1071 };
1072 int events_mask_len;
1073 int apic;
1074 u64 max_period;
1075 struct event_constraint *
1076 (*get_event_constraints)(struct cpu_hw_events *cpuc,
1077 int idx,
1078 struct perf_event *event);
1079
1080 void (*put_event_constraints)(struct cpu_hw_events *cpuc,
1081 struct perf_event *event);
1082
1083 void (*start_scheduling)(struct cpu_hw_events *cpuc);
1084
1085 void (*commit_scheduling)(struct cpu_hw_events *cpuc, int idx, int cntr);
1086
1087 void (*stop_scheduling)(struct cpu_hw_events *cpuc);
1088
1089 struct event_constraint *event_constraints;
1090 struct x86_pmu_quirk *quirks;
1091 void (*limit_period)(struct perf_event *event, s64 *l);
1092
1093 /* PMI handler bits */
1094 unsigned int late_ack :1,
1095 mid_ack :1,
1096 enabled_ack :1;
1097 /*
1098 * sysfs attrs
1099 */
1100 int attr_rdpmc_broken;
1101 int attr_rdpmc;
1102 struct attribute **format_attrs;
1103
1104 ssize_t (*events_sysfs_show)(char *page, u64 config);
1105 const struct attribute_group **attr_update;
1106
1107 unsigned long attr_freeze_on_smi;
1108
1109 /*
1110 * CPU Hotplug hooks
1111 */
1112 int (*cpu_prepare)(int cpu);
1113 void (*cpu_starting)(int cpu);
1114 void (*cpu_dying)(int cpu);
1115 void (*cpu_dead)(int cpu);
1116
1117 void (*check_microcode)(void);
1118 void (*sched_task)(struct perf_event_pmu_context *pmu_ctx,
1119 struct task_struct *task, bool sched_in);
1120
1121 /*
1122 * Intel Arch Perfmon v2+
1123 */
1124 u64 intel_ctrl;
1125 union perf_capabilities intel_cap;
1126
1127 /*
1128 * Intel DebugStore and PEBS bits
1129 */
1130 unsigned int bts :1,
1131 bts_active :1,
1132 ds_pebs :1,
1133 pebs_active :1,
1134 pebs_broken :1,
1135 pebs_prec_dist :1,
1136 pebs_no_tlb :1,
1137 pebs_no_isolation :1,
1138 pebs_block :1,
1139 pebs_ept :1,
1140 arch_pebs :1;
1141 int pebs_record_size;
1142 int pebs_buffer_size;
1143 u64 pebs_events_mask;
1144 int (*drain_pebs)(struct pt_regs *regs, struct perf_sample_data *data);
1145 struct event_constraint *pebs_constraints;
1146 void (*pebs_aliases)(struct perf_event *event);
1147 u64 (*pebs_latency_data)(struct perf_event *event, u64 status);
1148 unsigned long large_pebs_flags;
1149 u64 rtm_abort_event;
1150 u64 pebs_capable;
1151
1152 /*
1153 * Intel Architectural PEBS
1154 */
1155 struct arch_pebs_cap arch_pebs_cap;
1156
1157 /*
1158 * Intel LBR
1159 */
1160 unsigned int lbr_tos, lbr_from, lbr_to,
1161 lbr_info, lbr_nr; /* LBR base regs and size */
1162 union {
1163 u64 lbr_sel_mask; /* LBR_SELECT valid bits */
1164 u64 lbr_ctl_mask; /* LBR_CTL valid bits */
1165 };
1166 union {
1167 const int *lbr_sel_map; /* lbr_select mappings */
1168 int *lbr_ctl_map; /* LBR_CTL mappings */
1169 };
1170 u64 lbr_callstack_users; /* lbr callstack system wide users */
1171 bool lbr_double_abort; /* duplicated lbr aborts */
1172 bool lbr_pt_coexist; /* (LBR|BTS) may coexist with PT */
1173
1174 unsigned int lbr_has_info:1;
1175 unsigned int lbr_has_tsx:1;
1176 unsigned int lbr_from_flags:1;
1177 unsigned int lbr_to_cycles:1;
1178
1179 /*
1180 * Intel Architectural LBR CPUID Enumeration
1181 */
1182 unsigned int lbr_depth_mask:8;
1183 unsigned int lbr_deep_c_reset:1;
1184 unsigned int lbr_lip:1;
1185 unsigned int lbr_cpl:1;
1186 unsigned int lbr_filter:1;
1187 unsigned int lbr_call_stack:1;
1188 unsigned int lbr_mispred:1;
1189 unsigned int lbr_timed_lbr:1;
1190 unsigned int lbr_br_type:1;
1191 unsigned int lbr_counters:4;
1192
1193 void (*lbr_reset)(void);
1194 void (*lbr_read)(struct cpu_hw_events *cpuc);
1195 void (*lbr_save)(void *ctx);
1196 void (*lbr_restore)(void *ctx);
1197
1198 /*
1199 * Intel PT/LBR/BTS are exclusive
1200 */
1201 atomic_t lbr_exclusive[x86_lbr_exclusive_max];
1202
1203 /*
1204 * Intel perf metrics
1205 */
1206 int num_topdown_events;
1207
1208 /*
1209 * AMD bits
1210 */
1211 unsigned int amd_nb_constraints : 1;
1212 u64 perf_ctr_pair_en;
1213
1214 /*
1215 * Extra registers for events
1216 */
1217 struct extra_reg *extra_regs;
1218 unsigned int flags;
1219
1220 /*
1221 * Extended regs, e.g., vector registers
1222 * Utilize the same format as the XFEATURE_MASK_*
1223 */
1224 u64 ext_regs_mask;
1225
1226 /*
1227 * Intel host/guest support (KVM)
1228 */
1229 struct perf_guest_switch_msr *(*guest_get_msrs)(int *nr,
1230 struct x86_guest_pebs *guest_pebs);
1231
1232 /*
1233 * Check period value for PERF_EVENT_IOC_PERIOD ioctl.
1234 */
1235 int (*check_period) (struct perf_event *event, u64 period);
1236
1237 int (*aux_output_match) (struct perf_event *event);
1238
1239 void (*filter)(struct pmu *pmu, int cpu, bool *ret);
1240 /*
1241 * Hybrid support
1242 *
1243 * Most PMU capabilities are the same among different hybrid PMUs.
1244 * The global x86_pmu saves the architecture capabilities, which
1245 * are available for all PMUs. The hybrid_pmu only includes the
1246 * unique capabilities.
1247 */
1248 int num_hybrid_pmus;
1249 struct x86_hybrid_pmu *hybrid_pmu __counted_by_ptr(num_hybrid_pmus);
1250 enum intel_cpu_type (*get_hybrid_cpu_type) (void);
1251 };
1252
1253 struct x86_perf_task_context_opt {
1254 int lbr_callstack_users;
1255 int lbr_stack_state;
1256 int log_id;
1257 };
1258
1259 struct x86_perf_task_context {
1260 u64 lbr_sel;
1261 int tos;
1262 int valid_lbrs;
1263 struct x86_perf_task_context_opt opt;
1264 struct lbr_entry lbr[MAX_LBR_ENTRIES];
1265 };
1266
1267 struct x86_perf_task_context_arch_lbr {
1268 struct x86_perf_task_context_opt opt;
1269 struct lbr_entry entries[];
1270 };
1271
1272 /*
1273 * Add padding to guarantee the 64-byte alignment of the state buffer.
1274 *
1275 * The structure is dynamically allocated. The size of the LBR state may vary
1276 * based on the number of LBR registers.
1277 *
1278 * Do not put anything after the LBR state.
1279 */
1280 struct x86_perf_task_context_arch_lbr_xsave {
1281 struct x86_perf_task_context_opt opt;
1282
1283 union {
1284 struct xregs_state xsave;
1285 struct {
1286 struct fxregs_state i387;
1287 struct xstate_header header;
1288 struct arch_lbr_state lbr;
1289 } __attribute__ ((packed, aligned (XSAVE_ALIGNMENT)));
1290 };
1291 };
1292
1293 #define x86_add_quirk(func_) \
1294 do { \
1295 static struct x86_pmu_quirk __quirk __initdata = { \
1296 .func = func_, \
1297 }; \
1298 __quirk.next = x86_pmu.quirks; \
1299 x86_pmu.quirks = &__quirk; \
1300 } while (0)
1301
1302 /*
1303 * x86_pmu flags
1304 */
1305 #define PMU_FL_NO_HT_SHARING 0x1 /* no hyper-threading resource sharing */
1306 #define PMU_FL_HAS_RSP_1 0x2 /* has 2 equivalent offcore_rsp regs */
1307 #define PMU_FL_EXCL_CNTRS 0x4 /* has exclusive counter requirements */
1308 #define PMU_FL_EXCL_ENABLED 0x8 /* exclusive counter active */
1309 #define PMU_FL_PEBS_ALL 0x10 /* all events are valid PEBS events */
1310 #define PMU_FL_TFA 0x20 /* deal with TSX force abort */
1311 #define PMU_FL_PAIR 0x40 /* merge counters for large incr. events */
1312 #define PMU_FL_INSTR_LATENCY 0x80 /* Support Instruction Latency in PEBS Memory Info Record */
1313 #define PMU_FL_MEM_LOADS_AUX 0x100 /* Require an auxiliary event for the complete memory info */
1314 #define PMU_FL_RETIRE_LATENCY 0x200 /* Support Retire Latency in PEBS */
1315 #define PMU_FL_BR_CNTR 0x400 /* Support branch counter logging */
1316 #define PMU_FL_DYN_CONSTRAINT 0x800 /* Needs dynamic constraint */
1317 #define PMU_FL_HAS_OMR 0x1000 /* has 4 equivalent OMR regs */
1318
1319 #define EVENT_VAR(_id) event_attr_##_id
1320 #define EVENT_PTR(_id) &event_attr_##_id.attr.attr
1321
1322 #define EVENT_ATTR(_name, _id) \
1323 static struct perf_pmu_events_attr EVENT_VAR(_id) = { \
1324 .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \
1325 .id = PERF_COUNT_HW_##_id, \
1326 .event_str = NULL, \
1327 };
1328
1329 #define EVENT_ATTR_STR(_name, v, str) \
1330 static struct perf_pmu_events_attr event_attr_##v = { \
1331 .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \
1332 .id = 0, \
1333 .event_str = str, \
1334 };
1335
1336 #define EVENT_ATTR_STR_HT(_name, v, noht, ht) \
1337 static struct perf_pmu_events_ht_attr event_attr_##v = { \
1338 .attr = __ATTR(_name, 0444, events_ht_sysfs_show, NULL),\
1339 .id = 0, \
1340 .event_str_noht = noht, \
1341 .event_str_ht = ht, \
1342 }
1343
1344 #define EVENT_ATTR_STR_HYBRID(_name, v, str, _pmu) \
1345 static struct perf_pmu_events_hybrid_attr event_attr_##v = { \
1346 .attr = __ATTR(_name, 0444, events_hybrid_sysfs_show, NULL),\
1347 .id = 0, \
1348 .event_str = str, \
1349 .pmu_type = _pmu, \
1350 }
1351
1352 #define FORMAT_HYBRID_PTR(_id) (&format_attr_hybrid_##_id.attr.attr)
1353
1354 #define FORMAT_ATTR_HYBRID(_name, _pmu) \
1355 static struct perf_pmu_format_hybrid_attr format_attr_hybrid_##_name = {\
1356 .attr = __ATTR_RO(_name), \
1357 .pmu_type = _pmu, \
1358 }
1359
1360 struct pmu *x86_get_static_pmu(void);
1361 struct pmu *x86_get_pmu(unsigned int cpu);
1362 extern struct x86_pmu x86_pmu __read_mostly;
1363
1364 DECLARE_STATIC_CALL(x86_pmu_set_period, *x86_pmu.set_period);
1365 DECLARE_STATIC_CALL(x86_pmu_update, *x86_pmu.update);
1366 DECLARE_STATIC_CALL(x86_pmu_drain_pebs, *x86_pmu.drain_pebs);
1367 DECLARE_STATIC_CALL(x86_pmu_late_setup, *x86_pmu.late_setup);
1368 DECLARE_STATIC_CALL(x86_pmu_pebs_enable, *x86_pmu.pebs_enable);
1369 DECLARE_STATIC_CALL(x86_pmu_pebs_disable, *x86_pmu.pebs_disable);
1370 DECLARE_STATIC_CALL(x86_pmu_pebs_enable_all, *x86_pmu.pebs_enable_all);
1371 DECLARE_STATIC_CALL(x86_pmu_pebs_disable_all, *x86_pmu.pebs_disable_all);
1372
task_context_opt(void * ctx)1373 static __always_inline struct x86_perf_task_context_opt *task_context_opt(void *ctx)
1374 {
1375 if (cpu_feature_enabled(X86_FEATURE_ARCH_LBR))
1376 return &((struct x86_perf_task_context_arch_lbr *)ctx)->opt;
1377
1378 return &((struct x86_perf_task_context *)ctx)->opt;
1379 }
1380
x86_pmu_has_lbr_callstack(void)1381 static inline bool x86_pmu_has_lbr_callstack(void)
1382 {
1383 return x86_pmu.lbr_sel_map &&
1384 x86_pmu.lbr_sel_map[PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT] > 0;
1385 }
1386
1387 DECLARE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
1388 DECLARE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
1389
1390 int x86_perf_event_set_period(struct perf_event *event);
1391
1392 /*
1393 * Generalized hw caching related hw_event table, filled
1394 * in on a per model basis. A value of 0 means
1395 * 'not supported', -1 means 'hw_event makes no sense on
1396 * this CPU', any other value means the raw hw_event
1397 * ID.
1398 */
1399
1400 #define C(x) PERF_COUNT_HW_CACHE_##x
1401
1402 extern u64 __read_mostly hw_cache_event_ids
1403 [PERF_COUNT_HW_CACHE_MAX]
1404 [PERF_COUNT_HW_CACHE_OP_MAX]
1405 [PERF_COUNT_HW_CACHE_RESULT_MAX];
1406 extern u64 __read_mostly hw_cache_extra_regs
1407 [PERF_COUNT_HW_CACHE_MAX]
1408 [PERF_COUNT_HW_CACHE_OP_MAX]
1409 [PERF_COUNT_HW_CACHE_RESULT_MAX];
1410
1411 u64 x86_perf_event_update(struct perf_event *event);
1412
intel_pmu_topdown_event_update(struct perf_event * event,u64 * val)1413 static inline u64 intel_pmu_topdown_event_update(struct perf_event *event, u64 *val)
1414 {
1415 return x86_perf_event_update(event);
1416 }
1417 DECLARE_STATIC_CALL(intel_pmu_update_topdown_event, intel_pmu_topdown_event_update);
1418
x86_pmu_config_addr(int index)1419 static inline unsigned int x86_pmu_config_addr(int index)
1420 {
1421 return x86_pmu.eventsel + (x86_pmu.addr_offset ?
1422 x86_pmu.addr_offset(index, true) : index);
1423 }
1424
x86_pmu_event_addr(int index)1425 static inline unsigned int x86_pmu_event_addr(int index)
1426 {
1427 return x86_pmu.perfctr + (x86_pmu.addr_offset ?
1428 x86_pmu.addr_offset(index, false) : index);
1429 }
1430
x86_pmu_fixed_ctr_addr(int index)1431 static inline unsigned int x86_pmu_fixed_ctr_addr(int index)
1432 {
1433 return x86_pmu.fixedctr + (x86_pmu.addr_offset ?
1434 x86_pmu.addr_offset(index, false) : index);
1435 }
1436
x86_pmu_rdpmc_index(int index)1437 static inline int x86_pmu_rdpmc_index(int index)
1438 {
1439 return x86_pmu.rdpmc_index ? x86_pmu.rdpmc_index(index) : index;
1440 }
1441
1442 bool check_hw_exists(unsigned long *cntr_mask,
1443 unsigned long *fixed_cntr_mask);
1444
1445 int x86_add_exclusive(unsigned int what);
1446
1447 void x86_del_exclusive(unsigned int what);
1448
1449 int x86_reserve_hardware(void);
1450
1451 void x86_release_hardware(void);
1452
1453 int x86_pmu_max_precise(struct pmu *pmu);
1454
1455 void hw_perf_lbr_event_destroy(struct perf_event *event);
1456
1457 int x86_setup_perfctr(struct perf_event *event);
1458
1459 int x86_pmu_hw_config(struct perf_event *event);
1460
1461 void x86_pmu_disable_all(void);
1462
has_amd_brs(struct hw_perf_event * hwc)1463 static inline bool has_amd_brs(struct hw_perf_event *hwc)
1464 {
1465 return hwc->flags & PERF_X86_EVENT_AMD_BRS;
1466 }
1467
is_counter_pair(struct hw_perf_event * hwc)1468 static inline bool is_counter_pair(struct hw_perf_event *hwc)
1469 {
1470 return hwc->flags & PERF_X86_EVENT_PAIR;
1471 }
1472
__x86_pmu_enable_event(struct hw_perf_event * hwc,u64 enable_mask)1473 static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc,
1474 u64 enable_mask)
1475 {
1476 u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask);
1477
1478 if (hwc->extra_reg.reg)
1479 wrmsrq(hwc->extra_reg.reg, hwc->extra_reg.config);
1480
1481 /*
1482 * Add enabled Merge event on next counter
1483 * if large increment event being enabled on this counter
1484 */
1485 if (is_counter_pair(hwc))
1486 wrmsrq(x86_pmu_config_addr(hwc->idx + 1), x86_pmu.perf_ctr_pair_en);
1487
1488 wrmsrq(hwc->config_base, (hwc->config | enable_mask) & ~disable_mask);
1489 }
1490
1491 void x86_pmu_enable_all(int added);
1492
1493 int perf_assign_events(struct event_constraint **constraints, int n,
1494 int wmin, int wmax, int gpmax, int *assign);
1495 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign);
1496
1497 void x86_pmu_stop(struct perf_event *event, int flags);
1498
x86_pmu_disable_event(struct perf_event * event)1499 static inline void x86_pmu_disable_event(struct perf_event *event)
1500 {
1501 u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask);
1502 struct hw_perf_event *hwc = &event->hw;
1503
1504 wrmsrq(hwc->config_base, hwc->config & ~disable_mask);
1505
1506 if (is_counter_pair(hwc))
1507 wrmsrq(x86_pmu_config_addr(hwc->idx + 1), 0);
1508 }
1509
1510 void x86_pmu_enable_event(struct perf_event *event);
1511
1512 int x86_pmu_handle_irq(struct pt_regs *regs);
1513
1514 void x86_pmu_clear_perf_regs(struct pt_regs *regs);
1515
1516 void x86_pmu_update_perf_regs(struct perf_event *event,
1517 struct perf_sample_data *data,
1518 struct pt_regs *regs,
1519 bool from_pebs);
1520
1521 void x86_pmu_show_pmu_cap(struct pmu *pmu);
1522
x86_pmu_num_counters(struct pmu * pmu)1523 static inline int x86_pmu_num_counters(struct pmu *pmu)
1524 {
1525 return hweight64(hybrid(pmu, cntr_mask64));
1526 }
1527
x86_pmu_max_num_counters(struct pmu * pmu)1528 static inline int x86_pmu_max_num_counters(struct pmu *pmu)
1529 {
1530 return fls64(hybrid(pmu, cntr_mask64));
1531 }
1532
x86_pmu_num_counters_fixed(struct pmu * pmu)1533 static inline int x86_pmu_num_counters_fixed(struct pmu *pmu)
1534 {
1535 return hweight64(hybrid(pmu, fixed_cntr_mask64));
1536 }
1537
x86_pmu_max_num_counters_fixed(struct pmu * pmu)1538 static inline int x86_pmu_max_num_counters_fixed(struct pmu *pmu)
1539 {
1540 return fls64(hybrid(pmu, fixed_cntr_mask64));
1541 }
1542
x86_pmu_get_event_config(struct perf_event * event)1543 static inline u64 x86_pmu_get_event_config(struct perf_event *event)
1544 {
1545 return event->attr.config & hybrid(event->pmu, config_mask);
1546 }
1547
x86_pmu_has_rdpmc_user_disable(struct pmu * pmu)1548 static inline bool x86_pmu_has_rdpmc_user_disable(struct pmu *pmu)
1549 {
1550 return !!(hybrid(pmu, config_mask) &
1551 ARCH_PERFMON_EVENTSEL_RDPMC_USER_DISABLE);
1552 }
1553
1554 extern struct event_constraint emptyconstraint;
1555
1556 extern struct event_constraint unconstrained;
1557
kernel_ip(unsigned long ip)1558 static inline bool kernel_ip(unsigned long ip)
1559 {
1560 #ifdef CONFIG_X86_32
1561 return ip > PAGE_OFFSET;
1562 #else
1563 return (long)ip < 0;
1564 #endif
1565 }
1566
1567 /*
1568 * Not all PMUs provide the right context information to place the reported IP
1569 * into full context. Specifically segment registers are typically not
1570 * supplied.
1571 *
1572 * Assuming the address is a linear address (it is for IBS), we fake the CS and
1573 * vm86 mode using the known zero-based code segment and 'fix up' the registers
1574 * to reflect this.
1575 *
1576 * Intel PEBS/LBR appear to typically provide the effective address, nothing
1577 * much we can do about that but pray and treat it like a linear address.
1578 */
set_linear_ip(struct pt_regs * regs,unsigned long ip)1579 static inline void set_linear_ip(struct pt_regs *regs, unsigned long ip)
1580 {
1581 regs->cs = kernel_ip(ip) ? __KERNEL_CS : __USER_CS;
1582 if (regs->flags & X86_VM_MASK)
1583 regs->flags ^= (PERF_EFLAGS_VM | X86_VM_MASK);
1584 regs->ip = ip;
1585 }
1586
1587 /*
1588 * x86control flow change classification
1589 * x86control flow changes include branches, interrupts, traps, faults
1590 */
1591 enum {
1592 X86_BR_NONE = 0, /* unknown */
1593
1594 X86_BR_USER = 1 << 0, /* branch target is user */
1595 X86_BR_KERNEL = 1 << 1, /* branch target is kernel */
1596
1597 X86_BR_CALL = 1 << 2, /* call */
1598 X86_BR_RET = 1 << 3, /* return */
1599 X86_BR_SYSCALL = 1 << 4, /* syscall */
1600 X86_BR_SYSRET = 1 << 5, /* syscall return */
1601 X86_BR_INT = 1 << 6, /* sw interrupt */
1602 X86_BR_IRET = 1 << 7, /* return from interrupt */
1603 X86_BR_JCC = 1 << 8, /* conditional */
1604 X86_BR_JMP = 1 << 9, /* jump */
1605 X86_BR_IRQ = 1 << 10,/* hw interrupt or trap or fault */
1606 X86_BR_IND_CALL = 1 << 11,/* indirect calls */
1607 X86_BR_ABORT = 1 << 12,/* transaction abort */
1608 X86_BR_IN_TX = 1 << 13,/* in transaction */
1609 X86_BR_NO_TX = 1 << 14,/* not in transaction */
1610 X86_BR_ZERO_CALL = 1 << 15,/* zero length call */
1611 X86_BR_CALL_STACK = 1 << 16,/* call stack */
1612 X86_BR_IND_JMP = 1 << 17,/* indirect jump */
1613
1614 X86_BR_TYPE_SAVE = 1 << 18,/* indicate to save branch type */
1615
1616 };
1617
1618 #define X86_BR_PLM (X86_BR_USER | X86_BR_KERNEL)
1619 #define X86_BR_ANYTX (X86_BR_NO_TX | X86_BR_IN_TX)
1620
1621 #define X86_BR_ANY \
1622 (X86_BR_CALL |\
1623 X86_BR_RET |\
1624 X86_BR_SYSCALL |\
1625 X86_BR_SYSRET |\
1626 X86_BR_INT |\
1627 X86_BR_IRET |\
1628 X86_BR_JCC |\
1629 X86_BR_JMP |\
1630 X86_BR_IRQ |\
1631 X86_BR_ABORT |\
1632 X86_BR_IND_CALL |\
1633 X86_BR_IND_JMP |\
1634 X86_BR_ZERO_CALL)
1635
1636 #define X86_BR_ALL (X86_BR_PLM | X86_BR_ANY)
1637
1638 #define X86_BR_ANY_CALL \
1639 (X86_BR_CALL |\
1640 X86_BR_IND_CALL |\
1641 X86_BR_ZERO_CALL |\
1642 X86_BR_SYSCALL |\
1643 X86_BR_IRQ |\
1644 X86_BR_INT)
1645
1646 int common_branch_type(int type);
1647 int branch_type(unsigned long from, unsigned long to, int abort);
1648 int branch_type_fused(unsigned long from, unsigned long to, int abort,
1649 int *offset);
1650
1651 ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event);
1652 ssize_t intel_event_sysfs_show(char *page, u64 config);
1653
1654 ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr,
1655 char *page);
1656 ssize_t events_ht_sysfs_show(struct device *dev, struct device_attribute *attr,
1657 char *page);
1658 ssize_t events_hybrid_sysfs_show(struct device *dev,
1659 struct device_attribute *attr,
1660 char *page);
1661
1662 #ifdef CONFIG_CPU_SUP_AMD
1663
1664 int amd_pmu_init(void);
1665
1666 int amd_pmu_lbr_init(void);
1667 void amd_pmu_lbr_reset(void);
1668 void amd_pmu_lbr_read(void);
1669 void amd_pmu_lbr_add(struct perf_event *event);
1670 void amd_pmu_lbr_del(struct perf_event *event);
1671 void amd_pmu_lbr_sched_task(struct perf_event_pmu_context *pmu_ctx,
1672 struct task_struct *task, bool sched_in);
1673 void amd_pmu_lbr_enable_all(void);
1674 void amd_pmu_lbr_disable_all(void);
1675 int amd_pmu_lbr_hw_config(struct perf_event *event);
1676
__amd_pmu_lbr_disable(void)1677 static __always_inline void __amd_pmu_lbr_disable(void)
1678 {
1679 u64 dbg_ctl, dbg_extn_cfg;
1680
1681 rdmsrq(MSR_AMD_DBG_EXTN_CFG, dbg_extn_cfg);
1682 wrmsrq(MSR_AMD_DBG_EXTN_CFG, dbg_extn_cfg & ~DBG_EXTN_CFG_LBRV2EN);
1683
1684 if (cpu_feature_enabled(X86_FEATURE_AMD_LBR_PMC_FREEZE)) {
1685 rdmsrq(MSR_IA32_DEBUGCTLMSR, dbg_ctl);
1686 wrmsrq(MSR_IA32_DEBUGCTLMSR, dbg_ctl & ~DEBUGCTLMSR_FREEZE_LBRS_ON_PMI);
1687 }
1688 }
1689
1690 #ifdef CONFIG_PERF_EVENTS_AMD_BRS
1691
1692 #define AMD_FAM19H_BRS_EVENT 0xc4 /* RETIRED_TAKEN_BRANCH_INSTRUCTIONS */
1693
1694 int amd_brs_init(void);
1695 void amd_brs_disable(void);
1696 void amd_brs_enable(void);
1697 void amd_brs_enable_all(void);
1698 void amd_brs_disable_all(void);
1699 void amd_brs_drain(void);
1700 void amd_brs_lopwr_init(void);
1701 int amd_brs_hw_config(struct perf_event *event);
1702 void amd_brs_reset(void);
1703
amd_pmu_brs_add(struct perf_event * event)1704 static inline void amd_pmu_brs_add(struct perf_event *event)
1705 {
1706 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1707
1708 perf_sched_cb_inc(event->pmu);
1709 cpuc->lbr_users++;
1710 /*
1711 * No need to reset BRS because it is reset
1712 * on brs_enable() and it is saturating
1713 */
1714 }
1715
amd_pmu_brs_del(struct perf_event * event)1716 static inline void amd_pmu_brs_del(struct perf_event *event)
1717 {
1718 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1719
1720 cpuc->lbr_users--;
1721 WARN_ON_ONCE(cpuc->lbr_users < 0);
1722
1723 perf_sched_cb_dec(event->pmu);
1724 }
1725
1726 void amd_pmu_brs_sched_task(struct perf_event_pmu_context *pmu_ctx,
1727 struct task_struct *task, bool sched_in);
1728 #else
amd_brs_init(void)1729 static inline int amd_brs_init(void)
1730 {
1731 return 0;
1732 }
amd_brs_disable(void)1733 static inline void amd_brs_disable(void) {}
amd_brs_enable(void)1734 static inline void amd_brs_enable(void) {}
amd_brs_drain(void)1735 static inline void amd_brs_drain(void) {}
amd_brs_lopwr_init(void)1736 static inline void amd_brs_lopwr_init(void) {}
amd_brs_disable_all(void)1737 static inline void amd_brs_disable_all(void) {}
amd_brs_hw_config(struct perf_event * event)1738 static inline int amd_brs_hw_config(struct perf_event *event)
1739 {
1740 return 0;
1741 }
amd_brs_reset(void)1742 static inline void amd_brs_reset(void) {}
1743
amd_pmu_brs_add(struct perf_event * event)1744 static inline void amd_pmu_brs_add(struct perf_event *event)
1745 {
1746 }
1747
amd_pmu_brs_del(struct perf_event * event)1748 static inline void amd_pmu_brs_del(struct perf_event *event)
1749 {
1750 }
1751
amd_pmu_brs_sched_task(struct perf_event_pmu_context * pmu_ctx,struct task_struct * task,bool sched_in)1752 static inline void amd_pmu_brs_sched_task(struct perf_event_pmu_context *pmu_ctx,
1753 struct task_struct *task, bool sched_in)
1754 {
1755 }
1756
amd_brs_enable_all(void)1757 static inline void amd_brs_enable_all(void)
1758 {
1759 }
1760
1761 #endif
1762
1763 #else /* CONFIG_CPU_SUP_AMD */
1764
amd_pmu_init(void)1765 static inline int amd_pmu_init(void)
1766 {
1767 return 0;
1768 }
1769
amd_brs_init(void)1770 static inline int amd_brs_init(void)
1771 {
1772 return -EOPNOTSUPP;
1773 }
1774
amd_brs_drain(void)1775 static inline void amd_brs_drain(void)
1776 {
1777 }
1778
amd_brs_enable_all(void)1779 static inline void amd_brs_enable_all(void)
1780 {
1781 }
1782
amd_brs_disable_all(void)1783 static inline void amd_brs_disable_all(void)
1784 {
1785 }
1786 #endif /* CONFIG_CPU_SUP_AMD */
1787
is_pebs_pt(struct perf_event * event)1788 static inline int is_pebs_pt(struct perf_event *event)
1789 {
1790 return !!(event->hw.flags & PERF_X86_EVENT_PEBS_VIA_PT);
1791 }
1792
1793 #ifdef CONFIG_CPU_SUP_INTEL
1794
intel_pmu_has_bts_period(struct perf_event * event,u64 period)1795 static inline bool intel_pmu_has_bts_period(struct perf_event *event, u64 period)
1796 {
1797 struct hw_perf_event *hwc = &event->hw;
1798 unsigned int hw_event, bts_event;
1799
1800 /*
1801 * Only use BTS for fixed rate period==1 events.
1802 */
1803 if (event->attr.freq || period != 1)
1804 return false;
1805
1806 /*
1807 * BTS doesn't virtualize.
1808 */
1809 if (event->attr.exclude_host)
1810 return false;
1811
1812 hw_event = hwc->config & INTEL_ARCH_EVENT_MASK;
1813 bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
1814
1815 return hw_event == bts_event;
1816 }
1817
intel_pmu_has_bts(struct perf_event * event)1818 static inline bool intel_pmu_has_bts(struct perf_event *event)
1819 {
1820 struct hw_perf_event *hwc = &event->hw;
1821
1822 return intel_pmu_has_bts_period(event, hwc->sample_period);
1823 }
1824
__intel_pmu_pebs_disable_all(void)1825 static __always_inline void __intel_pmu_pebs_disable_all(void)
1826 {
1827 wrmsrq(MSR_IA32_PEBS_ENABLE, 0);
1828 }
1829
__intel_pmu_arch_lbr_disable(void)1830 static __always_inline void __intel_pmu_arch_lbr_disable(void)
1831 {
1832 wrmsrq(MSR_ARCH_LBR_CTL, 0);
1833 }
1834
__intel_pmu_lbr_disable(void)1835 static __always_inline void __intel_pmu_lbr_disable(void)
1836 {
1837 u64 debugctl;
1838
1839 rdmsrq(MSR_IA32_DEBUGCTLMSR, debugctl);
1840 debugctl &= ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_FREEZE_LBRS_ON_PMI);
1841 wrmsrq(MSR_IA32_DEBUGCTLMSR, debugctl);
1842 }
1843
1844 extern int __intel_pmu_quiesce(void);
1845 extern void __intel_pmu_resume(int pmu_enabled);
1846
1847 int intel_pmu_save_and_restart(struct perf_event *event);
1848
1849 struct event_constraint *
1850 x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
1851 struct perf_event *event);
1852
1853 extern int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu);
1854 extern void intel_cpuc_finish(struct cpu_hw_events *cpuc);
1855
1856 int intel_pmu_init(void);
1857
1858 int alloc_arch_pebs_buf_on_cpu(int cpu);
1859
1860 void release_arch_pebs_buf_on_cpu(int cpu);
1861
1862 void init_arch_pebs_on_cpu(int cpu);
1863
1864 void fini_arch_pebs_on_cpu(int cpu);
1865
1866 void init_debug_store_on_cpu(int cpu);
1867
1868 void fini_debug_store_on_cpu(int cpu);
1869
1870 void release_ds_buffers(void);
1871
1872 void reserve_ds_buffers(void);
1873
1874 void release_lbr_buffers(void);
1875
1876 void reserve_lbr_buffers(void);
1877
1878 extern struct event_constraint bts_constraint;
1879 extern struct event_constraint vlbr_constraint;
1880
1881 void intel_pmu_enable_bts(u64 config);
1882
1883 void intel_pmu_disable_bts(void);
1884
1885 int intel_pmu_drain_bts_buffer(void);
1886
1887 void intel_pmu_late_setup(void);
1888
1889 u64 grt_latency_data(struct perf_event *event, u64 status);
1890
1891 u64 cmt_latency_data(struct perf_event *event, u64 status);
1892
1893 u64 lnl_latency_data(struct perf_event *event, u64 status);
1894
1895 u64 arl_h_latency_data(struct perf_event *event, u64 status);
1896
1897 u64 pnc_latency_data(struct perf_event *event, u64 status);
1898
1899 u64 nvl_latency_data(struct perf_event *event, u64 status);
1900
1901 extern struct event_constraint intel_core2_pebs_event_constraints[];
1902
1903 extern struct event_constraint intel_atom_pebs_event_constraints[];
1904
1905 extern struct event_constraint intel_slm_pebs_event_constraints[];
1906
1907 extern struct event_constraint intel_glm_pebs_event_constraints[];
1908
1909 extern struct event_constraint intel_glp_pebs_event_constraints[];
1910
1911 extern struct event_constraint intel_grt_pebs_event_constraints[];
1912
1913 extern struct event_constraint intel_cmt_pebs_event_constraints[];
1914
1915 extern struct event_constraint intel_dkt_pebs_event_constraints[];
1916
1917 extern struct event_constraint intel_nehalem_pebs_event_constraints[];
1918
1919 extern struct event_constraint intel_westmere_pebs_event_constraints[];
1920
1921 extern struct event_constraint intel_snb_pebs_event_constraints[];
1922
1923 extern struct event_constraint intel_ivb_pebs_event_constraints[];
1924
1925 extern struct event_constraint intel_hsw_pebs_event_constraints[];
1926
1927 extern struct event_constraint intel_bdw_pebs_event_constraints[];
1928
1929 extern struct event_constraint intel_skl_pebs_event_constraints[];
1930
1931 extern struct event_constraint intel_icl_pebs_event_constraints[];
1932
1933 extern struct event_constraint intel_glc_pebs_event_constraints[];
1934
1935 extern struct event_constraint intel_lnc_pebs_event_constraints[];
1936
1937 extern struct event_constraint intel_pnc_pebs_event_constraints[];
1938
1939 struct event_constraint *intel_pebs_constraints(struct perf_event *event);
1940
1941 void intel_pmu_pebs_add(struct perf_event *event);
1942
1943 void intel_pmu_pebs_del(struct perf_event *event);
1944
1945 void intel_pmu_pebs_enable(struct perf_event *event);
1946
1947 void intel_pmu_pebs_disable(struct perf_event *event);
1948
1949 void intel_pmu_pebs_enable_all(void);
1950
1951 void intel_pmu_pebs_disable_all(void);
1952
1953 void intel_pmu_pebs_sched_task(struct perf_event_pmu_context *pmu_ctx, bool sched_in);
1954
1955 void intel_pmu_pebs_late_setup(struct cpu_hw_events *cpuc);
1956
1957 void intel_pmu_drain_pebs_buffer(void);
1958
1959 void intel_pmu_store_pebs_lbrs(struct lbr_entry *lbr);
1960
1961 void intel_pebs_init(void);
1962
1963 void intel_pmu_lbr_save_brstack(struct perf_sample_data *data,
1964 struct cpu_hw_events *cpuc,
1965 struct perf_event *event);
1966
1967 void intel_pmu_lbr_sched_task(struct perf_event_pmu_context *pmu_ctx,
1968 struct task_struct *task, bool sched_in);
1969
1970 u64 lbr_from_signext_quirk_wr(u64 val);
1971
1972 void intel_pmu_lbr_reset(void);
1973
1974 void intel_pmu_lbr_reset_32(void);
1975
1976 void intel_pmu_lbr_reset_64(void);
1977
1978 void intel_pmu_lbr_add(struct perf_event *event);
1979
1980 void intel_pmu_lbr_del(struct perf_event *event);
1981
1982 void intel_pmu_lbr_enable_all(bool pmi);
1983
1984 void intel_pmu_lbr_disable_all(void);
1985
1986 void intel_pmu_lbr_read(void);
1987
1988 void intel_pmu_lbr_read_32(struct cpu_hw_events *cpuc);
1989
1990 void intel_pmu_lbr_read_64(struct cpu_hw_events *cpuc);
1991
1992 void intel_pmu_lbr_save(void *ctx);
1993
1994 void intel_pmu_lbr_restore(void *ctx);
1995
1996 void intel_pmu_lbr_init_core(void);
1997
1998 void intel_pmu_lbr_init_nhm(void);
1999
2000 void intel_pmu_lbr_init_atom(void);
2001
2002 void intel_pmu_lbr_init_slm(void);
2003
2004 void intel_pmu_lbr_init_snb(void);
2005
2006 void intel_pmu_lbr_init_hsw(void);
2007
2008 void intel_pmu_lbr_init_skl(void);
2009
2010 void intel_pmu_lbr_init_knl(void);
2011
2012 void intel_pmu_lbr_init(void);
2013
2014 void intel_pmu_arch_lbr_init(void);
2015
2016 void intel_pmu_pebs_data_source_nhm(void);
2017
2018 void intel_pmu_pebs_data_source_skl(bool pmem);
2019
2020 void intel_pmu_pebs_data_source_adl(void);
2021
2022 void intel_pmu_pebs_data_source_grt(void);
2023
2024 void intel_pmu_pebs_data_source_mtl(void);
2025
2026 void intel_pmu_pebs_data_source_arl_h(void);
2027
2028 void intel_pmu_pebs_data_source_cmt(void);
2029
2030 void intel_pmu_pebs_data_source_lnl(void);
2031
2032 u64 intel_get_arch_pebs_data_config(struct perf_event *event);
2033
2034 int intel_pmu_setup_lbr_filter(struct perf_event *event);
2035
2036 void intel_pt_interrupt(void);
2037
2038 int intel_bts_interrupt(void);
2039
2040 void intel_bts_enable_local(void);
2041
2042 void intel_bts_disable_local(void);
2043
2044 int p4_pmu_init(void);
2045
2046 int p6_pmu_init(void);
2047
2048 int knc_pmu_init(void);
2049
is_ht_workaround_enabled(void)2050 static inline int is_ht_workaround_enabled(void)
2051 {
2052 return !!(x86_pmu.flags & PMU_FL_EXCL_ENABLED);
2053 }
2054
intel_pmu_pebs_mask(u64 cntr_mask)2055 static inline u64 intel_pmu_pebs_mask(u64 cntr_mask)
2056 {
2057 return MAX_PEBS_EVENTS_MASK & cntr_mask;
2058 }
2059
intel_pmu_max_num_pebs(struct pmu * pmu)2060 static inline int intel_pmu_max_num_pebs(struct pmu *pmu)
2061 {
2062 static_assert(MAX_PEBS_EVENTS == 32);
2063 return fls((u32)hybrid(pmu, pebs_events_mask));
2064 }
2065
intel_pmu_has_pebs(void)2066 static inline bool intel_pmu_has_pebs(void)
2067 {
2068 return x86_pmu.ds_pebs || x86_pmu.arch_pebs;
2069 }
2070
2071 #else /* CONFIG_CPU_SUP_INTEL */
2072
reserve_ds_buffers(void)2073 static inline void reserve_ds_buffers(void)
2074 {
2075 }
2076
release_ds_buffers(void)2077 static inline void release_ds_buffers(void)
2078 {
2079 }
2080
release_lbr_buffers(void)2081 static inline void release_lbr_buffers(void)
2082 {
2083 }
2084
reserve_lbr_buffers(void)2085 static inline void reserve_lbr_buffers(void)
2086 {
2087 }
2088
intel_pmu_init(void)2089 static inline int intel_pmu_init(void)
2090 {
2091 return 0;
2092 }
2093
intel_cpuc_prepare(struct cpu_hw_events * cpuc,int cpu)2094 static inline int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu)
2095 {
2096 return 0;
2097 }
2098
intel_cpuc_finish(struct cpu_hw_events * cpuc)2099 static inline void intel_cpuc_finish(struct cpu_hw_events *cpuc)
2100 {
2101 }
2102
is_ht_workaround_enabled(void)2103 static inline int is_ht_workaround_enabled(void)
2104 {
2105 return 0;
2106 }
2107 #endif /* CONFIG_CPU_SUP_INTEL */
2108
2109 #if ((defined CONFIG_CPU_SUP_CENTAUR) || (defined CONFIG_CPU_SUP_ZHAOXIN))
2110 int zhaoxin_pmu_init(void);
2111 #else
zhaoxin_pmu_init(void)2112 static inline int zhaoxin_pmu_init(void)
2113 {
2114 return 0;
2115 }
2116 #endif /*CONFIG_CPU_SUP_CENTAUR or CONFIG_CPU_SUP_ZHAOXIN*/
2117