1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Processor capabilities determination functions.
4 *
5 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
6 */
7 #include <linux/init.h>
8 #include <linux/kernel.h>
9 #include <linux/ptrace.h>
10 #include <linux/smp.h>
11 #include <linux/stddef.h>
12 #include <linux/export.h>
13 #include <linux/printk.h>
14 #include <linux/uaccess.h>
15
16 #include <asm/cpu-features.h>
17 #include <asm/elf.h>
18 #include <asm/fpu.h>
19 #include <asm/loongarch.h>
20 #include <asm/pgtable-bits.h>
21 #include <asm/setup.h>
22
23 /* Hardware capabilities */
24 unsigned int elf_hwcap __read_mostly;
25 EXPORT_SYMBOL_GPL(elf_hwcap);
26
27 /*
28 * Determine the FCSR mask for FPU hardware.
29 */
cpu_set_fpu_fcsr_mask(struct cpuinfo_loongarch * c)30 static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_loongarch *c)
31 {
32 unsigned long sr, mask, fcsr, fcsr0, fcsr1;
33
34 fcsr = c->fpu_csr0;
35 mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM;
36
37 sr = read_csr_euen();
38 enable_fpu();
39
40 fcsr0 = fcsr & mask;
41 write_fcsr(LOONGARCH_FCSR0, fcsr0);
42 fcsr0 = read_fcsr(LOONGARCH_FCSR0);
43
44 fcsr1 = fcsr | ~mask;
45 write_fcsr(LOONGARCH_FCSR0, fcsr1);
46 fcsr1 = read_fcsr(LOONGARCH_FCSR0);
47
48 write_fcsr(LOONGARCH_FCSR0, fcsr);
49
50 write_csr_euen(sr);
51
52 c->fpu_mask = ~(fcsr0 ^ fcsr1) & ~mask;
53 }
54
55 /* simd = -1/0/128/256 */
56 static unsigned int simd = -1U;
57
cpu_setup_simd(char * str)58 static int __init cpu_setup_simd(char *str)
59 {
60 get_option(&str, &simd);
61 pr_info("Set SIMD width = %u\n", simd);
62
63 return 0;
64 }
65
66 early_param("simd", cpu_setup_simd);
67
cpu_final_simd(void)68 static int __init cpu_final_simd(void)
69 {
70 struct cpuinfo_loongarch *c = &cpu_data[0];
71
72 if (simd < 128) {
73 c->options &= ~LOONGARCH_CPU_LSX;
74 elf_hwcap &= ~HWCAP_LOONGARCH_LSX;
75 }
76
77 if (simd < 256) {
78 c->options &= ~LOONGARCH_CPU_LASX;
79 elf_hwcap &= ~HWCAP_LOONGARCH_LASX;
80 }
81
82 simd = 0;
83
84 if (c->options & LOONGARCH_CPU_LSX)
85 simd = 128;
86
87 if (c->options & LOONGARCH_CPU_LASX)
88 simd = 256;
89
90 pr_info("Final SIMD width = %u\n", simd);
91
92 return 0;
93 }
94
95 arch_initcall(cpu_final_simd);
96
set_elf_platform(int cpu,const char * plat)97 static inline void set_elf_platform(int cpu, const char *plat)
98 {
99 if (cpu == 0)
100 __elf_platform = plat;
101 }
102
103 /* MAP BASE */
104 unsigned long vm_map_base;
105 EXPORT_SYMBOL(vm_map_base);
106
cpu_probe_addrbits(struct cpuinfo_loongarch * c)107 static void cpu_probe_addrbits(struct cpuinfo_loongarch *c)
108 {
109 #ifdef __NEED_ADDRBITS_PROBE
110 c->pabits = (read_cpucfg(LOONGARCH_CPUCFG1) & CPUCFG1_PABITS) >> 4;
111 c->vabits = (read_cpucfg(LOONGARCH_CPUCFG1) & CPUCFG1_VABITS) >> 12;
112 vm_map_base = 0UL - (1UL << c->vabits);
113 #endif
114 }
115
set_isa(struct cpuinfo_loongarch * c,unsigned int isa)116 static void set_isa(struct cpuinfo_loongarch *c, unsigned int isa)
117 {
118 switch (isa) {
119 case LOONGARCH_CPU_ISA_LA64:
120 c->isa_level |= LOONGARCH_CPU_ISA_LA64;
121 fallthrough;
122 case LOONGARCH_CPU_ISA_LA32S:
123 c->isa_level |= LOONGARCH_CPU_ISA_LA32S;
124 fallthrough;
125 case LOONGARCH_CPU_ISA_LA32R:
126 c->isa_level |= LOONGARCH_CPU_ISA_LA32R;
127 break;
128 }
129 }
130
cpu_probe_common(struct cpuinfo_loongarch * c)131 static void cpu_probe_common(struct cpuinfo_loongarch *c)
132 {
133 unsigned int config;
134 unsigned long asid_mask;
135
136 c->options = LOONGARCH_CPU_CPUCFG | LOONGARCH_CPU_CSR | LOONGARCH_CPU_VINT;
137
138 elf_hwcap = HWCAP_LOONGARCH_CPUCFG;
139
140 config = read_cpucfg(LOONGARCH_CPUCFG1);
141
142 switch (config & CPUCFG1_ISA) {
143 case 0:
144 set_isa(c, LOONGARCH_CPU_ISA_LA32R);
145 break;
146 case 1:
147 set_isa(c, LOONGARCH_CPU_ISA_LA32S);
148 break;
149 case 2:
150 set_isa(c, LOONGARCH_CPU_ISA_LA64);
151 break;
152 default:
153 pr_warn("Warning: unknown ISA level\n");
154 }
155
156 if (config & CPUCFG1_PAGING)
157 c->options |= LOONGARCH_CPU_TLB;
158 if (config & CPUCFG1_IOCSR)
159 c->options |= LOONGARCH_CPU_IOCSR;
160 if (config & CPUCFG1_MSGINT)
161 c->options |= LOONGARCH_CPU_MSGINT;
162 if (config & CPUCFG1_UAL) {
163 c->options |= LOONGARCH_CPU_UAL;
164 elf_hwcap |= HWCAP_LOONGARCH_UAL;
165 }
166 if (config & CPUCFG1_CRC32) {
167 c->options |= LOONGARCH_CPU_CRC32;
168 elf_hwcap |= HWCAP_LOONGARCH_CRC32;
169 }
170
171 config = read_cpucfg(LOONGARCH_CPUCFG2);
172 if (config & CPUCFG2_LAM) {
173 c->options |= LOONGARCH_CPU_LAM;
174 elf_hwcap |= HWCAP_LOONGARCH_LAM;
175 }
176 if (config & CPUCFG2_FP) {
177 c->options |= LOONGARCH_CPU_FPU;
178 elf_hwcap |= HWCAP_LOONGARCH_FPU;
179 }
180 #ifdef CONFIG_CPU_HAS_LSX
181 if ((config & CPUCFG2_LSX) && (simd >= 128)) {
182 c->options |= LOONGARCH_CPU_LSX;
183 elf_hwcap |= HWCAP_LOONGARCH_LSX;
184 }
185 #endif
186 #ifdef CONFIG_CPU_HAS_LASX
187 if ((config & CPUCFG2_LASX) && (simd >= 256)) {
188 c->options |= LOONGARCH_CPU_LASX;
189 elf_hwcap |= HWCAP_LOONGARCH_LASX;
190 }
191 #endif
192 if (config & CPUCFG2_COMPLEX) {
193 c->options |= LOONGARCH_CPU_COMPLEX;
194 elf_hwcap |= HWCAP_LOONGARCH_COMPLEX;
195 }
196 if (config & CPUCFG2_CRYPTO) {
197 c->options |= LOONGARCH_CPU_CRYPTO;
198 elf_hwcap |= HWCAP_LOONGARCH_CRYPTO;
199 }
200 if (config & CPUCFG2_PTW) {
201 c->options |= LOONGARCH_CPU_PTW;
202 elf_hwcap |= HWCAP_LOONGARCH_PTW;
203 }
204 if (config & CPUCFG2_LSPW) {
205 c->options |= LOONGARCH_CPU_LSPW;
206 elf_hwcap |= HWCAP_LOONGARCH_LSPW;
207 }
208 if (config & CPUCFG2_LVZP) {
209 c->options |= LOONGARCH_CPU_LVZ;
210 elf_hwcap |= HWCAP_LOONGARCH_LVZ;
211 }
212 #ifdef CONFIG_CPU_HAS_LBT
213 if (config & CPUCFG2_X86BT) {
214 c->options |= LOONGARCH_CPU_LBT_X86;
215 elf_hwcap |= HWCAP_LOONGARCH_LBT_X86;
216 }
217 if (config & CPUCFG2_ARMBT) {
218 c->options |= LOONGARCH_CPU_LBT_ARM;
219 elf_hwcap |= HWCAP_LOONGARCH_LBT_ARM;
220 }
221 if (config & CPUCFG2_MIPSBT) {
222 c->options |= LOONGARCH_CPU_LBT_MIPS;
223 elf_hwcap |= HWCAP_LOONGARCH_LBT_MIPS;
224 }
225 #endif
226
227 config = read_cpucfg(LOONGARCH_CPUCFG6);
228 if (config & CPUCFG6_PMP)
229 c->options |= LOONGARCH_CPU_PMP;
230
231 config = csr_read32(LOONGARCH_CSR_ASID);
232 config = (config & CSR_ASID_BIT) >> CSR_ASID_BIT_SHIFT;
233 asid_mask = GENMASK(config - 1, 0);
234 set_cpu_asid_mask(c, asid_mask);
235
236 config = read_csr_prcfg1();
237 c->timerbits = (config & CSR_CONF1_TMRBITS) >> CSR_CONF1_TMRBITS_SHIFT;
238 c->ksave_mask = GENMASK((config & CSR_CONF1_KSNUM) - 1, 0);
239 c->ksave_mask &= ~(EXC_KSAVE_MASK | PERCPU_KSAVE_MASK | KVM_KSAVE_MASK);
240
241 config = read_csr_prcfg3();
242 switch (config & CSR_CONF3_TLBTYPE) {
243 case 0:
244 c->tlbsizemtlb = 0;
245 c->tlbsizestlbsets = 0;
246 c->tlbsizestlbways = 0;
247 c->tlbsize = 0;
248 break;
249 case 1:
250 c->tlbsizemtlb = ((config & CSR_CONF3_MTLBSIZE) >> CSR_CONF3_MTLBSIZE_SHIFT) + 1;
251 c->tlbsizestlbsets = 0;
252 c->tlbsizestlbways = 0;
253 c->tlbsize = c->tlbsizemtlb + c->tlbsizestlbsets * c->tlbsizestlbways;
254 break;
255 case 2:
256 c->tlbsizemtlb = ((config & CSR_CONF3_MTLBSIZE) >> CSR_CONF3_MTLBSIZE_SHIFT) + 1;
257 c->tlbsizestlbsets = 1 << ((config & CSR_CONF3_STLBIDX) >> CSR_CONF3_STLBIDX_SHIFT);
258 c->tlbsizestlbways = ((config & CSR_CONF3_STLBWAYS) >> CSR_CONF3_STLBWAYS_SHIFT) + 1;
259 c->tlbsize = c->tlbsizemtlb + c->tlbsizestlbsets * c->tlbsizestlbways;
260 break;
261 default:
262 pr_warn("Warning: unknown TLB type\n");
263 }
264
265 if (get_num_brps() + get_num_wrps())
266 c->options |= LOONGARCH_CPU_WATCH;
267 }
268
269 #define MAX_NAME_LEN 32
270 #define VENDOR_OFFSET 0
271 #define CPUNAME_OFFSET 9
272
273 static char cpu_full_name[MAX_NAME_LEN] = " - ";
274
cpu_probe_loongson(struct cpuinfo_loongarch * c,unsigned int cpu)275 static inline void cpu_probe_loongson(struct cpuinfo_loongarch *c, unsigned int cpu)
276 {
277 uint32_t config;
278 uint64_t *vendor = (void *)(&cpu_full_name[VENDOR_OFFSET]);
279 uint64_t *cpuname = (void *)(&cpu_full_name[CPUNAME_OFFSET]);
280 const char *core_name = "Unknown";
281
282 switch (BIT(fls(c->isa_level) - 1)) {
283 case LOONGARCH_CPU_ISA_LA32R:
284 case LOONGARCH_CPU_ISA_LA32S:
285 c->cputype = CPU_LOONGSON32;
286 __cpu_family[cpu] = "Loongson-32bit";
287 break;
288 case LOONGARCH_CPU_ISA_LA64:
289 c->cputype = CPU_LOONGSON64;
290 __cpu_family[cpu] = "Loongson-64bit";
291 break;
292 }
293
294 switch (c->processor_id & PRID_SERIES_MASK) {
295 case PRID_SERIES_LA132:
296 core_name = "LA132";
297 break;
298 case PRID_SERIES_LA264:
299 core_name = "LA264";
300 break;
301 case PRID_SERIES_LA364:
302 core_name = "LA364";
303 break;
304 case PRID_SERIES_LA464:
305 core_name = "LA464";
306 break;
307 case PRID_SERIES_LA664:
308 core_name = "LA664";
309 break;
310 }
311
312 pr_info("%s Processor probed (%s Core)\n", __cpu_family[cpu], core_name);
313
314 if (!cpu_has_iocsr)
315 return;
316
317 if (!__cpu_full_name[cpu])
318 __cpu_full_name[cpu] = cpu_full_name;
319
320 *vendor = iocsr_read64(LOONGARCH_IOCSR_VENDOR);
321 *cpuname = iocsr_read64(LOONGARCH_IOCSR_CPUNAME);
322
323 config = iocsr_read32(LOONGARCH_IOCSR_FEATURES);
324 if (config & IOCSRF_CSRIPI)
325 c->options |= LOONGARCH_CPU_CSRIPI;
326 if (config & IOCSRF_EXTIOI)
327 c->options |= LOONGARCH_CPU_EXTIOI;
328 if (config & IOCSRF_FREQSCALE)
329 c->options |= LOONGARCH_CPU_SCALEFREQ;
330 if (config & IOCSRF_FLATMODE)
331 c->options |= LOONGARCH_CPU_FLATMODE;
332 if (config & IOCSRF_EIODECODE)
333 c->options |= LOONGARCH_CPU_EIODECODE;
334 if (config & IOCSRF_AVEC)
335 c->options |= LOONGARCH_CPU_AVECINT;
336 if (config & IOCSRF_REDIRECT)
337 c->options |= LOONGARCH_CPU_REDIRECTINT;
338 if (config & IOCSRF_VM)
339 c->options |= LOONGARCH_CPU_HYPERVISOR;
340 }
341
342 #ifdef CONFIG_64BIT
343 /* For use by uaccess.h */
344 u64 __ua_limit;
345 EXPORT_SYMBOL(__ua_limit);
346 #endif
347
348 const char *__cpu_family[NR_CPUS];
349 const char *__cpu_full_name[NR_CPUS];
350 const char *__elf_platform;
351
cpu_report(void)352 static void cpu_report(void)
353 {
354 struct cpuinfo_loongarch *c = ¤t_cpu_data;
355
356 pr_info("CPU%d revision is: %08x (%s)\n",
357 smp_processor_id(), c->processor_id, cpu_family_string());
358 if (c->options & LOONGARCH_CPU_FPU)
359 pr_info("FPU%d revision is: %08x\n", smp_processor_id(), c->fpu_vers);
360 }
361
cpu_probe(void)362 void cpu_probe(void)
363 {
364 unsigned int cpu = smp_processor_id();
365 struct cpuinfo_loongarch *c = ¤t_cpu_data;
366
367 /*
368 * Set a default ELF platform, cpu probe may later
369 * overwrite it with a more precise value
370 */
371 set_elf_platform(cpu, "loongarch");
372
373 c->cputype = CPU_UNKNOWN;
374 c->processor_id = read_cpucfg(LOONGARCH_CPUCFG0);
375 c->fpu_vers = (read_cpucfg(LOONGARCH_CPUCFG2) & CPUCFG2_FPVERS) >> 3;
376
377 c->fpu_csr0 = FPU_CSR_RN;
378 c->fpu_mask = FPU_CSR_RSVD;
379
380 cpu_probe_common(c);
381
382 per_cpu_trap_init(cpu);
383
384 switch (c->processor_id & PRID_COMP_MASK) {
385 case PRID_COMP_LOONGSON:
386 cpu_probe_loongson(c, cpu);
387 break;
388 }
389
390 BUG_ON(!__cpu_family[cpu]);
391 BUG_ON(c->cputype == CPU_UNKNOWN);
392
393 cpu_probe_addrbits(c);
394
395 #ifdef CONFIG_64BIT
396 if (cpu == 0)
397 __ua_limit = ~((1ull << cpu_vabits) - 1);
398 #endif
399
400 cpu_report();
401 }
402