1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #include <linux/module.h>
8 #include <linux/slab.h>
9 #include <linux/remoteproc.h>
10 #include <linux/firmware.h>
11 #include <linux/of.h>
12
13 #include "core.h"
14 #include "dp_tx.h"
15 #include "dp_rx.h"
16 #include "debug.h"
17 #include "hif.h"
18 #include "wow.h"
19 #include "fw.h"
20
21 unsigned int ath11k_debug_mask;
22 EXPORT_SYMBOL(ath11k_debug_mask);
23 module_param_named(debug_mask, ath11k_debug_mask, uint, 0644);
24 MODULE_PARM_DESC(debug_mask, "Debugging mask");
25
26 static unsigned int ath11k_crypto_mode;
27 module_param_named(crypto_mode, ath11k_crypto_mode, uint, 0644);
28 MODULE_PARM_DESC(crypto_mode, "crypto mode: 0-hardware, 1-software");
29
30 /* frame mode values are mapped as per enum ath11k_hw_txrx_mode */
31 unsigned int ath11k_frame_mode = ATH11K_HW_TXRX_NATIVE_WIFI;
32 module_param_named(frame_mode, ath11k_frame_mode, uint, 0644);
33 MODULE_PARM_DESC(frame_mode,
34 "Datapath frame mode (0: raw, 1: native wifi (default), 2: ethernet)");
35
36 bool ath11k_ftm_mode;
37 module_param_named(ftm_mode, ath11k_ftm_mode, bool, 0444);
38 MODULE_PARM_DESC(ftm_mode, "Boots up in factory test mode");
39
40 static const struct ath11k_hw_params ath11k_hw_params[] = {
41 {
42 .hw_rev = ATH11K_HW_IPQ8074,
43 .name = "ipq8074 hw2.0",
44 .fw = {
45 .dir = "IPQ8074/hw2.0",
46 .board_size = 256 * 1024,
47 .cal_offset = 128 * 1024,
48 },
49 .max_radios = 3,
50 .bdf_addr = 0x4B0C0000,
51 .hw_ops = &ipq8074_ops,
52 .ring_mask = &ath11k_hw_ring_mask_ipq8074,
53 .internal_sleep_clock = false,
54 .regs = &ipq8074_regs,
55 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074,
56 .host_ce_config = ath11k_host_ce_config_ipq8074,
57 .ce_count = 12,
58 .target_ce_config = ath11k_target_ce_config_wlan_ipq8074,
59 .target_ce_count = 11,
60 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq8074,
61 .svc_to_ce_map_len = 21,
62 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
63 .single_pdev_only = false,
64 .rxdma1_enable = true,
65 .num_rxdma_per_pdev = 1,
66 .rx_mac_buf_ring = false,
67 .vdev_start_delay = false,
68 .htt_peer_map_v2 = true,
69
70 .spectral = {
71 .fft_sz = 2,
72 /* HW bug, expected BIN size is 2 bytes but HW report as 4 bytes.
73 * so added pad size as 2 bytes to compensate the BIN size
74 */
75 .fft_pad_sz = 2,
76 .summary_pad_sz = 0,
77 .fft_hdr_len = 16,
78 .max_fft_bins = 512,
79 .fragment_160mhz = true,
80 },
81
82 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
83 BIT(NL80211_IFTYPE_AP) |
84 BIT(NL80211_IFTYPE_MESH_POINT),
85 .supports_monitor = true,
86 .full_monitor_mode = false,
87 .supports_shadow_regs = false,
88 .idle_ps = false,
89 .supports_sta_ps = false,
90 .coldboot_cal_mm = true,
91 .coldboot_cal_ftm = true,
92 .cbcal_restart_fw = true,
93 .fw_mem_mode = 0,
94 .num_vdevs = 16 + 1,
95 .num_peers = 512,
96 .supports_suspend = false,
97 .hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074),
98 .supports_regdb = false,
99 .fix_l1ss = true,
100 .credit_flow = false,
101 .max_tx_ring = DP_TCL_NUM_RING_MAX,
102 .hal_params = &ath11k_hw_hal_params_ipq8074,
103 .supports_dynamic_smps_6ghz = false,
104 .alloc_cacheable_memory = true,
105 .supports_rssi_stats = false,
106 .fw_wmi_diag_event = false,
107 .current_cc_support = false,
108 .dbr_debug_support = true,
109 .global_reset = false,
110 .bios_sar_capa = NULL,
111 .m3_fw_support = false,
112 .fixed_bdf_addr = true,
113 .fixed_mem_region = true,
114 .static_window_map = false,
115 .hybrid_bus_type = false,
116 .fixed_fw_mem = false,
117 .support_off_channel_tx = false,
118 .supports_multi_bssid = false,
119
120 .sram_dump = {},
121
122 .tcl_ring_retry = true,
123 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
124 .smp2p_wow_exit = false,
125 .support_dual_stations = false,
126 .pdev_suspend = false,
127 },
128 {
129 .hw_rev = ATH11K_HW_IPQ6018_HW10,
130 .name = "ipq6018 hw1.0",
131 .fw = {
132 .dir = "IPQ6018/hw1.0",
133 .board_size = 256 * 1024,
134 .cal_offset = 128 * 1024,
135 },
136 .max_radios = 2,
137 .bdf_addr = 0x4ABC0000,
138 .hw_ops = &ipq6018_ops,
139 .ring_mask = &ath11k_hw_ring_mask_ipq8074,
140 .internal_sleep_clock = false,
141 .regs = &ipq8074_regs,
142 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074,
143 .host_ce_config = ath11k_host_ce_config_ipq8074,
144 .ce_count = 12,
145 .target_ce_config = ath11k_target_ce_config_wlan_ipq8074,
146 .target_ce_count = 11,
147 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq6018,
148 .svc_to_ce_map_len = 19,
149 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
150 .single_pdev_only = false,
151 .rxdma1_enable = true,
152 .num_rxdma_per_pdev = 1,
153 .rx_mac_buf_ring = false,
154 .vdev_start_delay = false,
155 .htt_peer_map_v2 = true,
156
157 .spectral = {
158 .fft_sz = 4,
159 .fft_pad_sz = 0,
160 .summary_pad_sz = 0,
161 .fft_hdr_len = 16,
162 .max_fft_bins = 512,
163 .fragment_160mhz = true,
164 },
165
166 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
167 BIT(NL80211_IFTYPE_AP) |
168 BIT(NL80211_IFTYPE_MESH_POINT),
169 .supports_monitor = true,
170 .full_monitor_mode = false,
171 .supports_shadow_regs = false,
172 .idle_ps = false,
173 .supports_sta_ps = false,
174 .coldboot_cal_mm = true,
175 .coldboot_cal_ftm = true,
176 .cbcal_restart_fw = true,
177 .fw_mem_mode = 0,
178 .num_vdevs = 16 + 1,
179 .num_peers = 512,
180 .supports_suspend = false,
181 .hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074),
182 .supports_regdb = false,
183 .fix_l1ss = true,
184 .credit_flow = false,
185 .max_tx_ring = DP_TCL_NUM_RING_MAX,
186 .hal_params = &ath11k_hw_hal_params_ipq8074,
187 .supports_dynamic_smps_6ghz = false,
188 .alloc_cacheable_memory = true,
189 .supports_rssi_stats = false,
190 .fw_wmi_diag_event = false,
191 .current_cc_support = false,
192 .dbr_debug_support = true,
193 .global_reset = false,
194 .bios_sar_capa = NULL,
195 .m3_fw_support = false,
196 .fixed_bdf_addr = true,
197 .fixed_mem_region = true,
198 .static_window_map = false,
199 .hybrid_bus_type = false,
200 .fixed_fw_mem = false,
201 .support_off_channel_tx = false,
202 .supports_multi_bssid = false,
203
204 .sram_dump = {},
205
206 .tcl_ring_retry = true,
207 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
208 .smp2p_wow_exit = false,
209 .support_fw_mac_sequence = false,
210 .support_dual_stations = false,
211 .pdev_suspend = false,
212 },
213 {
214 .name = "qca6390 hw2.0",
215 .hw_rev = ATH11K_HW_QCA6390_HW20,
216 .fw = {
217 .dir = "QCA6390/hw2.0",
218 .board_size = 256 * 1024,
219 .cal_offset = 128 * 1024,
220 },
221 .max_radios = 3,
222 .bdf_addr = 0x4B0C0000,
223 .hw_ops = &qca6390_ops,
224 .ring_mask = &ath11k_hw_ring_mask_qca6390,
225 .internal_sleep_clock = true,
226 .regs = &qca6390_regs,
227 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390,
228 .host_ce_config = ath11k_host_ce_config_qca6390,
229 .ce_count = 9,
230 .target_ce_config = ath11k_target_ce_config_wlan_qca6390,
231 .target_ce_count = 9,
232 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
233 .svc_to_ce_map_len = 14,
234 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
235 .single_pdev_only = true,
236 .rxdma1_enable = false,
237 .num_rxdma_per_pdev = 2,
238 .rx_mac_buf_ring = true,
239 .vdev_start_delay = true,
240 .htt_peer_map_v2 = false,
241
242 .spectral = {
243 .fft_sz = 0,
244 .fft_pad_sz = 0,
245 .summary_pad_sz = 0,
246 .fft_hdr_len = 0,
247 .max_fft_bins = 0,
248 .fragment_160mhz = false,
249 },
250
251 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
252 BIT(NL80211_IFTYPE_AP) |
253 BIT(NL80211_IFTYPE_P2P_DEVICE) |
254 BIT(NL80211_IFTYPE_P2P_CLIENT) |
255 BIT(NL80211_IFTYPE_P2P_GO),
256 .supports_monitor = false,
257 .full_monitor_mode = false,
258 .supports_shadow_regs = true,
259 .idle_ps = true,
260 .supports_sta_ps = true,
261 .coldboot_cal_mm = false,
262 .coldboot_cal_ftm = false,
263 .cbcal_restart_fw = false,
264 .fw_mem_mode = 0,
265 .num_vdevs = 2 + 1,
266 .num_peers = 512,
267 .supports_suspend = true,
268 .hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074),
269 .supports_regdb = false,
270 .fix_l1ss = true,
271 .credit_flow = true,
272 .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390,
273 .hal_params = &ath11k_hw_hal_params_qca6390,
274 .supports_dynamic_smps_6ghz = false,
275 .alloc_cacheable_memory = false,
276 .supports_rssi_stats = true,
277 .fw_wmi_diag_event = true,
278 .current_cc_support = true,
279 .dbr_debug_support = false,
280 .global_reset = true,
281 .bios_sar_capa = NULL,
282 .m3_fw_support = true,
283 .fixed_bdf_addr = false,
284 .fixed_mem_region = false,
285 .static_window_map = false,
286 .hybrid_bus_type = false,
287 .fixed_fw_mem = false,
288 .support_off_channel_tx = true,
289 .supports_multi_bssid = true,
290
291 .sram_dump = {
292 .start = 0x01400000,
293 .end = 0x0171ffff,
294 },
295
296 .tcl_ring_retry = true,
297 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
298 .smp2p_wow_exit = false,
299 .support_fw_mac_sequence = true,
300 .support_dual_stations = true,
301 .pdev_suspend = false,
302 },
303 {
304 .name = "qcn9074 hw1.0",
305 .hw_rev = ATH11K_HW_QCN9074_HW10,
306 .fw = {
307 .dir = "QCN9074/hw1.0",
308 .board_size = 256 * 1024,
309 .cal_offset = 128 * 1024,
310 },
311 .max_radios = 1,
312 .single_pdev_only = false,
313 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9074,
314 .hw_ops = &qcn9074_ops,
315 .ring_mask = &ath11k_hw_ring_mask_qcn9074,
316 .internal_sleep_clock = false,
317 .regs = &qcn9074_regs,
318 .host_ce_config = ath11k_host_ce_config_qcn9074,
319 .ce_count = 6,
320 .target_ce_config = ath11k_target_ce_config_wlan_qcn9074,
321 .target_ce_count = 9,
322 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qcn9074,
323 .svc_to_ce_map_len = 18,
324 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
325 .rxdma1_enable = true,
326 .num_rxdma_per_pdev = 1,
327 .rx_mac_buf_ring = false,
328 .vdev_start_delay = false,
329 .htt_peer_map_v2 = true,
330
331 .spectral = {
332 .fft_sz = 2,
333 .fft_pad_sz = 0,
334 .summary_pad_sz = 16,
335 .fft_hdr_len = 24,
336 .max_fft_bins = 1024,
337 .fragment_160mhz = false,
338 },
339
340 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
341 BIT(NL80211_IFTYPE_AP) |
342 BIT(NL80211_IFTYPE_MESH_POINT),
343 .supports_monitor = true,
344 .full_monitor_mode = true,
345 .supports_shadow_regs = false,
346 .idle_ps = false,
347 .supports_sta_ps = false,
348 .coldboot_cal_mm = false,
349 .coldboot_cal_ftm = true,
350 .cbcal_restart_fw = true,
351 .fw_mem_mode = 2,
352 .num_vdevs = 8,
353 .num_peers = 128,
354 .supports_suspend = false,
355 .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074),
356 .supports_regdb = false,
357 .fix_l1ss = true,
358 .credit_flow = false,
359 .max_tx_ring = DP_TCL_NUM_RING_MAX,
360 .hal_params = &ath11k_hw_hal_params_ipq8074,
361 .supports_dynamic_smps_6ghz = true,
362 .alloc_cacheable_memory = true,
363 .supports_rssi_stats = false,
364 .fw_wmi_diag_event = false,
365 .current_cc_support = false,
366 .dbr_debug_support = true,
367 .global_reset = false,
368 .bios_sar_capa = NULL,
369 .m3_fw_support = true,
370 .fixed_bdf_addr = false,
371 .fixed_mem_region = false,
372 .static_window_map = true,
373 .hybrid_bus_type = false,
374 .fixed_fw_mem = false,
375 .support_off_channel_tx = false,
376 .supports_multi_bssid = false,
377
378 .sram_dump = {},
379
380 .tcl_ring_retry = true,
381 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
382 .smp2p_wow_exit = false,
383 .support_fw_mac_sequence = false,
384 .support_dual_stations = false,
385 .pdev_suspend = false,
386 },
387 {
388 .name = "wcn6855 hw2.0",
389 .hw_rev = ATH11K_HW_WCN6855_HW20,
390 .fw = {
391 .dir = "WCN6855/hw2.0",
392 .board_size = 256 * 1024,
393 .cal_offset = 128 * 1024,
394 },
395 .max_radios = 3,
396 .bdf_addr = 0x4B0C0000,
397 .hw_ops = &wcn6855_ops,
398 .ring_mask = &ath11k_hw_ring_mask_qca6390,
399 .internal_sleep_clock = true,
400 .regs = &wcn6855_regs,
401 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390,
402 .host_ce_config = ath11k_host_ce_config_qca6390,
403 .ce_count = 9,
404 .target_ce_config = ath11k_target_ce_config_wlan_qca6390,
405 .target_ce_count = 9,
406 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
407 .svc_to_ce_map_len = 14,
408 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
409 .single_pdev_only = true,
410 .rxdma1_enable = false,
411 .num_rxdma_per_pdev = 2,
412 .rx_mac_buf_ring = true,
413 .vdev_start_delay = true,
414 .htt_peer_map_v2 = false,
415
416 .spectral = {
417 .fft_sz = 0,
418 .fft_pad_sz = 0,
419 .summary_pad_sz = 0,
420 .fft_hdr_len = 0,
421 .max_fft_bins = 0,
422 .fragment_160mhz = false,
423 },
424
425 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
426 BIT(NL80211_IFTYPE_AP) |
427 BIT(NL80211_IFTYPE_P2P_DEVICE) |
428 BIT(NL80211_IFTYPE_P2P_CLIENT) |
429 BIT(NL80211_IFTYPE_P2P_GO),
430 .supports_monitor = false,
431 .full_monitor_mode = false,
432 .supports_shadow_regs = true,
433 .idle_ps = true,
434 .supports_sta_ps = true,
435 .coldboot_cal_mm = false,
436 .coldboot_cal_ftm = false,
437 .cbcal_restart_fw = false,
438 .fw_mem_mode = 0,
439 .num_vdevs = 2 + 1,
440 .num_peers = 512,
441 .supports_suspend = true,
442 .hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855),
443 .supports_regdb = true,
444 .fix_l1ss = false,
445 .credit_flow = true,
446 .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390,
447 .hal_params = &ath11k_hw_hal_params_qca6390,
448 .supports_dynamic_smps_6ghz = false,
449 .alloc_cacheable_memory = false,
450 .supports_rssi_stats = true,
451 .fw_wmi_diag_event = true,
452 .current_cc_support = true,
453 .dbr_debug_support = false,
454 .global_reset = true,
455 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855,
456 .m3_fw_support = true,
457 .fixed_bdf_addr = false,
458 .fixed_mem_region = false,
459 .static_window_map = false,
460 .hybrid_bus_type = false,
461 .fixed_fw_mem = false,
462 .support_off_channel_tx = true,
463 .supports_multi_bssid = true,
464
465 .sram_dump = {
466 .start = 0x01400000,
467 .end = 0x0177ffff,
468 },
469
470 .tcl_ring_retry = true,
471 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
472 .smp2p_wow_exit = false,
473 .support_fw_mac_sequence = true,
474 .support_dual_stations = true,
475 .pdev_suspend = false,
476 },
477 {
478 .name = "wcn6855 hw2.1",
479 .hw_rev = ATH11K_HW_WCN6855_HW21,
480 .fw = {
481 .dir = "WCN6855/hw2.1",
482 .board_size = 256 * 1024,
483 .cal_offset = 128 * 1024,
484 },
485 .max_radios = 3,
486 .bdf_addr = 0x4B0C0000,
487 .hw_ops = &wcn6855_ops,
488 .ring_mask = &ath11k_hw_ring_mask_qca6390,
489 .internal_sleep_clock = true,
490 .regs = &wcn6855_regs,
491 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390,
492 .host_ce_config = ath11k_host_ce_config_qca6390,
493 .ce_count = 9,
494 .target_ce_config = ath11k_target_ce_config_wlan_qca6390,
495 .target_ce_count = 9,
496 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
497 .svc_to_ce_map_len = 14,
498 .single_pdev_only = true,
499 .rxdma1_enable = false,
500 .num_rxdma_per_pdev = 2,
501 .rx_mac_buf_ring = true,
502 .vdev_start_delay = true,
503 .htt_peer_map_v2 = false,
504
505 .spectral = {
506 .fft_sz = 0,
507 .fft_pad_sz = 0,
508 .summary_pad_sz = 0,
509 .fft_hdr_len = 0,
510 .max_fft_bins = 0,
511 .fragment_160mhz = false,
512 },
513
514 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
515 BIT(NL80211_IFTYPE_AP) |
516 BIT(NL80211_IFTYPE_P2P_DEVICE) |
517 BIT(NL80211_IFTYPE_P2P_CLIENT) |
518 BIT(NL80211_IFTYPE_P2P_GO),
519 .supports_monitor = false,
520 .supports_shadow_regs = true,
521 .idle_ps = true,
522 .supports_sta_ps = true,
523 .coldboot_cal_mm = false,
524 .coldboot_cal_ftm = false,
525 .cbcal_restart_fw = false,
526 .fw_mem_mode = 0,
527 .num_vdevs = 2 + 1,
528 .num_peers = 512,
529 .supports_suspend = true,
530 .hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855),
531 .supports_regdb = true,
532 .fix_l1ss = false,
533 .credit_flow = true,
534 .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390,
535 .hal_params = &ath11k_hw_hal_params_qca6390,
536 .supports_dynamic_smps_6ghz = false,
537 .alloc_cacheable_memory = false,
538 .supports_rssi_stats = true,
539 .fw_wmi_diag_event = true,
540 .current_cc_support = true,
541 .dbr_debug_support = false,
542 .global_reset = true,
543 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855,
544 .m3_fw_support = true,
545 .fixed_bdf_addr = false,
546 .fixed_mem_region = false,
547 .static_window_map = false,
548 .hybrid_bus_type = false,
549 .fixed_fw_mem = false,
550 .support_off_channel_tx = true,
551 .supports_multi_bssid = true,
552
553 .sram_dump = {
554 .start = 0x01400000,
555 .end = 0x0177ffff,
556 },
557
558 .tcl_ring_retry = true,
559 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
560 .smp2p_wow_exit = false,
561 .support_fw_mac_sequence = true,
562 .support_dual_stations = true,
563 .pdev_suspend = false,
564 },
565 {
566 .name = "wcn6750 hw1.0",
567 .hw_rev = ATH11K_HW_WCN6750_HW10,
568 .fw = {
569 .dir = "WCN6750/hw1.0",
570 .board_size = 256 * 1024,
571 .cal_offset = 128 * 1024,
572 },
573 .max_radios = 1,
574 .bdf_addr = 0x4B0C0000,
575 .hw_ops = &wcn6750_ops,
576 .ring_mask = &ath11k_hw_ring_mask_wcn6750,
577 .internal_sleep_clock = false,
578 .regs = &wcn6750_regs,
579 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_WCN6750,
580 .host_ce_config = ath11k_host_ce_config_qca6390,
581 .ce_count = 9,
582 .target_ce_config = ath11k_target_ce_config_wlan_qca6390,
583 .target_ce_count = 9,
584 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
585 .svc_to_ce_map_len = 14,
586 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
587 .single_pdev_only = true,
588 .rxdma1_enable = false,
589 .num_rxdma_per_pdev = 1,
590 .rx_mac_buf_ring = true,
591 .vdev_start_delay = true,
592 .htt_peer_map_v2 = false,
593
594 .spectral = {
595 .fft_sz = 0,
596 .fft_pad_sz = 0,
597 .summary_pad_sz = 0,
598 .fft_hdr_len = 0,
599 .max_fft_bins = 0,
600 .fragment_160mhz = false,
601 },
602
603 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
604 BIT(NL80211_IFTYPE_AP),
605 .supports_monitor = false,
606 .supports_shadow_regs = true,
607 .idle_ps = true,
608 .supports_sta_ps = true,
609 .coldboot_cal_mm = true,
610 .coldboot_cal_ftm = true,
611 .cbcal_restart_fw = false,
612 .fw_mem_mode = 0,
613 .num_vdevs = 3,
614 .num_peers = 512,
615 .supports_suspend = false,
616 .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074),
617 .supports_regdb = true,
618 .fix_l1ss = false,
619 .credit_flow = true,
620 .max_tx_ring = DP_TCL_NUM_RING_MAX,
621 .hal_params = &ath11k_hw_hal_params_wcn6750,
622 .supports_dynamic_smps_6ghz = false,
623 .alloc_cacheable_memory = false,
624 .supports_rssi_stats = true,
625 .fw_wmi_diag_event = true,
626 .current_cc_support = true,
627 .dbr_debug_support = false,
628 .global_reset = false,
629 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855,
630 .m3_fw_support = false,
631 .fixed_bdf_addr = false,
632 .fixed_mem_region = false,
633 .static_window_map = true,
634 .hybrid_bus_type = true,
635 .fixed_fw_mem = true,
636 .support_off_channel_tx = true,
637 .supports_multi_bssid = true,
638
639 .sram_dump = {},
640
641 .tcl_ring_retry = false,
642 .tx_ring_size = DP_TCL_DATA_RING_SIZE_WCN6750,
643 .smp2p_wow_exit = true,
644 .support_fw_mac_sequence = true,
645 .support_dual_stations = false,
646 .pdev_suspend = true,
647 },
648 {
649 .hw_rev = ATH11K_HW_IPQ5018_HW10,
650 .name = "ipq5018 hw1.0",
651 .fw = {
652 .dir = "IPQ5018/hw1.0",
653 .board_size = 256 * 1024,
654 .cal_offset = 128 * 1024,
655 },
656 .max_radios = MAX_RADIOS_5018,
657 .bdf_addr = 0x4BA00000,
658 /* hal_desc_sz and hw ops are similar to qcn9074 */
659 .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074),
660 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074,
661 .ring_mask = &ath11k_hw_ring_mask_ipq8074,
662 .credit_flow = false,
663 .max_tx_ring = 1,
664 .spectral = {
665 .fft_sz = 2,
666 .fft_pad_sz = 0,
667 .summary_pad_sz = 16,
668 .fft_hdr_len = 24,
669 .max_fft_bins = 1024,
670 },
671 .internal_sleep_clock = false,
672 .regs = &ipq5018_regs,
673 .hw_ops = &ipq5018_ops,
674 .host_ce_config = ath11k_host_ce_config_qcn9074,
675 .ce_count = CE_CNT_5018,
676 .target_ce_config = ath11k_target_ce_config_wlan_ipq5018,
677 .target_ce_count = TARGET_CE_CNT_5018,
678 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq5018,
679 .svc_to_ce_map_len = SVC_CE_MAP_LEN_5018,
680 .ce_ie_addr = &ath11k_ce_ie_addr_ipq5018,
681 .ce_remap = &ath11k_ce_remap_ipq5018,
682 .rxdma1_enable = true,
683 .num_rxdma_per_pdev = RXDMA_PER_PDEV_5018,
684 .rx_mac_buf_ring = false,
685 .vdev_start_delay = false,
686 .htt_peer_map_v2 = true,
687 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
688 BIT(NL80211_IFTYPE_AP) |
689 BIT(NL80211_IFTYPE_MESH_POINT),
690 .supports_monitor = false,
691 .supports_sta_ps = false,
692 .supports_shadow_regs = false,
693 .fw_mem_mode = 0,
694 .num_vdevs = 16 + 1,
695 .num_peers = 512,
696 .supports_regdb = false,
697 .idle_ps = false,
698 .supports_suspend = false,
699 .hal_params = &ath11k_hw_hal_params_ipq8074,
700 .single_pdev_only = false,
701 .coldboot_cal_mm = true,
702 .coldboot_cal_ftm = true,
703 .cbcal_restart_fw = true,
704 .fix_l1ss = true,
705 .supports_dynamic_smps_6ghz = false,
706 .alloc_cacheable_memory = true,
707 .supports_rssi_stats = false,
708 .fw_wmi_diag_event = false,
709 .current_cc_support = false,
710 .dbr_debug_support = true,
711 .global_reset = false,
712 .bios_sar_capa = NULL,
713 .m3_fw_support = false,
714 .fixed_bdf_addr = true,
715 .fixed_mem_region = true,
716 .static_window_map = false,
717 .hybrid_bus_type = false,
718 .fixed_fw_mem = false,
719 .support_off_channel_tx = false,
720 .supports_multi_bssid = false,
721
722 .sram_dump = {},
723
724 .tcl_ring_retry = true,
725 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
726 .smp2p_wow_exit = false,
727 .support_fw_mac_sequence = false,
728 .support_dual_stations = false,
729 .pdev_suspend = false,
730 },
731 {
732 .name = "qca2066 hw2.1",
733 .hw_rev = ATH11K_HW_QCA2066_HW21,
734 .fw = {
735 .dir = "QCA2066/hw2.1",
736 .board_size = 256 * 1024,
737 .cal_offset = 128 * 1024,
738 },
739 .max_radios = 3,
740 .bdf_addr = 0x4B0C0000,
741 .hw_ops = &wcn6855_ops,
742 .ring_mask = &ath11k_hw_ring_mask_qca6390,
743 .internal_sleep_clock = true,
744 .regs = &wcn6855_regs,
745 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390,
746 .host_ce_config = ath11k_host_ce_config_qca6390,
747 .ce_count = 9,
748 .target_ce_config = ath11k_target_ce_config_wlan_qca6390,
749 .target_ce_count = 9,
750 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
751 .svc_to_ce_map_len = 14,
752 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
753 .single_pdev_only = true,
754 .rxdma1_enable = false,
755 .num_rxdma_per_pdev = 2,
756 .rx_mac_buf_ring = true,
757 .vdev_start_delay = true,
758 .htt_peer_map_v2 = false,
759
760 .spectral = {
761 .fft_sz = 0,
762 .fft_pad_sz = 0,
763 .summary_pad_sz = 0,
764 .fft_hdr_len = 0,
765 .max_fft_bins = 0,
766 .fragment_160mhz = false,
767 },
768
769 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
770 BIT(NL80211_IFTYPE_AP) |
771 BIT(NL80211_IFTYPE_P2P_DEVICE) |
772 BIT(NL80211_IFTYPE_P2P_CLIENT) |
773 BIT(NL80211_IFTYPE_P2P_GO),
774 .supports_monitor = false,
775 .full_monitor_mode = false,
776 .supports_shadow_regs = true,
777 .idle_ps = true,
778 .supports_sta_ps = true,
779 .coldboot_cal_mm = false,
780 .coldboot_cal_ftm = false,
781 .cbcal_restart_fw = false,
782 .fw_mem_mode = 0,
783 .num_vdevs = 2 + 1,
784 .num_peers = 512,
785 .supports_suspend = true,
786 .hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855),
787 .supports_regdb = true,
788 .fix_l1ss = false,
789 .credit_flow = true,
790 .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390,
791 .hal_params = &ath11k_hw_hal_params_qca6390,
792 .supports_dynamic_smps_6ghz = false,
793 .alloc_cacheable_memory = false,
794 .supports_rssi_stats = true,
795 .fw_wmi_diag_event = true,
796 .current_cc_support = true,
797 .dbr_debug_support = false,
798 .global_reset = true,
799 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855,
800 .m3_fw_support = true,
801 .fixed_bdf_addr = false,
802 .fixed_mem_region = false,
803 .static_window_map = false,
804 .hybrid_bus_type = false,
805 .fixed_fw_mem = false,
806 .support_off_channel_tx = true,
807 .supports_multi_bssid = true,
808
809 .sram_dump = {
810 .start = 0x01400000,
811 .end = 0x0177ffff,
812 },
813
814 .tcl_ring_retry = true,
815 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
816 .smp2p_wow_exit = false,
817 .support_fw_mac_sequence = true,
818 .support_dual_stations = true,
819 },
820 {
821 .name = "qca6698aq hw2.1",
822 .hw_rev = ATH11K_HW_QCA6698AQ_HW21,
823 .fw = {
824 .dir = "QCA6698AQ/hw2.1",
825 .board_size = 256 * 1024,
826 .cal_offset = 128 * 1024,
827 },
828 .max_radios = 3,
829 .bdf_addr = 0x4B0C0000,
830 .hw_ops = &wcn6855_ops,
831 .ring_mask = &ath11k_hw_ring_mask_qca6390,
832 .internal_sleep_clock = true,
833 .regs = &wcn6855_regs,
834 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390,
835 .host_ce_config = ath11k_host_ce_config_qca6390,
836 .ce_count = 9,
837 .target_ce_config = ath11k_target_ce_config_wlan_qca6390,
838 .target_ce_count = 9,
839 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
840 .svc_to_ce_map_len = 14,
841 .single_pdev_only = true,
842 .rxdma1_enable = false,
843 .num_rxdma_per_pdev = 2,
844 .rx_mac_buf_ring = true,
845 .vdev_start_delay = true,
846 .htt_peer_map_v2 = false,
847
848 .spectral = {
849 .fft_sz = 0,
850 .fft_pad_sz = 0,
851 .summary_pad_sz = 0,
852 .fft_hdr_len = 0,
853 .max_fft_bins = 0,
854 .fragment_160mhz = false,
855 },
856
857 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
858 BIT(NL80211_IFTYPE_AP) |
859 BIT(NL80211_IFTYPE_P2P_DEVICE) |
860 BIT(NL80211_IFTYPE_P2P_CLIENT) |
861 BIT(NL80211_IFTYPE_P2P_GO),
862 .supports_monitor = false,
863 .supports_shadow_regs = true,
864 .idle_ps = true,
865 .supports_sta_ps = true,
866 .coldboot_cal_mm = false,
867 .coldboot_cal_ftm = false,
868 .cbcal_restart_fw = false,
869 .fw_mem_mode = 0,
870 .num_vdevs = 2 + 1,
871 .num_peers = 512,
872 .supports_suspend = true,
873 .hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855),
874 .supports_regdb = true,
875 .fix_l1ss = false,
876 .credit_flow = true,
877 .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390,
878 .hal_params = &ath11k_hw_hal_params_qca6390,
879 .supports_dynamic_smps_6ghz = false,
880 .alloc_cacheable_memory = false,
881 .supports_rssi_stats = true,
882 .fw_wmi_diag_event = true,
883 .current_cc_support = true,
884 .dbr_debug_support = false,
885 .global_reset = true,
886 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855,
887 .m3_fw_support = true,
888 .fixed_bdf_addr = false,
889 .fixed_mem_region = false,
890 .static_window_map = false,
891 .hybrid_bus_type = false,
892 .fixed_fw_mem = false,
893 .support_off_channel_tx = true,
894 .supports_multi_bssid = true,
895
896 .sram_dump = {
897 .start = 0x01400000,
898 .end = 0x0177ffff,
899 },
900
901 .tcl_ring_retry = true,
902 .tx_ring_size = DP_TCL_DATA_RING_SIZE,
903 .smp2p_wow_exit = false,
904 .support_fw_mac_sequence = true,
905 .support_dual_stations = true,
906 .pdev_suspend = false,
907 },
908 };
909
ath11k_core_get_single_pdev(struct ath11k_base * ab)910 static inline struct ath11k_pdev *ath11k_core_get_single_pdev(struct ath11k_base *ab)
911 {
912 WARN_ON(!ab->hw_params.single_pdev_only);
913
914 return &ab->pdevs[0];
915 }
916
ath11k_fw_stats_pdevs_free(struct list_head * head)917 void ath11k_fw_stats_pdevs_free(struct list_head *head)
918 {
919 struct ath11k_fw_stats_pdev *i, *tmp;
920
921 list_for_each_entry_safe(i, tmp, head, list) {
922 list_del(&i->list);
923 kfree(i);
924 }
925 }
926
ath11k_fw_stats_vdevs_free(struct list_head * head)927 void ath11k_fw_stats_vdevs_free(struct list_head *head)
928 {
929 struct ath11k_fw_stats_vdev *i, *tmp;
930
931 list_for_each_entry_safe(i, tmp, head, list) {
932 list_del(&i->list);
933 kfree(i);
934 }
935 }
936
ath11k_fw_stats_bcn_free(struct list_head * head)937 void ath11k_fw_stats_bcn_free(struct list_head *head)
938 {
939 struct ath11k_fw_stats_bcn *i, *tmp;
940
941 list_for_each_entry_safe(i, tmp, head, list) {
942 list_del(&i->list);
943 kfree(i);
944 }
945 }
946
ath11k_fw_stats_init(struct ath11k * ar)947 void ath11k_fw_stats_init(struct ath11k *ar)
948 {
949 INIT_LIST_HEAD(&ar->fw_stats.pdevs);
950 INIT_LIST_HEAD(&ar->fw_stats.vdevs);
951 INIT_LIST_HEAD(&ar->fw_stats.bcn);
952
953 init_completion(&ar->fw_stats_complete);
954 }
955
ath11k_fw_stats_free(struct ath11k_fw_stats * stats)956 void ath11k_fw_stats_free(struct ath11k_fw_stats *stats)
957 {
958 ath11k_fw_stats_pdevs_free(&stats->pdevs);
959 ath11k_fw_stats_vdevs_free(&stats->vdevs);
960 ath11k_fw_stats_bcn_free(&stats->bcn);
961 }
962
ath11k_core_coldboot_cal_support(struct ath11k_base * ab)963 bool ath11k_core_coldboot_cal_support(struct ath11k_base *ab)
964 {
965 if (!ath11k_cold_boot_cal)
966 return false;
967
968 if (ath11k_ftm_mode)
969 return ab->hw_params.coldboot_cal_ftm;
970
971 else
972 return ab->hw_params.coldboot_cal_mm;
973 }
974
ath11k_core_suspend(struct ath11k_base * ab)975 int ath11k_core_suspend(struct ath11k_base *ab)
976 {
977 int ret;
978 struct ath11k_pdev *pdev;
979 struct ath11k *ar;
980
981 if (!ab->hw_params.supports_suspend)
982 return -EOPNOTSUPP;
983
984 /* so far single_pdev_only chips have supports_suspend as true
985 * and only the first pdev is valid.
986 */
987 pdev = ath11k_core_get_single_pdev(ab);
988 ar = pdev->ar;
989 if (!ar || ar->state != ATH11K_STATE_OFF)
990 return 0;
991
992 ret = ath11k_dp_rx_pktlog_stop(ab, true);
993 if (ret) {
994 ath11k_warn(ab, "failed to stop dp rx (and timer) pktlog during suspend: %d\n",
995 ret);
996 return ret;
997 }
998
999 ret = ath11k_mac_wait_tx_complete(ar);
1000 if (ret) {
1001 ath11k_warn(ab, "failed to wait tx complete: %d\n", ret);
1002 return ret;
1003 }
1004
1005 ret = ath11k_wow_enable(ab);
1006 if (ret) {
1007 ath11k_warn(ab, "failed to enable wow during suspend: %d\n", ret);
1008 return ret;
1009 }
1010
1011 ret = ath11k_dp_rx_pktlog_stop(ab, false);
1012 if (ret) {
1013 ath11k_warn(ab, "failed to stop dp rx pktlog during suspend: %d\n",
1014 ret);
1015 return ret;
1016 }
1017
1018 ath11k_ce_stop_shadow_timers(ab);
1019 ath11k_dp_stop_shadow_timers(ab);
1020
1021 ath11k_hif_irq_disable(ab);
1022 ath11k_hif_ce_irq_disable(ab);
1023
1024 ret = ath11k_hif_suspend(ab);
1025 if (ret) {
1026 ath11k_warn(ab, "failed to suspend hif: %d\n", ret);
1027 return ret;
1028 }
1029
1030 return 0;
1031 }
1032 EXPORT_SYMBOL(ath11k_core_suspend);
1033
ath11k_core_resume(struct ath11k_base * ab)1034 int ath11k_core_resume(struct ath11k_base *ab)
1035 {
1036 int ret;
1037 struct ath11k_pdev *pdev;
1038 struct ath11k *ar;
1039
1040 if (!ab->hw_params.supports_suspend)
1041 return -EOPNOTSUPP;
1042
1043 /* so far signle_pdev_only chips have supports_suspend as true
1044 * and only the first pdev is valid.
1045 */
1046 pdev = ath11k_core_get_single_pdev(ab);
1047 ar = pdev->ar;
1048 if (!ar || ar->state != ATH11K_STATE_OFF)
1049 return 0;
1050
1051 ret = ath11k_hif_resume(ab);
1052 if (ret) {
1053 ath11k_warn(ab, "failed to resume hif during resume: %d\n", ret);
1054 return ret;
1055 }
1056
1057 ath11k_hif_ce_irq_enable(ab);
1058 ath11k_hif_irq_enable(ab);
1059
1060 ret = ath11k_dp_rx_pktlog_start(ab);
1061 if (ret) {
1062 ath11k_warn(ab, "failed to start rx pktlog during resume: %d\n",
1063 ret);
1064 return ret;
1065 }
1066
1067 ret = ath11k_wow_wakeup(ab);
1068 if (ret) {
1069 ath11k_warn(ab, "failed to wakeup wow during resume: %d\n", ret);
1070 return ret;
1071 }
1072
1073 return 0;
1074 }
1075 EXPORT_SYMBOL(ath11k_core_resume);
1076
ath11k_core_check_cc_code_bdfext(const struct dmi_header * hdr,void * data)1077 static void ath11k_core_check_cc_code_bdfext(const struct dmi_header *hdr, void *data)
1078 {
1079 struct ath11k_base *ab = data;
1080 const char *magic = ATH11K_SMBIOS_BDF_EXT_MAGIC;
1081 struct ath11k_smbios_bdf *smbios = (struct ath11k_smbios_bdf *)hdr;
1082 ssize_t copied;
1083 size_t len;
1084 int i;
1085
1086 if (ab->qmi.target.bdf_ext[0] != '\0')
1087 return;
1088
1089 if (hdr->type != ATH11K_SMBIOS_BDF_EXT_TYPE)
1090 return;
1091
1092 if (hdr->length != ATH11K_SMBIOS_BDF_EXT_LENGTH) {
1093 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1094 "wrong smbios bdf ext type length (%d).\n",
1095 hdr->length);
1096 return;
1097 }
1098
1099 spin_lock_bh(&ab->base_lock);
1100
1101 switch (smbios->country_code_flag) {
1102 case ATH11K_SMBIOS_CC_ISO:
1103 ab->new_alpha2[0] = (smbios->cc_code >> 8) & 0xff;
1104 ab->new_alpha2[1] = smbios->cc_code & 0xff;
1105 ath11k_dbg(ab, ATH11K_DBG_BOOT, "smbios cc_code %c%c\n",
1106 ab->new_alpha2[0], ab->new_alpha2[1]);
1107 break;
1108 case ATH11K_SMBIOS_CC_WW:
1109 ab->new_alpha2[0] = '0';
1110 ab->new_alpha2[1] = '0';
1111 ath11k_dbg(ab, ATH11K_DBG_BOOT, "smbios worldwide regdomain\n");
1112 break;
1113 default:
1114 ath11k_dbg(ab, ATH11K_DBG_BOOT, "ignore smbios country code setting %d\n",
1115 smbios->country_code_flag);
1116 break;
1117 }
1118
1119 spin_unlock_bh(&ab->base_lock);
1120
1121 if (!smbios->bdf_enabled) {
1122 ath11k_dbg(ab, ATH11K_DBG_BOOT, "bdf variant name not found.\n");
1123 return;
1124 }
1125
1126 /* Only one string exists (per spec) */
1127 if (memcmp(smbios->bdf_ext, magic, strlen(magic)) != 0) {
1128 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1129 "bdf variant magic does not match.\n");
1130 return;
1131 }
1132
1133 len = min_t(size_t,
1134 strlen(smbios->bdf_ext), sizeof(ab->qmi.target.bdf_ext));
1135 for (i = 0; i < len; i++) {
1136 if (!isascii(smbios->bdf_ext[i]) || !isprint(smbios->bdf_ext[i])) {
1137 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1138 "bdf variant name contains non ascii chars.\n");
1139 return;
1140 }
1141 }
1142
1143 /* Copy extension name without magic prefix */
1144 copied = strscpy(ab->qmi.target.bdf_ext, smbios->bdf_ext + strlen(magic),
1145 sizeof(ab->qmi.target.bdf_ext));
1146 if (copied < 0) {
1147 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1148 "bdf variant string is longer than the buffer can accommodate\n");
1149 return;
1150 }
1151
1152 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1153 "found and validated bdf variant smbios_type 0x%x bdf %s\n",
1154 ATH11K_SMBIOS_BDF_EXT_TYPE, ab->qmi.target.bdf_ext);
1155 }
1156
ath11k_core_check_smbios(struct ath11k_base * ab)1157 int ath11k_core_check_smbios(struct ath11k_base *ab)
1158 {
1159 ab->qmi.target.bdf_ext[0] = '\0';
1160 dmi_walk(ath11k_core_check_cc_code_bdfext, ab);
1161
1162 if (ab->qmi.target.bdf_ext[0] == '\0')
1163 return -ENODATA;
1164
1165 return 0;
1166 }
1167
ath11k_core_check_dt(struct ath11k_base * ab)1168 int ath11k_core_check_dt(struct ath11k_base *ab)
1169 {
1170 size_t max_len = sizeof(ab->qmi.target.bdf_ext);
1171 const char *variant = NULL;
1172 struct device_node *node;
1173
1174 node = ab->dev->of_node;
1175 if (!node)
1176 return -ENOENT;
1177
1178 of_property_read_string(node, "qcom,calibration-variant",
1179 &variant);
1180 if (!variant)
1181 of_property_read_string(node, "qcom,ath11k-calibration-variant",
1182 &variant);
1183 if (!variant)
1184 return -ENODATA;
1185
1186 if (strscpy(ab->qmi.target.bdf_ext, variant, max_len) < 0)
1187 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1188 "bdf variant string is longer than the buffer can accommodate (variant: %s)\n",
1189 variant);
1190
1191 return 0;
1192 }
1193
1194 enum ath11k_bdf_name_type {
1195 ATH11K_BDF_NAME_FULL,
1196 ATH11K_BDF_NAME_BUS_NAME,
1197 ATH11K_BDF_NAME_CHIP_ID,
1198 };
1199
__ath11k_core_create_board_name(struct ath11k_base * ab,char * name,size_t name_len,bool with_variant,enum ath11k_bdf_name_type name_type)1200 static int __ath11k_core_create_board_name(struct ath11k_base *ab, char *name,
1201 size_t name_len, bool with_variant,
1202 enum ath11k_bdf_name_type name_type)
1203 {
1204 /* strlen(',variant=') + strlen(ab->qmi.target.bdf_ext) */
1205 char variant[9 + ATH11K_QMI_BDF_EXT_STR_LENGTH] = { 0 };
1206
1207 if (with_variant && ab->qmi.target.bdf_ext[0] != '\0')
1208 scnprintf(variant, sizeof(variant), ",variant=%s",
1209 ab->qmi.target.bdf_ext);
1210
1211 switch (ab->id.bdf_search) {
1212 case ATH11K_BDF_SEARCH_BUS_AND_BOARD:
1213 switch (name_type) {
1214 case ATH11K_BDF_NAME_FULL:
1215 scnprintf(name, name_len,
1216 "bus=%s,vendor=%04x,device=%04x,subsystem-vendor=%04x,subsystem-device=%04x,qmi-chip-id=%d,qmi-board-id=%d%s",
1217 ath11k_bus_str(ab->hif.bus),
1218 ab->id.vendor, ab->id.device,
1219 ab->id.subsystem_vendor,
1220 ab->id.subsystem_device,
1221 ab->qmi.target.chip_id,
1222 ab->qmi.target.board_id,
1223 variant);
1224 break;
1225 case ATH11K_BDF_NAME_BUS_NAME:
1226 scnprintf(name, name_len,
1227 "bus=%s",
1228 ath11k_bus_str(ab->hif.bus));
1229 break;
1230 case ATH11K_BDF_NAME_CHIP_ID:
1231 scnprintf(name, name_len,
1232 "bus=%s,qmi-chip-id=%d",
1233 ath11k_bus_str(ab->hif.bus),
1234 ab->qmi.target.chip_id);
1235 break;
1236 }
1237 break;
1238 default:
1239 scnprintf(name, name_len,
1240 "bus=%s,qmi-chip-id=%d,qmi-board-id=%d%s",
1241 ath11k_bus_str(ab->hif.bus),
1242 ab->qmi.target.chip_id,
1243 ab->qmi.target.board_id, variant);
1244 break;
1245 }
1246
1247 ath11k_dbg(ab, ATH11K_DBG_BOOT, "using board name '%s'\n", name);
1248
1249 return 0;
1250 }
1251
ath11k_core_create_board_name(struct ath11k_base * ab,char * name,size_t name_len)1252 static int ath11k_core_create_board_name(struct ath11k_base *ab, char *name,
1253 size_t name_len)
1254 {
1255 return __ath11k_core_create_board_name(ab, name, name_len, true,
1256 ATH11K_BDF_NAME_FULL);
1257 }
1258
ath11k_core_create_fallback_board_name(struct ath11k_base * ab,char * name,size_t name_len)1259 static int ath11k_core_create_fallback_board_name(struct ath11k_base *ab, char *name,
1260 size_t name_len)
1261 {
1262 return __ath11k_core_create_board_name(ab, name, name_len, false,
1263 ATH11K_BDF_NAME_FULL);
1264 }
1265
ath11k_core_create_bus_type_board_name(struct ath11k_base * ab,char * name,size_t name_len)1266 static int ath11k_core_create_bus_type_board_name(struct ath11k_base *ab, char *name,
1267 size_t name_len)
1268 {
1269 return __ath11k_core_create_board_name(ab, name, name_len, false,
1270 ATH11K_BDF_NAME_BUS_NAME);
1271 }
1272
ath11k_core_create_chip_id_board_name(struct ath11k_base * ab,char * name,size_t name_len)1273 static int ath11k_core_create_chip_id_board_name(struct ath11k_base *ab, char *name,
1274 size_t name_len)
1275 {
1276 return __ath11k_core_create_board_name(ab, name, name_len, false,
1277 ATH11K_BDF_NAME_CHIP_ID);
1278 }
1279
ath11k_core_firmware_request(struct ath11k_base * ab,const char * file)1280 const struct firmware *ath11k_core_firmware_request(struct ath11k_base *ab,
1281 const char *file)
1282 {
1283 const struct firmware *fw;
1284 char path[100];
1285 int ret;
1286
1287 if (file == NULL)
1288 return ERR_PTR(-ENOENT);
1289
1290 ath11k_core_create_firmware_path(ab, file, path, sizeof(path));
1291
1292 ret = firmware_request_nowarn(&fw, path, ab->dev);
1293 if (ret)
1294 return ERR_PTR(ret);
1295
1296 ath11k_dbg(ab, ATH11K_DBG_BOOT, "firmware request %s size %zu\n",
1297 path, fw->size);
1298
1299 return fw;
1300 }
1301
ath11k_core_free_bdf(struct ath11k_base * ab,struct ath11k_board_data * bd)1302 void ath11k_core_free_bdf(struct ath11k_base *ab, struct ath11k_board_data *bd)
1303 {
1304 if (!IS_ERR(bd->fw))
1305 release_firmware(bd->fw);
1306
1307 memset(bd, 0, sizeof(*bd));
1308 }
1309
ath11k_core_parse_bd_ie_board(struct ath11k_base * ab,struct ath11k_board_data * bd,const void * buf,size_t buf_len,const char * boardname,int ie_id,int name_id,int data_id)1310 static int ath11k_core_parse_bd_ie_board(struct ath11k_base *ab,
1311 struct ath11k_board_data *bd,
1312 const void *buf, size_t buf_len,
1313 const char *boardname,
1314 int ie_id,
1315 int name_id,
1316 int data_id)
1317 {
1318 const struct ath11k_fw_ie *hdr;
1319 bool name_match_found;
1320 int ret, board_ie_id;
1321 size_t board_ie_len;
1322 const void *board_ie_data;
1323
1324 name_match_found = false;
1325
1326 /* go through ATH11K_BD_IE_BOARD_/ATH11K_BD_IE_REGDB_ elements */
1327 while (buf_len > sizeof(struct ath11k_fw_ie)) {
1328 hdr = buf;
1329 board_ie_id = le32_to_cpu(hdr->id);
1330 board_ie_len = le32_to_cpu(hdr->len);
1331 board_ie_data = hdr->data;
1332
1333 buf_len -= sizeof(*hdr);
1334 buf += sizeof(*hdr);
1335
1336 if (buf_len < ALIGN(board_ie_len, 4)) {
1337 ath11k_err(ab, "invalid %s length: %zu < %zu\n",
1338 ath11k_bd_ie_type_str(ie_id),
1339 buf_len, ALIGN(board_ie_len, 4));
1340 ret = -EINVAL;
1341 goto out;
1342 }
1343
1344 if (board_ie_id == name_id) {
1345 ath11k_dbg_dump(ab, ATH11K_DBG_BOOT, "board name", "",
1346 board_ie_data, board_ie_len);
1347
1348 if (board_ie_len != strlen(boardname))
1349 goto next;
1350
1351 ret = memcmp(board_ie_data, boardname, strlen(boardname));
1352 if (ret)
1353 goto next;
1354
1355 name_match_found = true;
1356 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1357 "found match %s for name '%s'",
1358 ath11k_bd_ie_type_str(ie_id),
1359 boardname);
1360 } else if (board_ie_id == data_id) {
1361 if (!name_match_found)
1362 /* no match found */
1363 goto next;
1364
1365 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1366 "found %s for '%s'",
1367 ath11k_bd_ie_type_str(ie_id),
1368 boardname);
1369
1370 bd->data = board_ie_data;
1371 bd->len = board_ie_len;
1372
1373 ret = 0;
1374 goto out;
1375 } else {
1376 ath11k_warn(ab, "unknown %s id found: %d\n",
1377 ath11k_bd_ie_type_str(ie_id),
1378 board_ie_id);
1379 }
1380 next:
1381 /* jump over the padding */
1382 board_ie_len = ALIGN(board_ie_len, 4);
1383
1384 buf_len -= board_ie_len;
1385 buf += board_ie_len;
1386 }
1387
1388 /* no match found */
1389 ret = -ENOENT;
1390
1391 out:
1392 return ret;
1393 }
1394
ath11k_core_fetch_board_data_api_n(struct ath11k_base * ab,struct ath11k_board_data * bd,const char * boardname,int ie_id_match,int name_id,int data_id)1395 static int ath11k_core_fetch_board_data_api_n(struct ath11k_base *ab,
1396 struct ath11k_board_data *bd,
1397 const char *boardname,
1398 int ie_id_match,
1399 int name_id,
1400 int data_id)
1401 {
1402 size_t len, magic_len;
1403 const u8 *data;
1404 char *filename, filepath[100];
1405 size_t ie_len;
1406 struct ath11k_fw_ie *hdr;
1407 int ret, ie_id;
1408
1409 filename = ATH11K_BOARD_API2_FILE;
1410
1411 if (!bd->fw)
1412 bd->fw = ath11k_core_firmware_request(ab, filename);
1413
1414 if (IS_ERR(bd->fw))
1415 return PTR_ERR(bd->fw);
1416
1417 data = bd->fw->data;
1418 len = bd->fw->size;
1419
1420 ath11k_core_create_firmware_path(ab, filename,
1421 filepath, sizeof(filepath));
1422
1423 /* magic has extra null byte padded */
1424 magic_len = strlen(ATH11K_BOARD_MAGIC) + 1;
1425 if (len < magic_len) {
1426 ath11k_err(ab, "failed to find magic value in %s, file too short: %zu\n",
1427 filepath, len);
1428 ret = -EINVAL;
1429 goto err;
1430 }
1431
1432 if (memcmp(data, ATH11K_BOARD_MAGIC, magic_len)) {
1433 ath11k_err(ab, "found invalid board magic\n");
1434 ret = -EINVAL;
1435 goto err;
1436 }
1437
1438 /* magic is padded to 4 bytes */
1439 magic_len = ALIGN(magic_len, 4);
1440 if (len < magic_len) {
1441 ath11k_err(ab, "failed: %s too small to contain board data, len: %zu\n",
1442 filepath, len);
1443 ret = -EINVAL;
1444 goto err;
1445 }
1446
1447 data += magic_len;
1448 len -= magic_len;
1449
1450 while (len > sizeof(struct ath11k_fw_ie)) {
1451 hdr = (struct ath11k_fw_ie *)data;
1452 ie_id = le32_to_cpu(hdr->id);
1453 ie_len = le32_to_cpu(hdr->len);
1454
1455 len -= sizeof(*hdr);
1456 data = hdr->data;
1457
1458 if (len < ALIGN(ie_len, 4)) {
1459 ath11k_err(ab, "invalid length for board ie_id %d ie_len %zu len %zu\n",
1460 ie_id, ie_len, len);
1461 ret = -EINVAL;
1462 goto err;
1463 }
1464
1465 if (ie_id == ie_id_match) {
1466 ret = ath11k_core_parse_bd_ie_board(ab, bd, data,
1467 ie_len,
1468 boardname,
1469 ie_id_match,
1470 name_id,
1471 data_id);
1472 if (ret == -ENOENT)
1473 /* no match found, continue */
1474 goto next;
1475 else if (ret)
1476 /* there was an error, bail out */
1477 goto err;
1478 /* either found or error, so stop searching */
1479 goto out;
1480 }
1481 next:
1482 /* jump over the padding */
1483 ie_len = ALIGN(ie_len, 4);
1484
1485 len -= ie_len;
1486 data += ie_len;
1487 }
1488
1489 out:
1490 if (!bd->data || !bd->len) {
1491 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1492 "failed to fetch %s for %s from %s\n",
1493 ath11k_bd_ie_type_str(ie_id_match),
1494 boardname, filepath);
1495 ret = -ENODATA;
1496 goto err;
1497 }
1498
1499 return 0;
1500
1501 err:
1502 ath11k_core_free_bdf(ab, bd);
1503 return ret;
1504 }
1505
ath11k_core_fetch_board_data_api_1(struct ath11k_base * ab,struct ath11k_board_data * bd,const char * name)1506 int ath11k_core_fetch_board_data_api_1(struct ath11k_base *ab,
1507 struct ath11k_board_data *bd,
1508 const char *name)
1509 {
1510 bd->fw = ath11k_core_firmware_request(ab, name);
1511
1512 if (IS_ERR(bd->fw))
1513 return PTR_ERR(bd->fw);
1514
1515 bd->data = bd->fw->data;
1516 bd->len = bd->fw->size;
1517
1518 return 0;
1519 }
1520
1521 #define BOARD_NAME_SIZE 200
ath11k_core_fetch_bdf(struct ath11k_base * ab,struct ath11k_board_data * bd)1522 int ath11k_core_fetch_bdf(struct ath11k_base *ab, struct ath11k_board_data *bd)
1523 {
1524 char *boardname = NULL, *fallback_boardname = NULL, *chip_id_boardname = NULL;
1525 char *filename, filepath[100];
1526 int bd_api;
1527 int ret = 0;
1528
1529 filename = ATH11K_BOARD_API2_FILE;
1530 boardname = kzalloc(BOARD_NAME_SIZE, GFP_KERNEL);
1531 if (!boardname) {
1532 ret = -ENOMEM;
1533 goto exit;
1534 }
1535
1536 ret = ath11k_core_create_board_name(ab, boardname, BOARD_NAME_SIZE);
1537 if (ret) {
1538 ath11k_err(ab, "failed to create board name: %d", ret);
1539 goto exit;
1540 }
1541
1542 bd_api = 2;
1543 ret = ath11k_core_fetch_board_data_api_n(ab, bd, boardname,
1544 ATH11K_BD_IE_BOARD,
1545 ATH11K_BD_IE_BOARD_NAME,
1546 ATH11K_BD_IE_BOARD_DATA);
1547 if (!ret)
1548 goto exit;
1549
1550 fallback_boardname = kzalloc(BOARD_NAME_SIZE, GFP_KERNEL);
1551 if (!fallback_boardname) {
1552 ret = -ENOMEM;
1553 goto exit;
1554 }
1555
1556 ret = ath11k_core_create_fallback_board_name(ab, fallback_boardname,
1557 BOARD_NAME_SIZE);
1558 if (ret) {
1559 ath11k_err(ab, "failed to create fallback board name: %d", ret);
1560 goto exit;
1561 }
1562
1563 ret = ath11k_core_fetch_board_data_api_n(ab, bd, fallback_boardname,
1564 ATH11K_BD_IE_BOARD,
1565 ATH11K_BD_IE_BOARD_NAME,
1566 ATH11K_BD_IE_BOARD_DATA);
1567 if (!ret)
1568 goto exit;
1569
1570 chip_id_boardname = kzalloc(BOARD_NAME_SIZE, GFP_KERNEL);
1571 if (!chip_id_boardname) {
1572 ret = -ENOMEM;
1573 goto exit;
1574 }
1575
1576 ret = ath11k_core_create_chip_id_board_name(ab, chip_id_boardname,
1577 BOARD_NAME_SIZE);
1578 if (ret) {
1579 ath11k_err(ab, "failed to create chip id board name: %d", ret);
1580 goto exit;
1581 }
1582
1583 ret = ath11k_core_fetch_board_data_api_n(ab, bd, chip_id_boardname,
1584 ATH11K_BD_IE_BOARD,
1585 ATH11K_BD_IE_BOARD_NAME,
1586 ATH11K_BD_IE_BOARD_DATA);
1587
1588 if (!ret)
1589 goto exit;
1590
1591 bd_api = 1;
1592 ret = ath11k_core_fetch_board_data_api_1(ab, bd, ATH11K_DEFAULT_BOARD_FILE);
1593 if (ret) {
1594 ath11k_core_create_firmware_path(ab, filename,
1595 filepath, sizeof(filepath));
1596 ath11k_err(ab, "failed to fetch board data for %s from %s\n",
1597 boardname, filepath);
1598 if (memcmp(boardname, fallback_boardname, strlen(boardname)))
1599 ath11k_err(ab, "failed to fetch board data for %s from %s\n",
1600 fallback_boardname, filepath);
1601
1602 ath11k_err(ab, "failed to fetch board data for %s from %s\n",
1603 chip_id_boardname, filepath);
1604
1605 ath11k_err(ab, "failed to fetch board.bin from %s\n",
1606 ab->hw_params.fw.dir);
1607 }
1608
1609 exit:
1610 kfree(boardname);
1611 kfree(fallback_boardname);
1612 kfree(chip_id_boardname);
1613
1614 if (!ret)
1615 ath11k_dbg(ab, ATH11K_DBG_BOOT, "using board api %d\n", bd_api);
1616
1617 return ret;
1618 }
1619
ath11k_core_fetch_regdb(struct ath11k_base * ab,struct ath11k_board_data * bd)1620 int ath11k_core_fetch_regdb(struct ath11k_base *ab, struct ath11k_board_data *bd)
1621 {
1622 char boardname[BOARD_NAME_SIZE], default_boardname[BOARD_NAME_SIZE];
1623 int ret;
1624
1625 ret = ath11k_core_create_board_name(ab, boardname, BOARD_NAME_SIZE);
1626 if (ret) {
1627 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1628 "failed to create board name for regdb: %d", ret);
1629 goto exit;
1630 }
1631
1632 ret = ath11k_core_fetch_board_data_api_n(ab, bd, boardname,
1633 ATH11K_BD_IE_REGDB,
1634 ATH11K_BD_IE_REGDB_NAME,
1635 ATH11K_BD_IE_REGDB_DATA);
1636 if (!ret)
1637 goto exit;
1638
1639 ret = ath11k_core_create_bus_type_board_name(ab, default_boardname,
1640 BOARD_NAME_SIZE);
1641 if (ret) {
1642 ath11k_dbg(ab, ATH11K_DBG_BOOT,
1643 "failed to create default board name for regdb: %d", ret);
1644 goto exit;
1645 }
1646
1647 ret = ath11k_core_fetch_board_data_api_n(ab, bd, default_boardname,
1648 ATH11K_BD_IE_REGDB,
1649 ATH11K_BD_IE_REGDB_NAME,
1650 ATH11K_BD_IE_REGDB_DATA);
1651 if (!ret)
1652 goto exit;
1653
1654 ret = ath11k_core_fetch_board_data_api_1(ab, bd, ATH11K_REGDB_FILE_NAME);
1655 if (ret)
1656 ath11k_dbg(ab, ATH11K_DBG_BOOT, "failed to fetch %s from %s\n",
1657 ATH11K_REGDB_FILE_NAME, ab->hw_params.fw.dir);
1658
1659 exit:
1660 if (!ret)
1661 ath11k_dbg(ab, ATH11K_DBG_BOOT, "fetched regdb\n");
1662
1663 return ret;
1664 }
1665
ath11k_core_stop(struct ath11k_base * ab)1666 static void ath11k_core_stop(struct ath11k_base *ab)
1667 {
1668 if (!test_bit(ATH11K_FLAG_CRASH_FLUSH, &ab->dev_flags))
1669 ath11k_qmi_firmware_stop(ab);
1670
1671 ath11k_hif_stop(ab);
1672 ath11k_wmi_detach(ab);
1673 ath11k_dp_pdev_reo_cleanup(ab);
1674
1675 /* De-Init of components as needed */
1676 }
1677
ath11k_core_soc_create(struct ath11k_base * ab)1678 static int ath11k_core_soc_create(struct ath11k_base *ab)
1679 {
1680 int ret;
1681
1682 if (ath11k_ftm_mode) {
1683 ab->fw_mode = ATH11K_FIRMWARE_MODE_FTM;
1684 ath11k_info(ab, "Booting in factory test mode\n");
1685 }
1686
1687 ret = ath11k_qmi_init_service(ab);
1688 if (ret) {
1689 ath11k_err(ab, "failed to initialize qmi :%d\n", ret);
1690 return ret;
1691 }
1692
1693 ret = ath11k_debugfs_soc_create(ab);
1694 if (ret) {
1695 ath11k_err(ab, "failed to create ath11k debugfs\n");
1696 goto err_qmi_deinit;
1697 }
1698
1699 ret = ath11k_hif_power_up(ab);
1700 if (ret) {
1701 ath11k_err(ab, "failed to power up :%d\n", ret);
1702 goto err_debugfs_reg;
1703 }
1704
1705 return 0;
1706
1707 err_debugfs_reg:
1708 ath11k_debugfs_soc_destroy(ab);
1709 err_qmi_deinit:
1710 ath11k_qmi_deinit_service(ab);
1711 return ret;
1712 }
1713
ath11k_core_soc_destroy(struct ath11k_base * ab)1714 static void ath11k_core_soc_destroy(struct ath11k_base *ab)
1715 {
1716 ath11k_debugfs_soc_destroy(ab);
1717 ath11k_dp_free(ab);
1718 ath11k_reg_free(ab);
1719 ath11k_qmi_deinit_service(ab);
1720 }
1721
ath11k_core_pdev_create(struct ath11k_base * ab)1722 static int ath11k_core_pdev_create(struct ath11k_base *ab)
1723 {
1724 int ret;
1725
1726 ret = ath11k_debugfs_pdev_create(ab);
1727 if (ret) {
1728 ath11k_err(ab, "failed to create core pdev debugfs: %d\n", ret);
1729 return ret;
1730 }
1731
1732 ret = ath11k_dp_pdev_alloc(ab);
1733 if (ret) {
1734 ath11k_err(ab, "failed to attach DP pdev: %d\n", ret);
1735 goto err_pdev_debug;
1736 }
1737
1738 ret = ath11k_mac_register(ab);
1739 if (ret) {
1740 ath11k_err(ab, "failed register the radio with mac80211: %d\n", ret);
1741 goto err_dp_pdev_free;
1742 }
1743
1744 ret = ath11k_thermal_register(ab);
1745 if (ret) {
1746 ath11k_err(ab, "could not register thermal device: %d\n",
1747 ret);
1748 goto err_mac_unregister;
1749 }
1750
1751 ret = ath11k_spectral_init(ab);
1752 if (ret) {
1753 ath11k_err(ab, "failed to init spectral %d\n", ret);
1754 goto err_thermal_unregister;
1755 }
1756
1757 return 0;
1758
1759 err_thermal_unregister:
1760 ath11k_thermal_unregister(ab);
1761 err_mac_unregister:
1762 ath11k_mac_unregister(ab);
1763 err_dp_pdev_free:
1764 ath11k_dp_pdev_free(ab);
1765 err_pdev_debug:
1766 ath11k_debugfs_pdev_destroy(ab);
1767
1768 return ret;
1769 }
1770
ath11k_core_pdev_suspend_target(struct ath11k_base * ab)1771 static void ath11k_core_pdev_suspend_target(struct ath11k_base *ab)
1772 {
1773 struct ath11k *ar;
1774 struct ath11k_pdev *pdev;
1775 unsigned long time_left;
1776 int ret;
1777 int i;
1778
1779 if (!ab->hw_params.pdev_suspend)
1780 return;
1781
1782 for (i = 0; i < ab->num_radios; i++) {
1783 pdev = &ab->pdevs[i];
1784 ar = pdev->ar;
1785
1786 reinit_completion(&ab->htc_suspend);
1787
1788 ret = ath11k_wmi_pdev_suspend(ar, WMI_PDEV_SUSPEND_AND_DISABLE_INTR,
1789 pdev->pdev_id);
1790 if (ret) {
1791 ath11k_warn(ab, "could not suspend target :%d\n", ret);
1792 /* pointless to try other pdevs */
1793 return;
1794 }
1795
1796 time_left = wait_for_completion_timeout(&ab->htc_suspend, 3 * HZ);
1797
1798 if (!time_left) {
1799 ath11k_warn(ab, "suspend timed out - target pause event never came\n");
1800 /* pointless to try other pdevs */
1801 return;
1802 }
1803 }
1804 }
1805
ath11k_core_pdev_destroy(struct ath11k_base * ab)1806 static void ath11k_core_pdev_destroy(struct ath11k_base *ab)
1807 {
1808 ath11k_spectral_deinit(ab);
1809 ath11k_thermal_unregister(ab);
1810 ath11k_mac_unregister(ab);
1811 ath11k_core_pdev_suspend_target(ab);
1812 ath11k_hif_irq_disable(ab);
1813 ath11k_dp_pdev_free(ab);
1814 ath11k_debugfs_pdev_destroy(ab);
1815 }
1816
ath11k_core_start(struct ath11k_base * ab)1817 static int ath11k_core_start(struct ath11k_base *ab)
1818 {
1819 int ret;
1820
1821 ret = ath11k_wmi_attach(ab);
1822 if (ret) {
1823 ath11k_err(ab, "failed to attach wmi: %d\n", ret);
1824 return ret;
1825 }
1826
1827 ret = ath11k_htc_init(ab);
1828 if (ret) {
1829 ath11k_err(ab, "failed to init htc: %d\n", ret);
1830 goto err_wmi_detach;
1831 }
1832
1833 ret = ath11k_hif_start(ab);
1834 if (ret) {
1835 ath11k_err(ab, "failed to start HIF: %d\n", ret);
1836 goto err_wmi_detach;
1837 }
1838
1839 ret = ath11k_htc_wait_target(&ab->htc);
1840 if (ret) {
1841 ath11k_err(ab, "failed to connect to HTC: %d\n", ret);
1842 goto err_hif_stop;
1843 }
1844
1845 ret = ath11k_dp_htt_connect(&ab->dp);
1846 if (ret) {
1847 ath11k_err(ab, "failed to connect to HTT: %d\n", ret);
1848 goto err_hif_stop;
1849 }
1850
1851 ret = ath11k_wmi_connect(ab);
1852 if (ret) {
1853 ath11k_err(ab, "failed to connect wmi: %d\n", ret);
1854 goto err_hif_stop;
1855 }
1856
1857 ret = ath11k_htc_start(&ab->htc);
1858 if (ret) {
1859 ath11k_err(ab, "failed to start HTC: %d\n", ret);
1860 goto err_hif_stop;
1861 }
1862
1863 ret = ath11k_wmi_wait_for_service_ready(ab);
1864 if (ret) {
1865 ath11k_err(ab, "failed to receive wmi service ready event: %d\n",
1866 ret);
1867 goto err_hif_stop;
1868 }
1869
1870 ret = ath11k_mac_allocate(ab);
1871 if (ret) {
1872 ath11k_err(ab, "failed to create new hw device with mac80211 :%d\n",
1873 ret);
1874 goto err_hif_stop;
1875 }
1876
1877 ath11k_dp_pdev_pre_alloc(ab);
1878
1879 ret = ath11k_dp_pdev_reo_setup(ab);
1880 if (ret) {
1881 ath11k_err(ab, "failed to initialize reo destination rings: %d\n", ret);
1882 goto err_mac_destroy;
1883 }
1884
1885 ret = ath11k_wmi_cmd_init(ab);
1886 if (ret) {
1887 ath11k_err(ab, "failed to send wmi init cmd: %d\n", ret);
1888 goto err_reo_cleanup;
1889 }
1890
1891 ret = ath11k_wmi_wait_for_unified_ready(ab);
1892 if (ret) {
1893 ath11k_err(ab, "failed to receive wmi unified ready event: %d\n",
1894 ret);
1895 goto err_reo_cleanup;
1896 }
1897
1898 /* put hardware to DBS mode */
1899 if (ab->hw_params.single_pdev_only && ab->hw_params.num_rxdma_per_pdev > 1) {
1900 ret = ath11k_wmi_set_hw_mode(ab, WMI_HOST_HW_MODE_DBS);
1901 if (ret) {
1902 ath11k_err(ab, "failed to send dbs mode: %d\n", ret);
1903 goto err_hif_stop;
1904 }
1905 }
1906
1907 ret = ath11k_dp_tx_htt_h2t_ver_req_msg(ab);
1908 if (ret) {
1909 ath11k_err(ab, "failed to send htt version request message: %d\n",
1910 ret);
1911 goto err_reo_cleanup;
1912 }
1913
1914 return 0;
1915
1916 err_reo_cleanup:
1917 ath11k_dp_pdev_reo_cleanup(ab);
1918 err_mac_destroy:
1919 ath11k_mac_destroy(ab);
1920 err_hif_stop:
1921 ath11k_hif_stop(ab);
1922 err_wmi_detach:
1923 ath11k_wmi_detach(ab);
1924
1925 return ret;
1926 }
1927
ath11k_core_start_firmware(struct ath11k_base * ab,enum ath11k_firmware_mode mode)1928 static int ath11k_core_start_firmware(struct ath11k_base *ab,
1929 enum ath11k_firmware_mode mode)
1930 {
1931 int ret;
1932
1933 ath11k_ce_get_shadow_config(ab, &ab->qmi.ce_cfg.shadow_reg_v2,
1934 &ab->qmi.ce_cfg.shadow_reg_v2_len);
1935
1936 ret = ath11k_qmi_firmware_start(ab, mode);
1937 if (ret) {
1938 ath11k_err(ab, "failed to send firmware start: %d\n", ret);
1939 return ret;
1940 }
1941
1942 return ret;
1943 }
1944
ath11k_core_qmi_firmware_ready(struct ath11k_base * ab)1945 int ath11k_core_qmi_firmware_ready(struct ath11k_base *ab)
1946 {
1947 int ret;
1948
1949 ret = ath11k_core_start_firmware(ab, ab->fw_mode);
1950 if (ret) {
1951 ath11k_err(ab, "failed to start firmware: %d\n", ret);
1952 return ret;
1953 }
1954
1955 ret = ath11k_ce_init_pipes(ab);
1956 if (ret) {
1957 ath11k_err(ab, "failed to initialize CE: %d\n", ret);
1958 goto err_firmware_stop;
1959 }
1960
1961 ret = ath11k_dp_alloc(ab);
1962 if (ret) {
1963 ath11k_err(ab, "failed to init DP: %d\n", ret);
1964 goto err_firmware_stop;
1965 }
1966
1967 switch (ath11k_crypto_mode) {
1968 case ATH11K_CRYPT_MODE_SW:
1969 set_bit(ATH11K_FLAG_HW_CRYPTO_DISABLED, &ab->dev_flags);
1970 set_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags);
1971 break;
1972 case ATH11K_CRYPT_MODE_HW:
1973 clear_bit(ATH11K_FLAG_HW_CRYPTO_DISABLED, &ab->dev_flags);
1974 clear_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags);
1975 break;
1976 default:
1977 ath11k_info(ab, "invalid crypto_mode: %d\n", ath11k_crypto_mode);
1978 return -EINVAL;
1979 }
1980
1981 if (ath11k_frame_mode == ATH11K_HW_TXRX_RAW)
1982 set_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags);
1983
1984 mutex_lock(&ab->core_lock);
1985 ret = ath11k_core_start(ab);
1986 if (ret) {
1987 ath11k_err(ab, "failed to start core: %d\n", ret);
1988 goto err_dp_free;
1989 }
1990
1991 ret = ath11k_core_pdev_create(ab);
1992 if (ret) {
1993 ath11k_err(ab, "failed to create pdev core: %d\n", ret);
1994 goto err_core_stop;
1995 }
1996 ath11k_hif_irq_enable(ab);
1997 mutex_unlock(&ab->core_lock);
1998
1999 return 0;
2000
2001 err_core_stop:
2002 ath11k_core_stop(ab);
2003 ath11k_mac_destroy(ab);
2004 err_dp_free:
2005 ath11k_dp_free(ab);
2006 mutex_unlock(&ab->core_lock);
2007 err_firmware_stop:
2008 ath11k_qmi_firmware_stop(ab);
2009
2010 return ret;
2011 }
2012
ath11k_core_reconfigure_on_crash(struct ath11k_base * ab)2013 static int ath11k_core_reconfigure_on_crash(struct ath11k_base *ab)
2014 {
2015 int ret;
2016
2017 mutex_lock(&ab->core_lock);
2018 ath11k_thermal_unregister(ab);
2019 ath11k_dp_pdev_free(ab);
2020 ath11k_spectral_deinit(ab);
2021 ath11k_ce_cleanup_pipes(ab);
2022 ath11k_wmi_detach(ab);
2023 ath11k_dp_pdev_reo_cleanup(ab);
2024 mutex_unlock(&ab->core_lock);
2025
2026 ath11k_dp_free(ab);
2027 ath11k_hal_srng_deinit(ab);
2028
2029 ab->free_vdev_map = (1LL << (ab->num_radios * TARGET_NUM_VDEVS(ab))) - 1;
2030
2031 ret = ath11k_hal_srng_init(ab);
2032 if (ret)
2033 return ret;
2034
2035 clear_bit(ATH11K_FLAG_CRASH_FLUSH, &ab->dev_flags);
2036
2037 ret = ath11k_core_qmi_firmware_ready(ab);
2038 if (ret)
2039 goto err_hal_srng_deinit;
2040
2041 clear_bit(ATH11K_FLAG_RECOVERY, &ab->dev_flags);
2042
2043 return 0;
2044
2045 err_hal_srng_deinit:
2046 ath11k_hal_srng_deinit(ab);
2047 return ret;
2048 }
2049
ath11k_core_halt(struct ath11k * ar)2050 void ath11k_core_halt(struct ath11k *ar)
2051 {
2052 struct ath11k_base *ab = ar->ab;
2053
2054 lockdep_assert_held(&ar->conf_mutex);
2055
2056 ar->num_created_vdevs = 0;
2057 ar->allocated_vdev_map = 0;
2058
2059 ath11k_mac_scan_finish(ar);
2060 ath11k_mac_peer_cleanup_all(ar);
2061 cancel_delayed_work_sync(&ar->scan.timeout);
2062 cancel_work_sync(&ar->channel_update_work);
2063 cancel_work_sync(&ar->regd_update_work);
2064 cancel_work_sync(&ab->update_11d_work);
2065
2066 rcu_assign_pointer(ab->pdevs_active[ar->pdev_idx], NULL);
2067 synchronize_rcu();
2068 INIT_LIST_HEAD(&ar->arvifs);
2069 idr_init(&ar->txmgmt_idr);
2070 }
2071
ath11k_update_11d(struct work_struct * work)2072 static void ath11k_update_11d(struct work_struct *work)
2073 {
2074 struct ath11k_base *ab = container_of(work, struct ath11k_base, update_11d_work);
2075 struct ath11k *ar;
2076 struct ath11k_pdev *pdev;
2077 int ret, i;
2078
2079 for (i = 0; i < ab->num_radios; i++) {
2080 pdev = &ab->pdevs[i];
2081 ar = pdev->ar;
2082
2083 spin_lock_bh(&ab->base_lock);
2084 memcpy(&ar->alpha2, &ab->new_alpha2, 2);
2085 spin_unlock_bh(&ab->base_lock);
2086
2087 ath11k_dbg(ab, ATH11K_DBG_WMI, "update 11d new cc %c%c for pdev %d\n",
2088 ar->alpha2[0], ar->alpha2[1], i);
2089
2090 ret = ath11k_reg_set_cc(ar);
2091 if (ret)
2092 ath11k_warn(ar->ab,
2093 "pdev id %d failed set current country code: %d\n",
2094 i, ret);
2095 }
2096 }
2097
ath11k_core_pre_reconfigure_recovery(struct ath11k_base * ab)2098 void ath11k_core_pre_reconfigure_recovery(struct ath11k_base *ab)
2099 {
2100 struct ath11k *ar;
2101 struct ath11k_pdev *pdev;
2102 int i;
2103
2104 spin_lock_bh(&ab->base_lock);
2105 ab->stats.fw_crash_counter++;
2106 spin_unlock_bh(&ab->base_lock);
2107
2108 for (i = 0; i < ab->num_radios; i++) {
2109 pdev = &ab->pdevs[i];
2110 ar = pdev->ar;
2111 if (!ar || ar->state == ATH11K_STATE_OFF ||
2112 ar->state == ATH11K_STATE_FTM)
2113 continue;
2114
2115 ieee80211_stop_queues(ar->hw);
2116 ath11k_mac_drain_tx(ar);
2117 ar->state_11d = ATH11K_11D_IDLE;
2118 complete(&ar->completed_11d_scan);
2119 complete(&ar->scan.started);
2120 complete_all(&ar->scan.completed);
2121 complete(&ar->scan.on_channel);
2122 complete(&ar->peer_assoc_done);
2123 complete(&ar->peer_delete_done);
2124 complete(&ar->install_key_done);
2125 complete(&ar->vdev_setup_done);
2126 complete(&ar->vdev_delete_done);
2127 complete(&ar->bss_survey_done);
2128 complete(&ar->thermal.wmi_sync);
2129
2130 wake_up(&ar->dp.tx_empty_waitq);
2131 idr_for_each(&ar->txmgmt_idr,
2132 ath11k_mac_tx_mgmt_pending_free, ar);
2133 idr_destroy(&ar->txmgmt_idr);
2134 wake_up(&ar->txmgmt_empty_waitq);
2135
2136 ar->monitor_vdev_id = -1;
2137 clear_bit(ATH11K_FLAG_MONITOR_STARTED, &ar->monitor_flags);
2138 clear_bit(ATH11K_FLAG_MONITOR_VDEV_CREATED, &ar->monitor_flags);
2139 }
2140
2141 wake_up(&ab->wmi_ab.tx_credits_wq);
2142 wake_up(&ab->peer_mapping_wq);
2143
2144 reinit_completion(&ab->driver_recovery);
2145 }
2146
ath11k_core_post_reconfigure_recovery(struct ath11k_base * ab)2147 static void ath11k_core_post_reconfigure_recovery(struct ath11k_base *ab)
2148 {
2149 struct ath11k *ar;
2150 struct ath11k_pdev *pdev;
2151 int i;
2152
2153 for (i = 0; i < ab->num_radios; i++) {
2154 pdev = &ab->pdevs[i];
2155 ar = pdev->ar;
2156 if (!ar || ar->state == ATH11K_STATE_OFF)
2157 continue;
2158
2159 mutex_lock(&ar->conf_mutex);
2160
2161 switch (ar->state) {
2162 case ATH11K_STATE_ON:
2163 ar->state = ATH11K_STATE_RESTARTING;
2164 ath11k_core_halt(ar);
2165 ieee80211_restart_hw(ar->hw);
2166 break;
2167 case ATH11K_STATE_OFF:
2168 ath11k_warn(ab,
2169 "cannot restart radio %d that hasn't been started\n",
2170 i);
2171 break;
2172 case ATH11K_STATE_RESTARTING:
2173 break;
2174 case ATH11K_STATE_RESTARTED:
2175 ar->state = ATH11K_STATE_WEDGED;
2176 fallthrough;
2177 case ATH11K_STATE_WEDGED:
2178 ath11k_warn(ab,
2179 "device is wedged, will not restart radio %d\n", i);
2180 break;
2181 case ATH11K_STATE_FTM:
2182 ath11k_dbg(ab, ATH11K_DBG_TESTMODE,
2183 "fw mode reset done radio %d\n", i);
2184 break;
2185 }
2186
2187 mutex_unlock(&ar->conf_mutex);
2188 }
2189 complete(&ab->driver_recovery);
2190 }
2191
ath11k_core_restart(struct work_struct * work)2192 static void ath11k_core_restart(struct work_struct *work)
2193 {
2194 struct ath11k_base *ab = container_of(work, struct ath11k_base, restart_work);
2195 int ret;
2196
2197 ret = ath11k_core_reconfigure_on_crash(ab);
2198 if (ret) {
2199 ath11k_err(ab, "failed to reconfigure driver on crash recovery\n");
2200 return;
2201 }
2202
2203 if (ab->is_reset)
2204 complete_all(&ab->reconfigure_complete);
2205
2206 if (!ab->is_reset)
2207 ath11k_core_post_reconfigure_recovery(ab);
2208 }
2209
ath11k_core_reset(struct work_struct * work)2210 static void ath11k_core_reset(struct work_struct *work)
2211 {
2212 struct ath11k_base *ab = container_of(work, struct ath11k_base, reset_work);
2213 int reset_count, fail_cont_count;
2214 long time_left;
2215
2216 if (!(test_bit(ATH11K_FLAG_REGISTERED, &ab->dev_flags))) {
2217 ath11k_warn(ab, "ignore reset dev flags 0x%lx\n", ab->dev_flags);
2218 return;
2219 }
2220
2221 /* Sometimes the recovery will fail and then the next all recovery fail,
2222 * this is to avoid infinite recovery since it can not recovery success.
2223 */
2224 fail_cont_count = atomic_read(&ab->fail_cont_count);
2225
2226 if (fail_cont_count >= ATH11K_RESET_MAX_FAIL_COUNT_FINAL)
2227 return;
2228
2229 if (fail_cont_count >= ATH11K_RESET_MAX_FAIL_COUNT_FIRST &&
2230 time_before(jiffies, ab->reset_fail_timeout))
2231 return;
2232
2233 reset_count = atomic_inc_return(&ab->reset_count);
2234
2235 if (reset_count > 1) {
2236 /* Sometimes it happened another reset worker before the previous one
2237 * completed, then the second reset worker will destroy the previous one,
2238 * thus below is to avoid that.
2239 */
2240 ath11k_warn(ab, "already resetting count %d\n", reset_count);
2241
2242 reinit_completion(&ab->reset_complete);
2243 time_left = wait_for_completion_timeout(&ab->reset_complete,
2244 ATH11K_RESET_TIMEOUT_HZ);
2245
2246 if (time_left) {
2247 ath11k_dbg(ab, ATH11K_DBG_BOOT, "to skip reset\n");
2248 atomic_dec(&ab->reset_count);
2249 return;
2250 }
2251
2252 ab->reset_fail_timeout = jiffies + ATH11K_RESET_FAIL_TIMEOUT_HZ;
2253 /* Record the continuous recovery fail count when recovery failed*/
2254 atomic_inc(&ab->fail_cont_count);
2255 }
2256
2257 ath11k_dbg(ab, ATH11K_DBG_BOOT, "reset starting\n");
2258
2259 ab->is_reset = true;
2260 atomic_set(&ab->recovery_count, 0);
2261 reinit_completion(&ab->recovery_start);
2262 atomic_set(&ab->recovery_start_count, 0);
2263
2264 ath11k_coredump_collect(ab);
2265 ath11k_core_pre_reconfigure_recovery(ab);
2266
2267 reinit_completion(&ab->reconfigure_complete);
2268 ath11k_core_post_reconfigure_recovery(ab);
2269
2270 ath11k_dbg(ab, ATH11K_DBG_BOOT, "waiting recovery start...\n");
2271
2272 time_left = wait_for_completion_timeout(&ab->recovery_start,
2273 ATH11K_RECOVER_START_TIMEOUT_HZ);
2274
2275 ath11k_hif_irq_disable(ab);
2276 ath11k_hif_ce_irq_disable(ab);
2277
2278 ath11k_hif_power_down(ab);
2279 ath11k_hif_power_up(ab);
2280
2281 ath11k_dbg(ab, ATH11K_DBG_BOOT, "reset started\n");
2282 }
2283
ath11k_init_hw_params(struct ath11k_base * ab)2284 static int ath11k_init_hw_params(struct ath11k_base *ab)
2285 {
2286 const struct ath11k_hw_params *hw_params = NULL;
2287 int i;
2288
2289 for (i = 0; i < ARRAY_SIZE(ath11k_hw_params); i++) {
2290 hw_params = &ath11k_hw_params[i];
2291
2292 if (hw_params->hw_rev == ab->hw_rev)
2293 break;
2294 }
2295
2296 if (i == ARRAY_SIZE(ath11k_hw_params)) {
2297 ath11k_err(ab, "Unsupported hardware version: 0x%x\n", ab->hw_rev);
2298 return -EINVAL;
2299 }
2300
2301 ab->hw_params = *hw_params;
2302
2303 ath11k_info(ab, "%s\n", ab->hw_params.name);
2304
2305 return 0;
2306 }
2307
ath11k_core_pre_init(struct ath11k_base * ab)2308 int ath11k_core_pre_init(struct ath11k_base *ab)
2309 {
2310 int ret;
2311
2312 ret = ath11k_init_hw_params(ab);
2313 if (ret) {
2314 ath11k_err(ab, "failed to get hw params: %d\n", ret);
2315 return ret;
2316 }
2317
2318 ret = ath11k_fw_pre_init(ab);
2319 if (ret) {
2320 ath11k_err(ab, "failed to pre init firmware: %d", ret);
2321 return ret;
2322 }
2323
2324 return 0;
2325 }
2326 EXPORT_SYMBOL(ath11k_core_pre_init);
2327
ath11k_core_init(struct ath11k_base * ab)2328 int ath11k_core_init(struct ath11k_base *ab)
2329 {
2330 int ret;
2331
2332 ret = ath11k_core_soc_create(ab);
2333 if (ret) {
2334 ath11k_err(ab, "failed to create soc core: %d\n", ret);
2335 return ret;
2336 }
2337
2338 return 0;
2339 }
2340 EXPORT_SYMBOL(ath11k_core_init);
2341
ath11k_core_deinit(struct ath11k_base * ab)2342 void ath11k_core_deinit(struct ath11k_base *ab)
2343 {
2344 mutex_lock(&ab->core_lock);
2345
2346 ath11k_core_pdev_destroy(ab);
2347 ath11k_core_stop(ab);
2348
2349 mutex_unlock(&ab->core_lock);
2350
2351 ath11k_hif_power_down(ab);
2352 ath11k_mac_destroy(ab);
2353 ath11k_core_soc_destroy(ab);
2354 }
2355 EXPORT_SYMBOL(ath11k_core_deinit);
2356
ath11k_core_free(struct ath11k_base * ab)2357 void ath11k_core_free(struct ath11k_base *ab)
2358 {
2359 destroy_workqueue(ab->workqueue_aux);
2360 destroy_workqueue(ab->workqueue);
2361
2362 kfree(ab);
2363 }
2364 EXPORT_SYMBOL(ath11k_core_free);
2365
ath11k_core_alloc(struct device * dev,size_t priv_size,enum ath11k_bus bus)2366 struct ath11k_base *ath11k_core_alloc(struct device *dev, size_t priv_size,
2367 enum ath11k_bus bus)
2368 {
2369 struct ath11k_base *ab;
2370
2371 ab = kzalloc(sizeof(*ab) + priv_size, GFP_KERNEL);
2372 if (!ab)
2373 return NULL;
2374
2375 init_completion(&ab->driver_recovery);
2376
2377 ab->workqueue = create_singlethread_workqueue("ath11k_wq");
2378 if (!ab->workqueue)
2379 goto err_sc_free;
2380
2381 ab->workqueue_aux = create_singlethread_workqueue("ath11k_aux_wq");
2382 if (!ab->workqueue_aux)
2383 goto err_free_wq;
2384
2385 mutex_init(&ab->core_lock);
2386 mutex_init(&ab->tbl_mtx_lock);
2387 spin_lock_init(&ab->base_lock);
2388 mutex_init(&ab->vdev_id_11d_lock);
2389 init_completion(&ab->reset_complete);
2390 init_completion(&ab->reconfigure_complete);
2391 init_completion(&ab->recovery_start);
2392
2393 INIT_LIST_HEAD(&ab->peers);
2394 init_waitqueue_head(&ab->peer_mapping_wq);
2395 init_waitqueue_head(&ab->wmi_ab.tx_credits_wq);
2396 init_waitqueue_head(&ab->qmi.cold_boot_waitq);
2397 INIT_WORK(&ab->restart_work, ath11k_core_restart);
2398 INIT_WORK(&ab->update_11d_work, ath11k_update_11d);
2399 INIT_WORK(&ab->reset_work, ath11k_core_reset);
2400 INIT_WORK(&ab->dump_work, ath11k_coredump_upload);
2401 timer_setup(&ab->rx_replenish_retry, ath11k_ce_rx_replenish_retry, 0);
2402 init_completion(&ab->htc_suspend);
2403 init_completion(&ab->wow.wakeup_completed);
2404
2405 ab->dev = dev;
2406 ab->hif.bus = bus;
2407
2408 return ab;
2409
2410 err_free_wq:
2411 destroy_workqueue(ab->workqueue);
2412 err_sc_free:
2413 kfree(ab);
2414 return NULL;
2415 }
2416 EXPORT_SYMBOL(ath11k_core_alloc);
2417
2418 MODULE_DESCRIPTION("Core module for Qualcomm Atheros 802.11ax wireless LAN cards.");
2419 MODULE_LICENSE("Dual BSD/GPL");
2420