1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * rt722-sdca-sdw.h -- RT722 SDCA ALSA SoC audio driver header 4 * 5 * Copyright(c) 2023 Realtek Semiconductor Corp. 6 */ 7 8 #ifndef __RT722_SDW_H__ 9 #define __RT722_SDW_H__ 10 11 #include <linux/regmap.h> 12 #include <linux/soundwire/sdw_registers.h> 13 14 static const struct reg_default rt722_sdca_reg_defaults[] = { 15 { 0x202d, 0x00 }, 16 { 0x2f01, 0x00 }, 17 { 0x2f02, 0x09 }, 18 { 0x2f03, 0x00 }, 19 { 0x2f04, 0x00 }, 20 { 0x2f05, 0x0b }, 21 { 0x2f06, 0x01 }, 22 { 0x2f08, 0x00 }, 23 { 0x2f09, 0x00 }, 24 { 0x2f0a, 0x00 }, 25 { 0x2f35, 0x00 }, 26 { 0x2f36, 0x00 }, 27 { 0x2f50, 0xf0 }, 28 { 0x2f58, 0x07 }, 29 { 0x2f59, 0x07 }, 30 { 0x2f5a, 0x07 }, 31 { 0x2f5b, 0x07 }, 32 { 0x2f5c, 0x27 }, 33 { 0x2f5d, 0x07 }, 34 { 0x200003c, 0xc214 }, 35 { 0x2000046, 0x8004 }, 36 { 0x5810000, 0x702d }, 37 { 0x6100000, 0x0201 }, 38 { 0x6100006, 0x0005 }, 39 { 0x6100010, 0x2630 }, 40 { 0x6100011, 0x152f }, 41 { 0x6100013, 0x0102 }, 42 { 0x6100015, 0x2200 }, 43 { 0x6100017, 0x0102 }, 44 { 0x6100025, 0x2a29 }, 45 { 0x6100026, 0x2a00 }, 46 { 0x6100028, 0x2a2a }, 47 { 0x6100029, 0x4141 }, 48 { 0x6100055, 0x0000 }, 49 { SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05, RT722_SDCA_CTL_FU_MUTE, CH_L), 50 0x01 }, 51 { SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05, RT722_SDCA_CTL_FU_MUTE, CH_R), 52 0x01 }, 53 { SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05, RT722_SDCA_CTL_FU_VOLUME, 54 CH_L), 0x0000 }, 55 { SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05, RT722_SDCA_CTL_FU_VOLUME, 56 CH_R), 0x0000 }, 57 { SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F, RT722_SDCA_CTL_FU_MUTE, CH_L), 58 0x01 }, 59 { SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F, RT722_SDCA_CTL_FU_MUTE, CH_R), 60 0x01 }, 61 { SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F, RT722_SDCA_CTL_FU_VOLUME, 62 CH_L), 0x0000 }, 63 { SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F, RT722_SDCA_CTL_FU_VOLUME, 64 CH_R), 0x0000 }, 65 { SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE12, RT722_SDCA_CTL_REQ_POWER_STATE, 66 0), 0x03 }, 67 { SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_CS01, RT722_SDCA_CTL_SAMPLE_FREQ_INDEX, 68 0), 0x09 }, 69 { SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_CS11, RT722_SDCA_CTL_SAMPLE_FREQ_INDEX, 70 0), 0x09 }, 71 { SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE40, RT722_SDCA_CTL_REQ_POWER_STATE, 72 0), 0x03 }, 73 { SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PLATFORM_FU44, RT722_SDCA_CTL_FU_CH_GAIN, 74 CH_L), 0x0000 }, 75 { SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PLATFORM_FU44, RT722_SDCA_CTL_FU_CH_GAIN, 76 CH_R), 0x0000 }, 77 { SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_FU15, RT722_SDCA_CTL_FU_CH_GAIN, CH_01), 78 0x0000 }, 79 { SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_FU15, RT722_SDCA_CTL_FU_CH_GAIN, CH_02), 80 0x0000 }, 81 { SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_FU15, RT722_SDCA_CTL_FU_CH_GAIN, CH_03), 82 0x0000 }, 83 { SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_FU15, RT722_SDCA_CTL_FU_CH_GAIN, CH_04), 84 0x0000 }, 85 { SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, RT722_SDCA_CTL_FU_MUTE, CH_01), 86 0x01 }, 87 { SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, RT722_SDCA_CTL_FU_MUTE, CH_02), 88 0x01 }, 89 { SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, RT722_SDCA_CTL_FU_MUTE, CH_03), 90 0x01 }, 91 { SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, RT722_SDCA_CTL_FU_MUTE, CH_04), 92 0x01 }, 93 { SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, RT722_SDCA_CTL_FU_VOLUME, 94 CH_01), 0x0000 }, 95 { SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, RT722_SDCA_CTL_FU_VOLUME, 96 CH_02), 0x0000 }, 97 { SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, RT722_SDCA_CTL_FU_VOLUME, 98 CH_03), 0x0000 }, 99 { SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, RT722_SDCA_CTL_FU_VOLUME, 100 CH_04), 0x0000 }, 101 { SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_PDE2A, RT722_SDCA_CTL_REQ_POWER_STATE, 0), 102 0x03 }, 103 { SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_CS1F, RT722_SDCA_CTL_SAMPLE_FREQ_INDEX, 104 0), 0x09 }, 105 { SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_IT26, RT722_SDCA_CTL_VENDOR_DEF, 0), 106 0x00 }, 107 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06, RT722_SDCA_CTL_FU_MUTE, CH_L), 108 0x01 }, 109 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06, RT722_SDCA_CTL_FU_MUTE, CH_R), 110 0x01 }, 111 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06, RT722_SDCA_CTL_FU_VOLUME, CH_L), 112 0x0000 }, 113 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06, RT722_SDCA_CTL_FU_VOLUME, CH_R), 114 0x0000 }, 115 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_PDE23, RT722_SDCA_CTL_REQ_POWER_STATE, 0), 116 0x03 }, 117 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_CS31, RT722_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 118 0x09 }, 119 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_OT23, RT722_SDCA_CTL_VENDOR_DEF, 0), 0x00 }, 120 }; 121 122 #endif /* __RT722_SDW_H__ */ 123