1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __MACH_MMP_CLK_H 3 #define __MACH_MMP_CLK_H 4 5 #include <linux/clk-provider.h> 6 #include <linux/math.h> 7 #include <linux/pm_domain.h> 8 #include <linux/clkdev.h> 9 10 #define APBC_NO_BUS_CTRL BIT(0) 11 #define APBC_POWER_CTRL BIT(1) 12 13 14 /* Clock type "factor" */ 15 struct mmp_clk_factor_masks { 16 unsigned int factor; 17 unsigned int num_mask; 18 unsigned int den_mask; 19 unsigned int num_shift; 20 unsigned int den_shift; 21 unsigned int enable_mask; 22 }; 23 24 struct mmp_clk_factor { 25 struct clk_hw hw; 26 void __iomem *base; 27 struct mmp_clk_factor_masks *masks; 28 struct u32_fract *ftbl; 29 unsigned int ftbl_cnt; 30 spinlock_t *lock; 31 }; 32 33 extern struct clk *mmp_clk_register_factor(const char *name, 34 const char *parent_name, unsigned long flags, 35 void __iomem *base, struct mmp_clk_factor_masks *masks, 36 struct u32_fract *ftbl, unsigned int ftbl_cnt, 37 spinlock_t *lock); 38 39 /* Clock type "mix" */ 40 #define MMP_CLK_BITS_MASK(width, shift) \ 41 (((1 << (width)) - 1) << (shift)) 42 #define MMP_CLK_BITS_GET_VAL(data, width, shift) \ 43 ((data & MMP_CLK_BITS_MASK(width, shift)) >> (shift)) 44 #define MMP_CLK_BITS_SET_VAL(val, width, shift) \ 45 (((val) << (shift)) & MMP_CLK_BITS_MASK(width, shift)) 46 47 enum { 48 MMP_CLK_MIX_TYPE_V1, 49 MMP_CLK_MIX_TYPE_V2, 50 MMP_CLK_MIX_TYPE_V3, 51 }; 52 53 /* The register layout */ 54 struct mmp_clk_mix_reg_info { 55 void __iomem *reg_clk_ctrl; 56 void __iomem *reg_clk_sel; 57 u8 width_div; 58 u8 shift_div; 59 u8 width_mux; 60 u8 shift_mux; 61 u8 bit_fc; 62 }; 63 64 /* The suggested clock table from user. */ 65 struct mmp_clk_mix_clk_table { 66 unsigned long rate; 67 u8 parent_index; 68 unsigned int divisor; 69 unsigned int valid; 70 }; 71 72 struct mmp_clk_mix_config { 73 struct mmp_clk_mix_reg_info reg_info; 74 struct mmp_clk_mix_clk_table *table; 75 unsigned int table_size; 76 u32 *mux_table; 77 struct clk_div_table *div_table; 78 u8 div_flags; 79 u8 mux_flags; 80 }; 81 82 struct mmp_clk_mix { 83 struct clk_hw hw; 84 struct mmp_clk_mix_reg_info reg_info; 85 struct mmp_clk_mix_clk_table *table; 86 u32 *mux_table; 87 struct clk_div_table *div_table; 88 unsigned int table_size; 89 u8 div_flags; 90 u8 mux_flags; 91 unsigned int type; 92 spinlock_t *lock; 93 }; 94 95 extern const struct clk_ops mmp_clk_mix_ops; 96 extern struct clk *mmp_clk_register_mix(struct device *dev, 97 const char *name, 98 const char * const *parent_names, 99 u8 num_parents, 100 unsigned long flags, 101 struct mmp_clk_mix_config *config, 102 spinlock_t *lock); 103 104 105 /* Clock type "gate". MMP private gate */ 106 #define MMP_CLK_GATE_NEED_DELAY BIT(0) 107 108 struct mmp_clk_gate { 109 struct clk_hw hw; 110 void __iomem *reg; 111 u32 mask; 112 u32 val_enable; 113 u32 val_disable; 114 unsigned int flags; 115 spinlock_t *lock; 116 }; 117 118 extern const struct clk_ops mmp_clk_gate_ops; 119 extern struct clk *mmp_clk_register_gate(struct device *dev, const char *name, 120 const char *parent_name, unsigned long flags, 121 void __iomem *reg, u32 mask, u32 val_enable, 122 u32 val_disable, unsigned int gate_flags, 123 spinlock_t *lock); 124 125 extern struct clk *mmp_clk_register_apbc(const char *name, 126 const char *parent_name, void __iomem *base, 127 unsigned int delay, unsigned int apbc_flags, spinlock_t *lock); 128 extern struct clk *mmp_clk_register_apmu(const char *name, 129 const char *parent_name, void __iomem *base, u32 enable_mask, 130 spinlock_t *lock); 131 132 struct mmp_clk_unit { 133 unsigned int nr_clks; 134 struct clk **clk_table; 135 struct clk_onecell_data clk_data; 136 }; 137 138 struct mmp_param_fixed_rate_clk { 139 unsigned int id; 140 char *name; 141 const char *parent_name; 142 unsigned long flags; 143 unsigned long fixed_rate; 144 }; 145 void mmp_register_fixed_rate_clks(struct mmp_clk_unit *unit, 146 struct mmp_param_fixed_rate_clk *clks, 147 int size); 148 149 struct mmp_param_fixed_factor_clk { 150 unsigned int id; 151 char *name; 152 const char *parent_name; 153 unsigned long mult; 154 unsigned long div; 155 unsigned long flags; 156 }; 157 void mmp_register_fixed_factor_clks(struct mmp_clk_unit *unit, 158 struct mmp_param_fixed_factor_clk *clks, 159 int size); 160 161 struct mmp_param_general_gate_clk { 162 unsigned int id; 163 const char *name; 164 const char *parent_name; 165 unsigned long flags; 166 unsigned long offset; 167 u8 bit_idx; 168 u8 gate_flags; 169 spinlock_t *lock; 170 }; 171 void mmp_register_general_gate_clks(struct mmp_clk_unit *unit, 172 struct mmp_param_general_gate_clk *clks, 173 void __iomem *base, int size); 174 175 struct mmp_param_gate_clk { 176 unsigned int id; 177 char *name; 178 const char *parent_name; 179 unsigned long flags; 180 unsigned long offset; 181 u32 mask; 182 u32 val_enable; 183 u32 val_disable; 184 unsigned int gate_flags; 185 spinlock_t *lock; 186 }; 187 void mmp_register_gate_clks(struct mmp_clk_unit *unit, 188 struct mmp_param_gate_clk *clks, 189 void __iomem *base, int size); 190 191 struct mmp_param_mux_clk { 192 unsigned int id; 193 char *name; 194 const char * const *parent_name; 195 u8 num_parents; 196 unsigned long flags; 197 unsigned long offset; 198 u8 shift; 199 u8 width; 200 u8 mux_flags; 201 spinlock_t *lock; 202 }; 203 void mmp_register_mux_clks(struct mmp_clk_unit *unit, 204 struct mmp_param_mux_clk *clks, 205 void __iomem *base, int size); 206 207 struct mmp_param_div_clk { 208 unsigned int id; 209 char *name; 210 const char *parent_name; 211 unsigned long flags; 212 unsigned long offset; 213 u8 shift; 214 u8 width; 215 u8 div_flags; 216 spinlock_t *lock; 217 }; 218 void mmp_register_div_clks(struct mmp_clk_unit *unit, 219 struct mmp_param_div_clk *clks, 220 void __iomem *base, int size); 221 222 struct mmp_param_pll_clk { 223 unsigned int id; 224 char *name; 225 unsigned long default_rate; 226 unsigned long enable_offset; 227 u32 enable; 228 unsigned long offset; 229 u8 shift; 230 /* MMP3 specific: */ 231 unsigned long input_rate; 232 unsigned long postdiv_offset; 233 unsigned long postdiv_shift; 234 }; 235 void mmp_register_pll_clks(struct mmp_clk_unit *unit, 236 struct mmp_param_pll_clk *clks, 237 void __iomem *base, int size); 238 239 #define DEFINE_MIX_REG_INFO(w_d, s_d, w_m, s_m, fc) \ 240 { \ 241 .width_div = (w_d), \ 242 .shift_div = (s_d), \ 243 .width_mux = (w_m), \ 244 .shift_mux = (s_m), \ 245 .bit_fc = (fc), \ 246 } 247 248 void mmp_clk_init(struct device_node *np, struct mmp_clk_unit *unit, 249 int nr_clks); 250 void mmp_clk_add(struct mmp_clk_unit *unit, unsigned int id, 251 struct clk *clk); 252 253 /* Power islands */ 254 #define MMP_PM_DOMAIN_NO_DISABLE BIT(0) 255 256 struct generic_pm_domain *mmp_pm_domain_register(const char *name, 257 void __iomem *reg, 258 u32 power_on, u32 reset, u32 clock_enable, 259 unsigned int flags, spinlock_t *lock); 260 261 #endif 262