1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright (C) 2023 Intel Corporation */
3
4 #ifndef _IDPF_TXRX_H_
5 #define _IDPF_TXRX_H_
6
7 #include <linux/dim.h>
8
9 #include <net/libeth/cache.h>
10 #include <net/libeth/types.h>
11 #include <net/netdev_queues.h>
12 #include <net/tcp.h>
13 #include <net/xdp.h>
14
15 #include "idpf_lan_txrx.h"
16 #include "virtchnl2_lan_desc.h"
17
18 #define IDPF_LARGE_MAX_Q 256
19 #define IDPF_MAX_Q 16
20 #define IDPF_MIN_Q 2
21 /* Mailbox Queue */
22 #define IDPF_MAX_MBXQ 1
23
24 #define IDPF_MIN_TXQ_DESC 64
25 #define IDPF_MIN_RXQ_DESC 64
26 #define IDPF_MIN_TXQ_COMPLQ_DESC 256
27 #define IDPF_MAX_QIDS 256
28
29 /* Number of descriptors in a queue should be a multiple of 32. RX queue
30 * descriptors alone should be a multiple of IDPF_REQ_RXQ_DESC_MULTIPLE
31 * to achieve BufQ descriptors aligned to 32
32 */
33 #define IDPF_REQ_DESC_MULTIPLE 32
34 #define IDPF_REQ_RXQ_DESC_MULTIPLE (IDPF_MAX_BUFQS_PER_RXQ_GRP * 32)
35 #define IDPF_MIN_TX_DESC_NEEDED (MAX_SKB_FRAGS + 6)
36 #define IDPF_TX_WAKE_THRESH ((u16)IDPF_MIN_TX_DESC_NEEDED * 2)
37
38 #define IDPF_MAX_DESCS 8160
39 #define IDPF_MAX_TXQ_DESC ALIGN_DOWN(IDPF_MAX_DESCS, IDPF_REQ_DESC_MULTIPLE)
40 #define IDPF_MAX_RXQ_DESC ALIGN_DOWN(IDPF_MAX_DESCS, IDPF_REQ_RXQ_DESC_MULTIPLE)
41 #define MIN_SUPPORT_TXDID (\
42 VIRTCHNL2_TXDID_FLEX_FLOW_SCHED |\
43 VIRTCHNL2_TXDID_FLEX_TSO_CTX)
44
45 #define IDPF_DFLT_SINGLEQ_TX_Q_GROUPS 1
46 #define IDPF_DFLT_SINGLEQ_RX_Q_GROUPS 1
47 #define IDPF_DFLT_SINGLEQ_TXQ_PER_GROUP 4
48 #define IDPF_DFLT_SINGLEQ_RXQ_PER_GROUP 4
49
50 #define IDPF_COMPLQ_PER_GROUP 1
51 #define IDPF_SINGLE_BUFQ_PER_RXQ_GRP 1
52 #define IDPF_MAX_BUFQS_PER_RXQ_GRP 2
53 #define IDPF_BUFQ2_ENA 1
54 #define IDPF_NUMQ_PER_CHUNK 1
55
56 #define IDPF_DFLT_SPLITQ_TXQ_PER_GROUP 1
57 #define IDPF_DFLT_SPLITQ_RXQ_PER_GROUP 1
58
59 /* Default vector sharing */
60 #define IDPF_MBX_Q_VEC 1
61 #define IDPF_MIN_Q_VEC 1
62 #define IDPF_MIN_RDMA_VEC 2
63 /* Data vector for NOIRQ queues */
64 #define IDPF_RESERVED_VECS 1
65
66 #define IDPF_DFLT_TX_Q_DESC_COUNT 512
67 #define IDPF_DFLT_TX_COMPLQ_DESC_COUNT 512
68 #define IDPF_DFLT_RX_Q_DESC_COUNT 512
69
70 /* IMPORTANT: We absolutely _cannot_ have more buffers in the system than a
71 * given RX completion queue has descriptors. This includes _ALL_ buffer
72 * queues. E.g.: If you have two buffer queues of 512 descriptors and buffers,
73 * you have a total of 1024 buffers so your RX queue _must_ have at least that
74 * many descriptors. This macro divides a given number of RX descriptors by
75 * number of buffer queues to calculate how many descriptors each buffer queue
76 * can have without overrunning the RX queue.
77 *
78 * If you give hardware more buffers than completion descriptors what will
79 * happen is that if hardware gets a chance to post more than ring wrap of
80 * descriptors before SW gets an interrupt and overwrites SW head, the gen bit
81 * in the descriptor will be wrong. Any overwritten descriptors' buffers will
82 * be gone forever and SW has no reasonable way to tell that this has happened.
83 * From SW perspective, when we finally get an interrupt, it looks like we're
84 * still waiting for descriptor to be done, stalling forever.
85 */
86 #define IDPF_RX_BUFQ_DESC_COUNT(RXD, NUM_BUFQ) ((RXD) / (NUM_BUFQ))
87
88 #define IDPF_RX_BUFQ_WORKING_SET(rxq) ((rxq)->desc_count - 1)
89
90 #define IDPF_RX_BUMP_NTC(rxq, ntc) \
91 do { \
92 if (unlikely(++(ntc) == (rxq)->desc_count)) { \
93 ntc = 0; \
94 idpf_queue_change(GEN_CHK, rxq); \
95 } \
96 } while (0)
97
98 #define IDPF_SINGLEQ_BUMP_RING_IDX(q, idx) \
99 do { \
100 if (unlikely(++(idx) == (q)->desc_count)) \
101 idx = 0; \
102 } while (0)
103
104 #define IDPF_RX_BUF_STRIDE 32
105 #define IDPF_RX_BUF_POST_STRIDE 16
106 #define IDPF_LOW_WATERMARK 64
107
108 #define IDPF_TX_TSO_MIN_MSS 88
109
110 /* Minimum number of descriptors between 2 descriptors with the RE bit set;
111 * only relevant in flow scheduling mode
112 */
113 #define IDPF_TX_SPLITQ_RE_MIN_GAP 64
114
115 #define IDPF_RFL_BI_GEN_M BIT(16)
116 #define IDPF_RFL_BI_BUFID_M GENMASK(15, 0)
117
118 #define IDPF_RXD_EOF_SPLITQ VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS0_EOF_M
119 #define IDPF_RXD_EOF_SINGLEQ VIRTCHNL2_RX_BASE_DESC_STATUS_EOF_M
120
121 #define IDPF_DESC_UNUSED(txq) \
122 ((((txq)->next_to_clean > (txq)->next_to_use) ? 0 : (txq)->desc_count) + \
123 (txq)->next_to_clean - (txq)->next_to_use - 1)
124
125 #define IDPF_TX_COMPLQ_OVERFLOW_THRESH(txcq) ((txcq)->desc_count >> 1)
126 /* Determine the absolute number of completions pending, i.e. the number of
127 * completions that are expected to arrive on the TX completion queue.
128 */
129 #define IDPF_TX_COMPLQ_PENDING(txq) \
130 (((txq)->num_completions_pending >= (txq)->complq->num_completions ? \
131 0 : U32_MAX) + \
132 (txq)->num_completions_pending - (txq)->complq->num_completions)
133
134 #define IDPF_TXBUF_NULL U32_MAX
135
136 #define IDPF_TXD_LAST_DESC_CMD (IDPF_TX_DESC_CMD_EOP | IDPF_TX_DESC_CMD_RS)
137
138 #define IDPF_TX_FLAGS_TSO BIT(0)
139 #define IDPF_TX_FLAGS_IPV4 BIT(1)
140 #define IDPF_TX_FLAGS_IPV6 BIT(2)
141 #define IDPF_TX_FLAGS_TUNNEL BIT(3)
142 #define IDPF_TX_FLAGS_TSYN BIT(4)
143
144 struct libeth_rq_napi_stats;
145
146 union idpf_tx_flex_desc {
147 struct idpf_flex_tx_desc q; /* queue based scheduling */
148 struct idpf_flex_tx_sched_desc flow; /* flow based scheduling */
149 };
150
151 #define idpf_tx_buf libeth_sqe
152
153 /**
154 * struct idpf_tx_offload_params - Offload parameters for a given packet
155 * @tx_flags: Feature flags enabled for this packet
156 * @hdr_offsets: Offset parameter for single queue model
157 * @cd_tunneling: Type of tunneling enabled for single queue model
158 * @tso_len: Total length of payload to segment
159 * @mss: Segment size
160 * @tso_segs: Number of segments to be sent
161 * @tso_hdr_len: Length of headers to be duplicated
162 * @td_cmd: Command field to be inserted into descriptor
163 */
164 struct idpf_tx_offload_params {
165 u32 tx_flags;
166
167 u32 hdr_offsets;
168 u32 cd_tunneling;
169
170 u32 tso_len;
171 u16 mss;
172 u16 tso_segs;
173 u16 tso_hdr_len;
174
175 u16 td_cmd;
176 };
177
178 /**
179 * struct idpf_tx_splitq_params
180 * @dtype: General descriptor info
181 * @eop_cmd: Type of EOP
182 * @compl_tag: Associated tag for completion
183 * @td_tag: Descriptor tunneling tag
184 * @offload: Offload parameters
185 * @prev_ntu: stored TxQ next_to_use in case of rollback
186 * @prev_refill_ntc: stored refillq next_to_clean in case of packet rollback
187 * @prev_refill_gen: stored refillq generation bit in case of packet rollback
188 */
189 struct idpf_tx_splitq_params {
190 enum idpf_tx_desc_dtype_value dtype;
191 u16 eop_cmd;
192 union {
193 u16 compl_tag;
194 u16 td_tag;
195 };
196
197 struct idpf_tx_offload_params offload;
198
199 u16 prev_ntu;
200 u16 prev_refill_ntc;
201 bool prev_refill_gen;
202 };
203
204 enum idpf_tx_ctx_desc_eipt_offload {
205 IDPF_TX_CTX_EXT_IP_NONE = 0x0,
206 IDPF_TX_CTX_EXT_IP_IPV6 = 0x1,
207 IDPF_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
208 IDPF_TX_CTX_EXT_IP_IPV4 = 0x3
209 };
210
211 #define IDPF_TX_COMPLQ_CLEAN_BUDGET 256
212 #define IDPF_TX_MIN_PKT_LEN 17
213 #define IDPF_TX_DESCS_FOR_SKB_DATA_PTR 1
214 #define IDPF_TX_DESCS_PER_CACHE_LINE (L1_CACHE_BYTES / \
215 sizeof(struct idpf_flex_tx_desc))
216 #define IDPF_TX_DESCS_FOR_CTX 1
217 /* TX descriptors needed, worst case */
218 #define IDPF_TX_DESC_NEEDED (MAX_SKB_FRAGS + IDPF_TX_DESCS_FOR_CTX + \
219 IDPF_TX_DESCS_PER_CACHE_LINE + \
220 IDPF_TX_DESCS_FOR_SKB_DATA_PTR)
221
222 /* The size limit for a transmit buffer in a descriptor is (16K - 1).
223 * In order to align with the read requests we will align the value to
224 * the nearest 4K which represents our maximum read request size.
225 */
226 #define IDPF_TX_MAX_READ_REQ_SIZE SZ_4K
227 #define IDPF_TX_MAX_DESC_DATA (SZ_16K - 1)
228 #define IDPF_TX_MAX_DESC_DATA_ALIGNED \
229 ALIGN_DOWN(IDPF_TX_MAX_DESC_DATA, IDPF_TX_MAX_READ_REQ_SIZE)
230
231 #define idpf_rx_buf libeth_fqe
232
233 #define IDPF_RX_MAX_PTYPE_PROTO_IDS 32
234 #define IDPF_RX_MAX_PTYPE_SZ (sizeof(struct virtchnl2_ptype) + \
235 (sizeof(u16) * IDPF_RX_MAX_PTYPE_PROTO_IDS))
236 #define IDPF_RX_PTYPE_HDR_SZ sizeof(struct virtchnl2_get_ptype_info)
237 #define IDPF_RX_MAX_PTYPES_PER_BUF \
238 DIV_ROUND_DOWN_ULL((IDPF_CTLQ_MAX_BUF_LEN - IDPF_RX_PTYPE_HDR_SZ), \
239 IDPF_RX_MAX_PTYPE_SZ)
240
241 #define IDPF_GET_PTYPE_SIZE(p) struct_size((p), proto_id, (p)->proto_id_count)
242
243 #define IDPF_TUN_IP_GRE (\
244 IDPF_PTYPE_TUNNEL_IP |\
245 IDPF_PTYPE_TUNNEL_IP_GRENAT)
246
247 #define IDPF_TUN_IP_GRE_MAC (\
248 IDPF_TUN_IP_GRE |\
249 IDPF_PTYPE_TUNNEL_IP_GRENAT_MAC)
250
251 #define IDPF_RX_MAX_PTYPE 1024
252 #define IDPF_RX_MAX_BASE_PTYPE 256
253 #define IDPF_INVALID_PTYPE_ID 0xFFFF
254
255 enum idpf_tunnel_state {
256 IDPF_PTYPE_TUNNEL_IP = BIT(0),
257 IDPF_PTYPE_TUNNEL_IP_GRENAT = BIT(1),
258 IDPF_PTYPE_TUNNEL_IP_GRENAT_MAC = BIT(2),
259 };
260
261 struct idpf_ptype_state {
262 bool outer_ip:1;
263 bool outer_frag:1;
264 u8 tunnel_state:6;
265 };
266
267 /**
268 * enum idpf_queue_flags_t
269 * @__IDPF_Q_GEN_CHK: Queues operating in splitq mode use a generation bit to
270 * identify new descriptor writebacks on the ring. HW sets
271 * the gen bit to 1 on the first writeback of any given
272 * descriptor. After the ring wraps, HW sets the gen bit of
273 * those descriptors to 0, and continues flipping
274 * 0->1 or 1->0 on each ring wrap. SW maintains its own
275 * gen bit to know what value will indicate writebacks on
276 * the next pass around the ring. E.g. it is initialized
277 * to 1 and knows that reading a gen bit of 1 in any
278 * descriptor on the initial pass of the ring indicates a
279 * writeback. It also flips on every ring wrap.
280 * @__IDPF_Q_RFL_GEN_CHK: Refill queues are SW only, so Q_GEN acts as the HW
281 * bit and Q_RFL_GEN is the SW bit.
282 * @__IDPF_Q_FLOW_SCH_EN: Enable flow scheduling
283 * @__IDPF_Q_SW_MARKER: Used to indicate TX queue marker completions
284 * @__IDPF_Q_CRC_EN: enable CRC offload in singleq mode
285 * @__IDPF_Q_HSPLIT_EN: enable header split on Rx (splitq)
286 * @__IDPF_Q_PTP: indicates whether the Rx timestamping is enabled for the
287 * queue
288 * @__IDPF_Q_NOIRQ: queue is polling-driven and has no interrupt
289 * @__IDPF_Q_XDP: this is an XDP queue
290 * @__IDPF_Q_XSK: the queue has an XSk pool installed
291 * @__IDPF_Q_FLAGS_NBITS: Must be last
292 */
293 enum idpf_queue_flags_t {
294 __IDPF_Q_GEN_CHK,
295 __IDPF_Q_RFL_GEN_CHK,
296 __IDPF_Q_FLOW_SCH_EN,
297 __IDPF_Q_SW_MARKER,
298 __IDPF_Q_CRC_EN,
299 __IDPF_Q_HSPLIT_EN,
300 __IDPF_Q_PTP,
301 __IDPF_Q_NOIRQ,
302 __IDPF_Q_XDP,
303 __IDPF_Q_XSK,
304
305 __IDPF_Q_FLAGS_NBITS,
306 };
307
308 #define idpf_queue_set(f, q) __set_bit(__IDPF_Q_##f, (q)->flags)
309 #define idpf_queue_clear(f, q) __clear_bit(__IDPF_Q_##f, (q)->flags)
310 #define idpf_queue_change(f, q) __change_bit(__IDPF_Q_##f, (q)->flags)
311 #define idpf_queue_has(f, q) test_bit(__IDPF_Q_##f, (q)->flags)
312
313 #define idpf_queue_has_clear(f, q) \
314 __test_and_clear_bit(__IDPF_Q_##f, (q)->flags)
315 #define idpf_queue_assign(f, q, v) \
316 __assign_bit(__IDPF_Q_##f, (q)->flags, v)
317
318 /**
319 * struct idpf_vec_regs
320 * @dyn_ctl_reg: Dynamic control interrupt register offset
321 * @itrn_reg: Interrupt Throttling Rate register offset
322 * @itrn_index_spacing: Register spacing between ITR registers of the same
323 * vector
324 */
325 struct idpf_vec_regs {
326 u32 dyn_ctl_reg;
327 u32 itrn_reg;
328 u32 itrn_index_spacing;
329 };
330
331 /**
332 * struct idpf_intr_reg
333 * @dyn_ctl: Dynamic control interrupt register
334 * @dyn_ctl_intena_m: Mask for dyn_ctl interrupt enable
335 * @dyn_ctl_intena_msk_m: Mask for dyn_ctl interrupt enable mask
336 * @dyn_ctl_itridx_s: Register bit offset for ITR index
337 * @dyn_ctl_itridx_m: Mask for ITR index
338 * @dyn_ctl_intrvl_s: Register bit offset for ITR interval
339 * @dyn_ctl_wb_on_itr_m: Mask for WB on ITR feature
340 * @dyn_ctl_sw_itridx_ena_m: Mask for SW ITR index
341 * @dyn_ctl_swint_trig_m: Mask for dyn_ctl SW triggered interrupt enable
342 * @rx_itr: RX ITR register
343 * @tx_itr: TX ITR register
344 * @icr_ena: Interrupt cause register offset
345 * @icr_ena_ctlq_m: Mask for ICR
346 */
347 struct idpf_intr_reg {
348 void __iomem *dyn_ctl;
349 u32 dyn_ctl_intena_m;
350 u32 dyn_ctl_intena_msk_m;
351 u32 dyn_ctl_itridx_s;
352 u32 dyn_ctl_itridx_m;
353 u32 dyn_ctl_intrvl_s;
354 u32 dyn_ctl_wb_on_itr_m;
355 u32 dyn_ctl_sw_itridx_ena_m;
356 u32 dyn_ctl_swint_trig_m;
357 void __iomem *rx_itr;
358 void __iomem *tx_itr;
359 void __iomem *icr_ena;
360 u32 icr_ena_ctlq_m;
361 };
362
363 /**
364 * struct idpf_q_vector
365 * @vport: Vport back pointer
366 * @num_rxq: Number of RX queues
367 * @num_txq: Number of TX queues
368 * @num_bufq: Number of buffer queues
369 * @num_complq: number of completion queues
370 * @num_xsksq: number of XSk send queues
371 * @rx: Array of RX queues to service
372 * @tx: Array of TX queues to service
373 * @bufq: Array of buffer queues to service
374 * @complq: array of completion queues
375 * @xsksq: array of XSk send queues
376 * @intr_reg: See struct idpf_intr_reg
377 * @csd: XSk wakeup CSD
378 * @total_events: Number of interrupts processed
379 * @wb_on_itr: whether WB on ITR is enabled
380 * @napi: napi handler
381 * @tx_dim: Data for TX net_dim algorithm
382 * @tx_itr_value: TX interrupt throttling rate
383 * @tx_intr_mode: Dynamic ITR or not
384 * @tx_itr_idx: TX ITR index
385 * @rx_dim: Data for RX net_dim algorithm
386 * @rx_itr_value: RX interrupt throttling rate
387 * @rx_intr_mode: Dynamic ITR or not
388 * @rx_itr_idx: RX ITR index
389 * @v_idx: Vector index
390 */
391 struct idpf_q_vector {
392 __cacheline_group_begin_aligned(read_mostly);
393 struct idpf_vport *vport;
394
395 u16 num_rxq;
396 u16 num_txq;
397 u16 num_bufq;
398 u16 num_complq;
399 u16 num_xsksq;
400 struct idpf_rx_queue **rx;
401 struct idpf_tx_queue **tx;
402 struct idpf_buf_queue **bufq;
403 struct idpf_compl_queue **complq;
404 struct idpf_tx_queue **xsksq;
405
406 struct idpf_intr_reg intr_reg;
407 __cacheline_group_end_aligned(read_mostly);
408
409 __cacheline_group_begin_aligned(read_write);
410 call_single_data_t csd;
411
412 u16 total_events;
413 bool wb_on_itr;
414
415 struct napi_struct napi;
416
417 struct dim tx_dim;
418 u16 tx_itr_value;
419 bool tx_intr_mode;
420 u32 tx_itr_idx;
421
422 struct dim rx_dim;
423 u16 rx_itr_value;
424 bool rx_intr_mode;
425 u32 rx_itr_idx;
426 __cacheline_group_end_aligned(read_write);
427
428 __cacheline_group_begin_aligned(cold);
429 u16 v_idx;
430
431 __cacheline_group_end_aligned(cold);
432 };
433 libeth_cacheline_set_assert(struct idpf_q_vector, 136,
434 56 + sizeof(struct napi_struct) +
435 2 * sizeof(struct dim),
436 8);
437
438 struct idpf_rx_queue_stats {
439 u64_stats_t packets;
440 u64_stats_t bytes;
441 u64_stats_t rsc_pkts;
442 u64_stats_t hw_csum_err;
443 u64_stats_t hsplit_pkts;
444 u64_stats_t hsplit_buf_ovf;
445 u64_stats_t bad_descs;
446 };
447
448 struct idpf_tx_queue_stats {
449 u64_stats_t packets;
450 u64_stats_t bytes;
451 u64_stats_t lso_pkts;
452 u64_stats_t linearize;
453 u64_stats_t q_busy;
454 u64_stats_t skb_drops;
455 u64_stats_t dma_map_errs;
456 u64_stats_t tstamp_skipped;
457 };
458
459 #define IDPF_ITR_DYNAMIC 1
460 #define IDPF_ITR_MAX 0x1FE0
461 #define IDPF_ITR_20K 0x0032
462 #define IDPF_ITR_GRAN_S 1 /* Assume ITR granularity is 2us */
463 #define IDPF_ITR_MASK 0x1FFE /* ITR register value alignment mask */
464 #define ITR_REG_ALIGN(setting) ((setting) & IDPF_ITR_MASK)
465 #define IDPF_ITR_IS_DYNAMIC(itr_mode) (itr_mode)
466 #define IDPF_ITR_TX_DEF IDPF_ITR_20K
467 #define IDPF_ITR_RX_DEF IDPF_ITR_20K
468 /* Index used for 'SW ITR' update in DYN_CTL register */
469 #define IDPF_SW_ITR_UPDATE_IDX 2
470 /* Index used for 'No ITR' update in DYN_CTL register */
471 #define IDPF_NO_ITR_UPDATE_IDX 3
472 #define IDPF_ITR_IDX_SPACING(spacing, dflt) (spacing ? spacing : dflt)
473 #define IDPF_DIM_DEFAULT_PROFILE_IX 1
474
475 /**
476 * struct idpf_rx_queue - software structure representing a receive queue
477 * @rx: universal receive descriptor array
478 * @single_buf: buffer descriptor array in singleq
479 * @desc_ring: virtual descriptor ring address
480 * @bufq_sets: Pointer to the array of buffer queues in splitq mode
481 * @napi: NAPI instance corresponding to this queue (splitq)
482 * @xdp_prog: attached XDP program
483 * @rx_buf: See struct &libeth_fqe
484 * @pp: Page pool pointer in singleq mode
485 * @tail: Tail offset. Used for both queue models single and split.
486 * @flags: See enum idpf_queue_flags_t
487 * @idx: For RX queue, it is used to index to total RX queue across groups and
488 * used for skb reporting.
489 * @desc_count: Number of descriptors
490 * @num_xdp_txq: total number of XDP Tx queues
491 * @xdpsqs: shortcut for XDP Tx queues array
492 * @rxdids: Supported RX descriptor ids
493 * @truesize: data buffer truesize in singleq
494 * @rx_ptype_lkup: LUT of Rx ptypes
495 * @xdp_rxq: XDP queue info
496 * @next_to_use: Next descriptor to use
497 * @next_to_clean: Next descriptor to clean
498 * @next_to_alloc: RX buffer to allocate at
499 * @xdp: XDP buffer with the current frame
500 * @xsk: current XDP buffer in XSk mode
501 * @pool: XSk pool if installed
502 * @cached_phc_time: Cached PHC time for the Rx queue
503 * @stats_sync: See struct u64_stats_sync
504 * @q_stats: See union idpf_rx_queue_stats
505 * @q_id: Queue id
506 * @size: Length of descriptor ring in bytes
507 * @dma: Physical address of ring
508 * @q_vector: Backreference to associated vector
509 * @rx_buffer_low_watermark: RX buffer low watermark
510 * @rx_hbuf_size: Header buffer size
511 * @rx_buf_size: Buffer size
512 * @rx_max_pkt_size: RX max packet size
513 */
514 struct idpf_rx_queue {
515 __cacheline_group_begin_aligned(read_mostly);
516 union {
517 union virtchnl2_rx_desc *rx;
518 struct virtchnl2_singleq_rx_buf_desc *single_buf;
519
520 void *desc_ring;
521 };
522 union {
523 struct {
524 struct idpf_bufq_set *bufq_sets;
525 struct napi_struct *napi;
526 struct bpf_prog __rcu *xdp_prog;
527 };
528 struct {
529 struct libeth_fqe *rx_buf;
530 struct page_pool *pp;
531 void __iomem *tail;
532 };
533 };
534
535 DECLARE_BITMAP(flags, __IDPF_Q_FLAGS_NBITS);
536 u16 idx;
537 u16 desc_count;
538
539 u32 num_xdp_txq;
540 union {
541 struct idpf_tx_queue **xdpsqs;
542 struct {
543 u32 rxdids;
544 u32 truesize;
545 };
546 };
547 const struct libeth_rx_pt *rx_ptype_lkup;
548
549 struct xdp_rxq_info xdp_rxq;
550 __cacheline_group_end_aligned(read_mostly);
551
552 __cacheline_group_begin_aligned(read_write);
553 u32 next_to_use;
554 u32 next_to_clean;
555 u32 next_to_alloc;
556
557 union {
558 struct libeth_xdp_buff_stash xdp;
559 struct {
560 struct libeth_xdp_buff *xsk;
561 struct xsk_buff_pool *pool;
562 };
563 };
564 u64 cached_phc_time;
565
566 struct u64_stats_sync stats_sync;
567 struct idpf_rx_queue_stats q_stats;
568 __cacheline_group_end_aligned(read_write);
569
570 __cacheline_group_begin_aligned(cold);
571 u32 q_id;
572 u32 size;
573 dma_addr_t dma;
574
575 struct idpf_q_vector *q_vector;
576
577 u16 rx_buffer_low_watermark;
578 u16 rx_hbuf_size;
579 u16 rx_buf_size;
580 u16 rx_max_pkt_size;
581 __cacheline_group_end_aligned(cold);
582 };
583 libeth_cacheline_set_assert(struct idpf_rx_queue,
584 ALIGN(64, __alignof(struct xdp_rxq_info)) +
585 sizeof(struct xdp_rxq_info),
586 96 + offsetof(struct idpf_rx_queue, q_stats) -
587 offsetofend(struct idpf_rx_queue, cached_phc_time),
588 32);
589
590 /**
591 * struct idpf_tx_queue - software structure representing a transmit queue
592 * @base_tx: base Tx descriptor array
593 * @base_ctx: base Tx context descriptor array
594 * @flex_tx: flex Tx descriptor array
595 * @flex_ctx: flex Tx context descriptor array
596 * @desc_ring: virtual descriptor ring address
597 * @tx_buf: See struct idpf_tx_buf
598 * @txq_grp: See struct idpf_txq_group
599 * @complq: corresponding completion queue in XDP mode
600 * @dev: Device back pointer for DMA mapping
601 * @pool: corresponding XSk pool if installed
602 * @tail: Tail offset. Used for both queue models single and split
603 * @flags: See enum idpf_queue_flags_t
604 * @idx: For TX queue, it is used as index to map between TX queue group and
605 * hot path TX pointers stored in vport. Used in both singleq/splitq.
606 * @desc_count: Number of descriptors
607 * @tx_min_pkt_len: Min supported packet length
608 * @thresh: XDP queue cleaning threshold
609 * @netdev: &net_device corresponding to this queue
610 * @next_to_use: Next descriptor to use
611 * @next_to_clean: Next descriptor to clean
612 * @last_re: last descriptor index that RE bit was set
613 * @tx_max_bufs: Max buffers that can be transmitted with scatter-gather
614 * @cleaned_bytes: Splitq only, TXQ only: When a TX completion is received on
615 * the TX completion queue, it can be for any TXQ associated
616 * with that completion queue. This means we can clean up to
617 * N TXQs during a single call to clean the completion queue.
618 * cleaned_bytes|pkts tracks the clean stats per TXQ during
619 * that single call to clean the completion queue. By doing so,
620 * we can update BQL with aggregate cleaned stats for each TXQ
621 * only once at the end of the cleaning routine.
622 * @clean_budget: singleq only, queue cleaning budget
623 * @cleaned_pkts: Number of packets cleaned for the above said case
624 * @refillq: Pointer to refill queue
625 * @pending: number of pending descriptors to send in QB
626 * @xdp_tx: number of pending &xdp_buff or &xdp_frame buffers
627 * @timer: timer for XDP Tx queue cleanup
628 * @xdp_lock: lock for XDP Tx queues sharing
629 * @cached_tstamp_caps: Tx timestamp capabilities negotiated with the CP
630 * @tstamp_task: Work that handles Tx timestamp read
631 * @stats_sync: See struct u64_stats_sync
632 * @q_stats: See union idpf_tx_queue_stats
633 * @q_id: Queue id
634 * @size: Length of descriptor ring in bytes
635 * @dma: Physical address of ring
636 * @q_vector: Backreference to associated vector
637 * @buf_pool_size: Total number of idpf_tx_buf
638 * @rel_q_id: relative virtchnl queue index
639 */
640 struct idpf_tx_queue {
641 __cacheline_group_begin_aligned(read_mostly);
642 union {
643 struct idpf_base_tx_desc *base_tx;
644 struct idpf_base_tx_ctx_desc *base_ctx;
645 union idpf_tx_flex_desc *flex_tx;
646 union idpf_flex_tx_ctx_desc *flex_ctx;
647
648 void *desc_ring;
649 };
650 struct libeth_sqe *tx_buf;
651 union {
652 struct idpf_txq_group *txq_grp;
653 struct idpf_compl_queue *complq;
654 };
655 union {
656 struct device *dev;
657 struct xsk_buff_pool *pool;
658 };
659 void __iomem *tail;
660
661 DECLARE_BITMAP(flags, __IDPF_Q_FLAGS_NBITS);
662 u16 idx;
663 u16 desc_count;
664
665 union {
666 u16 tx_min_pkt_len;
667 u32 thresh;
668 };
669
670 struct net_device *netdev;
671 __cacheline_group_end_aligned(read_mostly);
672
673 __cacheline_group_begin_aligned(read_write);
674 u32 next_to_use;
675 u32 next_to_clean;
676
677 union {
678 struct {
679 u16 last_re;
680 u16 tx_max_bufs;
681
682 union {
683 u32 cleaned_bytes;
684 u32 clean_budget;
685 };
686 u16 cleaned_pkts;
687
688 struct idpf_sw_queue *refillq;
689 };
690 struct {
691 u32 pending;
692 u32 xdp_tx;
693
694 struct libeth_xdpsq_timer *timer;
695 struct libeth_xdpsq_lock xdp_lock;
696 };
697 };
698
699 struct idpf_ptp_vport_tx_tstamp_caps *cached_tstamp_caps;
700 struct work_struct *tstamp_task;
701
702 struct u64_stats_sync stats_sync;
703 struct idpf_tx_queue_stats q_stats;
704 __cacheline_group_end_aligned(read_write);
705
706 __cacheline_group_begin_aligned(cold);
707 u32 q_id;
708 u32 size;
709 dma_addr_t dma;
710
711 struct idpf_q_vector *q_vector;
712
713 u32 buf_pool_size;
714 u32 rel_q_id;
715 __cacheline_group_end_aligned(cold);
716 };
717 libeth_cacheline_set_assert(struct idpf_tx_queue, 64,
718 104 +
719 offsetof(struct idpf_tx_queue, cached_tstamp_caps) -
720 offsetofend(struct idpf_tx_queue, timer) +
721 offsetof(struct idpf_tx_queue, q_stats) -
722 offsetofend(struct idpf_tx_queue, tstamp_task),
723 32);
724
725 /**
726 * struct idpf_buf_queue - software structure representing a buffer queue
727 * @split_buf: buffer descriptor array
728 * @buf: &libeth_fqe for data buffers
729 * @pp: &page_pool for data buffers
730 * @xsk_buf: &xdp_buff for XSk Rx buffers
731 * @pool: &xsk_buff_pool on XSk queues
732 * @hdr_buf: &libeth_fqe for header buffers
733 * @hdr_pp: &page_pool for header buffers
734 * @tail: Tail offset
735 * @flags: See enum idpf_queue_flags_t
736 * @desc_count: Number of descriptors
737 * @thresh: refill threshold in XSk
738 * @next_to_use: Next descriptor to use
739 * @next_to_clean: Next descriptor to clean
740 * @next_to_alloc: RX buffer to allocate at
741 * @pending: number of buffers to refill (Xsk)
742 * @hdr_truesize: truesize for buffer headers
743 * @truesize: truesize for data buffers
744 * @q_id: Queue id
745 * @size: Length of descriptor ring in bytes
746 * @dma: Physical address of ring
747 * @q_vector: Backreference to associated vector
748 * @rx_buffer_low_watermark: RX buffer low watermark
749 * @rx_hbuf_size: Header buffer size
750 * @rx_buf_size: Buffer size
751 */
752 struct idpf_buf_queue {
753 __cacheline_group_begin_aligned(read_mostly);
754 struct virtchnl2_splitq_rx_buf_desc *split_buf;
755 union {
756 struct {
757 struct libeth_fqe *buf;
758 struct page_pool *pp;
759 };
760 struct {
761 struct libeth_xdp_buff **xsk_buf;
762 struct xsk_buff_pool *pool;
763 };
764 };
765 struct libeth_fqe *hdr_buf;
766 struct page_pool *hdr_pp;
767 void __iomem *tail;
768
769 DECLARE_BITMAP(flags, __IDPF_Q_FLAGS_NBITS);
770 u32 desc_count;
771
772 u32 thresh;
773 __cacheline_group_end_aligned(read_mostly);
774
775 __cacheline_group_begin_aligned(read_write);
776 u32 next_to_use;
777 u32 next_to_clean;
778 u32 next_to_alloc;
779
780 u32 pending;
781 u32 hdr_truesize;
782 u32 truesize;
783 __cacheline_group_end_aligned(read_write);
784
785 __cacheline_group_begin_aligned(cold);
786 u32 q_id;
787 u32 size;
788 dma_addr_t dma;
789
790 struct idpf_q_vector *q_vector;
791
792 u16 rx_buffer_low_watermark;
793 u16 rx_hbuf_size;
794 u16 rx_buf_size;
795 __cacheline_group_end_aligned(cold);
796 };
797 libeth_cacheline_set_assert(struct idpf_buf_queue, 64, 24, 32);
798
799 /**
800 * struct idpf_compl_queue - software structure representing a completion queue
801 * @comp: 8-byte completion descriptor array
802 * @comp_4b: 4-byte completion descriptor array
803 * @desc_ring: virtual descriptor ring address
804 * @txq_grp: See struct idpf_txq_group
805 * @flags: See enum idpf_queue_flags_t
806 * @desc_count: Number of descriptors
807 * @clean_budget: queue cleaning budget
808 * @netdev: &net_device corresponding to this queue
809 * @next_to_use: Next descriptor to use. Relevant in both split & single txq
810 * and bufq.
811 * @next_to_clean: Next descriptor to clean
812 * @num_completions: Only relevant for TX completion queue. It tracks the
813 * number of completions received to compare against the
814 * number of completions pending, as accumulated by the
815 * TX queues.
816 * @q_id: Queue id
817 * @size: Length of descriptor ring in bytes
818 * @dma: Physical address of ring
819 * @q_vector: Backreference to associated vector
820 */
821 struct idpf_compl_queue {
822 __cacheline_group_begin_aligned(read_mostly);
823 union {
824 struct idpf_splitq_tx_compl_desc *comp;
825 struct idpf_splitq_4b_tx_compl_desc *comp_4b;
826
827 void *desc_ring;
828 };
829 struct idpf_txq_group *txq_grp;
830
831 DECLARE_BITMAP(flags, __IDPF_Q_FLAGS_NBITS);
832 u32 desc_count;
833
834 u32 clean_budget;
835 struct net_device *netdev;
836 __cacheline_group_end_aligned(read_mostly);
837
838 __cacheline_group_begin_aligned(read_write);
839 u32 next_to_use;
840 u32 next_to_clean;
841
842 aligned_u64 num_completions;
843 __cacheline_group_end_aligned(read_write);
844
845 __cacheline_group_begin_aligned(cold);
846 u32 q_id;
847 u32 size;
848 dma_addr_t dma;
849
850 struct idpf_q_vector *q_vector;
851 __cacheline_group_end_aligned(cold);
852 };
853 libeth_cacheline_set_assert(struct idpf_compl_queue, 40, 16, 24);
854
855 /**
856 * struct idpf_sw_queue
857 * @ring: Pointer to the ring
858 * @flags: See enum idpf_queue_flags_t
859 * @desc_count: Descriptor count
860 * @next_to_use: Buffer to allocate at
861 * @next_to_clean: Next descriptor to clean
862 *
863 * Software queues are used in splitq mode to manage buffers between rxq
864 * producer and the bufq consumer. These are required in order to maintain a
865 * lockless buffer management system and are strictly software only constructs.
866 */
867 struct idpf_sw_queue {
868 __cacheline_group_begin_aligned(read_mostly);
869 u32 *ring;
870
871 DECLARE_BITMAP(flags, __IDPF_Q_FLAGS_NBITS);
872 u32 desc_count;
873 __cacheline_group_end_aligned(read_mostly);
874
875 __cacheline_group_begin_aligned(read_write);
876 u32 next_to_use;
877 u32 next_to_clean;
878 __cacheline_group_end_aligned(read_write);
879 };
880 libeth_cacheline_group_assert(struct idpf_sw_queue, read_mostly, 24);
881 libeth_cacheline_group_assert(struct idpf_sw_queue, read_write, 8);
882 libeth_cacheline_struct_assert(struct idpf_sw_queue, 24, 8);
883
884 /**
885 * struct idpf_rxq_set
886 * @rxq: RX queue
887 * @refillq: pointers to refill queues
888 *
889 * Splitq only. idpf_rxq_set associates an rxq with at an array of refillqs.
890 * Each rxq needs a refillq to return used buffers back to the respective bufq.
891 * Bufqs then clean these refillqs for buffers to give to hardware.
892 */
893 struct idpf_rxq_set {
894 struct idpf_rx_queue rxq;
895 struct idpf_sw_queue *refillq[IDPF_MAX_BUFQS_PER_RXQ_GRP];
896 };
897
898 /**
899 * struct idpf_bufq_set
900 * @bufq: Buffer queue
901 * @num_refillqs: Number of refill queues. This is always equal to num_rxq_sets
902 * in idpf_rxq_group.
903 * @refillqs: Pointer to refill queues array.
904 *
905 * Splitq only. idpf_bufq_set associates a bufq to an array of refillqs.
906 * In this bufq_set, there will be one refillq for each rxq in this rxq_group.
907 * Used buffers received by rxqs will be put on refillqs which bufqs will
908 * clean to return new buffers back to hardware.
909 *
910 * Buffers needed by some number of rxqs associated in this rxq_group are
911 * managed by at most two bufqs (depending on performance configuration).
912 */
913 struct idpf_bufq_set {
914 struct idpf_buf_queue bufq;
915 int num_refillqs;
916 struct idpf_sw_queue *refillqs;
917 };
918
919 /**
920 * struct idpf_rxq_group
921 * @vport: Vport back pointer
922 * @singleq: Struct with single queue related members
923 * @singleq.num_rxq: Number of RX queues associated
924 * @singleq.rxqs: Array of RX queue pointers
925 * @splitq: Struct with split queue related members
926 * @splitq.num_rxq_sets: Number of RX queue sets
927 * @splitq.rxq_sets: Array of RX queue sets
928 * @splitq.bufq_sets: Buffer queue set pointer
929 *
930 * In singleq mode, an rxq_group is simply an array of rxqs. In splitq, a
931 * rxq_group contains all the rxqs, bufqs and refillqs needed to
932 * manage buffers in splitq mode.
933 */
934 struct idpf_rxq_group {
935 struct idpf_vport *vport;
936
937 union {
938 struct {
939 u16 num_rxq;
940 struct idpf_rx_queue *rxqs[IDPF_LARGE_MAX_Q];
941 } singleq;
942 struct {
943 u16 num_rxq_sets;
944 struct idpf_rxq_set *rxq_sets[IDPF_LARGE_MAX_Q];
945 struct idpf_bufq_set *bufq_sets;
946 } splitq;
947 };
948 };
949
950 /**
951 * struct idpf_txq_group
952 * @vport: Vport back pointer
953 * @num_txq: Number of TX queues associated
954 * @txqs: Array of TX queue pointers
955 * @complq: Associated completion queue pointer, split queue only
956 * @num_completions_pending: Total number of completions pending for the
957 * completion queue, acculumated for all TX queues
958 * associated with that completion queue.
959 *
960 * Between singleq and splitq, a txq_group is largely the same except for the
961 * complq. In splitq a single complq is responsible for handling completions
962 * for some number of txqs associated in this txq_group.
963 */
964 struct idpf_txq_group {
965 struct idpf_vport *vport;
966
967 u16 num_txq;
968 struct idpf_tx_queue *txqs[IDPF_LARGE_MAX_Q];
969
970 struct idpf_compl_queue *complq;
971
972 aligned_u64 num_completions_pending;
973 };
974
idpf_q_vector_to_mem(const struct idpf_q_vector * q_vector)975 static inline int idpf_q_vector_to_mem(const struct idpf_q_vector *q_vector)
976 {
977 u32 cpu;
978
979 if (!q_vector)
980 return NUMA_NO_NODE;
981
982 cpu = cpumask_first(&q_vector->napi.config->affinity_mask);
983
984 return cpu < nr_cpu_ids ? cpu_to_mem(cpu) : NUMA_NO_NODE;
985 }
986
987 /**
988 * idpf_size_to_txd_count - Get number of descriptors needed for large Tx frag
989 * @size: transmit request size in bytes
990 *
991 * In the case where a large frag (>= 16K) needs to be split across multiple
992 * descriptors, we need to assume that we can have no more than 12K of data
993 * per descriptor due to hardware alignment restrictions (4K alignment).
994 */
idpf_size_to_txd_count(unsigned int size)995 static inline u32 idpf_size_to_txd_count(unsigned int size)
996 {
997 return DIV_ROUND_UP(size, IDPF_TX_MAX_DESC_DATA_ALIGNED);
998 }
999
1000 /**
1001 * idpf_tx_singleq_build_ctob - populate command tag offset and size
1002 * @td_cmd: Command to be filled in desc
1003 * @td_offset: Offset to be filled in desc
1004 * @size: Size of the buffer
1005 * @td_tag: td tag to be filled
1006 *
1007 * Returns the 64 bit value populated with the input parameters
1008 */
idpf_tx_singleq_build_ctob(u64 td_cmd,u64 td_offset,unsigned int size,u64 td_tag)1009 static inline __le64 idpf_tx_singleq_build_ctob(u64 td_cmd, u64 td_offset,
1010 unsigned int size, u64 td_tag)
1011 {
1012 return cpu_to_le64(IDPF_TX_DESC_DTYPE_DATA |
1013 (td_cmd << IDPF_TXD_QW1_CMD_S) |
1014 (td_offset << IDPF_TXD_QW1_OFFSET_S) |
1015 ((u64)size << IDPF_TXD_QW1_TX_BUF_SZ_S) |
1016 (td_tag << IDPF_TXD_QW1_L2TAG1_S));
1017 }
1018
1019 void idpf_tx_splitq_build_ctb(union idpf_tx_flex_desc *desc,
1020 struct idpf_tx_splitq_params *params,
1021 u16 td_cmd, u16 size);
1022 void idpf_tx_splitq_build_flow_desc(union idpf_tx_flex_desc *desc,
1023 struct idpf_tx_splitq_params *params,
1024 u16 td_cmd, u16 size);
1025 /**
1026 * idpf_tx_splitq_build_desc - determine which type of data descriptor to build
1027 * @desc: descriptor to populate
1028 * @params: pointer to tx params struct
1029 * @td_cmd: command to be filled in desc
1030 * @size: size of buffer
1031 */
idpf_tx_splitq_build_desc(union idpf_tx_flex_desc * desc,struct idpf_tx_splitq_params * params,u16 td_cmd,u16 size)1032 static inline void idpf_tx_splitq_build_desc(union idpf_tx_flex_desc *desc,
1033 struct idpf_tx_splitq_params *params,
1034 u16 td_cmd, u16 size)
1035 {
1036 if (params->dtype == IDPF_TX_DESC_DTYPE_FLEX_L2TAG1_L2TAG2)
1037 idpf_tx_splitq_build_ctb(desc, params, td_cmd, size);
1038 else
1039 idpf_tx_splitq_build_flow_desc(desc, params, td_cmd, size);
1040 }
1041
1042 /**
1043 * idpf_vport_intr_set_wb_on_itr - enable descriptor writeback on disabled interrupts
1044 * @q_vector: pointer to queue vector struct
1045 */
idpf_vport_intr_set_wb_on_itr(struct idpf_q_vector * q_vector)1046 static inline void idpf_vport_intr_set_wb_on_itr(struct idpf_q_vector *q_vector)
1047 {
1048 struct idpf_intr_reg *reg;
1049
1050 if (q_vector->wb_on_itr)
1051 return;
1052
1053 q_vector->wb_on_itr = true;
1054 reg = &q_vector->intr_reg;
1055
1056 writel(reg->dyn_ctl_wb_on_itr_m | reg->dyn_ctl_intena_msk_m |
1057 (IDPF_NO_ITR_UPDATE_IDX << reg->dyn_ctl_itridx_s),
1058 reg->dyn_ctl);
1059 }
1060
1061 /**
1062 * idpf_tx_splitq_get_free_bufs - get number of free buf_ids in refillq
1063 * @refillq: pointer to refillq containing buf_ids
1064 */
idpf_tx_splitq_get_free_bufs(struct idpf_sw_queue * refillq)1065 static inline u32 idpf_tx_splitq_get_free_bufs(struct idpf_sw_queue *refillq)
1066 {
1067 return (refillq->next_to_use > refillq->next_to_clean ?
1068 0 : refillq->desc_count) +
1069 refillq->next_to_use - refillq->next_to_clean - 1;
1070 }
1071
1072 int idpf_vport_singleq_napi_poll(struct napi_struct *napi, int budget);
1073 void idpf_vport_init_num_qs(struct idpf_vport *vport,
1074 struct virtchnl2_create_vport *vport_msg);
1075 void idpf_vport_calc_num_q_desc(struct idpf_vport *vport);
1076 int idpf_vport_calc_total_qs(struct idpf_adapter *adapter, u16 vport_index,
1077 struct virtchnl2_create_vport *vport_msg,
1078 struct idpf_vport_max_q *max_q);
1079 void idpf_vport_calc_num_q_groups(struct idpf_vport *vport);
1080 int idpf_vport_queues_alloc(struct idpf_vport *vport);
1081 void idpf_vport_queues_rel(struct idpf_vport *vport);
1082 void idpf_vport_intr_rel(struct idpf_vport *vport);
1083 int idpf_vport_intr_alloc(struct idpf_vport *vport);
1084 void idpf_vport_intr_update_itr_ena_irq(struct idpf_q_vector *q_vector);
1085 void idpf_vport_intr_deinit(struct idpf_vport *vport);
1086 int idpf_vport_intr_init(struct idpf_vport *vport);
1087 void idpf_vport_intr_ena(struct idpf_vport *vport);
1088 int idpf_config_rss(struct idpf_vport *vport);
1089 int idpf_init_rss(struct idpf_vport *vport);
1090 void idpf_deinit_rss(struct idpf_vport *vport);
1091 int idpf_rx_bufs_init_all(struct idpf_vport *vport);
1092
1093 struct idpf_q_vector *idpf_find_rxq_vec(const struct idpf_vport *vport,
1094 u32 q_num);
1095 struct idpf_q_vector *idpf_find_txq_vec(const struct idpf_vport *vport,
1096 u32 q_num);
1097 int idpf_qp_switch(struct idpf_vport *vport, u32 qid, bool en);
1098
1099 void idpf_tx_buf_hw_update(struct idpf_tx_queue *tx_q, u32 val,
1100 bool xmit_more);
1101 unsigned int idpf_size_to_txd_count(unsigned int size);
1102 netdev_tx_t idpf_tx_drop_skb(struct idpf_tx_queue *tx_q, struct sk_buff *skb);
1103 unsigned int idpf_tx_res_count_required(struct idpf_tx_queue *txq,
1104 struct sk_buff *skb, u32 *buf_count);
1105 void idpf_tx_timeout(struct net_device *netdev, unsigned int txqueue);
1106 netdev_tx_t idpf_tx_singleq_frame(struct sk_buff *skb,
1107 struct idpf_tx_queue *tx_q);
1108 netdev_tx_t idpf_tx_start(struct sk_buff *skb, struct net_device *netdev);
1109 bool idpf_rx_singleq_buf_hw_alloc_all(struct idpf_rx_queue *rxq,
1110 u16 cleaned_count);
1111 bool idpf_rx_process_skb_fields(struct sk_buff *skb,
1112 const struct libeth_xdp_buff *xdp,
1113 struct libeth_rq_napi_stats *rs);
1114 int idpf_tso(struct sk_buff *skb, struct idpf_tx_offload_params *off);
1115
1116 void idpf_wait_for_sw_marker_completion(const struct idpf_tx_queue *txq);
1117
1118 #endif /* !_IDPF_TXRX_H_ */
1119