1 /* 2 * SPDX-License-Identifier: MIT 3 * 4 * Copyright © 2017-2018 Intel Corporation 5 */ 6 7 #ifndef __I915_PMU_H__ 8 #define __I915_PMU_H__ 9 10 #include <linux/hrtimer.h> 11 #include <linux/perf_event.h> 12 #include <linux/spinlock_types.h> 13 #include <uapi/drm/i915_drm.h> 14 15 struct drm_i915_private; 16 struct intel_gt; 17 18 /* 19 * Non-engine events that we need to track enabled-disabled transition and 20 * current state. 21 */ 22 enum i915_pmu_tracked_events { 23 __I915_PMU_ACTUAL_FREQUENCY_ENABLED = 0, 24 __I915_PMU_REQUESTED_FREQUENCY_ENABLED, 25 __I915_PMU_RC6_RESIDENCY_ENABLED, 26 __I915_PMU_TRACKED_EVENT_COUNT, /* count marker */ 27 }; 28 29 /* 30 * Slots used from the sampling timer (non-engine events) with some extras for 31 * convenience. 32 */ 33 enum { 34 __I915_SAMPLE_FREQ_ACT = 0, 35 __I915_SAMPLE_FREQ_REQ, 36 __I915_SAMPLE_RC6, 37 __I915_SAMPLE_RC6_LAST_REPORTED, 38 __I915_NUM_PMU_SAMPLERS 39 }; 40 41 #define I915_PMU_MAX_GT 2 42 43 /* 44 * How many different events we track in the global PMU mask. 45 * 46 * It is also used to know to needed number of event reference counters. 47 */ 48 #define I915_PMU_MASK_BITS \ 49 (I915_ENGINE_SAMPLE_COUNT + \ 50 I915_PMU_MAX_GT * __I915_PMU_TRACKED_EVENT_COUNT) 51 52 #define I915_ENGINE_SAMPLE_COUNT (I915_SAMPLE_SEMA + 1) 53 54 struct i915_pmu_sample { 55 u64 cur; 56 }; 57 58 struct i915_pmu { 59 /** 60 * @base: PMU base. 61 */ 62 struct pmu base; 63 /** 64 * @registered: PMU is registered and not in the unregistering process. 65 */ 66 bool registered; 67 /** 68 * @name: Name as registered with perf core. 69 */ 70 const char *name; 71 /** 72 * @lock: Lock protecting enable mask and ref count handling. 73 */ 74 spinlock_t lock; 75 /** 76 * @unparked: GT unparked mask. 77 */ 78 unsigned int unparked; 79 /** 80 * @timer: Timer for internal i915 PMU sampling. 81 */ 82 struct hrtimer timer; 83 /** 84 * @enable: Bitmask of specific enabled events. 85 * 86 * For some events we need to track their state and do some internal 87 * house keeping. 88 * 89 * Each engine event sampler type and event listed in enum 90 * i915_pmu_tracked_events gets a bit in this field. 91 * 92 * Low bits are engine samplers and other events continue from there. 93 */ 94 u32 enable; 95 96 /** 97 * @timer_last: 98 * 99 * Timestamp of the previous timer invocation. 100 */ 101 ktime_t timer_last; 102 103 /** 104 * @enable_count: Reference counts for the enabled events. 105 * 106 * Array indices are mapped in the same way as bits in the @enable field 107 * and they are used to control sampling on/off when multiple clients 108 * are using the PMU API. 109 */ 110 unsigned int enable_count[I915_PMU_MASK_BITS]; 111 /** 112 * @timer_enabled: Should the internal sampling timer be running. 113 */ 114 bool timer_enabled; 115 /** 116 * @sample: Current and previous (raw) counters for sampling events. 117 * 118 * These counters are updated from the i915 PMU sampling timer. 119 * 120 * Only global counters are held here, while the per-engine ones are in 121 * struct intel_engine_cs. 122 */ 123 struct i915_pmu_sample sample[I915_PMU_MAX_GT][__I915_NUM_PMU_SAMPLERS]; 124 /** 125 * @sleep_last: Last time GT parked for RC6 estimation. 126 */ 127 ktime_t sleep_last[I915_PMU_MAX_GT]; 128 /** 129 * @irq_count: Number of interrupts 130 * 131 * Intentionally unsigned long to avoid atomics or heuristics on 32bit. 132 * 4e9 interrupts are a lot and postprocessing can really deal with an 133 * occasional wraparound easily. It's 32bit after all. 134 */ 135 unsigned long irq_count; 136 /** 137 * @events_attr_group: Device events attribute group. 138 */ 139 struct attribute_group events_attr_group; 140 /** 141 * @i915_attr: Memory block holding device attributes. 142 */ 143 void *i915_attr; 144 /** 145 * @pmu_attr: Memory block holding device attributes. 146 */ 147 void *pmu_attr; 148 }; 149 150 #ifdef CONFIG_PERF_EVENTS 151 void i915_pmu_register(struct drm_i915_private *i915); 152 void i915_pmu_unregister(struct drm_i915_private *i915); 153 void i915_pmu_gt_parked(struct intel_gt *gt); 154 void i915_pmu_gt_unparked(struct intel_gt *gt); 155 #else 156 static inline void i915_pmu_register(struct drm_i915_private *i915) {} 157 static inline void i915_pmu_unregister(struct drm_i915_private *i915) {} 158 static inline void i915_pmu_gt_parked(struct intel_gt *gt) {} 159 static inline void i915_pmu_gt_unparked(struct intel_gt *gt) {} 160 #endif 161 162 #endif 163