1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2023 Meta Platforms, Inc. and affiliates 4 * Copyright (c) 2023 Intel and affiliates 5 */ 6 7 #ifndef __DPLL_H__ 8 #define __DPLL_H__ 9 10 #include <uapi/linux/dpll.h> 11 #include <linux/device.h> 12 #include <linux/netlink.h> 13 #include <linux/netdevice.h> 14 #include <linux/notifier.h> 15 #include <linux/rtnetlink.h> 16 #include <net/netlink.h> 17 18 struct dpll_device; 19 struct dpll_pin; 20 struct dpll_pin_esync; 21 struct fwnode_handle; 22 struct ref_tracker; 23 24 struct dpll_device_ops { 25 int (*mode_get)(const struct dpll_device *dpll, void *dpll_priv, 26 enum dpll_mode *mode, struct netlink_ext_ack *extack); 27 int (*mode_set)(const struct dpll_device *dpll, void *dpll_priv, 28 enum dpll_mode mode, struct netlink_ext_ack *extack); 29 int (*supported_modes_get)(const struct dpll_device *dpll, 30 void *dpll_priv, unsigned long *modes, 31 struct netlink_ext_ack *extack); 32 int (*lock_status_get)(const struct dpll_device *dpll, void *dpll_priv, 33 enum dpll_lock_status *status, 34 enum dpll_lock_status_error *status_error, 35 struct netlink_ext_ack *extack); 36 int (*temp_get)(const struct dpll_device *dpll, void *dpll_priv, 37 s32 *temp, struct netlink_ext_ack *extack); 38 int (*clock_quality_level_get)(const struct dpll_device *dpll, 39 void *dpll_priv, 40 unsigned long *qls, 41 struct netlink_ext_ack *extack); 42 int (*phase_offset_monitor_set)(const struct dpll_device *dpll, 43 void *dpll_priv, 44 enum dpll_feature_state state, 45 struct netlink_ext_ack *extack); 46 int (*phase_offset_monitor_get)(const struct dpll_device *dpll, 47 void *dpll_priv, 48 enum dpll_feature_state *state, 49 struct netlink_ext_ack *extack); 50 int (*phase_offset_avg_factor_set)(const struct dpll_device *dpll, 51 void *dpll_priv, u32 factor, 52 struct netlink_ext_ack *extack); 53 int (*phase_offset_avg_factor_get)(const struct dpll_device *dpll, 54 void *dpll_priv, u32 *factor, 55 struct netlink_ext_ack *extack); 56 int (*freq_monitor_set)(const struct dpll_device *dpll, void *dpll_priv, 57 enum dpll_feature_state state, 58 struct netlink_ext_ack *extack); 59 int (*freq_monitor_get)(const struct dpll_device *dpll, void *dpll_priv, 60 enum dpll_feature_state *state, 61 struct netlink_ext_ack *extack); 62 }; 63 64 enum dpll_ffo_type { 65 DPLL_FFO_PORT_RXTX_RATE, 66 DPLL_FFO_PIN_DEVICE, 67 68 __DPLL_FFO_TYPE_MAX, 69 }; 70 71 struct dpll_ffo_param { 72 enum dpll_ffo_type type; 73 s64 ffo; 74 }; 75 76 struct dpll_pin_ops { 77 unsigned long supported_ffo; 78 int (*frequency_set)(const struct dpll_pin *pin, void *pin_priv, 79 const struct dpll_device *dpll, void *dpll_priv, 80 const u64 frequency, 81 struct netlink_ext_ack *extack); 82 int (*frequency_get)(const struct dpll_pin *pin, void *pin_priv, 83 const struct dpll_device *dpll, void *dpll_priv, 84 u64 *frequency, struct netlink_ext_ack *extack); 85 int (*direction_set)(const struct dpll_pin *pin, void *pin_priv, 86 const struct dpll_device *dpll, void *dpll_priv, 87 const enum dpll_pin_direction direction, 88 struct netlink_ext_ack *extack); 89 int (*direction_get)(const struct dpll_pin *pin, void *pin_priv, 90 const struct dpll_device *dpll, void *dpll_priv, 91 enum dpll_pin_direction *direction, 92 struct netlink_ext_ack *extack); 93 int (*state_on_pin_get)(const struct dpll_pin *pin, void *pin_priv, 94 const struct dpll_pin *parent_pin, 95 void *parent_pin_priv, 96 enum dpll_pin_state *state, 97 struct netlink_ext_ack *extack); 98 int (*state_on_dpll_get)(const struct dpll_pin *pin, void *pin_priv, 99 const struct dpll_device *dpll, 100 void *dpll_priv, enum dpll_pin_state *state, 101 struct netlink_ext_ack *extack); 102 int (*operstate_on_dpll_get)(const struct dpll_pin *pin, 103 void *pin_priv, 104 const struct dpll_device *dpll, 105 void *dpll_priv, 106 enum dpll_pin_operstate *operstate, 107 struct netlink_ext_ack *extack); 108 int (*state_on_pin_set)(const struct dpll_pin *pin, void *pin_priv, 109 const struct dpll_pin *parent_pin, 110 void *parent_pin_priv, 111 const enum dpll_pin_state state, 112 struct netlink_ext_ack *extack); 113 int (*state_on_dpll_set)(const struct dpll_pin *pin, void *pin_priv, 114 const struct dpll_device *dpll, 115 void *dpll_priv, 116 const enum dpll_pin_state state, 117 struct netlink_ext_ack *extack); 118 int (*prio_get)(const struct dpll_pin *pin, void *pin_priv, 119 const struct dpll_device *dpll, void *dpll_priv, 120 u32 *prio, struct netlink_ext_ack *extack); 121 int (*prio_set)(const struct dpll_pin *pin, void *pin_priv, 122 const struct dpll_device *dpll, void *dpll_priv, 123 const u32 prio, struct netlink_ext_ack *extack); 124 int (*phase_offset_get)(const struct dpll_pin *pin, void *pin_priv, 125 const struct dpll_device *dpll, void *dpll_priv, 126 s64 *phase_offset, 127 struct netlink_ext_ack *extack); 128 int (*phase_adjust_get)(const struct dpll_pin *pin, void *pin_priv, 129 const struct dpll_device *dpll, void *dpll_priv, 130 s32 *phase_adjust, 131 struct netlink_ext_ack *extack); 132 int (*phase_adjust_set)(const struct dpll_pin *pin, void *pin_priv, 133 const struct dpll_device *dpll, void *dpll_priv, 134 const s32 phase_adjust, 135 struct netlink_ext_ack *extack); 136 int (*ffo_get)(const struct dpll_pin *pin, void *pin_priv, 137 const struct dpll_device *dpll, void *dpll_priv, 138 struct dpll_ffo_param *ffo, 139 struct netlink_ext_ack *extack); 140 int (*measured_freq_get)(const struct dpll_pin *pin, void *pin_priv, 141 const struct dpll_device *dpll, 142 void *dpll_priv, u64 *measured_freq, 143 struct netlink_ext_ack *extack); 144 int (*esync_set)(const struct dpll_pin *pin, void *pin_priv, 145 const struct dpll_device *dpll, void *dpll_priv, 146 u64 freq, struct netlink_ext_ack *extack); 147 int (*esync_get)(const struct dpll_pin *pin, void *pin_priv, 148 const struct dpll_device *dpll, void *dpll_priv, 149 struct dpll_pin_esync *esync, 150 struct netlink_ext_ack *extack); 151 int (*ref_sync_set)(const struct dpll_pin *pin, void *pin_priv, 152 const struct dpll_pin *ref_sync_pin, 153 void *ref_sync_pin_priv, 154 const enum dpll_pin_state state, 155 struct netlink_ext_ack *extack); 156 int (*ref_sync_get)(const struct dpll_pin *pin, void *pin_priv, 157 const struct dpll_pin *ref_sync_pin, 158 void *ref_sync_pin_priv, 159 enum dpll_pin_state *state, 160 struct netlink_ext_ack *extack); 161 }; 162 163 struct dpll_pin_frequency { 164 u64 min; 165 u64 max; 166 }; 167 168 #define DPLL_PIN_FREQUENCY_RANGE(_min, _max) \ 169 { \ 170 .min = _min, \ 171 .max = _max, \ 172 } 173 174 #define DPLL_PIN_FREQUENCY(_val) DPLL_PIN_FREQUENCY_RANGE(_val, _val) 175 #define DPLL_PIN_FREQUENCY_1PPS \ 176 DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_1_HZ) 177 #define DPLL_PIN_FREQUENCY_10MHZ \ 178 DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_10_MHZ) 179 #define DPLL_PIN_FREQUENCY_IRIG_B \ 180 DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_10_KHZ) 181 #define DPLL_PIN_FREQUENCY_DCF77 \ 182 DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_77_5_KHZ) 183 184 struct dpll_pin_phase_adjust_range { 185 s32 min; 186 s32 max; 187 }; 188 189 struct dpll_pin_esync { 190 u64 freq; 191 const struct dpll_pin_frequency *range; 192 u8 range_num; 193 u8 pulse; 194 }; 195 196 struct dpll_pin_properties { 197 const char *board_label; 198 const char *panel_label; 199 const char *package_label; 200 enum dpll_pin_type type; 201 unsigned long capabilities; 202 u32 freq_supported_num; 203 struct dpll_pin_frequency *freq_supported; 204 struct dpll_pin_phase_adjust_range phase_range; 205 u32 phase_gran; 206 }; 207 208 #ifdef CONFIG_DPLL_REFCNT_TRACKER 209 typedef struct ref_tracker *dpll_tracker; 210 #else 211 typedef struct {} dpll_tracker; 212 #endif 213 214 #define DPLL_DEVICE_CREATED 1 215 #define DPLL_DEVICE_DELETED 2 216 #define DPLL_DEVICE_CHANGED 3 217 #define DPLL_PIN_CREATED 4 218 #define DPLL_PIN_DELETED 5 219 #define DPLL_PIN_CHANGED 6 220 221 struct dpll_device_notifier_info { 222 struct dpll_device *dpll; 223 u32 id; 224 u32 idx; 225 u64 clock_id; 226 enum dpll_type type; 227 }; 228 229 struct dpll_pin_notifier_info { 230 struct dpll_pin *pin; 231 u32 id; 232 u32 idx; 233 u64 clock_id; 234 const struct fwnode_handle *fwnode; 235 const struct dpll_pin_properties *prop; 236 u64 src_clock_id; 237 }; 238 239 #if IS_ENABLED(CONFIG_DPLL) 240 void dpll_netdev_pin_set(struct net_device *dev, struct dpll_pin *dpll_pin); 241 void dpll_netdev_pin_clear(struct net_device *dev); 242 243 static inline size_t dpll_netdev_pin_handle_size(void) 244 { 245 return nla_total_size(4); /* DPLL_A_PIN_ID */ 246 } 247 248 int dpll_netdev_add_pin_handle(struct sk_buff *msg, 249 const struct net_device *dev); 250 251 struct dpll_pin *fwnode_dpll_pin_find(struct fwnode_handle *fwnode, 252 dpll_tracker *tracker); 253 #else 254 static inline void 255 dpll_netdev_pin_set(struct net_device *dev, struct dpll_pin *dpll_pin) { } 256 static inline void dpll_netdev_pin_clear(struct net_device *dev) { } 257 258 static inline size_t dpll_netdev_pin_handle_size(void) 259 { 260 return 0; 261 } 262 263 static inline int 264 dpll_netdev_add_pin_handle(struct sk_buff *msg, const struct net_device *dev) 265 { 266 return 0; 267 } 268 269 static inline struct dpll_pin * 270 fwnode_dpll_pin_find(struct fwnode_handle *fwnode, dpll_tracker *tracker) 271 { 272 return NULL; 273 } 274 #endif 275 276 struct dpll_device * 277 dpll_device_get(u64 clock_id, u32 dev_driver_id, struct module *module, 278 dpll_tracker *tracker); 279 280 void dpll_device_put(struct dpll_device *dpll, dpll_tracker *tracker); 281 282 int dpll_device_register(struct dpll_device *dpll, enum dpll_type type, 283 const struct dpll_device_ops *ops, void *priv); 284 285 void dpll_device_unregister(struct dpll_device *dpll, 286 const struct dpll_device_ops *ops, void *priv); 287 288 #define DPLL_PIN_IDX_UNSPEC U32_MAX 289 290 struct dpll_pin * 291 dpll_pin_get(u64 clock_id, u32 dev_driver_id, struct module *module, 292 const struct dpll_pin_properties *prop, dpll_tracker *tracker); 293 294 int dpll_pin_register(struct dpll_device *dpll, struct dpll_pin *pin, 295 const struct dpll_pin_ops *ops, void *priv); 296 297 void dpll_pin_unregister(struct dpll_device *dpll, struct dpll_pin *pin, 298 const struct dpll_pin_ops *ops, void *priv); 299 300 void dpll_pin_put(struct dpll_pin *pin, dpll_tracker *tracker); 301 302 void dpll_pin_fwnode_set(struct dpll_pin *pin, struct fwnode_handle *fwnode); 303 304 int dpll_pin_on_pin_register(struct dpll_pin *parent, struct dpll_pin *pin, 305 const struct dpll_pin_ops *ops, void *priv); 306 307 void dpll_pin_on_pin_unregister(struct dpll_pin *parent, struct dpll_pin *pin, 308 const struct dpll_pin_ops *ops, void *priv); 309 310 int dpll_pin_ref_sync_pair_add(struct dpll_pin *pin, 311 struct dpll_pin *ref_sync_pin); 312 313 int __dpll_device_change_ntf(struct dpll_device *dpll); 314 int dpll_device_change_ntf(struct dpll_device *dpll); 315 316 int __dpll_pin_change_ntf(struct dpll_pin *pin); 317 int dpll_pin_change_ntf(struct dpll_pin *pin); 318 319 int register_dpll_notifier(struct notifier_block *nb); 320 321 int unregister_dpll_notifier(struct notifier_block *nb); 322 323 #endif 324