1 /* SPDX-License-Identifier: GPL-2.0 */
2
3 #ifndef _ASM_X86_NOSPEC_BRANCH_H_
4 #define _ASM_X86_NOSPEC_BRANCH_H_
5
6 #include <linux/static_key.h>
7 #include <linux/objtool.h>
8 #include <linux/linkage.h>
9
10 #include <asm/alternative.h>
11 #include <asm/cpufeatures.h>
12 #include <asm/msr-index.h>
13 #include <asm/unwind_hints.h>
14 #include <asm/percpu.h>
15 #include <asm/current.h>
16
17 /*
18 * Call depth tracking for Intel SKL CPUs to address the RSB underflow
19 * issue in software.
20 *
21 * The tracking does not use a counter. It uses uses arithmetic shift
22 * right on call entry and logical shift left on return.
23 *
24 * The depth tracking variable is initialized to 0x8000.... when the call
25 * depth is zero. The arithmetic shift right sign extends the MSB and
26 * saturates after the 12th call. The shift count is 5 for both directions
27 * so the tracking covers 12 nested calls.
28 *
29 * Call
30 * 0: 0x8000000000000000 0x0000000000000000
31 * 1: 0xfc00000000000000 0xf000000000000000
32 * ...
33 * 11: 0xfffffffffffffff8 0xfffffffffffffc00
34 * 12: 0xffffffffffffffff 0xffffffffffffffe0
35 *
36 * After a return buffer fill the depth is credited 12 calls before the
37 * next stuffing has to take place.
38 *
39 * There is a inaccuracy for situations like this:
40 *
41 * 10 calls
42 * 5 returns
43 * 3 calls
44 * 4 returns
45 * 3 calls
46 * ....
47 *
48 * The shift count might cause this to be off by one in either direction,
49 * but there is still a cushion vs. the RSB depth. The algorithm does not
50 * claim to be perfect and it can be speculated around by the CPU, but it
51 * is considered that it obfuscates the problem enough to make exploitation
52 * extremely difficult.
53 */
54 #define RET_DEPTH_SHIFT 5
55 #define RSB_RET_STUFF_LOOPS 16
56 #define RET_DEPTH_INIT 0x8000000000000000ULL
57 #define RET_DEPTH_INIT_FROM_CALL 0xfc00000000000000ULL
58 #define RET_DEPTH_CREDIT 0xffffffffffffffffULL
59
60 #ifdef CONFIG_CALL_THUNKS_DEBUG
61 # define CALL_THUNKS_DEBUG_INC_CALLS \
62 incq PER_CPU_VAR(__x86_call_count);
63 # define CALL_THUNKS_DEBUG_INC_RETS \
64 incq PER_CPU_VAR(__x86_ret_count);
65 # define CALL_THUNKS_DEBUG_INC_STUFFS \
66 incq PER_CPU_VAR(__x86_stuffs_count);
67 # define CALL_THUNKS_DEBUG_INC_CTXSW \
68 incq PER_CPU_VAR(__x86_ctxsw_count);
69 #else
70 # define CALL_THUNKS_DEBUG_INC_CALLS
71 # define CALL_THUNKS_DEBUG_INC_RETS
72 # define CALL_THUNKS_DEBUG_INC_STUFFS
73 # define CALL_THUNKS_DEBUG_INC_CTXSW
74 #endif
75
76 #if defined(CONFIG_MITIGATION_CALL_DEPTH_TRACKING) && !defined(COMPILE_OFFSETS)
77
78 #include <asm/asm-offsets.h>
79
80 #define CREDIT_CALL_DEPTH \
81 movq $-1, PER_CPU_VAR(pcpu_hot + X86_call_depth);
82
83 #define RESET_CALL_DEPTH \
84 xor %eax, %eax; \
85 bts $63, %rax; \
86 movq %rax, PER_CPU_VAR(pcpu_hot + X86_call_depth);
87
88 #define RESET_CALL_DEPTH_FROM_CALL \
89 movb $0xfc, %al; \
90 shl $56, %rax; \
91 movq %rax, PER_CPU_VAR(pcpu_hot + X86_call_depth); \
92 CALL_THUNKS_DEBUG_INC_CALLS
93
94 #define INCREMENT_CALL_DEPTH \
95 sarq $5, PER_CPU_VAR(pcpu_hot + X86_call_depth); \
96 CALL_THUNKS_DEBUG_INC_CALLS
97
98 #else
99 #define CREDIT_CALL_DEPTH
100 #define RESET_CALL_DEPTH
101 #define RESET_CALL_DEPTH_FROM_CALL
102 #define INCREMENT_CALL_DEPTH
103 #endif
104
105 /*
106 * Fill the CPU return stack buffer.
107 *
108 * Each entry in the RSB, if used for a speculative 'ret', contains an
109 * infinite 'pause; lfence; jmp' loop to capture speculative execution.
110 *
111 * This is required in various cases for retpoline and IBRS-based
112 * mitigations for the Spectre variant 2 vulnerability. Sometimes to
113 * eliminate potentially bogus entries from the RSB, and sometimes
114 * purely to ensure that it doesn't get empty, which on some CPUs would
115 * allow predictions from other (unwanted!) sources to be used.
116 *
117 * We define a CPP macro such that it can be used from both .S files and
118 * inline assembly. It's possible to do a .macro and then include that
119 * from C via asm(".include <asm/nospec-branch.h>") but let's not go there.
120 */
121
122 #define RETPOLINE_THUNK_SIZE 32
123 #define RSB_CLEAR_LOOPS 32 /* To forcibly overwrite all entries */
124
125 /*
126 * Common helper for __FILL_RETURN_BUFFER and __FILL_ONE_RETURN.
127 */
128 #define __FILL_RETURN_SLOT \
129 ANNOTATE_INTRA_FUNCTION_CALL; \
130 call 772f; \
131 int3; \
132 772:
133
134 /*
135 * Stuff the entire RSB.
136 *
137 * Google experimented with loop-unrolling and this turned out to be
138 * the optimal version - two calls, each with their own speculation
139 * trap should their return address end up getting used, in a loop.
140 */
141 #ifdef CONFIG_X86_64
142 #define __FILL_RETURN_BUFFER(reg, nr) \
143 mov $(nr/2), reg; \
144 771: \
145 __FILL_RETURN_SLOT \
146 __FILL_RETURN_SLOT \
147 add $(BITS_PER_LONG/8) * 2, %_ASM_SP; \
148 dec reg; \
149 jnz 771b; \
150 /* barrier for jnz misprediction */ \
151 lfence; \
152 CREDIT_CALL_DEPTH \
153 CALL_THUNKS_DEBUG_INC_CTXSW
154 #else
155 /*
156 * i386 doesn't unconditionally have LFENCE, as such it can't
157 * do a loop.
158 */
159 #define __FILL_RETURN_BUFFER(reg, nr) \
160 .rept nr; \
161 __FILL_RETURN_SLOT; \
162 .endr; \
163 add $(BITS_PER_LONG/8) * nr, %_ASM_SP;
164 #endif
165
166 /*
167 * Stuff a single RSB slot.
168 *
169 * To mitigate Post-Barrier RSB speculation, one CALL instruction must be
170 * forced to retire before letting a RET instruction execute.
171 *
172 * On PBRSB-vulnerable CPUs, it is not safe for a RET to be executed
173 * before this point.
174 */
175 #define __FILL_ONE_RETURN \
176 __FILL_RETURN_SLOT \
177 add $(BITS_PER_LONG/8), %_ASM_SP; \
178 lfence;
179
180 #ifdef __ASSEMBLY__
181
182 /*
183 * (ab)use RETPOLINE_SAFE on RET to annotate away 'bare' RET instructions
184 * vs RETBleed validation.
185 */
186 #define ANNOTATE_UNRET_SAFE ANNOTATE_RETPOLINE_SAFE
187
188 /*
189 * Abuse ANNOTATE_RETPOLINE_SAFE on a NOP to indicate UNRET_END, should
190 * eventually turn into its own annotation.
191 */
192 .macro VALIDATE_UNRET_END
193 #if defined(CONFIG_NOINSTR_VALIDATION) && \
194 (defined(CONFIG_MITIGATION_UNRET_ENTRY) || defined(CONFIG_MITIGATION_SRSO))
195 ANNOTATE_RETPOLINE_SAFE
196 nop
197 #endif
198 .endm
199
200 /*
201 * Emits a conditional CS prefix that is compatible with
202 * -mindirect-branch-cs-prefix.
203 */
204 .macro __CS_PREFIX reg:req
205 .irp rs,r8,r9,r10,r11,r12,r13,r14,r15
206 .ifc \reg,\rs
207 .byte 0x2e
208 .endif
209 .endr
210 .endm
211
212 /*
213 * JMP_NOSPEC and CALL_NOSPEC macros can be used instead of a simple
214 * indirect jmp/call which may be susceptible to the Spectre variant 2
215 * attack.
216 *
217 * NOTE: these do not take kCFI into account and are thus not comparable to C
218 * indirect calls, take care when using. The target of these should be an ENDBR
219 * instruction irrespective of kCFI.
220 */
221 .macro JMP_NOSPEC reg:req
222 #ifdef CONFIG_MITIGATION_RETPOLINE
223 __CS_PREFIX \reg
224 jmp __x86_indirect_thunk_\reg
225 #else
226 jmp *%\reg
227 int3
228 #endif
229 .endm
230
231 .macro CALL_NOSPEC reg:req
232 #ifdef CONFIG_MITIGATION_RETPOLINE
233 __CS_PREFIX \reg
234 call __x86_indirect_thunk_\reg
235 #else
236 call *%\reg
237 #endif
238 .endm
239
240 /*
241 * A simpler FILL_RETURN_BUFFER macro. Don't make people use the CPP
242 * monstrosity above, manually.
243 */
244 .macro FILL_RETURN_BUFFER reg:req nr:req ftr:req ftr2=ALT_NOT(X86_FEATURE_ALWAYS)
245 ALTERNATIVE_2 "jmp .Lskip_rsb_\@", \
246 __stringify(__FILL_RETURN_BUFFER(\reg,\nr)), \ftr, \
247 __stringify(nop;nop;__FILL_ONE_RETURN), \ftr2
248
249 .Lskip_rsb_\@:
250 .endm
251
252 /*
253 * The CALL to srso_alias_untrain_ret() must be patched in directly at
254 * the spot where untraining must be done, ie., srso_alias_untrain_ret()
255 * must be the target of a CALL instruction instead of indirectly
256 * jumping to a wrapper which then calls it. Therefore, this macro is
257 * called outside of __UNTRAIN_RET below, for the time being, before the
258 * kernel can support nested alternatives with arbitrary nesting.
259 */
260 .macro CALL_UNTRAIN_RET
261 #if defined(CONFIG_MITIGATION_UNRET_ENTRY) || defined(CONFIG_MITIGATION_SRSO)
262 ALTERNATIVE_2 "", "call entry_untrain_ret", X86_FEATURE_UNRET, \
263 "call srso_alias_untrain_ret", X86_FEATURE_SRSO_ALIAS
264 #endif
265 .endm
266
267 /*
268 * Mitigate RETBleed for AMD/Hygon Zen uarch. Requires KERNEL CR3 because the
269 * return thunk isn't mapped into the userspace tables (then again, AMD
270 * typically has NO_MELTDOWN).
271 *
272 * While retbleed_untrain_ret() doesn't clobber anything but requires stack,
273 * entry_ibpb() will clobber AX, CX, DX.
274 *
275 * As such, this must be placed after every *SWITCH_TO_KERNEL_CR3 at a point
276 * where we have a stack but before any RET instruction.
277 */
278 .macro __UNTRAIN_RET ibpb_feature, call_depth_insns
279 #if defined(CONFIG_MITIGATION_RETHUNK) || defined(CONFIG_MITIGATION_IBPB_ENTRY)
280 VALIDATE_UNRET_END
281 CALL_UNTRAIN_RET
282 ALTERNATIVE_2 "", \
283 "call entry_ibpb", \ibpb_feature, \
284 __stringify(\call_depth_insns), X86_FEATURE_CALL_DEPTH
285 #endif
286 .endm
287
288 #define UNTRAIN_RET \
289 __UNTRAIN_RET X86_FEATURE_ENTRY_IBPB, __stringify(RESET_CALL_DEPTH)
290
291 #define UNTRAIN_RET_VM \
292 __UNTRAIN_RET X86_FEATURE_IBPB_ON_VMEXIT, __stringify(RESET_CALL_DEPTH)
293
294 #define UNTRAIN_RET_FROM_CALL \
295 __UNTRAIN_RET X86_FEATURE_ENTRY_IBPB, __stringify(RESET_CALL_DEPTH_FROM_CALL)
296
297
298 .macro CALL_DEPTH_ACCOUNT
299 #ifdef CONFIG_MITIGATION_CALL_DEPTH_TRACKING
300 ALTERNATIVE "", \
301 __stringify(INCREMENT_CALL_DEPTH), X86_FEATURE_CALL_DEPTH
302 #endif
303 .endm
304
305 /*
306 * Macro to execute VERW instruction that mitigate transient data sampling
307 * attacks such as MDS. On affected systems a microcode update overloaded VERW
308 * instruction to also clear the CPU buffers. VERW clobbers CFLAGS.ZF.
309 *
310 * Note: Only the memory operand variant of VERW clears the CPU buffers.
311 */
312 .macro CLEAR_CPU_BUFFERS
313 #ifdef CONFIG_X86_64
314 ALTERNATIVE "", "verw mds_verw_sel(%rip)", X86_FEATURE_CLEAR_CPU_BUF
315 #else
316 /*
317 * In 32bit mode, the memory operand must be a %cs reference. The data
318 * segments may not be usable (vm86 mode), and the stack segment may not
319 * be flat (ESPFIX32).
320 */
321 ALTERNATIVE "", "verw %cs:mds_verw_sel", X86_FEATURE_CLEAR_CPU_BUF
322 #endif
323 .endm
324
325 #ifdef CONFIG_X86_64
326 .macro CLEAR_BRANCH_HISTORY
327 ALTERNATIVE "", "call clear_bhb_loop", X86_FEATURE_CLEAR_BHB_LOOP
328 .endm
329
330 .macro CLEAR_BRANCH_HISTORY_VMEXIT
331 ALTERNATIVE "", "call clear_bhb_loop", X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT
332 .endm
333 #else
334 #define CLEAR_BRANCH_HISTORY
335 #define CLEAR_BRANCH_HISTORY_VMEXIT
336 #endif
337
338 #else /* __ASSEMBLY__ */
339
340 typedef u8 retpoline_thunk_t[RETPOLINE_THUNK_SIZE];
341 extern retpoline_thunk_t __x86_indirect_thunk_array[];
342 extern retpoline_thunk_t __x86_indirect_call_thunk_array[];
343 extern retpoline_thunk_t __x86_indirect_jump_thunk_array[];
344
345 #ifdef CONFIG_MITIGATION_RETHUNK
346 extern void __x86_return_thunk(void);
347 #else
__x86_return_thunk(void)348 static inline void __x86_return_thunk(void) {}
349 #endif
350
351 #ifdef CONFIG_MITIGATION_UNRET_ENTRY
352 extern void retbleed_return_thunk(void);
353 #else
retbleed_return_thunk(void)354 static inline void retbleed_return_thunk(void) {}
355 #endif
356
357 extern void srso_alias_untrain_ret(void);
358
359 #ifdef CONFIG_MITIGATION_SRSO
360 extern void srso_return_thunk(void);
361 extern void srso_alias_return_thunk(void);
362 #else
srso_return_thunk(void)363 static inline void srso_return_thunk(void) {}
srso_alias_return_thunk(void)364 static inline void srso_alias_return_thunk(void) {}
365 #endif
366
367 extern void retbleed_return_thunk(void);
368 extern void srso_return_thunk(void);
369 extern void srso_alias_return_thunk(void);
370
371 extern void entry_untrain_ret(void);
372 extern void entry_ibpb(void);
373
374 #ifdef CONFIG_X86_64
375 extern void clear_bhb_loop(void);
376 #endif
377
378 extern void (*x86_return_thunk)(void);
379
380 extern void __warn_thunk(void);
381
382 #ifdef CONFIG_MITIGATION_CALL_DEPTH_TRACKING
383 extern void call_depth_return_thunk(void);
384
385 #define CALL_DEPTH_ACCOUNT \
386 ALTERNATIVE("", \
387 __stringify(INCREMENT_CALL_DEPTH), \
388 X86_FEATURE_CALL_DEPTH)
389
390 #ifdef CONFIG_CALL_THUNKS_DEBUG
391 DECLARE_PER_CPU(u64, __x86_call_count);
392 DECLARE_PER_CPU(u64, __x86_ret_count);
393 DECLARE_PER_CPU(u64, __x86_stuffs_count);
394 DECLARE_PER_CPU(u64, __x86_ctxsw_count);
395 #endif
396 #else /* !CONFIG_MITIGATION_CALL_DEPTH_TRACKING */
397
call_depth_return_thunk(void)398 static inline void call_depth_return_thunk(void) {}
399 #define CALL_DEPTH_ACCOUNT ""
400
401 #endif /* CONFIG_MITIGATION_CALL_DEPTH_TRACKING */
402
403 #ifdef CONFIG_MITIGATION_RETPOLINE
404
405 #define GEN(reg) \
406 extern retpoline_thunk_t __x86_indirect_thunk_ ## reg;
407 #include <asm/GEN-for-each-reg.h>
408 #undef GEN
409
410 #define GEN(reg) \
411 extern retpoline_thunk_t __x86_indirect_call_thunk_ ## reg;
412 #include <asm/GEN-for-each-reg.h>
413 #undef GEN
414
415 #define GEN(reg) \
416 extern retpoline_thunk_t __x86_indirect_jump_thunk_ ## reg;
417 #include <asm/GEN-for-each-reg.h>
418 #undef GEN
419
420 #ifdef CONFIG_X86_64
421
422 /*
423 * Emits a conditional CS prefix that is compatible with
424 * -mindirect-branch-cs-prefix.
425 */
426 #define __CS_PREFIX(reg) \
427 ".irp rs,r8,r9,r10,r11,r12,r13,r14,r15\n" \
428 ".ifc \\rs," reg "\n" \
429 ".byte 0x2e\n" \
430 ".endif\n" \
431 ".endr\n"
432
433 /*
434 * Inline asm uses the %V modifier which is only in newer GCC
435 * which is ensured when CONFIG_MITIGATION_RETPOLINE is defined.
436 */
437 #ifdef CONFIG_MITIGATION_RETPOLINE
438 #define CALL_NOSPEC __CS_PREFIX("%V[thunk_target]") \
439 "call __x86_indirect_thunk_%V[thunk_target]\n"
440 #else
441 #define CALL_NOSPEC "call *%[thunk_target]\n"
442 #endif
443
444 # define THUNK_TARGET(addr) [thunk_target] "r" (addr)
445
446 #else /* CONFIG_X86_32 */
447 /*
448 * For i386 we use the original ret-equivalent retpoline, because
449 * otherwise we'll run out of registers. We don't care about CET
450 * here, anyway.
451 */
452 # define CALL_NOSPEC \
453 ALTERNATIVE_2( \
454 ANNOTATE_RETPOLINE_SAFE \
455 "call *%[thunk_target]\n", \
456 " jmp 904f;\n" \
457 " .align 16\n" \
458 "901: call 903f;\n" \
459 "902: pause;\n" \
460 " lfence;\n" \
461 " jmp 902b;\n" \
462 " .align 16\n" \
463 "903: lea 4(%%esp), %%esp;\n" \
464 " pushl %[thunk_target];\n" \
465 " ret;\n" \
466 " .align 16\n" \
467 "904: call 901b;\n", \
468 X86_FEATURE_RETPOLINE, \
469 "lfence;\n" \
470 ANNOTATE_RETPOLINE_SAFE \
471 "call *%[thunk_target]\n", \
472 X86_FEATURE_RETPOLINE_LFENCE)
473
474 # define THUNK_TARGET(addr) [thunk_target] "rm" (addr)
475 #endif
476 #else /* No retpoline for C / inline asm */
477 # define CALL_NOSPEC "call *%[thunk_target]\n"
478 # define THUNK_TARGET(addr) [thunk_target] "rm" (addr)
479 #endif
480
481 /* The Spectre V2 mitigation variants */
482 enum spectre_v2_mitigation {
483 SPECTRE_V2_NONE,
484 SPECTRE_V2_RETPOLINE,
485 SPECTRE_V2_LFENCE,
486 SPECTRE_V2_EIBRS,
487 SPECTRE_V2_EIBRS_RETPOLINE,
488 SPECTRE_V2_EIBRS_LFENCE,
489 SPECTRE_V2_IBRS,
490 };
491
492 /* The indirect branch speculation control variants */
493 enum spectre_v2_user_mitigation {
494 SPECTRE_V2_USER_NONE,
495 SPECTRE_V2_USER_STRICT,
496 SPECTRE_V2_USER_STRICT_PREFERRED,
497 SPECTRE_V2_USER_PRCTL,
498 SPECTRE_V2_USER_SECCOMP,
499 };
500
501 /* The Speculative Store Bypass disable variants */
502 enum ssb_mitigation {
503 SPEC_STORE_BYPASS_NONE,
504 SPEC_STORE_BYPASS_DISABLE,
505 SPEC_STORE_BYPASS_PRCTL,
506 SPEC_STORE_BYPASS_SECCOMP,
507 };
508
509 static __always_inline
alternative_msr_write(unsigned int msr,u64 val,unsigned int feature)510 void alternative_msr_write(unsigned int msr, u64 val, unsigned int feature)
511 {
512 asm volatile(ALTERNATIVE("", "wrmsr", %c[feature])
513 : : "c" (msr),
514 "a" ((u32)val),
515 "d" ((u32)(val >> 32)),
516 [feature] "i" (feature)
517 : "memory");
518 }
519
520 extern u64 x86_pred_cmd;
521
indirect_branch_prediction_barrier(void)522 static inline void indirect_branch_prediction_barrier(void)
523 {
524 alternative_msr_write(MSR_IA32_PRED_CMD, x86_pred_cmd, X86_FEATURE_USE_IBPB);
525 }
526
527 /* The Intel SPEC CTRL MSR base value cache */
528 extern u64 x86_spec_ctrl_base;
529 DECLARE_PER_CPU(u64, x86_spec_ctrl_current);
530 extern void update_spec_ctrl_cond(u64 val);
531 extern u64 spec_ctrl_current(void);
532
533 /*
534 * With retpoline, we must use IBRS to restrict branch prediction
535 * before calling into firmware.
536 *
537 * (Implemented as CPP macros due to header hell.)
538 */
539 #define firmware_restrict_branch_speculation_start() \
540 do { \
541 preempt_disable(); \
542 alternative_msr_write(MSR_IA32_SPEC_CTRL, \
543 spec_ctrl_current() | SPEC_CTRL_IBRS, \
544 X86_FEATURE_USE_IBRS_FW); \
545 alternative_msr_write(MSR_IA32_PRED_CMD, PRED_CMD_IBPB, \
546 X86_FEATURE_USE_IBPB_FW); \
547 } while (0)
548
549 #define firmware_restrict_branch_speculation_end() \
550 do { \
551 alternative_msr_write(MSR_IA32_SPEC_CTRL, \
552 spec_ctrl_current(), \
553 X86_FEATURE_USE_IBRS_FW); \
554 preempt_enable(); \
555 } while (0)
556
557 DECLARE_STATIC_KEY_FALSE(switch_to_cond_stibp);
558 DECLARE_STATIC_KEY_FALSE(switch_mm_cond_ibpb);
559 DECLARE_STATIC_KEY_FALSE(switch_mm_always_ibpb);
560
561 DECLARE_STATIC_KEY_FALSE(mds_idle_clear);
562
563 DECLARE_STATIC_KEY_FALSE(switch_mm_cond_l1d_flush);
564
565 DECLARE_STATIC_KEY_FALSE(mmio_stale_data_clear);
566
567 extern u16 mds_verw_sel;
568
569 #include <asm/segment.h>
570
571 /**
572 * mds_clear_cpu_buffers - Mitigation for MDS and TAA vulnerability
573 *
574 * This uses the otherwise unused and obsolete VERW instruction in
575 * combination with microcode which triggers a CPU buffer flush when the
576 * instruction is executed.
577 */
mds_clear_cpu_buffers(void)578 static __always_inline void mds_clear_cpu_buffers(void)
579 {
580 static const u16 ds = __KERNEL_DS;
581
582 /*
583 * Has to be the memory-operand variant because only that
584 * guarantees the CPU buffer flush functionality according to
585 * documentation. The register-operand variant does not.
586 * Works with any segment selector, but a valid writable
587 * data segment is the fastest variant.
588 *
589 * "cc" clobber is required because VERW modifies ZF.
590 */
591 asm volatile("verw %[ds]" : : [ds] "m" (ds) : "cc");
592 }
593
594 /**
595 * mds_idle_clear_cpu_buffers - Mitigation for MDS vulnerability
596 *
597 * Clear CPU buffers if the corresponding static key is enabled
598 */
mds_idle_clear_cpu_buffers(void)599 static __always_inline void mds_idle_clear_cpu_buffers(void)
600 {
601 if (static_branch_likely(&mds_idle_clear))
602 mds_clear_cpu_buffers();
603 }
604
605 #endif /* __ASSEMBLY__ */
606
607 #endif /* _ASM_X86_NOSPEC_BRANCH_H_ */
608