1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Checksum routines
4 *
5 * Copyright (C) 2023 Rivos Inc.
6 */
7 #ifndef __ASM_RISCV_CHECKSUM_H
8 #define __ASM_RISCV_CHECKSUM_H
9
10 #include <linux/in6.h>
11 #include <linux/uaccess.h>
12
13 #define ip_fast_csum ip_fast_csum
14
15 extern unsigned int do_csum(const unsigned char *buff, int len);
16 #define do_csum do_csum
17
18 /* Default version is sufficient for 32 bit */
19 #ifndef CONFIG_32BIT
20 #define _HAVE_ARCH_IPV6_CSUM
21 __sum16 csum_ipv6_magic(const struct in6_addr *saddr,
22 const struct in6_addr *daddr,
23 __u32 len, __u8 proto, __wsum sum);
24 #endif
25
26 /* Define riscv versions of functions before importing asm-generic/checksum.h */
27 #include <asm-generic/checksum.h>
28
29 /**
30 * Quickly compute an IP checksum with the assumption that IPv4 headers will
31 * always be in multiples of 32-bits, and have an ihl of at least 5.
32 *
33 * @ihl: the number of 32 bit segments and must be greater than or equal to 5.
34 * @iph: assumed to be word aligned given that NET_IP_ALIGN is set to 2 on
35 * riscv, defining IP headers to be aligned.
36 */
ip_fast_csum(const void * iph,unsigned int ihl)37 static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl)
38 {
39 unsigned long csum = 0;
40 int pos = 0;
41
42 do {
43 csum += ((const unsigned int *)iph)[pos];
44 if (IS_ENABLED(CONFIG_32BIT))
45 csum += csum < ((const unsigned int *)iph)[pos];
46 } while (++pos < ihl);
47
48 /*
49 * ZBB only saves three instructions on 32-bit and five on 64-bit so not
50 * worth checking if supported without Alternatives.
51 */
52 if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && IS_ENABLED(CONFIG_TOOLCHAIN_HAS_ZBB)) {
53 unsigned long fold_temp;
54
55 asm goto(ALTERNATIVE("j %l[no_zbb]", "nop", 0,
56 RISCV_ISA_EXT_ZBB, 1)
57 :
58 :
59 :
60 : no_zbb);
61
62 if (IS_ENABLED(CONFIG_32BIT)) {
63 asm(".option push \n\
64 .option arch,+zbb \n\
65 not %[fold_temp], %[csum] \n\
66 rori %[csum], %[csum], 16 \n\
67 sub %[csum], %[fold_temp], %[csum] \n\
68 .option pop"
69 : [csum] "+r" (csum), [fold_temp] "=&r" (fold_temp));
70 } else {
71 asm(".option push \n\
72 .option arch,+zbb \n\
73 rori %[fold_temp], %[csum], 32 \n\
74 add %[csum], %[fold_temp], %[csum] \n\
75 srli %[csum], %[csum], 32 \n\
76 not %[fold_temp], %[csum] \n\
77 roriw %[csum], %[csum], 16 \n\
78 subw %[csum], %[fold_temp], %[csum] \n\
79 .option pop"
80 : [csum] "+r" (csum), [fold_temp] "=&r" (fold_temp));
81 }
82 return (__force __sum16)(csum >> 16);
83 }
84 no_zbb:
85 #ifndef CONFIG_32BIT
86 csum += ror64(csum, 32);
87 csum >>= 32;
88 #endif
89 return csum_fold((__force __wsum)csum);
90 }
91
92 #endif /* __ASM_RISCV_CHECKSUM_H */
93