1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * OpenRISC Linux 4 * 5 * Linux architectural port borrowing liberally from similar works of 6 * others. All original copyrights apply as per the original source 7 * declaration. 8 * 9 * OpenRISC implementation: 10 * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com> 11 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se> 12 * et al. 13 */ 14 15 #ifndef __ASM_OPENRISC_CPUINFO_H 16 #define __ASM_OPENRISC_CPUINFO_H 17 18 #include <asm/spr.h> 19 #include <asm/spr_defs.h> 20 21 struct cache_desc { 22 u32 size; 23 u32 sets; 24 u32 block_size; 25 u32 ways; 26 }; 27 28 struct cpuinfo_or1k { 29 u32 clock_frequency; 30 31 struct cache_desc icache; 32 struct cache_desc dcache; 33 34 u16 coreid; 35 }; 36 37 extern struct cpuinfo_or1k cpuinfo_or1k[NR_CPUS]; 38 extern void setup_cpuinfo(void); 39 40 /* 41 * Check if the cache component exists. 42 */ 43 extern bool cpu_cache_is_present(const unsigned int cache_type); 44 45 #endif /* __ASM_OPENRISC_CPUINFO_H */ 46