1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 */ 6 7 #ifndef __ARM_KVM_INIT_H__ 8 #define __ARM_KVM_INIT_H__ 9 10 #ifndef __ASSEMBLY__ 11 #error Assembly-only header 12 #endif 13 14 #include <asm/kvm_arm.h> 15 #include <asm/ptrace.h> 16 #include <asm/sysreg.h> 17 #include <linux/irqchip/arm-gic-v3.h> 18 19 .macro init_el2_hcr val 20 mov_q x0, \val 21 22 /* 23 * Compliant CPUs advertise their VHE-onlyness with 24 * ID_AA64MMFR4_EL1.E2H0 < 0. On such CPUs HCR_EL2.E2H is RES1, but it 25 * can reset into an UNKNOWN state and might not read as 1 until it has 26 * been initialized explicitly. 27 * 28 * Fruity CPUs seem to have HCR_EL2.E2H set to RAO/WI, but 29 * don't advertise it (they predate this relaxation). 30 * 31 * Initalize HCR_EL2.E2H so that later code can rely upon HCR_EL2.E2H 32 * indicating whether the CPU is running in E2H mode. 33 */ 34 mrs_s x1, SYS_ID_AA64MMFR4_EL1 35 sbfx x1, x1, #ID_AA64MMFR4_EL1_E2H0_SHIFT, #ID_AA64MMFR4_EL1_E2H0_WIDTH 36 cmp x1, #0 37 b.ge .LnVHE_\@ 38 39 orr x0, x0, #HCR_E2H 40 .LnVHE_\@: 41 msr_hcr_el2 x0 42 isb 43 .endm 44 45 .macro __init_el2_sctlr 46 mov_q x0, INIT_SCTLR_EL2_MMU_OFF 47 msr sctlr_el2, x0 48 isb 49 .endm 50 51 .macro __init_el2_hcrx 52 mrs x0, id_aa64mmfr1_el1 53 ubfx x0, x0, #ID_AA64MMFR1_EL1_HCX_SHIFT, #4 54 cbz x0, .Lskip_hcrx_\@ 55 mov_q x0, (HCRX_EL2_MSCEn | HCRX_EL2_TCR2En | HCRX_EL2_EnFPM) 56 57 /* Enable GCS if supported */ 58 mrs_s x1, SYS_ID_AA64PFR1_EL1 59 ubfx x1, x1, #ID_AA64PFR1_EL1_GCS_SHIFT, #4 60 cbz x1, .Lset_hcrx_\@ 61 orr x0, x0, #HCRX_EL2_GCSEn 62 63 .Lset_hcrx_\@: 64 msr_s SYS_HCRX_EL2, x0 65 .Lskip_hcrx_\@: 66 .endm 67 68 /* Check if running in host at EL2 mode, i.e., (h)VHE. Jump to fail if not. */ 69 .macro __check_hvhe fail, tmp 70 mrs \tmp, hcr_el2 71 and \tmp, \tmp, #HCR_E2H 72 cbz \tmp, \fail 73 .endm 74 75 /* 76 * Allow Non-secure EL1 and EL0 to access physical timer and counter. 77 * This is not necessary for VHE, since the host kernel runs in EL2, 78 * and EL0 accesses are configured in the later stage of boot process. 79 * Note that when HCR_EL2.E2H == 1, CNTHCTL_EL2 has the same bit layout 80 * as CNTKCTL_EL1, and CNTKCTL_EL1 accessing instructions are redefined 81 * to access CNTHCTL_EL2. This allows the kernel designed to run at EL1 82 * to transparently mess with the EL0 bits via CNTKCTL_EL1 access in 83 * EL2. 84 */ 85 .macro __init_el2_timers 86 mov x0, #3 // Enable EL1 physical timers 87 __check_hvhe .LnVHE_\@, x1 88 lsl x0, x0, #10 89 .LnVHE_\@: 90 msr cnthctl_el2, x0 91 msr cntvoff_el2, xzr // Clear virtual offset 92 .endm 93 94 /* Branch to skip_label if SPE version is less than given version */ 95 .macro __spe_vers_imp skip_label, version, tmp 96 mrs \tmp, id_aa64dfr0_el1 97 ubfx \tmp, \tmp, #ID_AA64DFR0_EL1_PMSVer_SHIFT, #4 98 cmp \tmp, \version 99 b.lt \skip_label 100 .endm 101 102 .macro __init_el2_debug 103 mrs x1, id_aa64dfr0_el1 104 ubfx x0, x1, #ID_AA64DFR0_EL1_PMUVer_SHIFT, #4 105 cmp x0, #ID_AA64DFR0_EL1_PMUVer_NI 106 ccmp x0, #ID_AA64DFR0_EL1_PMUVer_IMP_DEF, #4, ne 107 b.eq .Lskip_pmu_\@ // Skip if no PMU present or IMP_DEF 108 mrs x0, pmcr_el0 // Disable debug access traps 109 ubfx x0, x0, #11, #5 // to EL2 and allow access to 110 .Lskip_pmu_\@: 111 csel x2, xzr, x0, eq // all PMU counters from EL1 112 113 /* Statistical profiling */ 114 __spe_vers_imp .Lskip_spe_\@, ID_AA64DFR0_EL1_PMSVer_IMP, x0 // Skip if SPE not present 115 116 mrs_s x0, SYS_PMBIDR_EL1 // If SPE available at EL2, 117 and x0, x0, #(1 << PMBIDR_EL1_P_SHIFT) 118 cbnz x0, .Lskip_spe_el2_\@ // then permit sampling of physical 119 mov x0, #(1 << PMSCR_EL2_PCT_SHIFT | \ 120 1 << PMSCR_EL2_PA_SHIFT) 121 msr_s SYS_PMSCR_EL2, x0 // addresses and physical counter 122 .Lskip_spe_el2_\@: 123 mov x0, #MDCR_EL2_E2PB_MASK 124 orr x2, x2, x0 // If we don't have VHE, then 125 // use EL1&0 translation. 126 127 .Lskip_spe_\@: 128 /* Trace buffer */ 129 ubfx x0, x1, #ID_AA64DFR0_EL1_TraceBuffer_SHIFT, #4 130 cbz x0, .Lskip_trace_\@ // Skip if TraceBuffer is not present 131 132 mrs_s x0, SYS_TRBIDR_EL1 133 and x0, x0, TRBIDR_EL1_P 134 cbnz x0, .Lskip_trace_\@ // If TRBE is available at EL2 135 136 mov x0, #MDCR_EL2_E2TB_MASK 137 orr x2, x2, x0 // allow the EL1&0 translation 138 // to own it. 139 140 .Lskip_trace_\@: 141 msr mdcr_el2, x2 // Configure debug traps 142 .endm 143 144 /* LORegions */ 145 .macro __init_el2_lor 146 mrs x1, id_aa64mmfr1_el1 147 ubfx x0, x1, #ID_AA64MMFR1_EL1_LO_SHIFT, 4 148 cbz x0, .Lskip_lor_\@ 149 msr_s SYS_LORC_EL1, xzr 150 .Lskip_lor_\@: 151 .endm 152 153 /* Stage-2 translation */ 154 .macro __init_el2_stage2 155 msr vttbr_el2, xzr 156 .endm 157 158 /* GICv3 system register access */ 159 .macro __init_el2_gicv3 160 mrs x0, id_aa64pfr0_el1 161 ubfx x0, x0, #ID_AA64PFR0_EL1_GIC_SHIFT, #4 162 cbz x0, .Lskip_gicv3_\@ 163 164 mrs_s x0, SYS_ICC_SRE_EL2 165 orr x0, x0, #ICC_SRE_EL2_SRE // Set ICC_SRE_EL2.SRE==1 166 orr x0, x0, #ICC_SRE_EL2_ENABLE // Set ICC_SRE_EL2.Enable==1 167 msr_s SYS_ICC_SRE_EL2, x0 168 isb // Make sure SRE is now set 169 mrs_s x0, SYS_ICC_SRE_EL2 // Read SRE back, 170 tbz x0, #0, .Lskip_gicv3_\@ // and check that it sticks 171 msr_s SYS_ICH_HCR_EL2, xzr // Reset ICH_HCR_EL2 to defaults 172 .Lskip_gicv3_\@: 173 .endm 174 175 /* GICv5 system register access */ 176 .macro __init_el2_gicv5 177 mrs_s x0, SYS_ID_AA64PFR2_EL1 178 ubfx x0, x0, #ID_AA64PFR2_EL1_GCIE_SHIFT, #4 179 cbz x0, .Lskip_gicv5_\@ 180 181 mov x0, #(ICH_HFGITR_EL2_GICRCDNMIA | \ 182 ICH_HFGITR_EL2_GICRCDIA | \ 183 ICH_HFGITR_EL2_GICCDDI | \ 184 ICH_HFGITR_EL2_GICCDEOI | \ 185 ICH_HFGITR_EL2_GICCDHM | \ 186 ICH_HFGITR_EL2_GICCDRCFG | \ 187 ICH_HFGITR_EL2_GICCDPEND | \ 188 ICH_HFGITR_EL2_GICCDAFF | \ 189 ICH_HFGITR_EL2_GICCDPRI | \ 190 ICH_HFGITR_EL2_GICCDDIS | \ 191 ICH_HFGITR_EL2_GICCDEN) 192 msr_s SYS_ICH_HFGITR_EL2, x0 // Disable instruction traps 193 mov_q x0, (ICH_HFGRTR_EL2_ICC_PPI_ACTIVERn_EL1 | \ 194 ICH_HFGRTR_EL2_ICC_PPI_PRIORITYRn_EL1 | \ 195 ICH_HFGRTR_EL2_ICC_PPI_PENDRn_EL1 | \ 196 ICH_HFGRTR_EL2_ICC_PPI_ENABLERn_EL1 | \ 197 ICH_HFGRTR_EL2_ICC_PPI_HMRn_EL1 | \ 198 ICH_HFGRTR_EL2_ICC_IAFFIDR_EL1 | \ 199 ICH_HFGRTR_EL2_ICC_ICSR_EL1 | \ 200 ICH_HFGRTR_EL2_ICC_PCR_EL1 | \ 201 ICH_HFGRTR_EL2_ICC_HPPIR_EL1 | \ 202 ICH_HFGRTR_EL2_ICC_HAPR_EL1 | \ 203 ICH_HFGRTR_EL2_ICC_CR0_EL1 | \ 204 ICH_HFGRTR_EL2_ICC_IDRn_EL1 | \ 205 ICH_HFGRTR_EL2_ICC_APR_EL1) 206 msr_s SYS_ICH_HFGRTR_EL2, x0 // Disable reg read traps 207 mov_q x0, (ICH_HFGWTR_EL2_ICC_PPI_ACTIVERn_EL1 | \ 208 ICH_HFGWTR_EL2_ICC_PPI_PRIORITYRn_EL1 | \ 209 ICH_HFGWTR_EL2_ICC_PPI_PENDRn_EL1 | \ 210 ICH_HFGWTR_EL2_ICC_PPI_ENABLERn_EL1 | \ 211 ICH_HFGWTR_EL2_ICC_ICSR_EL1 | \ 212 ICH_HFGWTR_EL2_ICC_PCR_EL1 | \ 213 ICH_HFGWTR_EL2_ICC_CR0_EL1 | \ 214 ICH_HFGWTR_EL2_ICC_APR_EL1) 215 msr_s SYS_ICH_HFGWTR_EL2, x0 // Disable reg write traps 216 .Lskip_gicv5_\@: 217 .endm 218 219 .macro __init_el2_hstr 220 msr hstr_el2, xzr // Disable CP15 traps to EL2 221 .endm 222 223 /* Virtual CPU ID registers */ 224 .macro __init_el2_nvhe_idregs 225 mrs x0, midr_el1 226 mrs x1, mpidr_el1 227 msr vpidr_el2, x0 228 msr vmpidr_el2, x1 229 .endm 230 231 /* Coprocessor traps */ 232 .macro __init_el2_cptr 233 __check_hvhe .LnVHE_\@, x1 234 mov x0, #CPACR_EL1_FPEN 235 msr cpacr_el1, x0 236 b .Lskip_set_cptr_\@ 237 .LnVHE_\@: 238 mov x0, #0x33ff 239 msr cptr_el2, x0 // Disable copro. traps to EL2 240 .Lskip_set_cptr_\@: 241 .endm 242 243 /* 244 * Configure BRBE to permit recording cycle counts and branch mispredicts. 245 * 246 * At any EL, to record cycle counts BRBE requires that both BRBCR_EL2.CC=1 and 247 * BRBCR_EL1.CC=1. 248 * 249 * At any EL, to record branch mispredicts BRBE requires that both 250 * BRBCR_EL2.MPRED=1 and BRBCR_EL1.MPRED=1. 251 * 252 * Set {CC,MPRED} in BRBCR_EL2 in case nVHE mode is used and we are 253 * executing in EL1. 254 */ 255 .macro __init_el2_brbe 256 mrs x1, id_aa64dfr0_el1 257 ubfx x1, x1, #ID_AA64DFR0_EL1_BRBE_SHIFT, #4 258 cbz x1, .Lskip_brbe_\@ 259 260 mov_q x0, BRBCR_ELx_CC | BRBCR_ELx_MPRED 261 msr_s SYS_BRBCR_EL2, x0 262 .Lskip_brbe_\@: 263 .endm 264 265 /* Disable any fine grained traps */ 266 .macro __init_el2_fgt 267 mrs x1, id_aa64mmfr0_el1 268 ubfx x1, x1, #ID_AA64MMFR0_EL1_FGT_SHIFT, #4 269 cbz x1, .Lskip_fgt_\@ 270 271 mov x0, xzr 272 mov x2, xzr 273 /* If SPEv1p2 is implemented, */ 274 __spe_vers_imp .Lskip_spe_fgt_\@, #ID_AA64DFR0_EL1_PMSVer_V1P2, x1 275 /* Disable PMSNEVFR_EL1 read and write traps */ 276 orr x0, x0, #HDFGRTR_EL2_nPMSNEVFR_EL1_MASK 277 orr x2, x2, #HDFGWTR_EL2_nPMSNEVFR_EL1_MASK 278 279 .Lskip_spe_fgt_\@: 280 mrs x1, id_aa64dfr0_el1 281 ubfx x1, x1, #ID_AA64DFR0_EL1_BRBE_SHIFT, #4 282 cbz x1, .Lskip_brbe_fgt_\@ 283 284 /* 285 * Disable read traps for the following registers 286 * 287 * [BRBSRC|BRBTGT|RBINF]_EL1 288 * [BRBSRCINJ|BRBTGTINJ|BRBINFINJ|BRBTS]_EL1 289 */ 290 orr x0, x0, #HDFGRTR_EL2_nBRBDATA_MASK 291 292 /* 293 * Disable write traps for the following registers 294 * 295 * [BRBSRCINJ|BRBTGTINJ|BRBINFINJ|BRBTS]_EL1 296 */ 297 orr x2, x2, #HDFGWTR_EL2_nBRBDATA_MASK 298 299 /* Disable read and write traps for [BRBCR|BRBFCR]_EL1 */ 300 orr x0, x0, #HDFGRTR_EL2_nBRBCTL_MASK 301 orr x2, x2, #HDFGWTR_EL2_nBRBCTL_MASK 302 303 /* Disable read traps for BRBIDR_EL1 */ 304 orr x0, x0, #HDFGRTR_EL2_nBRBIDR_MASK 305 306 .Lskip_brbe_fgt_\@: 307 308 .Lset_debug_fgt_\@: 309 msr_s SYS_HDFGRTR_EL2, x0 310 msr_s SYS_HDFGWTR_EL2, x2 311 312 mov x0, xzr 313 mov x2, xzr 314 315 mrs x1, id_aa64dfr0_el1 316 ubfx x1, x1, #ID_AA64DFR0_EL1_BRBE_SHIFT, #4 317 cbz x1, .Lskip_brbe_insn_fgt_\@ 318 319 /* Disable traps for BRBIALL instruction */ 320 orr x2, x2, #HFGITR_EL2_nBRBIALL_MASK 321 322 /* Disable traps for BRBINJ instruction */ 323 orr x2, x2, #HFGITR_EL2_nBRBINJ_MASK 324 325 .Lskip_brbe_insn_fgt_\@: 326 mrs x1, id_aa64pfr1_el1 327 ubfx x1, x1, #ID_AA64PFR1_EL1_SME_SHIFT, #4 328 cbz x1, .Lskip_sme_fgt_\@ 329 330 /* Disable nVHE traps of TPIDR2 and SMPRI */ 331 orr x0, x0, #HFGRTR_EL2_nSMPRI_EL1_MASK 332 orr x0, x0, #HFGRTR_EL2_nTPIDR2_EL0_MASK 333 334 .Lskip_sme_fgt_\@: 335 mrs_s x1, SYS_ID_AA64MMFR3_EL1 336 ubfx x1, x1, #ID_AA64MMFR3_EL1_S1PIE_SHIFT, #4 337 cbz x1, .Lskip_pie_fgt_\@ 338 339 /* Disable trapping of PIR_EL1 / PIRE0_EL1 */ 340 orr x0, x0, #HFGRTR_EL2_nPIR_EL1 341 orr x0, x0, #HFGRTR_EL2_nPIRE0_EL1 342 343 .Lskip_pie_fgt_\@: 344 mrs_s x1, SYS_ID_AA64MMFR3_EL1 345 ubfx x1, x1, #ID_AA64MMFR3_EL1_S1POE_SHIFT, #4 346 cbz x1, .Lskip_poe_fgt_\@ 347 348 /* Disable trapping of POR_EL0 */ 349 orr x0, x0, #HFGRTR_EL2_nPOR_EL0 350 351 .Lskip_poe_fgt_\@: 352 /* GCS depends on PIE so we don't check it if PIE is absent */ 353 mrs_s x1, SYS_ID_AA64PFR1_EL1 354 ubfx x1, x1, #ID_AA64PFR1_EL1_GCS_SHIFT, #4 355 cbz x1, .Lskip_gce_fgt_\@ 356 357 /* Disable traps of access to GCS registers at EL0 and EL1 */ 358 orr x0, x0, #HFGRTR_EL2_nGCS_EL1_MASK 359 orr x0, x0, #HFGRTR_EL2_nGCS_EL0_MASK 360 361 .Lskip_gce_fgt_\@: 362 363 .Lset_fgt_\@: 364 msr_s SYS_HFGRTR_EL2, x0 365 msr_s SYS_HFGWTR_EL2, x0 366 msr_s SYS_HFGITR_EL2, x2 367 368 mrs x1, id_aa64pfr0_el1 // AMU traps UNDEF without AMU 369 ubfx x1, x1, #ID_AA64PFR0_EL1_AMU_SHIFT, #4 370 cbz x1, .Lskip_amu_fgt_\@ 371 372 msr_s SYS_HAFGRTR_EL2, xzr 373 374 .Lskip_amu_fgt_\@: 375 376 .Lskip_fgt_\@: 377 .endm 378 379 .macro __init_el2_fgt2 380 mrs x1, id_aa64mmfr0_el1 381 ubfx x1, x1, #ID_AA64MMFR0_EL1_FGT_SHIFT, #4 382 cmp x1, #ID_AA64MMFR0_EL1_FGT_FGT2 383 b.lt .Lskip_fgt2_\@ 384 385 mov x0, xzr 386 mrs x1, id_aa64dfr0_el1 387 ubfx x1, x1, #ID_AA64DFR0_EL1_PMUVer_SHIFT, #4 388 cmp x1, #ID_AA64DFR0_EL1_PMUVer_V3P9 389 b.lt .Lskip_pmuv3p9_\@ 390 391 orr x0, x0, #HDFGRTR2_EL2_nPMICNTR_EL0 392 orr x0, x0, #HDFGRTR2_EL2_nPMICFILTR_EL0 393 orr x0, x0, #HDFGRTR2_EL2_nPMUACR_EL1 394 .Lskip_pmuv3p9_\@: 395 /* If SPE is implemented, */ 396 __spe_vers_imp .Lskip_spefds_\@, ID_AA64DFR0_EL1_PMSVer_IMP, x1 397 /* we can read PMSIDR and */ 398 mrs_s x1, SYS_PMSIDR_EL1 399 and x1, x1, #PMSIDR_EL1_FDS 400 /* if FEAT_SPE_FDS is implemented, */ 401 cbz x1, .Lskip_spefds_\@ 402 /* disable traps of PMSDSFR to EL2. */ 403 orr x0, x0, #HDFGRTR2_EL2_nPMSDSFR_EL1 404 405 .Lskip_spefds_\@: 406 msr_s SYS_HDFGRTR2_EL2, x0 407 msr_s SYS_HDFGWTR2_EL2, x0 408 msr_s SYS_HFGRTR2_EL2, xzr 409 msr_s SYS_HFGWTR2_EL2, xzr 410 msr_s SYS_HFGITR2_EL2, xzr 411 .Lskip_fgt2_\@: 412 .endm 413 414 /** 415 * Initialize EL2 registers to sane values. This should be called early on all 416 * cores that were booted in EL2. Note that everything gets initialised as 417 * if VHE was not available. The kernel context will be upgraded to VHE 418 * if possible later on in the boot process 419 * 420 * Regs: x0, x1 and x2 are clobbered. 421 */ 422 .macro init_el2_state 423 __init_el2_sctlr 424 __init_el2_hcrx 425 __init_el2_timers 426 __init_el2_debug 427 __init_el2_brbe 428 __init_el2_lor 429 __init_el2_stage2 430 __init_el2_gicv3 431 __init_el2_gicv5 432 __init_el2_hstr 433 __init_el2_nvhe_idregs 434 __init_el2_cptr 435 __init_el2_fgt 436 __init_el2_fgt2 437 .endm 438 439 #ifndef __KVM_NVHE_HYPERVISOR__ 440 // This will clobber tmp1 and tmp2, and expect tmp1 to contain 441 // the id register value as read from the HW 442 .macro __check_override idreg, fld, width, pass, fail, tmp1, tmp2 443 ubfx \tmp1, \tmp1, #\fld, #\width 444 cbz \tmp1, \fail 445 446 adr_l \tmp1, \idreg\()_override 447 ldr \tmp2, [\tmp1, FTR_OVR_VAL_OFFSET] 448 ldr \tmp1, [\tmp1, FTR_OVR_MASK_OFFSET] 449 ubfx \tmp2, \tmp2, #\fld, #\width 450 ubfx \tmp1, \tmp1, #\fld, #\width 451 cmp \tmp1, xzr 452 and \tmp2, \tmp2, \tmp1 453 csinv \tmp2, \tmp2, xzr, ne 454 cbnz \tmp2, \pass 455 b \fail 456 .endm 457 458 // This will clobber tmp1 and tmp2 459 .macro check_override idreg, fld, pass, fail, tmp1, tmp2 460 mrs \tmp1, \idreg\()_el1 461 __check_override \idreg \fld 4 \pass \fail \tmp1 \tmp2 462 .endm 463 #else 464 // This will clobber tmp 465 .macro __check_override idreg, fld, width, pass, fail, tmp, ignore 466 ldr_l \tmp, \idreg\()_el1_sys_val 467 ubfx \tmp, \tmp, #\fld, #\width 468 cbnz \tmp, \pass 469 b \fail 470 .endm 471 472 .macro check_override idreg, fld, pass, fail, tmp, ignore 473 __check_override \idreg \fld 4 \pass \fail \tmp \ignore 474 .endm 475 #endif 476 477 .macro finalise_el2_state 478 check_override id_aa64pfr0, ID_AA64PFR0_EL1_MPAM_SHIFT, .Linit_mpam_\@, .Lskip_mpam_\@, x1, x2 479 480 .Linit_mpam_\@: 481 msr_s SYS_MPAM2_EL2, xzr // use the default partition 482 // and disable lower traps 483 mrs_s x0, SYS_MPAMIDR_EL1 484 tbz x0, #MPAMIDR_EL1_HAS_HCR_SHIFT, .Lskip_mpam_\@ // skip if no MPAMHCR reg 485 msr_s SYS_MPAMHCR_EL2, xzr // clear TRAP_MPAMIDR_EL1 -> EL2 486 487 .Lskip_mpam_\@: 488 check_override id_aa64pfr1, ID_AA64PFR1_EL1_GCS_SHIFT, .Linit_gcs_\@, .Lskip_gcs_\@, x1, x2 489 490 .Linit_gcs_\@: 491 msr_s SYS_GCSCR_EL1, xzr 492 msr_s SYS_GCSCRE0_EL1, xzr 493 494 .Lskip_gcs_\@: 495 check_override id_aa64pfr0, ID_AA64PFR0_EL1_SVE_SHIFT, .Linit_sve_\@, .Lskip_sve_\@, x1, x2 496 497 .Linit_sve_\@: /* SVE register access */ 498 __check_hvhe .Lcptr_nvhe_\@, x1 499 500 // (h)VHE case 501 mrs x0, cpacr_el1 // Disable SVE traps 502 orr x0, x0, #CPACR_EL1_ZEN 503 msr cpacr_el1, x0 504 b .Lskip_set_cptr_\@ 505 506 .Lcptr_nvhe_\@: // nVHE case 507 mrs x0, cptr_el2 // Disable SVE traps 508 bic x0, x0, #CPTR_EL2_TZ 509 msr cptr_el2, x0 510 .Lskip_set_cptr_\@: 511 isb 512 mov x1, #ZCR_ELx_LEN_MASK // SVE: Enable full vector 513 msr_s SYS_ZCR_EL2, x1 // length for EL1. 514 515 .Lskip_sve_\@: 516 check_override id_aa64pfr1, ID_AA64PFR1_EL1_SME_SHIFT, .Linit_sme_\@, .Lskip_sme_\@, x1, x2 517 518 .Linit_sme_\@: /* SME register access and priority mapping */ 519 __check_hvhe .Lcptr_nvhe_sme_\@, x1 520 521 // (h)VHE case 522 mrs x0, cpacr_el1 // Disable SME traps 523 orr x0, x0, #CPACR_EL1_SMEN 524 msr cpacr_el1, x0 525 b .Lskip_set_cptr_sme_\@ 526 527 .Lcptr_nvhe_sme_\@: // nVHE case 528 mrs x0, cptr_el2 // Disable SME traps 529 bic x0, x0, #CPTR_EL2_TSM 530 msr cptr_el2, x0 531 .Lskip_set_cptr_sme_\@: 532 isb 533 534 mrs x1, sctlr_el2 535 orr x1, x1, #SCTLR_ELx_ENTP2 // Disable TPIDR2 traps 536 msr sctlr_el2, x1 537 isb 538 539 mov x0, #0 // SMCR controls 540 541 // Full FP in SM? 542 mrs_s x1, SYS_ID_AA64SMFR0_EL1 543 __check_override id_aa64smfr0, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, .Linit_sme_fa64_\@, .Lskip_sme_fa64_\@, x1, x2 544 545 .Linit_sme_fa64_\@: 546 orr x0, x0, SMCR_ELx_FA64_MASK 547 .Lskip_sme_fa64_\@: 548 549 // ZT0 available? 550 mrs_s x1, SYS_ID_AA64SMFR0_EL1 551 __check_override id_aa64smfr0, ID_AA64SMFR0_EL1_SMEver_SHIFT, 4, .Linit_sme_zt0_\@, .Lskip_sme_zt0_\@, x1, x2 552 .Linit_sme_zt0_\@: 553 orr x0, x0, SMCR_ELx_EZT0_MASK 554 .Lskip_sme_zt0_\@: 555 556 orr x0, x0, #SMCR_ELx_LEN_MASK // Enable full SME vector 557 msr_s SYS_SMCR_EL2, x0 // length for EL1. 558 559 mrs_s x1, SYS_SMIDR_EL1 // Priority mapping supported? 560 ubfx x1, x1, #SMIDR_EL1_SMPS_SHIFT, #1 561 cbz x1, .Lskip_sme_\@ 562 563 msr_s SYS_SMPRIMAP_EL2, xzr // Make all priorities equal 564 .Lskip_sme_\@: 565 .endm 566 567 #endif /* __ARM_KVM_INIT_H__ */ 568